JP2010033690A - Shift register circuit - Google Patents

Abstract

In a shift register that requires a plurality of start pulses and a gate line driving circuit using the same, the number of start pulses that must be input from the outside is reduced.
A gate line driving circuit 30 receives two start pulses having different phases, shift registers SR ₁ , SR ₂ ,... Required for the operation, and a first start pulse SP1 input from the outside, and delays it. And a start pulse generation circuit 32 for generating a second start pulse SP2 to be activated. The shift registers SR ₁ , SR ₂ ,... Operate based on the first start pulse SP 1 input from the outside and the second start pulse SP 2 generated by the start pulse generation circuit 32.
[Selection] Figure 2

Description

  The present invention relates to a scanning line driving circuit, and in particular, a shift register circuit applicable to a scanning line driving circuit that is configured by using only field effect transistors of the same conductivity type used in, for example, an image display device. It is about.

  In an image display device such as a liquid crystal display device (hereinafter “display device”), a gate line (scanning line) is provided for each pixel row (pixel line) of a display panel in which a plurality of pixels are arranged in a matrix, and a display signal is displayed. The display image is updated by sequentially selecting and driving the gate lines in one horizontal period (1H period). As such a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, that is, gate lines, a shift register that performs a shift operation that makes a round in one frame period of a display signal can be used. .

  A shift register as a gate line driving circuit is configured by cascading a plurality of shift register circuits provided for each pixel line, that is, for each gate line. In this specification, each of the plurality of shift register circuits constituting the gate line driving circuit is referred to as a “unit shift register”. In other words, the output terminals of the individual unit shift registers constituting the gate line driving circuit are connected not only to the corresponding gate lines but also to the input terminals of the next stage or subsequent stage unit shift registers.

  The shift register used in the gate line driver circuit is preferably configured using only field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display device. For this reason, various shift registers configured using only N-type or P-type field effect transistors and display devices equipped with the shift registers have been proposed (for example, Patent Documents 1 and 2 below).

JP 2007-257813 A JP 2008-287753 A

  In particular, since the gate line driving circuit needs to be activated by charging the gate line at a high speed by its output signal, each unit shift register constituting the gate line driving circuit is required to have high driving ability (ability to flow current). .

  The above-described gate line driving circuit of Patent Document 1 was devised by the present inventor. FIG. 2 of the same document discloses the configuration of the gate line driving circuit, and FIG. 3 discloses the circuit configuration of the unit shift register. Has been. FIG. 5 of the present specification shows the same unit shift register as that of FIG.

  The unit shift register of FIG. 5 operates the first transistor (Q1) by operating the second transistor (Q3) for charging the gate of the first transistor (Q1) that activates the output signal G in the non-saturation region. The gate-source voltage at the time of turning on is increased, thereby increasing the drive capability of the unit shift register. However, unlike a general unit shift register, in order to operate the unit shift register of FIG. 5, it is necessary to supply two input signals (start pulses) having different phases (details will be described later).

  In Patent Document 1, two start pulses SP1 and SP2 are supplied from the outside in order to operate a gate line driving circuit (multi-stage shift register) configured using such a unit shift register. Normally, when the number of externally input signals (external signals) increases, the number of necessary circuits such as an external signal generation circuit and a level shifter that adjusts the level of the external signal increases, which increases the cost of the apparatus.

  The present invention has been made to solve the above-described problems. In a shift register that requires a plurality of start pulses and a gate line driving circuit using the shift register, start pulses that must be input from the outside are provided. The purpose is to reduce the number.

  A shift register circuit according to a first aspect of the present invention includes a start pulse generation circuit that receives a first start pulse and generates a second start pulse that is activated after the first start pulse, and a plurality of cascaded connections A shift register circuit including a unit shift register. Each of the unit shift registers includes first and second input terminals, a first output terminal for outputting an output signal, a first clock terminal to which a predetermined clock signal is input, and the first clock terminal. A first transistor for supplying an input clock signal to the first output terminal; a second transistor for supplying a potential of a power supply terminal to a first node connected to a control electrode of the first transistor; and the first input terminal. In response to a signal input to the second transistor, a charging circuit for charging a second node to which the control electrode of the second transistor is connected, and boosting the second node in response to a signal input to the second input terminal And a booster circuit. In the first stage of the plurality of unit shift registers, the first start pulse is input to the first input terminal, and the second start pulse is input to the second input terminal. In the second stage of the shift register, the second start pulse is input to the first input terminal, the output signal of the first stage is input to the second input terminal, and the plurality of unit shifts In each of the third and subsequent stages of the register, the output signal of the previous two stages is input to the first input terminal, and the output signal of the previous stage is input to the second input terminal.

  The shift register circuit according to the second aspect of the present invention is a multistage shift register circuit capable of forward shift for shifting a signal from the preceding stage to the subsequent stage and reverse shift for shifting the signal from the subsequent stage to the preceding stage. A forward start pulse generating circuit for receiving a forward first start pulse and generating a forward second start pulse that activates behind the forward first start pulse during forward shift, and a reverse first A reverse start pulse generating circuit for receiving a start pulse and generating a reverse second start pulse that activates behind the reverse first start pulse during reverse shift; The multi-stage unit shift register includes first to fourth input terminals, a first output terminal for outputting an output signal, a first clock terminal to which a predetermined clock signal is input, and the first shift terminal. A first transistor for supplying a clock signal input to one clock terminal to the first output terminal; first and second voltage signal terminals for supplying complementary first and second voltage signals; A second transistor for supplying a potential of the voltage signal terminal to a first node connected to a control electrode of the first transistor; and a potential of the first voltage signal terminal in accordance with a signal input to the first input terminal. A third transistor that supplies a second node to which a control electrode of the second transistor is connected; a first capacitive element that couples between the second input terminal and the second node; and the second voltage signal terminal. A fourth transistor for supplying a potential to the first node, and a third node to which the control electrode of the fourth transistor connects the potential of the second voltage signal terminal according to a signal input to the third input terminal And a second capacitor element coupled between the fourth input terminal and the third node. In the first stage unit shift register, the forward first start pulse is input to the first input terminal, and the forward second start pulse is input to the second input terminal. In the first unit shift register, the forward second start pulse is input to the first input terminal, the output signal of the first stage is input to the second input terminal, and the third and subsequent stages. In each of the unit shift registers, the output signal of the immediately preceding stage is input to the first input terminal, the output signal of the immediately preceding stage is input to the second input terminal, and the unit shift of the last stage is performed. In the register, the reverse first start pulse is input to the third input terminal, the reverse second start pulse is input to the fourth input terminal, and the unit shift register in the second stage from the last is input. Each of the unit shift registers before and after the last three stages is input with the reverse second start pulse being input to the third input terminal and the output signal of the last stage being input to the fourth input terminal. , The output signal of the next two stages is input to the third input terminal, and the output signal of the next stage is input to the fourth input terminal.

  According to the shift register circuit of the present invention, even when a unit shift register that requires two or more input signals having different phases is used, the number of start pulses that need to be input from the outside can be reduced. Therefore, the cost of the apparatus can be reduced as compared with the prior art.

It is a schematic block diagram which shows the structure of the display apparatus which concerns on embodiment of this invention. 1 is a diagram illustrating a configuration of a gate line driving circuit according to a first embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a start pulse generation circuit according to the first embodiment. FIG. 4 is a signal waveform diagram for explaining the operation of the start pulse generation circuit according to the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a unit shift register according to the first embodiment. FIG. 6 is a timing diagram illustrating an operation of the unit shift register according to the first embodiment. FIG. 6 is a signal waveform diagram illustrating an operation of the gate line driving circuit according to the first embodiment. FIG. 5 is a diagram showing a configuration of a gate line driving circuit according to a second embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a unit shift register according to a second embodiment. FIG. 6 is a diagram illustrating a specific circuit configuration of first and second start pulse generation circuits according to a second embodiment. FIG. 10 is a signal waveform diagram illustrating an operation of the gate line driving circuit according to the second embodiment. FIG. 6 is a diagram illustrating a configuration of a gate line driving circuit according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration of a forward start pulse generation circuit according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration of a reverse start pulse generation circuit according to a third embodiment. FIG. 13 is a signal waveform diagram for illustrating the operation of the third embodiment forward start pulse generation circuit. FIG. 6 is a circuit diagram illustrating a configuration of a unit shift register according to a third embodiment. FIG. 10 is a timing diagram illustrating an operation of a unit shift register according to the third embodiment. FIG. 10 is a signal waveform diagram showing an operation of the gate line driving circuit according to the third embodiment. FIG. 10 is a signal waveform diagram showing an operation of the gate line driving circuit according to the third embodiment. 12 is a circuit diagram showing a configuration of a unit shift register according to a first modification of the third embodiment. FIG. FIG. 10 is a circuit diagram showing a configuration of a unit shift register according to a second modification of the third embodiment. FIG. 10 is a circuit diagram showing a configuration of a unit shift register according to a second modification of the third embodiment. FIG. 10 is a diagram illustrating a configuration of a gate line driving circuit according to a fourth embodiment. FIG. 6 is a circuit diagram showing a configuration of a forward start pulse generation circuit and a reverse reset signal generation circuit according to a fourth embodiment. FIG. 6 is a circuit diagram showing configurations of a reverse start pulse generation circuit and a forward reset signal generation circuit according to a fourth embodiment. FIG. 10 is a signal waveform diagram showing an operation of the gate line driving circuit according to the fourth embodiment. FIG. 10 is a signal waveform diagram showing an operation of the gate line driving circuit according to the fourth embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

  The transistor used in each embodiment is an insulated gate field effect transistor. In the insulated gate field effect transistor, the electric conductivity between the drain region and the source region in the semiconductor layer is controlled by the electric field in the gate insulating film. As a material of the semiconductor layer in which the drain region and the source region are formed, an organic semiconductor such as polysilicon, amorphous silicon, or pentacene, an oxide semiconductor such as single crystal silicon or IGZO (In-Ga-Zn-O), or the like is used. be able to.

  As is well known, each transistor has a control electrode (gate (electrode) in the narrow sense), one current electrode (drain (electrode) or source (electrode) in the narrow sense)), and the other current electrode (in the narrow sense, the drain (electrode) or the source (electrode)). In a narrow sense, it is an element having at least three electrodes including a source (electrode) or a drain (electrode). The transistor functions as a switching element in which a channel is formed between the drain and the source by applying a predetermined voltage to the gate. The drain and source of the transistor have basically the same structure, and their names are interchanged depending on the applied voltage condition. For example, in the case of an N-type transistor, an electrode having a relatively high potential is referred to as a drain and a low electrode is referred to as a source (in the case of a P-type transistor, the opposite is true).

  Unless otherwise specified, these transistors may be formed on a semiconductor substrate, or may be a thin film transistor (TFT) formed on an insulating substrate such as glass. The substrate over which the transistor is formed may be a single crystal substrate or an insulating substrate such as SOI, glass, or resin.

  The gate line driving circuit of the present invention is configured using only a single conductivity type transistor. For example, an N-type transistor becomes active (on state, conductive state) when the gate-source voltage becomes H (high) level higher than the threshold voltage of the transistor, and L ( At a low level, it becomes inactive (off state, non-conductive state). Therefore, in a circuit using an N-type transistor, the H level of the signal is “active level” and the L level is “inactive level”. In addition, each node of a circuit configured using an N-type transistor is charged to become an H level, thereby causing a change from an inactive level to an active level, and being discharged to an L level. A change from to inactive level occurs.

  Conversely, a P-type transistor becomes active (on state, conductive state) when the gate-source voltage becomes L level lower than the threshold voltage of the transistor (a negative value with respect to the source). It becomes inactive (OFF state, non-conducting state) at an H level higher than the voltage. Therefore, in a circuit using a P-type transistor, the L level of the signal is “active level” and the H level is “inactive level”. In addition, each node of the circuit configured using the P-type transistor has a charge / discharge relationship opposite to that in the case of the N-type transistor, and is charged to the L level, so that the inactive level changes from the inactive level to the active level. When the change occurs and is discharged to the H level, a change from the active level to the inactive level occurs.

  In this specification, the change from the inactive level to the active level is defined as “pull-up”, and the change from the active level to the inactive level is defined as “pull-down”. That is, in a circuit using an N-type transistor, a change from the L level to the H level is defined as “pull-up”, and a change from the H level to the L level is defined as “pull-down”. A change from the level to the L level is defined as “pull-up”, and a change from the L level to the H level is defined as “pull-down”.

  In this specification, “connection” between two elements, between two nodes, or between one element and one node is a connection through other elements (elements, switches, etc.). In the following description, it is assumed to include a state that is substantially equivalent to a direct connection. For example, even if two elements are connected via a switch, if they can function in the same way as when they are directly connected, the two elements are “connected”. Express.

In the present invention, clock signals having different phases (multiphase clock signals) are used. In the following description, for the sake of simplicity, a certain interval is provided between the active period of one clock signal and the active period of the clock signal to be activated next (for example, times t _{0 to} t in FIG. 4). ₁ intervals, intervals between times t _{2 and} t ₃ , etc.). However, in the present invention, it is sufficient that the active periods of the clock signals do not substantially overlap, and the above-described interval may not be provided. For example, if the activation level is H level, the falling timing of one clock signal and the rising timing of the clock signal to be activated next may be simultaneous.

<Embodiment 1>
FIG. 1 is a schematic block diagram showing a configuration of a display device according to Embodiment 1 of the present invention, and shows an overall configuration of a liquid crystal display device 10 as a representative example of the display device.

  The liquid crystal display device 10 includes a liquid crystal array unit 20, a gate line driving circuit (scanning line driving circuit) 30, and a source driver 40. As will be apparent from the following description, the start signal generator according to the embodiment of the present invention is mounted on the gate line driving circuit 30.

The liquid crystal array unit 20 includes a plurality of pixels 25 arranged in a matrix. Each of the pixel rows (hereinafter also referred to as “pixel lines”) is provided with gate lines GL ₁ , GL ₂ ... (Generically referred to as “gate lines GL”), and each pixel row (hereinafter also referred to as “pixel column”). Are respectively provided with data lines DL ₁ , DL ₂ ... (Generic name “data line DL”). FIG. 1 representatively shows the pixels 25 in the first and second columns of the first row, and the corresponding gate lines GL ₁ and data lines DL ₁ and DL ₂ .

  Each pixel 25 includes a pixel switch element 26 provided between the corresponding data line DL and the pixel node Np, a capacitor 27 and a liquid crystal display element 28 connected in parallel between the pixel node Np and the common electrode node NC. have. The orientation of the liquid crystal in the liquid crystal display element 28 changes according to the voltage difference between the pixel node Np and the common electrode node NC, and the display brightness of the liquid crystal display element 28 changes in response to this. Thereby, the luminance of each pixel can be controlled by the display voltage transmitted to the pixel node Np via the data line DL and the pixel switch element 26. That is, by applying an intermediate voltage difference between the voltage difference corresponding to the maximum luminance and the voltage difference corresponding to the minimum luminance between the pixel node Np and the common electrode node NC, the intermediate luminance is reduced. Obtainable. Therefore, gradation brightness can be obtained by setting the display voltage stepwise.

  The gate line driving circuit 30 sequentially selects and drives the gate lines GL based on a predetermined scanning cycle. The gate electrodes of the pixel switch elements 26 are connected to the corresponding gate lines GL. While a specific gate line GL is selected, the pixel switch element 26 is in a conductive state in each pixel connected thereto, and the pixel node Np is connected to the corresponding data line DL. The display voltage transmitted to the pixel node Np is held by the capacitor 27. In general, the pixel switch element 26 includes a TFT formed on the same insulator substrate (glass substrate, resin substrate, etc.) as the liquid crystal display element 28.

The source driver 40 is for outputting a display voltage, which is set stepwise by a display signal SIG that is an N-bit digital signal, to the data line DL. Here, as an example, the display signal SIG is a 6-bit signal and is composed of display signal bits DB0 to DB5. Based on the 6-bit display signal SIG, 2 ⁶ = 64 gradation display is possible in each pixel. Furthermore, if one color display unit is formed by three pixels of R (Red), G (Green), and B (Blue), approximately 260,000 colors can be displayed.

  As shown in FIG. 1, the source driver 40 includes a shift register 50, data latch circuits 52 and 54, a gradation voltage generation circuit 60, a decode circuit 70, and an analog amplifier 80.

  In the display signal SIG, display signal bits DB0 to DB5 corresponding to the display brightness of each pixel 25 are serially generated. That is, the display signal bits DB0 to DB5 at each timing indicate the display luminance in any one pixel 25 in the liquid crystal array unit 20.

  The shift register 50 instructs the data latch circuit 52 to take in the display signal bits DB0 to DB5 at a timing synchronized with a cycle in which the setting of the display signal SIG is switched. The data latch circuit 52 sequentially takes in the serially generated display signal SIG and holds the display signal SIG for one pixel line.

  The latch signal LT input to the data latch circuit 54 is activated at the timing when the display signal SIG for one pixel line is taken into the data latch circuit 52. In response thereto, the data latch circuit 54 takes in the display signal SIG for one pixel line held in the data latch circuit 52 at that time.

  The gradation voltage generation circuit 60 is composed of 63 voltage dividing resistors connected in series between the high voltage VDH and the low voltage VDL, and generates 64 gradation voltages V1 to V64, respectively.

The decode circuit 70 decodes the display signal SIG held in the data latch circuit 54 and outputs a voltage to each decode output node Nd ₁ , Nd ₂ ... (Generic name “decode output node Nd”) based on the decode result. Are selected from the gradation voltages V1 to V64 and output.

As a result, at the decode output node Nd, a display voltage (one of the gradation voltages V1 to V64) corresponding to the display signal SIG for one pixel line held in the data latch circuit 54 is simultaneously (in parallel). ) Is output. In FIG. 1, the decode output nodes Nd ₁ and Nd ₂ corresponding to the data lines DL ₁ and DL ₂ in the first column and the second column are representatively shown.

The analog amplifier 80 amplifies the analog voltage corresponding to each display voltage output from the decode circuit 70 to the decode output nodes Nd ₁ , Nd ₂ ... And outputs them to the data lines DL ₁ , DL ₂ .

The source driver 40 repeatedly outputs a display voltage corresponding to a series of display signals SIG to the data line DL for each pixel line based on a predetermined scanning cycle, and the gate line driving circuit 30 is synchronized with the scanning cycle. By sequentially driving the gate lines GL ₁ , GL ₂ ..., An image is displayed on the liquid crystal array unit 20 based on the display signal SIG.

  1 illustrates the configuration of the liquid crystal display device 10 in which the gate line driving circuit 30 and the source driver 40 are integrally formed with the liquid crystal array unit 20, but the gate line driving circuit 30, the liquid crystal array unit 20, and the like. And the source driver 40 can be provided as an external circuit of the liquid crystal array unit 20, or the gate line driving circuit 30 and the source driver 40 can be provided as an external circuit of the liquid crystal array unit 20.

FIG. 2 is a diagram showing a configuration of the gate line driving circuit 30 according to the first embodiment. The gate line driving circuit 30 includes a start pulse generation circuit 32 and a multistage shift register including a plurality of unit shift registers SR ₁ , SR ₂ , SR ₃ , SR ₄ . For convenience of explanation, the shift register circuits SR ₁ , SR ₂ ... Are collectively referred to as “unit shift register SR”). One unit shift register SR is provided for each pixel line, that is, for each gate line GL. This multistage shift register has the same configuration as that shown in FIG.

  The start pulse generation circuit 32 receives a first start pulse SP1 (external start pulse) input from the outside of the gate line driving circuit 30 at its input terminal INA, and is activated after the first start pulse SP1. A start pulse SP2 (internal start pulse) is generated and output from the output terminal OUTA.

  The first start pulse SP1 is a signal that becomes H level (active level) for a length corresponding to approximately one horizontal period at a timing corresponding to the head of each frame period of the image signal. The start pulse generation circuit 32 sets the second start pulse SP2 to the H level for one horizontal period after the first start pulse SP1 returns from the H level to the L level. That is, the phase of the second start pulse SP2 is delayed by one horizontal period with respect to the first start pulse SP1.

  Therefore, in the present embodiment, the first and second start pulses SP1 and SP2 are sequentially set to the H level (active level) at the timing corresponding to the head of each frame period of the image signal. As a result, the first and second start pulses SP1 and SP2 are the same as the start pulses SP1 and SP2 used in the shift register of FIG. The specific configuration and operation of the start pulse generation circuit 32 will be described later.

As shown in FIG. 2, each of the unit shift registers SR has a clock terminal CK, a reset terminal RST, an output terminal OUT, a first input terminal IN1, and a second input terminal IN2. The first start pulse SP1 is input to the first input terminal IN1 of the unit shift register SR ₁ of the first stage (the forefront). The second start pulse SP2 has a second input terminal IN2 of the shift register SR ₁ foremost stage is input to the first input terminal IN1 of the unit shift register SR ₂ of the second stage.

  The clock signal generator 31 supplies three-phase clock signals CLK1, CLK2, and CLK3 having different phases to the unit shift register SR of the gate line driving circuit 30. The clock signals CLK1, CLK2, and CLK3 are controlled to be repeatedly activated in this order at a timing synchronized with the scanning period of the display device. That is, the clock signals CLK1, CLK2, and CLK3 are out of phase by one horizontal period (1H period).

As shown in FIG. 2, a predetermined one of the clock signals CLK1, CLK2, and CLK3 output from the clock signal generator 31 is supplied to the clock terminal CK of each unit shift register SR. In the present embodiment, the output signal G ₁ of the first stage unit shift register SR ₁ is set to be activated when the clock signal CLK ₁ is activated.

In this case, the clock signal CLK1 is supplied to the [3k-2] stage unit shift registers SR ₁ , SR ₄ , SR ₇ ..., And the clock signal CLK2 is the [3k-1] stage unit shift registers SR ₂ , SR. ₅ , SR ₈ ..., And the clock signal CLK ₃ is supplied to unit shift registers SR ₃ , SR ₆ , SR ₉ ... In the [3k] stage (k is a natural number). As described above, the clock signals CLK1, CLK2, and CLK3 are activated in this order, so that the clock terminals CK of the shift register circuits SR ₁ , SR ₂ , SR ₃ .

The first and second input terminals IN1, IN2 of the unit shift register SR ₁ of the first stage (first stage), the first and second start pulses respectively SP1, SP2 is input. In the unit shift register SR ₂ of the second stage, the second start pulse SP2 is input to the first input terminal IN1, the second input terminal IN2 output signal G of the unit shift register SR ₁ of the first stage ₁ is entered. In the third and subsequent unit shift registers SR _n , the first input terminal IN1 receives the output signal G _n−2 of the unit shift register SR _n−2 of the previous two stages (previous stage). The output signal G _n−1 of the unit shift register SR _{n−1 at} the immediately preceding stage is input to the input terminal IN2.

Output signals G ₁ , G ₂ , G ₃ ,... (Hereinafter collectively referred to as “output signal G”) of each unit shift register SR are output to the corresponding gate lines GL as horizontal (or vertical) scanning pulses. . That is, the output signal G functions as a “gate line drive signal” for driving the gate line GL. Further, the output signal G of each unit shift register SR is also input to the preceding reset terminal RST.

  In the gate line driving circuit 30 of FIG. 2, each unit shift register SR is synchronized with the clock signals CLK1, CLK2, and CLK3, and the signals (start pulse or itself) input to the first and second input terminals IN1 and IN2. In addition, the output signal G of the preceding stage is transmitted to the corresponding gate line GL and the unit shift register SR that is subsequent to itself while being shifted in time by one horizontal period (details of the operation of the unit shift register SR will be described later). ). As a result, the series of unit shift registers SR function as a so-called “gate line driving unit” that sequentially activates (selects) the gate lines GL at a timing based on a predetermined scanning cycle.

  Hereinafter, a specific configuration of the gate line driving circuit 30 according to the present embodiment will be described. First, the specific configuration of the start pulse generation circuit 32 will be described. As described above, the first start pulse SP1 is a single pulse having a pulse width of approximately one horizontal period. The second start pulse SP2 generated by the start pulse generation circuit 32 is a single pulse obtained by temporally shifting the first start pulse SP1 by one horizontal period (delaying the phase). Therefore, as the start pulse generation circuit 32, a one-stage shift register, that is, a unit shift register circuit can be used.

The start pulse generation circuit 32 is not required to have a high driving capability, unlike the unit shift registers SR ₁ , SR ₂ ... That drive the gate line GL that is a large capacitive load. Therefore, unlike the unit shift register SR of Patent Document 1, a mechanism for increasing the driving capability is not provided, and a simple unit shift register with one input and one output can be used.

  FIG. 3 is a circuit diagram showing a configuration example of the start pulse generation circuit 32 according to the first embodiment. This circuit corresponds to, for example, the unit shift register disclosed in FIG. 2 of JP-T-06-505605. It is assumed that all the transistors constituting the start pulse generation circuit 32 are N-type TFTs. In the following, it is assumed that the threshold voltages are all equal, and the value is described as Vth.

  As shown in FIG. 3, the start pulse generation circuit 32 includes a clock terminal CKA, a reset terminal, in addition to an input terminal INA to which the first start pulse SP1 is input and an output terminal OUTA for outputting the second start pulse SP2. A terminal RSTA, a first power supply terminal S1, and a second power supply terminal S2 are provided. The first power supply terminal S1 is supplied with a low potential power supply potential (hereinafter referred to as “low power supply potential”) VSS, and the second power supply terminal S2 is supplied with a high potential power supply potential (hereinafter referred to as “high power supply potential”) VDD1. Is done.

  In the following description, the low-side power supply potential VSS is treated as the circuit reference potential. However, in actual use, the reference potential is set based on the voltage of data written to the pixel. For example, the high-side power supply potential VDD1 is 17V, and the low-side power supply The potential VSS is set to −12V or the like.

  Here, for simplification of description, the level of the high-side power supply potential VDD1, the potentials of the clock signals CLK1 to CLK3 and the H level of the first start pulse SP1 are all equal, and the level is expressed as VDD (that is, VDD = VDD1). The L level potentials of the clock signals CLK1 to CLK3 and the first start pulse SP1 are assumed to be equal to the low-side power supply potential VSS.

The clock terminal CKA of the start pulse generating circuit 32, a clock signal CLK3 which is activated immediately before the clock signal CLK1 supplied to the clock terminal CK of the unit shift register SR ₁ of the first stage is supplied. The first start pulse SP1 is a single pulse, and its active period is set to overlap with the active period of the clock signal CLK2 activated immediately before the clock signal CLK3 input to the clock terminal CKA. Further, the clock signal CLK1 whose active period does not overlap with both the clock signal CLK3 input to the clock terminal CKA and the first start pulse SP1 input to the input terminal INA is input to the reset terminal RSTA.

  As shown in FIG. 3, the start pulse generation circuit 32 includes N-type transistors Q1A to Q6A and a capacitive element C1A. The transistor Q1A is connected between the output terminal OUTA and the clock terminal CKA, and supplies the clock signal CLK3 supplied to the clock terminal CKA to the output terminal OUTA. The transistor Q2A is connected between the output terminal OUTA and the first power supply terminal S1, and discharges the output terminal OUTA. As shown in FIG. 3, a node connected to the gate (control electrode) of the transistor Q1A is defined as a node N1A, and a node connected to the gate of the transistor Q2A is defined as a node N2A.

  A capacitive element C1A (step-up capacitor) is provided between the gate and source of the transistor Q1A (that is, between the output terminal OUTA and the node N1A). The capacitive element C1A is for increasing the boosting effect of the node N1A accompanying the level increase of the output terminal OUTA. However, the capacitor C1A can be replaced if the gate-channel capacitance of the transistor Q1A is sufficiently large, and may be omitted in such a case.

  The transistor Q3A has a gate connected to the input terminal INA, and is connected between the node N1A and the second power supply terminal S2. That is, the transistor Q3A charges the node N1A by supplying the potential of the second power supply terminal S2 to the node N1A in response to the first start pulse SP1. The transistor Q4A has a gate connected to the node N2A, and is connected between the node N1A and the first power supply terminal S1. The drain of the transistor Q3A may be connected to the input terminal INA instead of the second power supply terminal S2.

  The transistor Q5A has a gate connected to the reset terminal RSTA, and is connected between the second power supply terminal S2 and the node N2A. That is, the transistor Q5A charges the node N2A by supplying the potential of the second power supply terminal S2 to the node N2A according to the clock signal CLK1. The drain of the transistor Q5A may be connected to the reset terminal RSTA instead of the second power supply terminal S2.

  The transistor Q6A has a gate connected to the input terminal INA, and is connected between the node N2A and the first power supply terminal S1. That is, the transistor Q6A discharges the node N2A in response to the first start pulse SP1.

FIG. 4 is a signal waveform diagram for explaining the operation of the start pulse generation circuit 32 of FIG. At time t ₀ before the activation of the first start pulse SP1, the clock signal CLK1 is at the H level. Since the active periods of the clock signals CLK1 to CLK3 do not overlap, the clock signals CLK2 and CLK3 are at the L level at this time.

Therefore, at time t ₀ , the transistors Q3A and Q6A of the start pulse generation circuit 32 are in the off state, the transistor Q5A is in the on state, and the node N2A is charged to the H level (VDD−Vth). Therefore, the transistors Q2A and Q4A are on. Thus, since the transistor Q3A is off and the transistor Q4A is on, the node N1A is at L level (VSS), and the transistor Q1A is off. Since the transistor Q2A is on, the output terminal OUTA (second start pulse SP2) is at the L level (VSS).

When the clock signal CLK1 becomes the L level at time t _1, the transistor Q5A is turned off, the first start pulse SP1 has maintained the L level, the transistor Q6A is kept off, the high impedance at the node N2A The state is held at the H level. Therefore, since transistors Q2A and Q4A are maintained in the on state, output terminal OUTA and node N1A do not change from the L level.

The start pulse SP1 at time t ₂ is becomes H level, the transistor Q6A is turned on, the node N2A is being discharged L level. Accordingly, the transistors Q2A and Q4A are turned off. Since the transistor Q3A is also turned on when the first start pulse SP1 becomes H level, the node N1A is charged and becomes H level (VDD-Vth). Thereby, the transistor Q1A is turned on. At this time, since the clock signal CLK3 is at the L level, the output terminal OUTA remains at the L level.

When the start pulse SP1 becomes L level at time t _3, the transistors Q6A is turned off, the node N2A becomes the L level of the high impedance state. The transistor Q3A is also turned off, and the node N1A is at a high impedance H level.

When the clock signal CLK3 becomes H level at time t _4, the elevated levels is transmitted to the output terminal OUTA through the transistor Q1A in the non-saturation region on state, also increases the level of the output terminal OUTA. As a result, the second start pulse SP2 output from the start pulse generation circuit 32 becomes H level.

  This potential change of the output terminal OUTA raises the level of the node N1A due to the coupling through the capacitive element C1A. By the boosting action of the node N1A, the transistor Q1A can continue the operation in the non-saturation region even when the level of the output terminal OUTA rises, and raises the output terminal OUTA to the same potential VDD as the H level of the clock signal CLK3. Can do. The level of the node N1A at this time is 2 · VDD−Vth when the parasitic capacitance of the node N1A is ignored.

When the clock signal CLK3 becomes L level at time t _5, the output terminal OUTA is discharged through the transistor Q1A, its level also becomes L level (VSS) and the clock signal CLK3. The coupling via the time capacitive element C1A, also decreases the level of the node N1A, node N1A returns to the same potential VDD-Vth and before being boosted (time t _3).

When the clock signal CLK1 becomes H level at time t _6, the transistor Q5A is turned on. At this time, since the first start pulse SP1 is at the L level, the transistors Q3A and Q6A are in the off state. Therefore, the node N2A is charged and becomes H level, and the transistors Q2A and Q4A are turned on. Thus, since the transistor Q3A is turned off and the transistor Q4A is turned on, the node N1A is discharged to L level (VSS), and the transistor Q1A is turned off. As a result, the transistor Q1A is turned off and the transistor Q2A is turned on, so that the output terminal OUTA becomes L level (VSS). That is, the start pulse generation circuit 32 returns to the state at time t ₀ described above.

After time t ₇ , the transistor Q5A is turned off every time the clock signal CLK1 becomes L level. However, since the first start pulse SP1 is maintained at L level until the beginning of the next frame period, the transistors Q3A and Q6A are in the meantime. Maintained off. Accordingly, since the node N1A is maintained at the L level and the node N2A is maintained at the H level, the transistor Q1A is kept off and the transistor Q2A is kept on. Therefore, the second start pulse SP2 is maintained at the L level with low impedance until the first start pulse SP1 is activated at the beginning of the next frame period.

  As a result, the second start pulse SP2 generated by the start pulse generation circuit 32 is a single pulse that is activated with a delay of one horizontal period with respect to the first start pulse SP1. As can be understood from the above description, the second start pulse SP2 is a signal of the high-side power supply potential VDD and the L-level potential is the low-side power supply potential VSS, similarly to the first start pulse SP1.

Also in the first start pulse SP1 is activated without the time t ₇ after the period, the transistor Q5A is turned repeatedly ON in response to activation of the clock signal CLK1, the node N2A is repeatedly charged. Therefore, even if a leak current is generated in transistor Q6A, it is possible to prevent the level of node N2A from decreasing. Thereby, the transistors Q2A and Q4A are maintained at a low resistance, the node N1A and the output terminal OUTA can be maintained at the L level with a low impedance, and the generation of an erroneous signal can be prevented.

  The configuration of the start pulse generation circuit 32 shown in FIG. 3 is merely an example, and the second start pulse SP2, which is a single pulse delayed by one horizontal period with respect to the first start pulse SP1, can be generated. A circuit having a configuration may be used. For example, the circuit configuration of the unit shift register SR disclosed in FIG. 12 of Japanese Patent Laid-Open No. 2000-155550, FIG. 1 of Japanese Patent Laid-Open No. 2002-313093, FIG.

Next, a specific configuration of the unit shift register SR driven using the first and second start pulses SP1 and SP2 will be described. FIG. 5 is a circuit diagram showing a configuration of the unit shift register SR according to the first embodiment. In the gate line driving circuit 30 of the present embodiment, the unit shift registers SR ₁ , SR ₂ ,... Connected in cascade are basically all of the same configuration, so that the first stage is typically shown in FIG. The unit shift register SR ₁ is shown.

As shown in FIG. 5, the unit shift register SR _1, the first and second input terminals IN1, IN2 shown in FIG. 2, the clock terminal CK, in addition to the reset terminal RST and the output terminal OUT, and the low-side power supply potential VSS The first power supply terminal S1 to be supplied, the second power supply terminal S2 to which the high-side power supply potentials VDD1 and VDD2 are supplied, and the third power supply terminal S3, respectively. The potential VDD2 may be at the same level as the potential VDD1.

  The output stage of the unit shift register SR includes a transistor Q1 connected between the output terminal OUT and the clock terminal CK, and a transistor Q2 connected between the output terminal OUT and the first power supply terminal S1. That is, the transistor Q1 supplies a clock signal input to the clock terminal CK to the output terminal OUT (first transistor), and the transistor Q2 supplies the potential of the first power supply terminal S1 to the output terminal OUT. It is. As shown in FIG. 5, a node connected to the gate (control electrode) of the transistor Q1 is defined as a node N1 (first node), and a node connected to the gate of the transistor Q2 is defined as a node N2.

  A boosting capacitive element C1 (boosting capacitor) is provided between the gate and source of the transistor Q1 (that is, between the output terminal OUT and the node N1). The capacitive element C1 is for enhancing the boosting effect of the node N1 accompanying the increase in the level of the output terminal OUT. However, the capacitor C1 can be replaced if the gate-channel capacitance of the transistor Q1 is sufficiently large, and may be omitted in such a case.

  A transistor Q3 (second transistor) for supplying the potential of the second power supply terminal S2 to the node N1 is connected between the node N1 and the second power supply terminal S2. A transistor Q4 is connected between the node N1 and the first power supply terminal S1. Transistor Q4 has its gate connected to node N2. Here, the gate node of the transistor Q3 is defined as a node N3 (second node).

  A transistor Q8 having a gate connected to the first input terminal IN1 is connected between the node N3 and the second power supply terminal S2. The drain of the transistor Q8 may be connected to the input terminal IN1 instead of the second power supply terminal S2.

  A capacitive element C2 is connected between the node N3 and the second input terminal IN2. Further, the transistor Q5 and the transistor Q9 are connected between the node N3 and the first power supply terminal S1. The gate of transistor Q5 is connected to reset terminal RST, and the gate of transistor Q9 is connected to node N2.

  A transistor Q6 is connected between the node N2 and the third power supply terminal S3, and a transistor Q7 is connected between the node N2 and the first power supply terminal S1. The gate of the transistor Q6 is connected to the third power supply terminal S3 together with the drain (the transistor Q6 is diode-connected), and the gate of the transistor Q7 is connected to the node N3.

  The transistor Q7 is set to have a sufficiently larger driving capability (ability to flow current) than the transistor Q6. That is, the on-resistance of the transistor Q7 is sufficiently smaller than the on-resistance of the transistor Q6. Therefore, when the potential of the node N3 (the gate of the transistor Q7) increases, the potential of the node N2 decreases, and when the potential of the node N3 decreases, the potential of the node N2 increases. That is, the transistors Q6 and Q7 constitute a ratio type inverter whose operation is defined by the ratio of the on-resistance values of the transistors Q6 and Q7. The inverter has a node N3 as an input end and a node N2 as an output end, and constitutes a “pull-down drive circuit” that drives a transistor Q2 for pulling down an output terminal OUT.

Figure 6 is a timing chart showing the operation of the unit shift register SR ₁ of FIG. Hereinafter, a specific operation of the unit shift register SR ₁ will be described with reference to FIG. Time t ₁ to time t ₈ shown in FIG. 6 correspond to each time shown in FIG.

As mentioned earlier, to the clock terminal CK of the unit shift register SR _1, it is assumed that the clock signal CLK1 is input. Further, as shown in FIG. 4, the active period of the first start pulse SP1 input from the outside overlaps with the active period of the clock signal CLK2, and the active period of the second start pulse SP2 generated by the start pulse generating circuit 32 is It is assumed that it overlaps with the active period of the clock signal CLK3. That is, the first start pulse SP1 is activated prior to two horizontal periods of the output signal G ₁ of the unit shift register SR _1, the first start pulse SP1 is activated before one horizontal period of the output signal G _1.

  Assuming that the start pulse generation circuit 32 is the circuit of FIG. 3 and that the H level of the clock signals CLK1 to CLK3 and the first start pulse SP1 is equal to the high-side power supply potential VDD1, the H level of the second start pulse SP2 is also The potentials are equal to VDD1. Again, this level is represented as VDD (ie, VDD = VDD1).

First, as an initial state of the unit shift register SR ₁ at time t ₁ , it is assumed that the nodes N1 and N3 are at the L level (VSS) and the node N2 is at the H level (VDD2-Vth) (hereinafter, this state is referred to as “reset”). State "). The clock terminal CK (clock signal CLK1), the reset terminal RST (next-stage output signal G ₂ ), the first input terminal IN1 (first start pulse SP1), and the second input terminal IN2 (second start pulse SP2) are Both are assumed to be at the L level. In the reset state, the transistor Q1 is off (cut-off state) and the transistor Q2 is on (conduction state), so that the output terminal OUT (output signal G ₁ ) is L regardless of the level of the clock terminal CK (clock signal CLK1). Keep on level. That is, the gate lines GL ₁ to the unit shift register SR ₁ is connected in the inactive state (non-selected state).

From this state, when the first start pulse SP1 at time t ₂ becomes the H level, the transistor Q8 is turned on so that the first input terminal IN1 of the unit shift register SR ₁ becomes the H level. At this time, since the node N2 is at the L level, the transistor Q9 is also turned on. However, since the transistor Q8 is set to have sufficiently higher driving capability than the transistor Q9, the on-resistance of the transistor Q8 is sufficiently lower than the on-resistance of the transistor Q9. The node N3 is charged by the charge supplied through the transistor Q8, and its level rises. That is, the transistor Q8 functions as a charging circuit that charges the gate (node N3) of the transistor Q3 based on a signal input to the first input terminal IN1.

  When the level of the node N3 rises, the transistor Q7 starts to conduct and the level of the node N2 falls. As a result, the resistance value of the transistor Q9 increases, and the level of the node N3 rapidly increases. In response, transistor Q7 is fully turned on. As a result, the node N2 becomes L level (VSS), the transistor Q9 is turned off, and the node N3 becomes H level.

  In order to raise the level of the node N3, it is necessary to charge the gate-channel capacitance (gate capacitance) of the transistor Q3 and the capacitance element C2 connected to the node N3, and these capacitance values are the gate capacitance of the transistor Q1 in the output stage. Since the capacity element C1 is as small as about 1/5 to 1/10, the node N3 can be charged at high speed. Therefore, although the transistor Q8 operates in the source follower mode, which is not good at high speed charging, the level of the node N3 rises to the theoretical value at high speed. That is, the level V3a of the node N3 after being charged by the transistor Q8 is expressed by the following equation (1).

V3a = VDD−Vth (1)
When node N3 becomes H level, transistor Q3 is turned on. At this time, since the node N2 is at L level, the transistor Q4 is off. Therefore, the node N1 is charged through the transistor Q3, and its level rises.

  In order to increase the level of the node N1, it is necessary to charge the gate capacitances of the capacitive element C1 and the transistor Q1, but since the capacitance values thereof are relatively large as described above, it is difficult to charge the node N1 at high speed. is there. Further, since the transistor Q3 operates in the source follower mode, it is difficult to raise the level of the node N1 to the theoretical value (VDD−2 × Vth) in a short time. Therefore, if the pulse width of the first start pulse SP1 is not sufficiently wide, the level of the node N1 at this time rises only to a certain level smaller than the theoretical value.

When the first start pulse SP1 returns to the L level at time t ₃ , the transistor Q8 is turned off. Thereafter, the nodes N1 and N3 are in a floating state, and the transistors Q7 and Q9 function as flip-flops. The levels of N1 and N3 are maintained.

When the At time t ₄ the second start pulse SP2 becomes H level, the second input terminal IN2 of the unit shift register SR becomes H level (VDD), the node N3 is boosted by capacitive coupling through the capacitance element C2 . That is, the capacitive element C2 functions as a booster circuit that boosts the charged node N3 based on a signal input to the second input terminal IN2.

  The level of the node N3 after boosting by the capacitive element C2 rises by the amplitude VDD of the second start pulse SP2 with respect to before boosting. That is, the level V3b of the node N3 at this time is expressed by the following equation (2).

V3b = 2 × VDD−Vth (2)
In this state, since the voltage between the gate (node N3) and the source (node N1) of the transistor Q3 is sufficiently high, the transistor Q3 charges the node N1 not in the source follower mode but in the non-saturated region (non-saturated operation). To do. Therefore, the node N1 is charged at high speed and becomes H level, and the node N1 level reaches VDD (= VDD1) without loss of the threshold voltage Vth. In such a state where the nodes N1 and N3 are at the H level and the node N2 is at the L level (hereinafter, this state is referred to as “set state”), the transistor Q1 is turned on and the transistor Q2 is turned off.

If then the time t ₅ in the second start pulse SP2 is returned to L level, the second input terminal IN2 becomes L level, the level is lowered to follow that of node N3, returning to the step-up prior to VDD-Vth. At this time, since the level of the node N1 is VDD (= VDD1), the transistor Q3 is turned off. However, since the node N1 is in a floating state, the level of the node N1 is maintained at VDD after that (the set state is also maintained). )

The unit shift register SR ₁ becomes the set state, the transistor Q1 is on, transistor Q2 is off, the clock signal CLK1 of the clock terminal CK becomes H level at time t _6, the output terminal OUT (output signal G ₁ ) Level rises. At this time, the level of the node N1 is boosted by a specific voltage by capacitive coupling via the capacitive element C1 and the gate capacitance of the transistor Q1 (therefore, the node N1 may be referred to as a “boost node”).

Compared to the sum of the capacitance value of the gate capacitance and the capacitance element C1 of the transistor Q1, the parasitic capacitance of the node N1 is assumed to sufficiently small, the level of the node N1 when the boosted in response to increased levels of the output signals G ₁ Becomes 2 × VDD. Thus the gate-source voltage of the transistor Q1 is kept large, the level of the output signal G ₁ rises to a high speed following the clock signal CLK1. At this time, the transistor Q1 performs a non-saturated operation, so that there is no loss corresponding to the threshold voltage Vth. Therefore, the H level of the output signal G ₁ becomes the same VDD as the H level of the clock signal CLK 1.

The output signal G _{1 that} has become H level at time t ₆ maintains the H level and activates the gate line GL ₁ (sets it to the selected state) while the clock signal CLK 1 is at H level. Thereafter, when the clock signal CLK1 returns to L level at time t _7, even if the output signal G ₁ becomes L level by following, gate lines (return to the non-selected state) is deactivated. At this time, the level of the node N1 also drops to VDD before being boosted.

Then, at time t ₈ the clock signal CLK2 becomes H level, the next-stage output signal G ₂ (second stage) becomes H level, it is input to the reset terminal RST of the unit shift register SR ₁ Transistor Q5 is turned on. As a result, the level of the node N3 falls and the transistor Q7 is turned off, so that the node N2 becomes H level. Responsively, transistors Q4 and Q9 are turned on, and nodes N1 and N3 are at L level. As a result, the unit shift register SR ₁ returns to the reset state, and the transistor Q1 is turned off and the transistor Q2 is turned on.

The reset state of the unit shift register SR ₁ is maintained until the first and second start pulses SP1 and SP2 are activated in the next frame period.

  As described above, according to the unit shift register SR of FIG. 5, since the transistor Q3 operates in the non-saturation region when the node N1 is charged, the transistor Q3 can charge the node N1 to the potential VDD at high speed. . Therefore, even when the pulse width of the clock signal is narrowed, the gate-source voltage of the transistor Q1 when the output signal G is activated can be maintained large, and a decrease in the driving capability of the unit shift register SR is suppressed. Therefore, the speed of the shift register circuit can be increased, and this can contribute to an increase in resolution of a display device using the gate line driving circuit constituted thereby.

  The absolute value (2 × VDD−Vth) of the gate (node N1A) of the transistor Q1A when the start pulse generating circuit 32 activates the second start pulse SP2 is the gate of the transistor Q1 of the unit shift register SR. Although it does not become as large as the absolute value (2 × VDD) of the potential of (node N1), there is no problem because the start pulse generation circuit 32 does not require high driving capability as described above.

To summarize the operation of the unit shift register SR ₁ of the above, the unit shift register SR _1, the period in which the signal of the first input terminal IN1 and the second input terminal IN2 is not activated is in the reset state, during which the transistor Q1 is turned off Since the transistor Q2 is on, the output terminal OUT is maintained at the low impedance L level (VSS). When a pulse signal is input in the order of the first input terminal IN1 and the second input terminal IN2, the set state is entered. The transistor Q1 is turned on in the set state, the transistor Q2 is off, while the clock signal CLK1 of the clock terminal CK is at the H level, the output signal G ₁ is to activate the gate lines GL ₁ becomes H level. Thereafter the next-stage output signal G ₂ input to the reset terminal RST returns to the reset state upon activation.

In the unit shift register SR ₂ of the second stage, the second start pulse SP2 is input to the first input terminal IN1, the second input terminal IN2 output signal G ₁ of the unit shift register SR ₁ of the first stage Is entered. As a result, the unit shift register SR ₂ performs the same operation as described above with a delay of one horizontal period with respect to the unit shift register SR ₁ . Therefore, the output signal G ₂ of the unit shift register SR ₂ will be activated with a delay of one horizontal period to the output signal G ₁ of the unit shift register SR _1.

In the third and subsequent unit shift registers SR _n , the output signal G _n−2 of the previous two stages is input to the first input terminal IN1, and the output of the immediately preceding stage is input to the second input terminal IN2. A signal G _n-1 is input. As a result, the output signal G _n of each unit shift register SR is activated with a delay of one horizontal period with respect to the output signal G _{n−1 at the} immediately preceding stage.

Accordingly, in a plurality of unit shift registers SR gate line driver circuit connected in cascade 30 (FIG. 2), as shown in FIG. 7, the first and second start pulses SP1 to the unit shift register SR ₁ of the first stage , SP2 are activated, and the output signals G ₁ , G ₂ , G ₃ ... Are sequentially activated at a timing synchronized with the clock signals CLK1, CLK2, CLK3 (that is, every one horizontal period). Thereby, the gate line driving circuit 30 can sequentially drive the gate lines GL ₁ , GL ₂ , GL ₃ ... In a predetermined scanning cycle.

  As described above, the gate line driving circuit 30 which is a shift register according to the present invention receives the first start pulse SP1 input from the outside, and is activated with a delay of one horizontal period with respect to the first start pulse SP2. A start pulse generation circuit 32 is provided. Therefore, even when using the unit shift register SR that requires two input signals having different phases as shown in FIG. 5, only one start pulse needs to be input from the outside. Therefore, the cost of the apparatus can be reduced as compared with the prior art.

<Embodiment 2>
In the first embodiment, the present invention is applied to the gate line driving circuit 30 including a unit shift register that is driven using two input signals having different phases. In the second embodiment, the present invention is applied to the gate line driving circuit 30 including a unit shift register driven using three input signals having different phases.

FIG. 8 is a diagram showing a configuration of the gate line driving circuit 30 according to the second embodiment. The gate line driving circuit 30 is a multistage shift register including first and second start pulse generating circuits 321 and 322 and a plurality of unit shift registers SR ₁ , SR ₂ , SR ₃ , SR ₄ . including.

The configuration of the unit shift register SR of the present embodiment is shown in FIG. In the gate line driving circuit 30, the unit shift registers SR ₁ , SR ₂ ,... Connected in cascade are basically all of the same configuration, and therefore, in FIG. _n is shown. The unit shift register SR is the same as the unit shift register disclosed in FIG. The unit shift register SR operates based on three input signals having different phases, and a multi-stage shift register formed by cascading a plurality of the input signals is driven using four-phase clock signals CLK1 to CLK4. Is done.

  In the unit shift register SR of FIG. 5, the transistor Q3 is non-saturated by providing a charging circuit (transistor Q8) and a booster circuit (capacitor C2) at the gate (node N3) of the transistor Q3 for charging the node N1. Made it work. The unit shift register SR of FIG. 9 is obtained by applying the technique to the gate of the transistor Q8 that is a charging circuit of the node N3. That is, by providing a similar charging circuit and booster circuit at the gate of the transistor Q8, the transistor Q8 is also operated in a non-saturated manner.

  As shown in FIG. 9, the unit shift register SR has first, second, and third input terminals IN1, IN2, IN3. As in FIG. 5, the output stage of the unit shift register SR includes a transistor Q1 (first transistor) connected between the output terminal OUT and the clock terminal CK, and between the output terminal OUT and the first power supply terminal S1. The transistor Q2 is connected.

  A capacitive element C1 is connected between the output terminal OUT and the gate (node N1) of the transistor Q1 to enhance the boosting effect of the node N1 due to the level increase of the output terminal OUT. The capacitor C1 can also be replaced when the gate-channel capacitance of the transistor Q1 is sufficiently large, and may be omitted in such a case.

  A transistor Q3 (second transistor) for supplying the potential of the second power supply terminal S2 to the node N1 is connected between the node N1 and the second power supply terminal S2. A transistor Q4 is connected between the node N1 and the first power supply terminal S1. The gate of the transistor Q4 is connected to the gate (node N2) of the transistor Q2.

  A transistor Q8 that functions as a charging circuit for the node N3 is connected between the gate (node N3) of the transistor Q3 and the second power supply terminal S2. As described above, in the unit shift register SR of FIG. 9, a charging circuit and a booster circuit are provided at the gate (node N4) of the transistor Q8. That is, as a charging circuit for the node N4, a transistor Q11 having a gate connected to the first input terminal IN1 and connected between the node N4 and the second power supply terminal S2 is provided. Further, a capacitive element C2 connected between the node N4 and the second input terminal IN2 is provided as a booster circuit (first booster circuit) at the node N4. The drain of the transistor Q11 may be connected to the first input terminal IN1 instead of the second power supply terminal S2.

  Further, the unit shift register SR includes a capacitive element C3 connected between the node N3 and the third input terminal IN3. The capacitive element C3 functions as a booster circuit (second booster circuit) at the node N3.

  A transistor Q9 having a gate connected to the node N2 is connected between the node N3 and the first power supply terminal S1. Between the node N4 and the first power supply terminal S1, a transistor Q12 whose gate is connected to the node N2 and a transistor Q5 whose gate is connected to the reset terminal RST are connected. The inverter (pull-down drive circuit) composed of the transistors Q6 and Q7 is connected so that the node N4 is an input end and the node N2 is an output end.

  The first and second start pulse generation circuits 321 and 322 may be the same as the start pulse generation circuit 32 of the first embodiment. FIG. 10 is a diagram showing a specific circuit configuration of the first and second start pulse generation circuits 321 and 322 of the present embodiment. Here, as shown in the figure, the first and second start pulse generation circuits 321 and 322 have the same configuration as that shown in FIG.

  The first start pulse generating circuit 321 receives a start pulse SP1 input from the outside of the gate line driving circuit 30 at its input terminal INA, and generates a second start pulse SP2 that is activated after the first start pulse SP1. Then, it is output from the output terminal OUTA. The second start pulse SP2 generated by the first start pulse generation circuit 321 is input to the input terminal INA of the second start pulse generation circuit 322.

  The second start pulse generation circuit 322 receives the second start pulse SP2 at its input terminal INA, generates a third start pulse SP3 that is activated later than the second start pulse SP2, and outputs it from the output terminal OUTA. Output.

  Therefore, in the present embodiment, the first, second and third start pulses SP1, SP2 and SP3 are set to the H level (active level) in this order at the timing corresponding to the head of each frame period of the image signal. That is, these first to third start pulses SP1 to SP3 are the same as the start pulses SP1 to SP3 used in the shift register of FIG. 7 of Patent Document 1 (signal waveform diagram of FIG. 8 of Patent Document 1). reference).

  As shown in FIG. 8, the gate line driving circuit 30 of this embodiment is driven by four-phase clock signals CLK1 to CLK4 having different phases. The clock signals CLK1 to CLK4 are controlled to be repeatedly activated in the order of CLK1, CLK2, CLK3, and CLK4.

In the present embodiment, the output signal G ₁ of the first stage unit shift register SR ₁ is set to be activated when the clock signal CLK ₁ is activated. In this case, the clock signal CLK1 is supplied to the [4k-3] stage unit shift registers SR ₁ , SR ₅ , SR ₉ ..., And the clock signal CLK2 is the [4k-2] stage unit shift registers SR ₂ , SR. ₆ , SR ₁₀ ..., The clock signal CLK 3 is supplied to the [4k−1] stage unit shift registers SR ₃ , SR ₇ , SR ₁₁ ..., And the clock signal CLK 4 is the [4k] stage unit shift register. SR ₄ , SR ₈ , SR ₁₂ ... (K is a natural number).

On the other hand, as shown in FIG. 10, a clock signal CLK4 that is activated immediately before the clock signal CLK1 is supplied to the clock terminal CKA of the second start pulse generation circuit 322, and a clock is supplied to the clock terminal CKA of the first start pulse generation circuit 321. A clock signal CLK3 that is activated immediately before the signal CLK4 is supplied. The active period of the first start pulse SP1, which is a single pulse, is controlled so as to overlap the active period of the clock signal CLK2 that is activated immediately before the clock signal CLK3. As a result, the output signal G ₁ of the unit shift register SR _1, the first start pulse SP1 is activated prior third horizontal period, the second start pulse SP2 is activated before two horizontal periods, the third start pulse SP3 Is activated one horizontal period before.

  Note that the clock signal CLK4 (or the clock signal CLK1) whose active period does not overlap with the first start pulse SP1 and the second start pulse SP2 is input to the reset terminal RSTA of the first start pulse generation circuit 321. The reset signal RSTA of the second start pulse generation circuit 322 receives the clock signal CLK1 (or the clock signal CLK2) whose active period does not overlap with the second start pulse SP2 and the third start pulse SP3.

As shown in FIG. 8, the unit first shift register SR ₁ of the first stage (first stage), the second and third input terminals IN1, IN2, IN3, first, second and third, respectively Start pulses SP1, SP2 and SP3 are input. In the unit shift register SR ₂ of the second stage, the second start pulse SP2 is input to the first input terminal IN1, the third start pulse SP3 is input to the second input terminal IN2, a third input terminal IN3 output signals G ₁ of the first stage is input. In the unit shift register SR ₃ of the third stage, a third start pulse SP3 is input to the first input terminal IN1, the output signal G ₁ of the first stage is input to the second input terminal IN2, a third input output signals G ₂ of the second stage is inputted to the terminal IN3.

In the unit shift register SR _n in the fourth and subsequent stages, the first input terminal IN1 receives the output signal G _{n-3 of the} previous three stages, and the second input terminal IN2 outputs the output signal of the previous two stages. G _n−2 is input, and the output signal G _n−1 of the immediately preceding stage is input to the third input terminal IN3.

In the unit shift register SR _n of FIG. 9, the node N4 (the gate of the transistor Q8) is charged to the level of VDD−Vth by the output signal G _{n−3 of the} three previous stages input to the first input terminal IN1. Thereby, the transistor Q8 is turned on. At this time, the level of the node N3 rises only to VDD-2 × Vth. However, after that, the node N4 is boosted to a level of 2 × VDD−Vth by the output signal G _{n−2 of the} previous stage input to the third input terminal IN3. As a result, the transistor Q8 is desaturated, and the node N3 is charged to VDD1 (= VDD) level at high speed. Therefore, when the output signal G _{n-1 of the} immediately preceding stage input to the first input terminal IN1 becomes H level (VDD), the level of the node N3 reaches 2 × VDD level by capacitive coupling through the capacitive element C2. The node N1 is charged (precharged) to the VDD level at high speed through the transistor Q3.

  As described above, according to the unit shift register SR of FIG. 9, the transistor Q8 is desaturated by the functions of the transistor Q11 (charging circuit) and the capacitive element C3 (first boosting circuit), so that the gate of the transistor Q3 (node N3) ) Can be boosted to a level (2 × VDD) higher than the unit shift register of FIG. 5 by the threshold voltage Vth. Therefore, it becomes possible to charge node N1 at higher speed. Therefore, even when the pulse width of the clock signal is further narrowed, a decrease in the driving capability of the transistor Q1 is suppressed. Therefore, the speed of the shift register circuit can be increased, and this can contribute to an increase in resolution of a display device using the gate line driving circuit constituted thereby.

  The specific operation of the unit shift register SR in FIG. 9 is performed except that charging and boosting of the node N3 are performed according to three signals input to the first to third input terminals IN1 to IN3. It is almost the same as FIG. Therefore, the operation when a plurality of unit shift registers SR of FIG. 9 are connected in cascade to form a gate line driving circuit is as shown in the timing chart of FIG.

That is, activation of the first to third start pulses SP1 to SP3 is triggered, and then the output signals G ₁ , G ₂ , G ₃ ... Are synchronized with the clock signals CLK 1 to CLK 4 (every horizontal period). It is activated sequentially. Thereby, the gate line driving circuit 30 can sequentially drive the gate lines GL ₁ , GL ₂ , GL ₃ ... With a predetermined scanning cycle.

  As described above, the gate line driving circuit 30 which is a shift register according to the present invention receives the first start pulse SP1 input from the outside, and is activated with a delay of one horizontal period with respect to the first start pulse SP2. And first and second start pulse generation circuits 321 and 322 for generating a third start pulse SP3 that is activated with a delay of two horizontal periods. Therefore, even when the unit shift register SR that requires three input signals having different phases as shown in FIG. 9 is used, only one start pulse needs to be input from the outside. Therefore, the cost of the apparatus can be reduced as compared with the prior art.

In the above description, the first start pulse SP1 has been set to activate only before 3 horizontal periods of the output signal G ₁ of the first stage, 4 the output signal G ₁ of the first stage You may set so that it may activate only a horizontal period. That is, as in the above example, when the output signal G ₁ of the first stage unit shift register SR ₁ is activated when the clock signal CLK ₁ is activated, the first start pulse SP 1 is activated. It may be a single pulse whose period overlaps with the active period of the clock signal CLK1. In that case, the clock signal CLK4 is input to the reset terminal RSTA of the first start pulse generation circuit 321.

<Embodiment 3>
FIG. 12 is a block diagram showing a configuration of the gate line driving circuit 30 according to the third embodiment of the present invention. The gate line driving circuit 30 is composed of a shift register (bidirectional shift register) capable of switching the signal shift direction. That is, the gate line driving circuit 30 is formed by cascading m unit shift registers SR ₁ , SR ₂ , SR ₃ ,..., SR _m (bidirectional unit shift registers) capable of switching the signal shift direction. Yes.

The voltage signal generator 37 generates a first voltage signal Vn and a second voltage signal Vr that determine the shift direction of the signal in the unit shift register. When the voltage signal generator 37 shifts the signal in the direction from the front stage to the rear stage (in the order of the unit shift registers SR ₁ , SR ₂ , SR ₃ ...) (This direction is defined as “forward direction”), The 1 voltage signal Vn is set to the H level, and the second voltage signal Vr is set to the L level. Conversely, when the signal is shifted in the direction from the rear stage to the front stage (in the order of the unit shift registers SR _m , SR _m−1 , SR _{m− 2} ...) (This direction is defined as “reverse direction”), the second The voltage signal Vr is set to H level and the first voltage signal Vn is set to L level.

  The clock signal generator 31 generates three-phase clock signals CLK1 to CLK3 having different phases. The clock signal generator 31 according to the present embodiment activates the clock signals CLK1 to CLK3. The (phase relationship) can be changed according to the signal shift direction by changing the connection of the switch, program, or wiring. Specifically, in the case of forward shift, activation is performed in the order of CLK1, CLK2, CLK3, CLK1,..., And in the case of reverse shift, activation is performed in the order of CLK3, CLK2, CLK1, CLK3,.

  The exchange of the order in which the clock signals CLK1, CLK2, and CLK3 are activated by the connection of the wiring is effective when the shift direction is fixed in one direction before the display device is manufactured. Further, the exchange by the switch or the program is effective when the shift direction is fixed in one direction after the display device is manufactured, or when the shift direction can be changed during use of the display device.

Each unit shift register of this embodiment includes a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a fourth input terminal IN4, an output terminal OUT, a clock terminal CK, and a first voltage signal input terminal T1. And a second voltage signal input terminal T2. As shown in FIG. 12, a predetermined one of the clock signals CLK1, CLK2, and CLK3 output from the clock signal generator 31 is supplied to the clock terminal CK of each unit shift register SR. Specifically, the clock signal CLK1 is supplied to the [3k-2] stage unit shift register circuits SR ₁ , SR ₄ , SR ₇ ..., And the clock signal CLK2 is the [3k-1] stage unit shift register SR. ₂ , SR ₅ , SR ₈ ... And the clock signal CLK ₃ is supplied to unit shift registers SR ₃ , SR ₆ , SR ₉ ... In the [3k] stage (k is a natural number).

Since the number of scanning lines of a normal display device is not a multiple of 3, the clock signal supplied to the last clock terminal CK is determined by the number of scanning lines of the display device in a shift register using a three-phase clock signal. In Figure 12, the clock terminal CK of the unit shift register SR _m of the m-th stage is the last stage (m-th stage), the clock signal CLK2 is shown an example to be supplied.

Forward start pulse generation circuit 33 receives the output signal G ₁ of the gate line driving circuit forward input from an external 30 first start pulse SPN1 (external forward start pulse) and the leading stage of the unit shift register SR ₁ The second forward start pulse SPn2 is output. The forward first start pulse SPn1 is a single pulse that is activated for approximately one horizontal period at the timing corresponding to the beginning of each frame period of the image signal during forward shift, and the timing at which each frame period ends during reverse shift. Thus, it becomes a single pulse that is activated for approximately one horizontal period.

The forward start pulse generation circuit 33 activates the forward second start pulse SPn2 for one horizontal period one horizontal period after the activation of the forward first start pulse SPn1 during forward shift, and the unit during reverse shift. operating the output signal G ₁ of the shift register SR ₁ after one horizontal period the forward second start pulse SPn2 to activate one horizontal period.

That is, the forward second start pulse SPn2 is a single pulse in which the forward first start pulse SPn1 is temporally shifted (delayed in phase) by one horizontal period during forward shift, and the unit shift register SR during reverse shift. _{The single} output signal G ₁ is a single pulse obtained by temporally shifting (delaying the phase) by one horizontal period. Therefore, as the forward start pulse generation circuit 33, a one-stage bidirectional shift register circuit can be used (a specific configuration of the forward start pulse generation circuit 33 will be described later).

Reverse start pulse generation circuit 34 receives the output signal G _m of the unit shift register in the reverse direction the first start pulse SPR1 (external reverse start pulse) and the last stage is input from the outside of the gate line drive circuit 30 SR _m The reverse second start pulse SPr2 is output. The reverse first start pulse SPr1 is a single pulse that is activated for approximately one horizontal period at the timing corresponding to the head of each frame period of the image signal during the backward shift, and the timing at which each frame period ends during the forward shift. Thus, it becomes a single pulse that is activated for approximately one horizontal period.

The reverse start pulse generation circuit 34 activates the reverse second start pulse SPr2 for one horizontal period one horizontal period after the activation of the reverse first start pulse SPr1 during the reverse shift, and the unit during the forward shift. operating the shift register SR reverse second start pulse SPr2 from the output signal G _m after one horizontal period of _m so as to only activate one horizontal period.

That is, the backward second start pulse SPr2 is a single pulse obtained by temporally shifting the backward first start pulse SPr1 by one horizontal period (delaying the phase) during the backward shift, and during the forward shift, the unit shift register SR. the output signal G _m of _m was only temporally shifted one horizontal period becomes (delayed phase) single pulse. Therefore, a single-stage bidirectional shift register circuit can also be used as the reverse direction start pulse generation circuit 34 (a specific configuration of the reverse direction start pulse generation circuit 34 will also be described later).

Referring again to FIG. 12, the first and second input terminals IN1, IN2 of the unit shift register SR ₁ of the first stage (first stage), the first forward respectively, and the second start pulse SPN1, SPN2 Is entered. In the second stage unit shift register SR ₂ , the forward second start pulse SPn 2 is input to the first input terminal IN ₁ , and the output signal G of the previous stage unit shift register SR ₁ is input to the second input terminal IN 2. ₁ is entered.

In the unit shift register SR _n of the third and subsequent stages, the first input terminal IN1 is connected to the output terminal OUT of the two preceding unit shift register SR _n-2, a second input terminal IN2 is the shift unit immediately before stage The resistor SR _n-1 is connected to the output terminal OUT.

The last stage the third and fourth input terminals IN3, IN4 of the unit shift register SR _m of (the m-th stage), the first and second start pulse opposite directions SPR1, SPr2 is input. In the unit shift register SR _{m−1 at the} second (m−1) th stage from the end, the reverse second start pulse SPr2 is input to the third input terminal IN3, and the next input terminal IN4 is the next. output signals G _m of the unit shift register SR _m stages is input.

In the unit shift register SR _n before the last three stages, the third input terminal IN3 is connected to the output terminal OUT of the _second stage unit shift register SR _{n + 2} and the fourth input terminal IN4 is the next stage unit. Connected to the output terminal OUT of the shift register SR _{n + 1} .

  The first and second voltage signals Vn and Vr generated by the voltage signal generator 37 are supplied to the first and second voltage signal terminals T1 and T2 of each unit shift register SR, respectively.

  Here, the configuration of the forward start pulse generation circuit 33 according to the third embodiment will be described. FIG. 13 is a circuit diagram of the forward start pulse generation circuit 33. Here, an example in which a one-stage bidirectional shift register circuit is used as the forward start pulse generation circuit 33 is shown.

  The forward start pulse generation circuit 33 includes a forward input terminal INnA, a reverse input terminal INrA, an output terminal OUTA, a clock terminal CKA, first and second voltage signal terminals T1A and T2A, first and second power supply terminals S1, S2 is provided.

The forward input terminal INNA, is input forward first start pulse SPN1, the reverse input terminal INRA, the output signal G ₁ of the unit shift register SR ₁ is input. The forward second start pulse SPn2 is output from the output terminal OUTA. The clock terminal CKA, to the clock signal CLK1 supplied to the clock terminal CK of the unit shift register SR _1, (activated earlier) only the phase advances one horizontal period when the forward shift clock signal CLK3 is supplied . The first and second voltage signal terminals T1A and T2A are supplied with the first and second voltage signals Vn and Vr output from the voltage signal generator 37, respectively.

Active period of the forward first start pulse SPn1 a single pulse, the clock signal supplied to the clock terminal CK of the forward start pulse generation circuit clock signal CLK3 is input to the clock terminal CKA 33 and the unit shift register SR ₁ It is set so that both CLK1 and the active period do not overlap. Here, the active period of the forward first start pulse SPn1 is set to overlap the active period of the clock signal CLK2.

  The low power supply potential VSS is supplied to the first power supply terminal S1, and the high power supply potential VDD1 is supplied to the second power supply terminal S2. Here, for the sake of simplicity, the high-side power supply potential VDD1 level, the clock signals CLK1 to CLK3, the forward first start pulse SPn1, the backward first start pulse SPr1, and the first and second voltage signals Vn and Vr are at the H level. It is assumed that the potentials are all equal, and the value is VDD (VDD = VDD1). The L level potentials of the clock signals CLK1 to CLK3, the forward first start pulse SPn1, the backward first start pulse SPr1, and the first and second voltage signals Vn and Vr are equal to the low-side power supply potential VSS (= 0). Shall.

  As shown in FIG. 13, the forward start pulse generation circuit 33 includes N-type transistors Q1A, Q2A, Q3nA, Q3rA, Q4A, Q6A, Q5nA, Q5rA, Q7A and a capacitive element C1A. The transistor Q1A is connected between the output terminal OUTA and the clock terminal CKA, and supplies the clock signal CLK3 supplied to the clock terminal CKA to the output terminal OUTA. The transistor Q2A is connected between the output terminal OUTA and the first power supply terminal S1, and discharges the output terminal OUTA. A node to which the gate (control electrode) of the transistor Q1A is connected is defined as “node N1A”, and a node to which the gate of the transistor Q2A is connected is defined as “node N2A”.

  A capacitive element C1A is provided between the gate and source of the transistor Q1A (that is, between the output terminal OUTA and the node N1A). The capacitive element C1A is for increasing the boosting effect of the node N1A accompanying the level increase of the output terminal OUTA. However, the capacitor C1A can be replaced if the gate-channel capacitance of the transistor Q1A is sufficiently large, and may be omitted in such a case.

The transistor Q3nA has a gate connected to the forward input terminal INnA, and is connected between the node N1A and the first voltage signal terminal T1A. That is, the transistor Q3nA supplies the potential of the first voltage signal terminal T1A to the node N1A in response to the activation of the forward first start pulse SPn1. The transistor Q3rA has a gate connected to the reverse input terminal INrA, and is connected between the node N1A and the second voltage signal terminal T2A. That transistor Q3rA in response to activation of the output signal G ₁ of the unit shift register SR _1, supplying the potential of the second voltage signal terminal T2A to node N1A.

  The transistor Q4A has a gate connected to the node N2A, and is connected between the node N1A and the first power supply terminal S1. That is, transistor Q4A discharges node N1A when node N2A is at the active level.

  The transistor Q6A has a gate connected to the second power supply terminal S2, and is connected between the second power supply terminal S2 and the node N2A (the transistor Q6A is diode-connected). The transistor Q7A has a gate connected to the node N1A, and is connected between the node N2A and the first power supply terminal S1. The transistor Q7A has an on-resistance set sufficiently lower than that of the transistor Q6A, and the transistors Q6A and Q7A constitute a ratio type inverter having the node N1A as an input end and the node N2A as an output end. In the inverter, the transistor Q6A functions as a load element, and the transistor Q7A functions as a drive element.

  The transistor Q5nA has a gate connected to the forward input terminal INnA, and is connected between the node N2A and the second voltage signal terminal T2A. The transistor Q5nA charges the node N1A by the transistor Q3nA by discharging the node N2A to the L level and turning off the transistor Q4A when the forward first start pulse SPn1 is activated during the forward shift. To work. Therefore, the on-resistance of the transistor Q5nA is set to be sufficiently smaller than that of the transistor Q6A. Note that the transistor Q5nA is not necessarily provided as long as the on-resistance of the transistor Q3nA is sufficiently small and the node N1A can be charged at high speed without the transistor Q5nA.

The transistor Q5rA has a gate connected to the reverse input terminal INrA, and is connected between the first voltage signal terminal T1A and the node N2A. Transistor Q5rA, at the time of backward shift, the output signal G ₁ of the unit shift register SR ₁ in response to activation, by turning off the transistor Q4A the L level to discharge node N2A, nodes N1A by transistor Q3rA It works to speed up charging. Therefore, the on-resistance of the transistor Q5rA is also set sufficiently smaller than that of the transistor Q6A. Note that the transistor Q5rA is not necessarily provided as long as the on-resistance of the transistor Q3rA is sufficiently small and the node N1A can be charged at high speed without the transistor Q5rA.

  Next, the configuration of the reverse start pulse generation circuit 34 according to the third embodiment will be described. FIG. 14 is a circuit diagram showing a configuration example of the reverse start pulse generation circuit 34. As the reverse start pulse generation circuit 34, a one-stage bidirectional shift register is used. As shown in the figure, the reverse start pulse generation circuit 34 has the same configuration as the forward start pulse generation circuit 33 of FIG.

The forward input terminal INnB reverse start pulse generation circuit 34, is inputted an output signal G _m of the unit shift register SR _m, the reverse input terminal INRB, reverse first start pulse SPr1 is input. The reverse second start pulse SPr2 is output from the output terminal OUTB.

The clock terminal CKB, to the clock signal CLK2 supplied to the clock terminal CK of the unit shift register SR _m, 1 horizontal period by the phase advances to the reverse shift (activate first) clock signal CLK3 is supplied . The first and second voltage signal terminals T1B and T2B are supplied with the first and second voltage signals Vn and Vr, respectively.

Active period of reverse first start pulse SPr1 a single pulse, the clock signal supplied to the clock terminal CK of the clock signal CLK3 and the unit shift register SR _m is input to the clock terminal CKB of the reverse start pulse generation circuit 34 It is set so that both CLK2 and the active period do not overlap. Here, the active period of the reverse first start pulse SPr1 is set to overlap the active period of the clock signal CLK1.

  As shown in FIG. 14, the reverse start pulse generation circuit 34 includes N-type transistors Q1B, Q2B, Q3nB, Q3rB, Q4B, Q6B, Q5nB, Q5rB, Q7B and a capacitive element C1B.

  The transistor Q1B is connected between the output terminal OUTB and the clock terminal CKB, and the transistor Q2B is connected between the output terminal OUTB and the first power supply terminal S1. A node to which the gate (control electrode) of the transistor Q1B is connected is defined as “node N1B”, and a node to which the gate of the transistor Q2B is connected is defined as “node N2B”.

  A capacitive element C1B (step-up capacitor) is provided between the gate and source of the transistor Q1B. Capacitance element C1B can be replaced when the gate-channel capacitance of transistor Q1B is sufficiently large, and may be omitted in such a case.

  The transistor Q3nB has a gate connected to the forward input terminal INnB, and is connected between the node N1B and the first voltage signal terminal T1B. The transistor Q3rB has a gate connected to the reverse input terminal INrB, and is connected between the node N1B and the second voltage signal terminal T2B. The transistor Q4B has a gate connected to the node N2B, and is connected between the node N1B and the first power supply terminal S1.

  The transistor Q6B has a gate connected to the second power supply terminal S2, and is connected between the second power supply terminal S2 and the node N2B. The transistor Q7B is set to have a sufficiently lower on-resistance than the transistor Q6B, has a gate connected to the node N1B, and is connected between the node N2B and the first power supply terminal S1. The transistors Q6B and Q7B constitute a ratio type inverter having the node N1B as an input end and the node N2B as an output end.

  The transistor Q5nB has a gate connected to the forward input terminal INnB, and is connected between the node N2B and the second voltage signal terminal T2B. Transistor Q5nB is set to have a sufficiently smaller on-resistance than transistor Q6B. If the on-resistance of the transistor Q3nB is sufficiently small and the node N1B can be charged at high speed during the forward shift without providing the transistor Q5nB, it is not necessary to provide the transistor Q5nB.

  The transistor Q5rB has a gate connected to the reverse input terminal INrB, and is connected between the first voltage signal terminal T1B and the node N2B. The on-resistance of the transistor Q5rB is also set sufficiently smaller than that of the transistor Q6B. If the on-resistance of the transistor Q3rB is sufficiently small and the node N1B can be charged at high speed during reverse shift without providing the transistor Q5rB, the transistor Q5rB need not be provided.

  The operations of the forward start pulse generation circuit 33 in FIG. 13 and the reverse start pulse generation circuit 34 in FIG. 14 will be described below.

  First, the operation of the forward start pulse generation circuit 33 during forward shift will be described. FIG. 15 is a signal waveform diagram for explaining the operation. At the time of forward shift, the first voltage signal Vn is set to H level and the second voltage signal Vr is set to L level, so that the potential of the first voltage signal terminal T1A of the forward start pulse generation circuit 33 is VDD and the second voltage The potential of the signal terminal T2A is VSS. The clock signals CLK1 to CLK3 are activated in the order of CLK1, CLK2, CLK3, CLK1,.

Time t ₀ in FIG. 15 is immediately before the forward first start pulse SPn1 is activated during the forward shift. In this embodiment, since the active period of the forward first start pulse SPn1 is set to overlap the active period of the clock signal CLK2, at time t _0, the clock signal CLK1 to activated before clock signal CLK2 Is at the H level. At this time, the clock signals CLK2 and CLK3 are at the L level.

Further, in the forward start pulse generation circuit 33 at time t ₀ , it is assumed that the node N1A is at the L level (VSS) and the node N2A is at the H level (VDD−Vth). Therefore, the transistor Q1A is off, the transistor Q2A is on, and the forward second start pulse SPn2 is at the L level. The gate line driving circuit 30, so that starts operating in response to the activation of the forward first start pulse SPN1, the output signal G ₁ of the unit shift register SR ₁ of the leading stage at this time is at the L level.

At time t ₁ , the clock signal CLK 1 becomes L level, but at this time, there is no level change of each node in the forward start pulse generation circuit 33.

Then in time t _2, the a forward first start pulse SPn1 the clock signal CLK2 becomes H level, the transistors Q5nA, Q3nA is turned on. Therefore, the node N2A is discharged and becomes L level, and the node N1A is charged and becomes H level. Since the transistor Q4A is turned off when the node N2A becomes L level, the H level potential of the node N1A becomes VDD-Vth. As a result, the transistor Q1A is turned on and the transistor Q2A is turned off. At this time, since the clock signal CLK3 is at L level, the output terminal OUTA remains at L level. At this time, the transistor Q7A is also on.

At time t _3, a forward first start pulse SPn1 the clock signal CLK2 becomes L level, the transistor Q5nA is becomes off, the node N1A is maintained at H level of the high-impedance state (floating state). At this time, the transistor Q5nA is also turned off. However, since the node N1A is maintained at the H level and the transistor Q7A is maintained on, the node N2A is maintained at the L level with low impedance.

When the clock signal CLK3 becomes H level at time t _4, the elevated levels is transmitted to the output terminal OUTA through the transistor Q1A in the non-saturation region on state, also increases the level of the output terminal OUTA. As a result, the forward second start pulse SPn2 becomes H level.

  This potential change of the output terminal OUTA raises the level of the node N1A due to the coupling through the capacitive element C1A. By the boosting action of the node N1A, the transistor Q1A can continue the operation in the non-saturation region even when the level of the output terminal OUTA rises, and raises the output terminal OUTA to the same potential VDD as the H level of the clock signal CLK3. Can do. If the parasitic capacitance of the node N1A is ignored, the level of the node N1A after the boosting is 2 · VDD−Vth.

The clock signal CLK3 at time t ₅ is becomes the L level, the output terminal OUTA becomes L level is discharged through transistor Q1A (VSS). The coupling via the time capacitive element C1A, also decreases the level of the node N1A, node N1A returns to the same potential VDD-Vth and before being boosted (time t _3).

When the clock signal CLK1 at time t ₆ is H level, the output signal G ₁ of the unit shift register SR ₁ of the leading stage is activated. Accordingly, the transistor Q3rA is turned on, and the node N1A becomes L level. Accordingly, transistor Q7A is turned off, so that node N2A is charged by the current flowing through transistor Q6A. At this time, the transistor Q5rA is also turned on, so that the node N2A is also charged by the transistor Q5rA. Since the transistor Q5rA has a lower on-resistance than the transistor Q6A, the node N2A is mainly charged by the transistor Q5rA.

As a result, the node N2A becomes H level (VDD−Vth), so that the transistors Q2A and Q4A are turned on. Therefore, the node N1A becomes L level (VSS), and the transistor Q1A is turned off. The output terminal OUTA is maintained at the L level (VSS) by the on-state transistor Q2A. As a result, the forward start pulse generation circuit 33 is reset to the state at the time t ₀ described above.

Time t ₇ or later, the transistor Q6A the on state, the node N2A is maintained at H level. Thereby, transistors Q2A and Q4A are kept on, so that node N1A and output terminal OUTA are both kept at the L level. Therefore, the forward second start pulse SPn2 is maintained at the L level with low impedance until the forward first start pulse SPn1 is activated again at the beginning of the next frame period.

  Next, the operation of the forward start pulse generation circuit 33 during reverse shift will be described. At the time of reverse shift, the first voltage signal Vn is set to L level and the second voltage signal Vr is set to H level, and the clock signals CLK1 to CLK3 are activated in the order of CLK3, CLK2, CLK1, CLK3.

During the reverse shift, the potential of the first voltage signal terminal T1 is VSS and the potential of the second voltage signal terminal T2 is VDD. Therefore, the output signal G ₁ of the unit shift register SR ₁ is input to the reverse input terminal INrA is activated, transistor Q5rA discharges the node N2A the transistor Q3rA charges the node N1A. As a result, in the forward start pulse generation circuit 33, the transistor Q1A is turned on and the transistor Q2A is turned off.

In this state, when the clock signal CLK3 becomes H level, the forward second start pulse SPn2 is activated. The output signal G ₁ of the unit shift register SR ₁ becomes H level in synchronization with the clock signal CLK1, and the clock signal CLK3 becomes H level after one horizontal period. Thus, the forward second start pulse SPn2 during reverse shift with respect to the output signal G ₁ of the unit shift register SR ₁ is activated with a delay of one horizontal period.

  Here, at the time of reverse shift, the forward first start pulse SPn1 is activated one horizontal period after the forward second start pulse SPn2 is activated. Therefore, in the forward start pulse generation circuit 33 during reverse shift, after activating the forward second start pulse SPn2, the node N1A is discharged by the transistor Q3nA and the node N2A is charged by the transistor Q5nA.

  Thus, the forward start pulse generation circuit 33 is reset to the state where the transistor Q1A is off and the transistor Q2A is on, and thereafter the forward second start pulse SPn2 is maintained at the L level. That is, the forward first start pulse SPn1 at the time of reverse shift is used as a signal for resetting the forward start pulse generation circuit 33.

As described above, the forward start pulse generation circuit 33 outputs the forward second start pulse SPn2 to the signal (forward first start pulse SPn1) input to the forward input terminal INnA during the forward shift. An operation of activating by delaying the horizontal period is performed. Also when reverse shift, the forward second start pulse SPN2, the operation of activating delayed by 1 horizontal period with respect to signals input to the reverse input terminal INRA (output signal G ₁ of the unit shift register SR ₁₎ Do.

  Next, the operation of the reverse start pulse generation circuit 34 will be described. Since the reverse start pulse generation circuit 34 has the same circuit configuration as the forward start pulse generation circuit 33, the operation thereof is the same as that of the forward start pulse generation circuit 33.

Or reverse start pulse generation circuit 34, at the time of forward shift, reverse second start pulse SPr2, signal input to the forward input terminal INnB (output signal G _m of the unit shift register SR _m of the final stage) In contrast, the activation operation is performed with a delay of one horizontal period. Further, at the time of reverse shift, an operation of activating by delaying by one horizontal period with respect to the reverse second start pulse SPr2 and the signal (reverse first start pulse SPr1) input to the reverse input terminal INrB is performed.

  During the forward shift, the reverse first start pulse SPr1 is activated one horizontal period after the reverse second start pulse SPr2 is activated. Therefore, in the reverse start pulse generation circuit 34 at the time of forward shift, after activating the reverse second start pulse SPr2, the node N1B is discharged by the transistor Q3nB and the node N2B is charged by the transistor Q5nB.

  As a result, the reverse start pulse generation circuit 34 is reset to the state in which the transistor Q1B is off and the transistor Q2B is on, and thereafter maintains the reverse second start pulse SPr2 at the L level. That is, the reverse first start pulse SPr1 during the forward shift is used as a signal for resetting the reverse start pulse generation circuit 34.

On the other hand, at the time of backward shift, reverse start pulse generation circuit 34 is reset by the output signal G _m of the unit shift register SR _m to activate after one horizontal period of the reverse second start pulse SPr2.

Next, the configuration of the unit shift register SR used in the gate line driving circuit 30 in FIG. 12 will be described. FIG. 16 is a circuit diagram of the bidirectional unit shift register SR according to the present embodiment. In the gate line driving circuit 30, the configuration of each unit shift register SR connected in cascade are the same: essentially, here will be described representatively for the n-th stage of the unit shift register SR _n. Also, all the transistors constituting each unit shift register SR are assumed to be N-type TFTs.

The unit shift register SR _n has a low potential in addition to the first to fourth input terminals IN1 to IN4, the output terminal OUT, the clock terminal CK, and the first and second voltage terminals T1 and T2 shown in FIG. The first power supply terminal S1 to which the side power supply potential VSS is supplied and the second power supply terminal S2 to which the high potential side power supply potential VDD1 is supplied.

The output stage of the unit shift register SR _n includes a transistor Q1 connected between the output terminal OUT and the clock terminal CK, and a transistor Q2 connected between the output terminal OUT and the first power supply terminal S1. . That is, the transistor Q1 is a transistor that supplies a clock signal input to the clock terminal CK to the output terminal OUT, and the transistor Q2 supplies the potential of the first power supply terminal S1 to the output terminal OUT, so that the output terminal OUT It is a transistor which discharges. Here, a node to which the gate of the transistor Q1 is connected is defined as “node N1”, and a node to which the gate of the transistor Q2 is connected is defined as “node N2”.

  A capacitive element C1 is provided between the gate and source of the transistor Q1 (that is, between the output terminal OUT and the node N1). The capacitive element C1 is for enhancing the boosting effect of the node N1 accompanying the increase in the level of the output terminal OUT. However, the capacitor C1 can be replaced if the gate-channel capacitance of the transistor Q1 is sufficiently large, and may be omitted in such a case.

  The transistor Q3n connected between the node N1 and the first voltage signal terminal T1 is a transistor for supplying the first voltage signal Vn input to the first voltage signal terminal T1 to the node N1. A node to which the gate of the transistor Q3n is connected is defined as “node N3n”.

  A transistor Q8n whose gate is connected to the first input terminal IN1 is connected between the first voltage signal terminal T1 and the node N3n. The transistor Q8n is a transistor that supplies the first voltage signal Vn to the node N3n based on a signal input to the first input terminal IN1. A capacitive element C2n is connected between the node N3n and the second input terminal IN2. The capacitive element C2n functions as a coupling capacitor between the second input terminal IN2 and the node N3n, and also functions as a stabilizing capacitor for stabilizing the level of the node N3n.

Between the node N3n a first power supply terminal S1 has a gate connected to the output terminal OUT of the unit shift register SR _n, transistor Q5n are connected to discharge the node N3n. Note that the gate of the transistor Q5n may be connected to the fourth input terminal IN4 (the output terminal OUT of the next stage).

The circuit comprising the transistors Q3n, Q5n, Q8n and the capacitive element C2n drives the transistor Q1 that activates (pulls up) the output signal G _n during the selection period of the gate line GL _n during forward shift. It functions as a “pull-up circuit”.

  On the other hand, the transistor Q3r connected between the node N1 and the second voltage signal terminal T2 is a transistor for supplying the second voltage signal Vr input to the second voltage signal terminal T2 to the node N1. A node to which the gate of the transistor Q3r is connected is defined as “node N3r”.

  A transistor Q8r whose gate is connected to the third input terminal IN3 is connected between the second voltage signal terminal T2 and the node N3r. The transistor Q8r is a transistor that supplies the second voltage signal Vr to the node N3r based on a signal input to the third input terminal IN3. A capacitive element C2r is connected between the node N3r and the fourth input terminal IN4. The capacitive element C2r functions as a coupling capacitor between the fourth input terminal IN4 and the node N3r, and also functions as a stabilizing capacitor for stabilizing the level of the node N3r.

Between the node N3R and the first power supply terminal S1 has a gate connected to the output terminal OUT of the unit shift register SR _n, transistor Q5r is connected to discharge the node N3R. The gate of the transistor Q5r may be connected to the second input terminal IN2 (the previous output terminal OUT).

The circuit comprising the transistors Q3r, Q5r, Q8r and the capacitive element C2r drives the transistor Q1 that activates (pulls up) the output signal G _n during the selection period of the gate line GL _n during reverse shift. It functions as a “pull-up circuit”.

The transistor Q6 is connected between the node N2 and the second power supply terminal S2, and its gate is connected to the second power supply terminal S2 like the drain (that is, the transistor Q6 is diode-connected). The transistor Q7 is connected between the node N2 and the first power supply terminal S1, and the gate is connected to the node N1. The on-resistance is set to be sufficiently smaller than that of the transistor Q6, and these transistors Q6 and Q7 constitute a ratio type inverter having the node N1 as an input end and the node N2 as an output end. The inverter functions as a “pull-down circuit” that drives the transistor Q2 for inactivating (pull-down) the output signal G _n during the non-selection period of the gate line GL _n .

Also as can be seen from Figure 16, the unit shift register SR _n is, in addition to the transistor Q2, are provided to the node N2 transistor Q4 whose gate is connected, Q9n, the Q9r. The transistor Q4 is connected between the node N1 and the first power supply terminal S1, the transistor Q9n is connected between the node N3n and the first power supply terminal S1, and the transistor Q9r is connected between the node N3r and the first power supply terminal S1. Connected to. That is, the transistors Q2, Q4, Q9n, and Q9r are turned on while the node N2 is at the H level (that is, the non-selection period). To work.

FIG. 17 is a timing chart showing the operation of the unit shift register SR shown in FIG. Hereinafter, a specific operation of the unit shift register SR will be described with reference to FIG. Here again, the operation of the n-th stage unit shift register SR _n will be described as a representative.

The description will be made assuming that the clock signal CLK1 is input to the clock terminal CK of the unit shift register SR _n (for example, the unit shift registers SR ₁ and SR ₄ in FIG. 12 correspond to this). Further, the clock signals CLK1 to CLK3, the first and second start pulses SPn1 and SPn2 in the forward direction, the first and second start pulses SPr1 and SPr2 in the reverse direction, and the first and second voltage signals Vn and Vr are at the H level. Is equal to the high-side power supply potential VDD1 and its value is VDD (VDD1 = VDD). Further, it is assumed that the threshold voltages of the transistors constituting the unit shift register SR _n are all Vth.

As shown in FIG. 12, the first and second start pulses SPn1 and SPn2 in the forward direction and the first and second start pulses SPr1 and SPr2 in the reverse direction are exceptionally inputted to the first two stages and the last two stages. but the following two preceding output signal G _n-2 to the first input terminal IN1 of the unit shift register SR _n is the second input terminal IN2 is the output signal G _n-1 of the immediately preceding stage, a third input In the following description, it is assumed that the output signal G _{n + 2 at the second} stage is input to the terminal IN3, and the output signal G _{n + 1 at the} next stage is input to the fourth input terminal IN4.

  As described above, the gate of the transistor Q5n may be connected to either the output terminal OUT or the fourth input terminal IN4. Similarly, the gate of the transistor Q5r is either the output terminal OUT or the second input terminal IN2. However, it is assumed here that both of them are connected to the output terminal OUT.

  First, the case where the gate line driving circuit 30 performs the forward shift operation will be described. At this time, the voltage signal generator 32 of FIG. 12 sets the first voltage signal Vn to the H level (VDD) and sets the second voltage signal Vr to the L level (VSS).

Here, as an initial state, it is assumed that the nodes N1, N3n, and N3r are at the L level (VSS). At this time, the node N2 becomes H level (VDD-Vth) by the action of the inverter (pull-down circuit) including the transistors Q6 and Q7 (hereinafter, the state where the node N1 is L level and the node N2 is H level is referred to as “reset state”. "). The levels of the clock terminal CK (clock signal CLK1) and the first to fourth input terminals IN1 to IN4 are all L level. In the reset state, since the transistor Q1 is off and the transistor Q2 is on, the output terminal OUT (output signal G _n ) is kept at the L level regardless of the level of the clock terminal CK (clock signal CLK1). That is, the unit shift register SR _n is in a non-selected state.

From that state, at time t ₁₁ , the output signal G _{n−2 of the} previous stage input to the first input terminal IN 1 (in the case of the first stage, the forward first start pulse SPn 1, in the case of the second stage When the forward second start pulse SPn2) becomes H level, the transistor Q8n is turned on. Since the first voltage signal Vn is at the H level during the forward shift, when the transistor Q8n is turned on, the level of the node N3n increases, and accordingly the transistor Q3n is turned on.

  At this time, since the node N2 is at the H level, the transistors Q4 and Q9n are also turned on. However, the transistors Q8n and Q3n are set to have sufficiently small on-resistances than the transistors Q4 and Q9n, respectively. Each rises. Accordingly, the output of the inverter (pull-down circuit) composed of transistors Q6 and Q7 is inverted, and node N2 becomes L level (≈VSS). Thereby, the transistors Q4 and Q9n are turned off, so that the level rising speed of the nodes N1 and N3n increases. The nodes N1 and N3n are at the H level, but at this time, the potential of the node N3n is VDD-Vth, and the level of the node N1 rises only to VDD-2 × Vth at the maximum (in this way, the node N1 is at the H level) The state where the node N2 is at the L level is referred to as a “set state”).

At time t _12, but the two previous stage output signal G _n-2 is turned off transistor Q8n comes to L level, since the off also the transistor Q4, Q9n, node N1, N3n each of the H level in a floating state Maintained.

Subsequently, at time t ₁₃ , when the output signal G _{n-1 of the} immediately preceding stage input to the second input terminal IN2 (forward second start pulse SPn2 in the first stage) becomes H level, the capacitive element C2n The node N3n is boosted by the coupling via. The capacitance value of the capacitive element C2n is set to be sufficiently larger than the parasitic capacitance value of the node N3n. Therefore, the level of the node N3n is substantially _{equal to} the amplitude of the output signal G _n-1 (VDD−Vth). VDD) and rises to approximately 2 × VDD−Vth.

  As a result, the voltage between the gate (node N3n) and the drain (node N1) of the transistor Q3n satisfies the condition that the transistor Q3n operates in the unsaturated castle. Thus, transistor Q3n operates in the non-saturated region and charges node N1. At this time, the node N1 is charged (precharged) at a high speed and is not accompanied by a voltage loss corresponding to the threshold voltage of the transistor Q3n, so that the level of the node N1 rises to VDD by this charging.

At time t ₁₄ maintains the output signal G _n-1 of the immediately preceding stage becomes L level, the level of the node N3n returns to VDD-Vth, the transistor Q3n is turned off, the level of the node N1 is at VDD in a floating state Is done. The level of the node N3n is also maintained at VDD-Vth.

Then at time t _15, when the clock signal CLK1 becomes H level, through the transistor Q1, that level is transmitted to the output terminal OUT, and the level of the output signal G _n rises. Since the output terminal OUT and the node N1 are coupled via the capacitive element C1 and the channel capacitance of the transistor Q1, the node N1 is boosted as the level of the output terminal OUT increases. As a result, the transistor Q1 operates in the non-saturated region, and the level of the output signal _Gn rises to the same VDD as the H level of the clock signal CLK1. By the step-up operation of the node N1, the level of the node N1 is further increased from the previous value (VDD) by the increase of the output terminal OUT, and finally becomes 2 × VDD.

Since the output signal G _n is input to the gate of the transistor Q5n, the transistor Q5n is turned on at this time, and the node N3n is discharged (pull-down) to the L level (VSS). By keeping the VSS to the gate potential of the transistor Q3n at this point, after time t ₁₇ to the transistor Q3n, it is possible to prevent the through current flowing through Q3r occurs.

As described above, the fourth input terminal IN4 may be connected to the gate of the transistor Q5n (that is, the output signal G _{n + 1} of the next stage may be input to the gate of the transistor Q5n). In this case the above through-current also is substantially suppressed, and the transistor Q3r the transistor Q3n is turned off is turned on, it means that performed substantially simultaneously at time t _17, the instantaneous through current at that time May occur.

At time t _16, the clock signal CLK1 becomes the L level, the output terminal OUT is discharged through the transistor Q1, its level to the L level (VSS) following the level drop of the clock signal CLK1. At this time, contrary to the case at time t ₁₅ , the level of the node N1 is lowered by the level drop of the output terminal OUT by the coupling through the channel capacitance of the capacitive element C1 and the transistor Q1, and is the value before being boosted. Return to (VDD).

When the clock signal CLK2 becomes H level at time t _17, it enters the next stage of the unit shift register SR n _{+ 1} of the selection period. That is, the next-stage output signal G _{n + 1} (reverse second start pulse SPr2 in the case of the m- _th stage) input to the fourth input terminal IN4 of the unit shift register SR _n becomes the H level.

The capacitance value of the capacitive element C2r is set sufficiently large with respect to the parasitic capacitance of the node 4 as in the relationship between the capacitive element C2n and the parasitic capacitance of the node N3n. Therefore, due to the coupling through the capacitive element C2n, the level of the node N3r increases from the previous value (VSS) by the amplitude (VDD) of the output signal _{Gn + 1} of the next stage, and becomes approximately VDD. Then, the transistor Q3r is turned on, the node N1 is discharged and becomes L level (VSS), and the transistor Q1 is turned off. Responsively inverter node N2 inverts the output of the (pull-down circuit) becomes H level (VDD-Vth), the transistor Q2, Q4 are turned on (i.e. the unit shift register SR _n is the reset state).

As a result, the node N1 and the output terminal OUT are set to L level with low impedance, and the unit shift register SR _n is in a non-selected state. Since the transistors Q9n and Q9r are turned on when the node N2 becomes H level, both the nodes N3n and N3r become L level with low impedance. At this time, the node N3r is discharged at a speed corresponding to a time constant determined by the on-resistance value of the transistor Q9r and the capacitance value of the capacitive element C2r and changes to the L level (see FIG. 17). The transistor Q9r is provided for the purpose of maintaining the L level of the node N3r and does not require a large driving capability, so the on-resistance value is set to be relatively large. Therefore, it takes a certain time to discharge the node N3r.

  When the node N3r becomes L level, the transistor Q3r is turned off. At this time, since the transistor Q4 is already turned on, the L level of the node N1 is maintained in a low impedance state.

At time t ₁₈ , the clock signal CLK2 becomes L level and the output signal G _{n + 1 of the} next stage becomes L level. When the level of the output signal G _{n + 1 at} the next stage decreases, the node N3r is pulled down to a potential lower than VSS due to the coupling between the second input terminal IN2 and the node N3r via the capacitive element C2r. However, since the transistor Q9r is on, the potential of the node N3r immediately returns to the potential VSS when the decrease of the output signal G _{n + 1 at} the next stage ends (see FIG. 17).

At time t _19, when the clock signal CLK3 becomes H level, now becomes the unit shift register SR n _{+ 2} of the selection period after two stages. That is, the output signal G _{n + 2} in the second stage input to the third input terminal IN3 of the unit shift register SR _n (in the case of the m-th stage, the reverse direction first start pulse SPr1, the n−1-th stage) In this case, the reverse direction second start pulse SPr2) becomes H level. Depending transistor Q8r is but turned on, the node for N3r is already fixed to the L level by the transistor Q9r, operation of the transistor Q8r at this time does not affect the signal of the shift operation in the unit shift register SR _n.

To summarize the above-described forward shift operation, the unit shift register SR _n maintains the reset state while the signals at the first and second input terminals IN1 and IN2 are inactive. Since the transistor Q1 is off and the transistor Q2 is on in the reset state, the output terminal OUT (gate line GL _n ) is maintained at the L level (VSS) with low impedance.

Then, when the output signal G _n−2 of the immediately preceding stage input to the first input terminal IN1 is activated, the transistor Q8n is turned on, the node N3n is charged and becomes H level (VDD−Vth). Accordingly, transistor Q3n is turned on and node N1 is charged (first preliminary charge). However, in the charging at this time, the level of the node N1 rises only to VDD-2 × Vth at the maximum.

Next, when the output signal G _n−1 of the previous stage is input to the second input terminal IN2, the node N3n is boosted to the level of 2 × VDD−Vth by the capacitive element C2n. In response, transistor Q3n operates in the non-saturated region to charge node N1 (second preliminary charge). Therefore, the level of the node N1 is raised to VDD.

As a result, the unit shift register SR _n enters a set state in which the node N1 is precharged to a sufficiently high level. Since the transistor Q1 is turned on and the transistor Q2 is turned off in the set state, the output signal _Gn is activated while the clock signal CLK1 at the clock terminal CK is at the H level. Thereafter, when the output signal G _{n + 1 of the} next stage input to the fourth input terminal IN4 is activated, the original reset state is restored.

Considering the operation during forward shift of the unit shift register SR _n and the operation during forward shift of the forward start pulse generation circuit 33 and the reverse start pulse generation circuit 34 described above, the configuration of FIG. The operation at the time of forward shift of the gate line driving circuit 30 is as shown in the timing chart of FIG.

That is, when the forward first start pulse SPn1 is activated at the timing corresponding to the head of the frame period, the forward start pulse generation circuit 33 activates the forward second start pulse SPn2 after one horizontal period. Then, the output signals G ₁ , G ₂ ,... Of the unit shift registers SR ₁ , SR ₂ , SR ₃ ,... Are synchronized with the clock signals CLK 1, CLK 2, CLK 3 (ie, every horizontal period). G ₃ ... Are activated in order. Thereby, the gate line driving circuit 30 can sequentially drive the gate lines GL ₁ , GL ₂ , GL ₃ ... In a predetermined scanning cycle.

When the output signal G _{m of the} last unit shift register SR _m is activated, the reverse start pulse generation circuit 34 activates the reverse second start pulse SPr2 after one horizontal period. Whereby the unit shift register SR _m of the final stage is in the reset state. Further, after one horizontal period, the reverse first start pulse SPr1 is activated, and the reverse start pulse generation circuit 34 is reset.

Next, the operation of the unit shift register SR _n at the time of reverse shift will be described. At the time of reverse shift, the first voltage signal Vn is set to L level (VSS), and the second voltage signal Vr is set to H level (VDD). As a result, contrary to the forward shift, the transistor Q3n functions to discharge the node N1, and the transistor Q3r functions to charge the node N1. The transistor Q8r functions to charge the gate (node N3r) of the transistor Q3r, and the capacitive element C2r functions to boost the node N3r after the charging.

As a result, in the unit shift register SR _n , the operations of the transistors Q3n and Q8n and the capacitive element C2n (forward pull-up circuit) and the transistors Q3r and Q8r and the capacitive element C2r (reverse pull-up) with respect to the forward shift. Circuit) operation is switched.

Therefore, the operation of the unit shift register SR _n at the time of reverse shift is as follows. That is, the unit shift register SR _n maintains the reset state while the signals of the third and fourth input terminals IN3 and IN4 are inactive. Since the transistor Q1 is off and the transistor Q2 is on in the reset state, the output terminal OUT (gate line GL _n ) is maintained at the L level (VSS) with low impedance.

When the second-stage output signal G _{n + 2} input to the third input terminal IN3 is activated, the transistor Q8r is turned on, and the node N3r is charged to H level (VDD−Vth). Accordingly, transistor Q3r is turned on and node N1 is charged. However, in the charging at this time (first preliminary charging), the level of the node N1 rises only to VDD-2 × Vth at the maximum.

However, when the next-stage output signal G _{n + 1} is subsequently input to the fourth input terminal IN4, the node N3r is boosted to the level of 2 × VDD−Vth by the capacitive element C2r. Accordingly, the transistor Q3r operates in the non-saturated region and charges the node N1 (second preliminary charge). Thereby, the level of the node N1 is raised to VDD.

As a result, the unit shift register SR _n is set in a state where the node N1 is set to a sufficiently high level. Since the transistor Q1 is turned on and the transistor Q2 is turned off in the set state, the output signal _Gn is activated while the clock signal CLK1 at the clock terminal CK is at the H level. After that, when the output signal G _n−1 at the immediately preceding stage is input to the second input terminal IN2, the original reset state is restored.

Considering the operation at the time of reverse shift of the unit shift register SR _n and the operation at the time of reverse shift of the forward start pulse generation circuit 33 and the reverse direction start pulse generation circuit 34 described above, the configuration of FIG. The operation at the time of reverse shift of the gate line driving circuit 30 is as shown in the timing chart of FIG.

That is, when the reverse first start pulse SPr1 is activated at a timing corresponding to the head of the frame period, the reverse start pulse generation circuit 34 activates the reverse second start pulse SPr2 with a delay of one horizontal period. . Then to it a trigger, the clock signal CLK3, CLK2, at a timing synchronized to the CLK1 (i.e. in each horizontal period), the unit shift register _{SR m, SR m-1,} SR m-2 ... output signals G _m of G _m-1 , G _m-2 ... Are activated in order. As a result, the gate line driving circuit 30 can sequentially drive the gate lines GL _m , GL _m−1 , GL _m−2 ... With a predetermined scanning cycle.

When the output signal G ₁ of the unit shift register SR _{1 at} the foremost stage is activated, the forward start pulse generation circuit 33 activates the forward second start pulse SPn2 after one horizontal period. As a result, the unit shift register SR _{1 in the} foremost stage is reset. Further, after one horizontal period, the forward first start pulse SPn1 is activated, and the forward start pulse generation circuit 33 is reset.

  As described above, the gate line driving circuit 30 according to the present embodiment generates the forward second start pulse SPn2 that is activated with a delay of one horizontal period during the forward shift with respect to the forward first start pulse SPn1. A start pulse generation circuit 33 and a reverse start pulse generation circuit 34 that generates a reverse second start pulse SPr2 that is activated with a delay of one horizontal period when the reverse shift is performed with respect to the reverse first start pulse SPr1. Therefore, as shown in FIG. 16, even when the gate line driving circuit 30 is configured using the unit shift register SR that requires two input signals at the time of the forward shift and the reverse shift, the forward-direction It is only necessary to input two start pulses, one start pulse SPn1 and a reverse first start pulse SPr1. Therefore, it can contribute to the reduction of the cost of the apparatus.

The configuration of the forward start pulse generation circuit 33 shown in FIG. 13 and the configuration of the forward and reverse start pulse generation circuit 34 shown in FIG. 14 are merely examples. The forward start pulse generation circuit 33 activates the forward second start pulse SPn2 with a delay of one horizontal period from the forward first start pulse SPn1 at the time of forward shift, and at the front stage unit at the time of reverse shift. as long as it can be one horizontal period from the output signal G ₁ of the shift register SR ₁ delay activates may be used circuit having another configuration. Similarly, the reverse direction start pulse generation circuit 34 activates the reverse direction second start pulse SPr2 with a delay of one horizontal period from the reverse direction first start pulse SPr1 at the time of reverse shift, and at the end at the time of reverse shift. as long as it can activate a delay of one horizontal period from the output signals G _m of the unit shift register SR _m stages, it may be used circuit having another configuration.

  In the forward start pulse generation circuit 33 of FIG. 13, the absolute value (2 × VDD−Vth) of the potential of the gate (node N1A) of the transistor Q1A when the forward second start pulse SPn2 is activated is a unit shift. The absolute value (2 × VDD) of the potential of the gate (node N1) of the transistor Q1 when the register SR activates the output signal G is not increased. Similarly, in the forward / reverse start pulse generation circuit 34 of FIG. 14, the absolute value (2 × VDD−Vth) of the potential of the gate (node N1B) of the transistor Q1B when the reverse second start pulse SPr2 is activated. Is not as large as the absolute value (2 × VDD) of the potential of the gate (node N1) of the transistor Q1 when the unit shift register SR activates the output signal G. However, the forward direction start pulse generation circuit 33 and the reverse direction start pulse generation circuit 34 do not drive the gate line GL and do not require a high driving capability, so there is no problem. Rather, an increase in circuit area can be suppressed by using a relatively simple circuit configuration as shown in FIGS.

[First change example]
In the unit shift register SR shown in FIG. 16, an inverter circuit (transistors Q6 and Q7) having the node N1 as an input terminal is used as a pull-down circuit. However, in the present embodiment, the nodes N3n and N3r are used as input terminals instead. A modified example using a NOR circuit is shown.

FIG. 20 is a circuit diagram showing a unit shift register SR _{n according} to the first modification of the third embodiment. The unit shift register SR _n is obtained by replacing the transistor Q7 with two transistors Q7n and Q7r in the circuit of FIG. The transistor Q7n is connected between the node N2 and the first power supply terminal S1, and its gate is connected to the node N3r. The transistor Q7r is also connected between the node N2 and the first power supply terminal S1, and its gate is connected to the node N3r.

However, in the unit shift register SR _n having the configuration of FIG. 20, the output signal G _{n + 1} of the next stage is input to the gate of the transistor Q5n, and the output signal G _{n−1 of the} previous stage is input to the gate of the transistor Q5r. (The reason will be described later).

  Transistors Q7n and Q7r are each set to have a sufficiently smaller on-resistance than transistor Q6. Therefore, when both the nodes N3r and N3r are at the L level and both the transistors Q7n and Q7r are off, the node N2 is at the H level. However, when at least one of the nodes N3r and N3r is at the H level, the node N2 Become a level. That is, the transistors Q6, Q7n, and Q7r form a NOR circuit having the nodes N3r and N3r as input ends and the node N2 as an output end.

As shown in the timing chart of FIG. 17, in the case of forward shift, the level of the node N3n is the same timing as the node N1 (timing at which the output signal G _{n-2 of the two} previous stages is input (time t ₁ )). Stand up at. In the case of reverse shift (not shown), the level of the node N3r rises at the same timing as the node N1 (timing at which the output signal G _{n + 2 at the second} stage is input). Accordingly, the unit shift register SR _n of FIG. 20 can operate almost in the same manner as the circuit of FIG. 16, and the same effect can be obtained.

For example, in the forward shift operation, when the level of the node N3n rises in response to the activation of the output signal _{Gn-1 at} the immediately preceding stage, the node N3n becomes a level higher than the node N1. The same applies to the node N3r in the backward shift operation. Therefore, the driving capability of the transistors Q7n and Q7r in FIG. 20 whose gates are connected to the nodes N3n and N3r is higher than that of the transistor Q7 in FIG. 16 in which the gates are connected to the node N1. Therefore, according to the circuit of FIG. 20, when the transistor Q3 starts charging the node N1, the node N2 can be more reliably set to the L level, and the operation reliability can be improved.

However, two transistors to discharge the node N2 (transistors Q7n, Q7r) to become necessary, it should be noted that increases the formation area of the circuit than the unit shift register SR _n of FIG.

Furthermore, it should be noted that the unit shift register SR _n of FIG. 20 should not supply the output signal G _n of the unit shift register SR _n to the gates of the transistors Q5n and Q5r, unlike the circuit of FIG. It is. If the output signal G _n is supplied to the gates of the transistors Q5n and Q5r in the circuit of FIG. 20, the transistors Q7n and Q7r are turned off during the period (selection period) when the output signal G _n is at the H level. Node N2 becomes H level. Sonaruto, transistor Q2 despite active period of the output signal G _n is turned on, problem of lowering the level of the output signal G _n occurs. In order to prevent this, in the circuit of FIG. 20, output signals G _{n + 1} and G _n−1 of the next stage and the immediately preceding stage are supplied to the gates of the transistors Q5n and Q5r, respectively.

[Second modification]
In a display device including a gate line driving circuit using a shift register, in order to increase the resolution of the display panel, it is necessary to increase the operating speed of the shift register by increasing the frequency of the clock signal for driving the shift register. . However, when the clock signal has a high frequency, the pulse width is narrowed and the operation margin of the shift register is reduced. Therefore, in order to suppress the margin reduction, the pulse width of the clock signal is set as wide as possible. That is, the interval between the active periods of the clock signals (for example, the interval between times t _{12 and} t _{13 in} FIG. 17) is set very short.

Since a certain time is required for discharging the output terminal OUT, if the interval between the active periods of the clock signals becomes very short, for example, during forward shift, the level of the output signal G _n of the unit shift register SR _n before drops sufficiently, is the next-stage output signal G _{n + 1} levels may begin to rise. In such a case, the following problems occur in the circuits of FIGS. That is, before the output terminal OUT is sufficiently discharged, the level of the node N3r increases, the transistor Q3r is turned on, and the level of the node N1 decreases. As a result, the resistance value of the transistor Q1 is increased, which causes a problem that the falling speed of the output signal _Gn (discharge speed of the output terminal OUT) is decreased.

One countermeasure is to set the on-resistance value of the transistor Q2 low so that the output terminal OUT is quickly discharged through the transistor Q2 when the output signal G _{n + 1} at the next stage rises. Can be mentioned. However, in order to reduce the on-resistance of the transistor Q2, it is necessary to increase the gate width, which increases the circuit area. Therefore, in this modification, a configuration of a unit shift register that can solve the above problem while suppressing an increase in circuit area is shown.

FIG. 21 is a circuit diagram of a unit shift register SR _{n according to} a second modification of the third embodiment. In the unit shift register SR _n , transistors Q10n and Q10r are provided instead of the capacitive elements C2n and C2r in the circuit of FIG. 16, and the transistor Q11n is connected between the node N1 and the first voltage signal terminal T1, and the node N1. And the second voltage signal terminal T2 are respectively connected to transistors Q11r. The gate of the transistor Q11n is connected to the first input terminal IN1, and the gate of the transistor Q11r is connected to the third input terminal IN3.

  The transistor Q10n has a gate connected to the node N3n and two current electrodes (source and drain) both connected to the second input terminal IN2. In a field effect transistor, when a voltage higher than a threshold voltage is applied to a gate electrode, the drain-source is electrically connected by a conductive channel formed directly under the gate electrode through a gate insulating film in a semiconductor substrate. It is an element that conducts when connected to. Therefore, the conductive field effect transistor has a certain capacitance (gate capacitance) between the gate and the channel. In other words, it can function as a capacitor element in which the channel and gate electrode in the semiconductor substrate are both terminals and the gate insulating film is a dielectric layer.

  Accordingly, the transistor Q10n selectively functions as a capacitive element according to the voltage between the node N3n and the second input terminal IN2 (functions as a capacitive element only when the node N3n is at an active level).

  On the other hand, the transistor Q10r has a gate connected to the node N3r and two current electrodes (source and drain) both connected to the fourth input terminal IN4. Therefore, the transistor Q10r has the node N3r and the fourth input terminal IN4 as both terminals, and selectively functions as a capacitive element according to the voltage between them (functions as a capacitive element only when the node N3r is at an active level). A capacitive element using the gate and channel of a MOS transistor as both electrodes like the transistors Q10n and Q10r is referred to as a "MOS capacitive element".

The operation of the unit shift register SR _n of FIG. 21 is almost the same as that of FIG. 16, but differs in the following points. For example, in the case of forward shift, the node N3r is at L level immediately before the output signal G _{n + 1 of the} next stage is activated (time t _{17 in} FIG. ₁₇ ). That is, the transistor Q10r, which is a MOS capacitor, has no channel and does not function as a capacitor. Therefore, even if the output signal G _{n + 1 at the} next stage becomes H level, the level of the node N3r does not rise, and the transistor Q3r remains off. Therefore, at this time, the node N1 is not discharged, and the on-resistance of the transistor Q1 is kept low. Thereafter, the node N1 is discharged by the transistor Q11r that is turned on in response to the activation of the output signal G _{n + 2 at} the next two stages.

In this way, in the unit shift register SR _n of FIG. 21, the timing at which the node N1 is discharged is delayed by one horizontal period from the case of the circuit of FIG. Accordingly, a margin of about one horizontal period is ensured between the start of discharge of the output terminal OUT and the start of discharge of the node N1. Therefore, even _if the level of the output signal G _{n + 1} of the next stage may start to rise before the level of the output signal G _n of the unit shift register SR _n is sufficiently lowered, the above problem can be avoided.

  Although explanation is omitted, of course, the same effect can be obtained at the time of reverse shift. In the configuration of FIG. 21, it is not necessary to increase the gate width of the transistor Q2, so that an increase in circuit area is also suppressed.

Transistors Q11n and Q11r also contribute to charging node N1, respectively. For example, at the time of forward shift, the transistor Q11r can charge the node N1 to the maximum VDD-Vth in response to the activation of the output signal _Gn-2 of the previous two stages. In response to activation of the output signal G _{n + 2} , the node N1 can be charged up to the maximum VDD−Vth. Therefore, in this modified example, an effect that the charging speed of the node N1 is improved is also obtained.

This modified example can also be applied to the unit shift register SR _n of FIG. In that case, transistors Q10n and Q10r are provided instead of the capacitive elements C2n and C2r in the circuit of FIG. 20, and the transistor Q11n is connected between the node N1 and the first voltage signal terminal T1, and the node N1 and the second voltage. The transistor Q11r may be connected to the signal terminal T2. FIG. 22 shows a circuit diagram thereof.

<Embodiment 4>
According to the above-described third embodiment, the gate line driving circuit 30 including the unit shift register SR that requires two input signals at the time of forward shift and reverse shift must also be input from the outside. Only two pulses (forward first start pulse SPn1 and reverse first start pulse SPr1) are required.

  In the present embodiment, the number of necessary start pulses is further reduced, and only one start pulse is required in the gate line driving circuit 30 including the unit shift register SR that requires two input signals at the time of forward shift and reverse shift, respectively. The form which should just be supplied from the outside is shown.

  FIG. 23 is a block diagram showing a configuration of the gate line driving circuit 30 according to the fourth embodiment. In the gate line driving circuit 30, a reverse reset signal generation circuit 35 is provided further upstream of the forward start pulse generation circuit 33, and a forward reset signal generation circuit 36 is further downstream of the reverse start pulse generation circuit 34. Is provided. Here, it is assumed that the unit shift register SR constituting the gate line driving circuit 30 is the unit shift register SR (FIG. 16 or FIG. 20) of the third embodiment or the first modification example thereof.

In the gate line driving circuit 30, only the first start pulse SP1 is inputted as the start pulse inputted from the outside as in the first embodiment. The first start pulse SP1 has a forward input terminal INnA forward start pulse generation circuit 33, a first input terminal IN1 of the unit shift register SR _1, the third input terminal IN3 of the unit shift register SR _m, reverse This is supplied to the reverse direction input terminal INrB of the start pulse generation circuit 34.

  The reverse reset signal generation circuit 35 generates a reverse reset signal RSr for resetting the forward start pulse generation circuit 33 (transistor Q1A is turned off and transistor Q2A is turned on) at the time of reverse shift. It is. This reverse reset signal RSr is a signal corresponding to the forward first start pulse SPn1 during the reverse shift in the third embodiment, that is, the forward second pulse generated by the forward start pulse generation circuit 33 during the reverse shift. This signal is activated with a delay of one horizontal period with respect to the start pulse SPn2.

  The forward reset signal generation circuit 36 generates a forward reset signal RSn for resetting the reverse start pulse generation circuit 34 (transistor Q1B is turned off and transistor Q2B is turned on) at the time of forward shift. It is. The forward reset signal RSn is a signal corresponding to the reverse first start pulse SPr1 at the time of forward shift in the third embodiment, that is, the reverse second signal generated by the reverse start pulse generation circuit 34 at the time of reverse shift. This signal is activated with a delay of one horizontal period with respect to the start pulse SPr2.

  FIG. 24 is a circuit diagram showing a configuration of the forward start pulse generation circuit 33 and the reverse reset signal generation circuit 35 according to the present embodiment.

  As shown in the figure, the forward start pulse generation circuit 33 of the present embodiment resets the forward start pulse generation circuit 33 with respect to the circuit of FIG. 13 (the forward start pulse generation circuit 33 of the first embodiment). Transistors Q8A and Q9A are provided for this purpose. The transistor Q8A has a gate connected to the reset terminal RSTA that receives the reverse reset signal RSr, and is connected between the node N2A and the second power supply terminal S2. The transistor Q9A has a gate connected to the reset terminal RSTA, and is connected between the node N1A and the first power supply terminal S1.

  The operation of the forward start pulse generation circuit 33 is basically the same as the circuit of FIG. However, when the reverse reset signal RSr is activated, the transistors Q8A and Q9A are turned on, and the node N1A is in the L level and the node N2B is in the H level. That is, the transistor Q1A is reset to the off state and the transistor Q2A is reset to the on state, and the forward second start pulse SPn2 is fixed at the L level with low impedance.

  On the other hand, the reverse direction reset signal generation circuit 35 has the same configuration as the circuit of FIG. Transistors Q1C, Q2C, Q3nC, Q3rC, Q4C, Q5nC, Q5rC, Q6C, Q7C and capacitive element C1C in FIG. 24 are transistors Q1A, Q2A, Q3nA, Q3rA, Q4A, Q5nA, Q5rA, Q6A, Q7A and This corresponds to the capacitive element C1A.

  However, the drains of the transistors Q3nC and Q5rC are connected not to the first voltage signal terminal T1 but to the second power supply terminal S2. The sources of the transistors Q3rC and Q5nC are connected not to the second voltage signal terminal T2 but to the first power supply terminal S1.

  Specifically, as shown in FIG. 24, the transistor Q1C is connected between the output terminal OUTC of the reverse reset signal RSr and the clock terminal CKC, and the transistor Q2C is connected between the output terminal OUTC and the first power supply terminal S1. Connecting. A node to which the gate of the transistor Q1C is connected is defined as “node N1C”, and a node to which the gate of the transistor Q2C is connected is defined as “node N2C”.

  A capacitive element C1C (boost capacitor) is provided between the gate and source of the transistor Q1C. Capacitance element C1C can be replaced with the gate capacitance of transistor Q1C.

  The transistor Q3nC has a gate connected to the input terminal INC, and is connected between the node N1C and the second power supply terminal S2. The transistor Q3rC has a gate connected to the reset terminal RSTC, and is connected between the node N1C and the first power supply terminal S1. The transistor Q4C has a gate connected to the node N2C, and is connected between the node N1C and the first power supply terminal S1.

  The transistor Q6C has a gate connected to the second power supply terminal S2, and is connected between the second power supply terminal S2 and the node N2C. The transistor Q7C has a gate connected to the node N1C, and is connected between the node N2C and the first power supply terminal S1. The transistors Q6C and Q7C constitute a ratio type inverter having the node N1C as an input end and the node N2C as an output end.

  The transistor Q5nC has a gate connected to the input terminal INC, and is connected between the node N2C and the first power supply terminal S1. The transistor Q5rC has a gate connected to the reset terminal RSTC, and is connected between the second power supply terminal S2 and the node N2C. The transistors Q5nC and Q5rC can be omitted if the on-resistance of the transistors Q3nC and Q3rC is sufficiently low.

  As shown in FIG. 24, the forward second start pulse SPn2 output from the forward start pulse generation circuit 33 is supplied to the input terminal INC. The clock terminal CKC is supplied with a clock signal CLK2 whose phase is delayed by one horizontal period at the time of reverse shift with respect to the clock signal CLK3 supplied to the clock terminal CKA of the forward direction start pulse generation circuit 33. The reset terminal RSTC is supplied with a clock signal CLK1 whose phase is delayed by one horizontal period at the time of reverse shift with respect to the clock signal CLK2 supplied to the clock terminal CKC.

  The operation principle of the reverse reset signal generation circuit 35 of FIG. 24 is the same as that of FIG. However, although the circuit of FIG. 13 can function as a one-stage bidirectional unit shift register, in the circuit of FIG. 24, the drains of the transistors Q3nC and Q5rC are fixed to the high-side power supply potential VDD1, and the sources of the transistors Q3rC and Q5nC Is fixed at the low-side power supply potential VSS, so that it is possible to shift in one direction to activate the reverse reset signal RSr after the signal of the input terminal INC is activated.

  Since the forward second start pulse SPn2 output from the forward start pulse generation circuit 33, which is the next stage of the reverse reset signal generation circuit 35, is supplied to the input terminal INC, the reverse reset signal generation circuit 35 is in the reverse direction. Only a shift will be performed. That is, the reverse reset signal generation circuit 35 activates the reverse reset signal RSr with a delay of one horizontal period from the forward second start pulse SPn2 exclusively during the reverse shift.

  Note that the reverse reset signal generation circuit 35 does not activate the reverse reset signal RSr in response to the activation of the forward second start pulse SPn2 during the forward shift. In the forward shift, the transistor Q1C is once turned on when the forward second start pulse SPn2 is activated. However, the reverse reset signal RSr is activated from the phase relationship of the clock signals CLK1 to CLK3 during the forward shift. Before being done, transistor Q3rC discharges node N1C, and transistor Q1C is turned off. Therefore, the reverse reset signal RSr is not activated during the forward shift.

  On the other hand, FIG. 25 is a circuit diagram showing the configurations of the reverse start pulse generation circuit 34 and the forward reset signal generation circuit 36 according to the present embodiment.

  As shown in the figure, the reverse start pulse generation circuit 34 of the present embodiment resets the reverse start pulse generation circuit 34 with respect to the circuit of FIG. 14 (reverse start pulse generation circuit 34 of the first embodiment). Transistors Q8B and Q9B are provided. Transistor Q8B has a gate connected to reset terminal RSTB that receives forward reset signal RSn, and is connected between node N2B and second power supply terminal S2. The transistor Q9B has a gate connected to the reset terminal RSTB, and is connected between the node N1B and the first power supply terminal S1.

  The operation of the reverse start pulse generation circuit 34 is basically the same as the circuit of FIG. However, when the forward reset signal RSn is activated, the transistors Q8B and Q9B are turned on, and the node N1B is in the L level and the node N2B is in the H level. That is, the transistor Q1B is reset to the off state and the transistor Q2B is reset to the on state, and the reverse second start pulse SPr2 is fixed at the L level with low impedance.

  On the other hand, the forward reset signal generation circuit 36 has the same configuration as the circuit of FIG. Transistors Q1D, Q2D, Q3nD, Q3rD, Q4D, Q5nD, Q5rD, Q6D, Q7D and capacitive element C1D in FIG. 25 are transistors Q1B, Q2B, Q3nB, Q3rB, Q4B, Q5nB, Q5rB, Q6B, Q7B and This corresponds to the capacitive element C1B.

  However, the drains of the transistors Q3nD and Q5rD are connected not to the first voltage signal terminal T1 but to the second power supply terminal S2. The sources of the transistors Q3rD and Q5nD are connected not to the second voltage signal terminal T2 but to the first power supply terminal S1.

  Specifically, as shown in FIG. 25, the transistor Q1D is connected between the output terminal OUTD of the forward reset signal RSn and the clock terminal CKD, and the transistor Q2D is connected between the output terminal OUTD and the first power supply terminal S1. Connecting. A node to which the gate of the transistor Q1D is connected is defined as “node N1D”, and a node to which the gate of the transistor Q2D is connected is defined as “node N2D”.

  A capacitive element C1D (step-up capacitor) is provided between the gate and source of the transistor Q1D. The capacitive element C1D may be replaced with the gate capacitance of the transistor Q1.

  The transistor Q3nD has a gate connected to the input terminal IND, and is connected between the node N1D and the second power supply terminal S2. The transistor Q3rD has a gate connected to the reset terminal RSTD, and is connected between the node N1D and the first power supply terminal S1. The transistor Q4D has a gate connected to the node N2D, and is connected between the node N1D and the first power supply terminal S1.

  The transistor Q6D has a gate connected to the second power supply terminal S2, and is connected between the second power supply terminal S2 and the node N2D. The transistor Q7D has a gate connected to the node N1D, and is connected between the node N2D and the first power supply terminal S1. The transistors Q6D and Q7D constitute a ratio type inverter having the node N1D as an input end and the node N2D as an output end.

  The transistor Q5nD has a gate connected to the input terminal IND, and is connected between the node N2D and the first power supply terminal S1. The transistor Q5rD has a gate connected to the reset terminal RSTD, and is connected between the second power supply terminal S2 and the node N2D. The transistors Q5nD and Q5rD may be omitted when the on-resistances of the transistors Q3nD and Q3rD are sufficiently low.

  As shown in FIG. 25, the reverse second start pulse SPr2 output from the reverse start pulse generation circuit 34 is supplied to the input terminal IND. The clock terminal CKD is supplied with a clock signal CLK1 whose phase is delayed by one horizontal period at the time of forward shift with respect to the clock signal CLK3 supplied to the clock terminal CKD of the reverse direction start pulse generation circuit 34. The reset terminal RSTD is supplied with a clock signal CLK2 whose phase is delayed by one horizontal period at the time of forward shift with respect to the clock signal CLK1 supplied to the clock terminal CKD.

  The operation principle of the circuit of FIG. 25 is the same as that of the circuit of FIG. However, although the circuit of FIG. 14 can function as a one-stage bidirectional unit shift register, in the circuit of FIG. 25, the drains of the transistors Q3nD and Q5rD are fixed to the high-side power supply potential VDD1, and the sources of the transistors Q3rD and Q5nD Is fixed at the low-side power supply potential VSS, so that only a forward shift is possible. That is, the forward reset signal generation circuit 36 activates the forward reset signal RSn with a delay of one horizontal period from the backward second start pulse SPr2 exclusively during forward shift.

  Note that the forward reset signal generation circuit 36 does not activate the forward reset signal RSn in response to the activation of the backward second start pulse SPr2 during the backward shift. In the reverse shift, when the reverse second start pulse SPr2 is activated, the transistor Q1D is once turned on. However, the forward reset signal RSn is activated due to the phase relationship of the clock signals CLK1 to CLK3 during the reverse shift. Before being done, transistor Q3rD discharges node N1D and transistor Q1D returns to off. Therefore, the forward reset signal RSn is not activated during the forward shift.

  Considering the operations of the forward start pulse generation circuit 33, the reverse start pulse generation circuit 34, the reverse reset signal generation circuit 35, and the forward reset signal generation circuit 36 described above, the gate line driving circuit according to the present embodiment. The operation at the time of 30 forward shifts is as shown in the timing chart of FIG.

That is, when the first start pulse SP1 is activated at the timing corresponding to the head of the frame period, the forward start pulse generation circuit 33 activates the forward second start pulse SPn2 after one horizontal period. Then, the output signals G ₁ , G ₂ , G of the unit shift registers SR ₁ , SR ₂ , SR ₃ ... Are synchronized with the clock signals CLK 1, CLK 2, CLK 3 (ie, every horizontal period). ₃ ... are activated in turn. Thereby, the gate line driving circuit 30 can sequentially drive the gate lines GL ₁ , GL ₂ , GL ₃ ... In a predetermined scanning cycle.

When the output signal G _{m of the} last unit shift register SR _m is activated, the reverse start pulse generation circuit 34 activates the reverse second start pulse SPr2 after one horizontal period. Whereby the unit shift register SR _m of the final stage is in the reset state.

  When the reverse second start pulse SPr2 is activated, the forward reset signal generation circuit 36 activates the forward reset signal RSn after one horizontal period. In response, the reverse direction start pulse generation circuit 34 is reset. The forward reset signal generation circuit 36 is then reset in response to the activation of the clock signal CLK2.

The forward start pulse generation circuit 33 at the time of forward shift is reset in response to the activation of the output signal G ₁ of the unit shift register SR ₁ as in the case of the third embodiment. As described above, the reverse reset signal RSr output from the reverse reset signal generation circuit 35 is not activated during the forward shift.

The first start pulse SP1 has a third input terminal IN3 of the unit shift register SR _m of the final stage as shown in FIG. 23, is also supplied to the reverse input terminal INrB reverse start pulse generation circuit 34. As can be seen from the description in the third embodiment, the unit shift register SR _m during forward shift activates the output signal G _m according to signals of the first and second input terminals IN1, IN2 are activated and of letting, no signal of the third input terminal IN3 activates the output signal G _m accordingly be activated. Therefore operation of the unit shift register SR _m during forward shift is not affected by the first start pulse SP1.

  Similarly, the reverse start pulse generation circuit 34 at the time of forward shift activates the reverse second start pulse SPr2 in response to the signal at the forward input terminal INnB becoming H level. Even if the signal at the terminal INrB is activated, the reverse second start pulse SPr2 is not activated accordingly. Therefore, the operation of the reverse start pulse generation circuit 34 during the forward shift is not affected by the first start pulse SP1.

On the other hand, the operation at the time of reverse shift of the gate line driving circuit 30 is as shown in the timing chart of FIG. That is, when the first start pulse SP1 is activated at the timing corresponding to the head of the frame period, the reverse start pulse generation circuit 34 activates the reverse second start pulse SPr2 after one horizontal period. Then to it a trigger, the clock signal CLK3, CLK2, at a timing synchronized to the CLK1 (i.e. in each horizontal period), the unit shift register _{SR m, SR m-1,} SR m-2 ... output signals G _m of G _m-1 , G _m-2 ... Are activated in order. As a result, the gate line driving circuit 30 can sequentially drive the gate lines GL _m , GL _m−1 , GL _m−2 ... With a predetermined scanning cycle.

When the output signal G ₁ of the unit shift register SR _{1 at} the foremost stage is activated, the forward start pulse generation circuit 33 activates the forward second start pulse SPn2 after one horizontal period. As a result, the unit shift register SR _{1 in the} foremost stage is reset.

  When the forward second start pulse SPn2 is activated, the backward reset signal generation circuit 35 activates the backward reset signal RSr after one horizontal period. Accordingly, the forward start pulse generation circuit 33 is reset. The reverse reset signal generation circuit 35 is then reset in response to the activation of the clock signal CLK1.

Incidentally, reverse start pulse generation circuit 34 at the time of backward shift is reset in response to activation of the output signal G _m the same manner as in the case unit shift register SR _m of the third embodiment. As described above, the forward reset signal RSn output from the forward reset signal generation circuit 36 is not activated during the backward shift.

The first start pulse SP1 has a first input terminal IN1 of the unit shift register SR ₁ as the leading stage in FIG. 23, is also supplied to the forward input terminal INnA forward start pulse generation circuit 33. As can be seen from the description in the third embodiment, the unit shift register SR ₁ at the time of reverse shift activates the output signal G ₁ in response to the activation of the signals at the third and fourth input terminals IN3 and IN4. and of letting the signal of the first input terminal IN1 it is not possible to activate the output signal G ₁ accordingly be activated. Therefore operation of the unit shift register SR ₁ of the reverse shift is not affected by the first start pulse SP1.

  Similarly, the forward start pulse generation circuit 33 at the time of backward shift activates the forward second start pulse SPn2 in response to the signal at the backward input terminal INrA becoming H level. Even if the signal at the terminal INnA is activated, the forward second start pulse SPn2 is not activated accordingly. Therefore, the operation of the forward start pulse generation circuit 33 during the reverse shift is not affected by the first start pulse SP1.

  As described above, according to the gate line driving circuit 30 according to the present embodiment, by inputting only one start pulse (first start pulse SP1) from the outside, both forward and reverse shift operations are performed. Is possible.

[Example of change]
In the above description, it is assumed that the unit shift register SR constituting the gate line driving circuit 30 is the unit shift register SR (FIG. 16 or FIG. 20) according to the third embodiment or the first modification example. It is also possible to use the unit shift register SR (FIG. 21 or FIG. 22) of the second modification of the third embodiment.

The unit shift register SR shown in FIGS. 21 and 22 needs to be in a reset state after two horizontal periods after the activation of its own output signal G. In the configuration of the gate line driving circuit 30 shown in FIG. can not be a unit shift register SR _m of the final stage in the reset state, can not be a unit shift register SR ₁ of the first stage in the reset state when backward shift.

When using the order unit shift register SR of FIG. 21 or FIG. 22, the forward unit shift register at the time of shift SR _m is the reset state in response to activation of a forward reset signal RSn, the unit shift register SR ₁ is in the reverse shift Needs to be changed so that the reset state is set in response to the activation of the reverse reset signal RSr.

Specifically, the configuration of the unit shift registers SR ₁ and SR _m of FIGS. 21 and 22 may be changed as follows. For example, by supplying a reverse reset signal RSr to the gate of the transistor Q11n of the unit shift register SR _1, modified to provide a forward reset signal RSn to the gate of the transistor Q11r of the unit shift register SR _m. In that case, the transistor Q11n of the unit shift register SR _1, since it is sufficient discharge the node N1 to the active period of the reverse reset signal RSr exclusively its source connected to the first power supply terminal S1 not the first voltage signal terminal T1 Alternatively, a clock signal whose active period does not overlap with the reverse reset signal RSr may be supplied. The transistor Q11r of the unit shift register SR _m, since it is sufficient exclusively discharge the node N1 to the active period of a forward reset signal RSn, its source, be connected to the first power supply terminal S1 not the second voltage signal terminal T2 Alternatively, a clock signal whose active period does not overlap with the forward reset signal RSn may be supplied.

Further, for example, the unit shift register SR _1, additionally provided a transistor discharges the node N1 in response to activation of a reverse reset signal RSr, the unit shift register SR _m, node in response to the activation of the forward reset signal RSn A transistor for discharging N1 may be provided separately.

  30 gate line driving circuit, 31 clock signal generator, 32, 321, 322 start pulse generating circuit, 33 forward start pulse generating circuit, 34 reverse start pulse generating circuit, 35 reverse reset signal generating circuit, 36 forward reset Signal generation circuit, GL gate line, SP1 to SP3, first to third start pulses, SR unit shift register.

Claims (18)

A start pulse generating circuit that receives the first start pulse and generates a second start pulse that is activated later than the first start pulse;
A shift register circuit comprising a plurality of cascaded unit shift registers,
Each of the unit shift registers is
First and second input terminals;
A first output terminal for outputting an output signal;
A first clock terminal to which a predetermined clock signal is input;
A first transistor for supplying a clock signal input to the first clock terminal to the first output terminal;
A second transistor for supplying a potential of a power supply terminal to a first node to which the control electrode of the first transistor is connected;
A charging circuit that charges a second node to which the control electrode of the second transistor is connected in response to a signal input to the first input terminal;
A booster circuit that boosts the second node in response to a signal input to the second input terminal;
In the first stage of the plurality of unit shift registers,
The first start pulse is input to the first input terminal;
The second start pulse is input to the second input terminal;
In the second stage of the plurality of unit shift registers,
The second start pulse is input to the first input terminal;
The output signal of the first stage is input to the second input terminal,
In each of the third and subsequent stages of the plurality of unit shift registers,
The output signal of the previous two stages is input to the first input terminal,
A shift register circuit, wherein the output signal of the immediately preceding stage is inputted to the second input terminal. The shift register circuit according to claim 1,
The start pulse generation circuit includes:
A third input terminal to which the first start pulse is input;
A second output terminal for outputting the second start pulse;
A second clock terminal to which a predetermined clock signal is input;
A third transistor for supplying a clock signal input to the second clock terminal to the second output terminal;
And a fourth transistor for charging a third node connected to the control electrode of the third transistor in response to the first start pulse. A shift register circuit according to claim 2,
The absolute value of the potential of the first node when the unit shift register activates the output signal is the absolute value of the potential of the third node when the start pulse generation circuit activates the second start pulse. A shift register circuit characterized by being larger than a value. A first start pulse generating circuit that receives the first start pulse and generates a second start pulse that is activated later than the first start pulse;
A second start pulse generating circuit that receives the second start pulse and generates a third start pulse that is activated later than the second start pulse;
A shift register circuit comprising a plurality of cascaded unit shift registers,
Each of the unit shift registers is
First, second and third input terminals;
A first output terminal for outputting an output signal;
A first clock terminal to which a predetermined clock signal is input;
A first transistor for supplying a clock signal input to the first clock terminal to the first output terminal;
A second transistor for supplying a potential of a power supply terminal to a first node to which the control electrode of the first transistor is connected;
A third transistor for supplying a potential of the power supply terminal to a second node to which a control electrode of the second transistor is connected;
A charging circuit that charges a third node to which the control electrode of the third transistor is connected in response to a signal input to the first input terminal;
A first booster circuit for boosting the third node in response to a signal input to the second input terminal;
A second booster circuit that boosts the second node in response to a signal input to the third input terminal;
In the first stage of the plurality of unit shift registers,
The first start pulse is input to the first input terminal;
The second start pulse is input to the second input terminal;
The third start pulse is input to the third input terminal;
In the second stage of the plurality of unit shift registers,
The second start pulse is input to the first input terminal;
The third start pulse is input to the second input terminal;
The output signal of the first stage is input to the third input terminal,
In the third stage of the plurality of unit shift registers,
The third start pulse is input to the first input terminal;
The output signal of the first stage is input to the second input terminal,
The output signal of the second stage is input to the third input terminal,
In each of the fourth and subsequent stages of the plurality of unit shift registers,
The output signal of the previous three stages is input to the first input terminal,
The second previous output signal is input to the second input terminal,
A shift register circuit, wherein the output signal of the immediately preceding stage is input to the third input terminal. A shift register circuit according to claim 4,
Each of the first and second start pulse generation circuits includes:
A fourth input terminal, a second output terminal and a second clock terminal;
A fourth transistor for supplying a clock signal input to the second clock terminal to the second output terminal;
A fifth transistor for charging a fourth node connected to a control electrode of the fourth transistor in response to a signal input to the fourth input terminal;
In the first start pulse generation circuit,
The first start pulse is input to the fourth input terminal;
The second start pulse is output from the second output terminal,
In the first start pulse generation circuit,
The second start pulse is input to the fourth input terminal;
The shift register circuit, wherein the third start pulse is output from the second output terminal. A shift register circuit according to claim 5,
The absolute value of the potential of the first node when the unit shift register activates the output signal is the value when the first and second start pulse generation circuits activate the second and third start pulses, respectively. A shift register circuit having a potential greater than the absolute value of the potential of the fourth node. A multi-stage shift register circuit capable of forward shift that shifts a signal from the front stage to the rear stage and reverse shift that shifts the signal from the rear stage to the front stage,
A forward start pulse generating circuit that receives a forward first start pulse and generates a forward second start pulse that is activated later than the forward first start pulse at the time of forward shift;
A reverse start pulse generating circuit that receives a reverse first start pulse and generates a reverse second start pulse that activates behind the reverse first start pulse during reverse shift;
The unit shift register which is each stage of the multi-stage,
First to fourth input terminals;
A first output terminal for outputting an output signal;
A first clock terminal to which a predetermined clock signal is input;
A first transistor for supplying a clock signal input to the first clock terminal to the first output terminal;
First and second voltage signal terminals to which first and second voltage signals complementary to each other are supplied;
A second transistor for supplying a potential of the first voltage signal terminal to a first node to which a control electrode of the first transistor is connected;
A third transistor that supplies a potential of the first voltage signal terminal to a second node connected to a control electrode of the second transistor in response to a signal input to the first input terminal;
A first capacitive element coupled between the second input terminal and the second node;
A fourth transistor for supplying the potential of the second voltage signal terminal to the first node;
A fifth transistor that supplies a potential of the second voltage signal terminal to a third node connected to a control electrode of the fourth transistor in response to a signal input to the third input terminal;
A second capacitive element coupled between the fourth input terminal and the third node;
In the first stage unit shift register,
The forward first start pulse is input to the first input terminal,
The forward second start pulse is input to the second input terminal;
In the second stage unit shift register,
The forward second start pulse is input to the first input terminal;
The output signal of the first stage is input to the second input terminal,
In each unit shift register after the third stage,
The output signal of the previous two stages is input to the first input terminal,
The output signal of the immediately preceding stage is input to the second input terminal,
In the last unit shift register,
The reverse first start pulse is input to the third input terminal,
The reverse second start pulse is input to the fourth input terminal;
In the second unit shift register from the end,
The reverse second start pulse is input to the third input terminal,
The output signal of the last stage is input to the fourth input terminal,
In each unit shift register before the last three stages,
The output signal of the next two stages is input to the third input terminal,
A shift register circuit, wherein the output signal of the next stage is input to the fourth input terminal. A shift register circuit according to claim 7,
The forward start pulse generation circuit includes:
A second output terminal for outputting the forward second start pulse;
A second clock terminal to which a predetermined clock signal is input;
A sixth transistor for supplying a clock signal input to the second clock terminal to the second output terminal;
The first and second voltage signal terminals;
A seventh transistor for supplying a potential of the first voltage signal terminal to a fourth node connected to a control electrode of the sixth transistor in response to the forward first start pulse;
An eighth transistor for supplying the potential of the second voltage signal terminal to the fourth node in response to an output signal of the first stage unit shift register;
The reverse start pulse generation circuit includes:
A third output terminal for outputting the reverse second start pulse;
A third clock terminal to which a predetermined clock signal is input;
A ninth transistor for supplying a clock signal input to the third clock terminal to the third output terminal;
The first and second voltage signal terminals;
A tenth transistor for supplying a potential of the first voltage signal terminal to a fifth node connected to a control electrode of the ninth transistor in response to an output signal of the last unit shift register;
11. A shift register circuit comprising: an eleventh transistor for supplying the potential of the second voltage signal terminal to the fourth node in response to the reverse first start pulse. A shift register circuit according to claim 8,
The absolute value of the potential of the first node when the unit shift register activates the output signal is the fourth node when the forward start pulse generation circuit activates the forward second start pulse. The shift register circuit is characterized in that the absolute value of the potential of the second node is larger than the absolute value of the potential of the fifth node when the reverse direction start pulse generation circuit activates the reverse direction second start pulse. A shift register circuit according to any one of claims 7 to 9,
The first node of each of the unit shift registers is
At the time of forward shift, it is discharged in response to the activation of the output signal of one or two subsequent stages,
A shift register circuit which is discharged in response to the activation of the output signal of one or two stages before itself during reverse shift. A multi-stage shift register circuit capable of forward shift that shifts a signal from the front stage to the rear stage and reverse shift that shifts the signal from the rear stage to the front stage,
A forward start pulse generating circuit for receiving a first start pulse and generating a forward second start pulse that activates behind the first start pulse during forward shift;
A reverse start pulse generation circuit that receives the first start pulse and generates a reverse second start pulse that activates behind the first start pulse during reverse shift;
The unit shift register which is each stage of the multi-stage,
First to fourth input terminals;
A first output terminal for outputting an output signal;
A first clock terminal to which a predetermined clock signal is input;
A first transistor for supplying a clock signal input to the first clock terminal to the first output terminal;
First and second voltage signal terminals to which first and second voltage signals complementary to each other are supplied;
A second transistor for supplying a potential of the first voltage signal terminal to a first node to which a control electrode of the first transistor is connected;
A third transistor that supplies a potential of the first voltage signal terminal to a second node connected to a control electrode of the second transistor in response to a signal input to the first input terminal;
A first capacitive element coupled between the second input terminal and the second node;
A fourth transistor for supplying the potential of the second voltage signal terminal to the first node;
A fifth transistor that supplies a potential of the second voltage signal terminal to a third node connected to a control electrode of the fourth transistor in response to a signal input to the third input terminal;
A second capacitive element coupled between the fourth input terminal and the third node;
In the first stage unit shift register,
The first start pulse is input to the first input terminal;
The forward second start pulse is input to the second input terminal;
In the second stage unit shift register,
The forward second start pulse is input to the first input terminal;
The output signal of the first stage is input to the second input terminal,
In each unit shift register after the third stage,
The output signal of the previous two stages is input to the first input terminal,
The output signal of the immediately preceding stage is input to the second input terminal,
In the last unit shift register,
The first start pulse is input to the third input terminal;
The reverse second start pulse is input to the fourth input terminal;
In the second unit shift register from the end,
The reverse second start pulse is input to the third input terminal,
The output signal of the last stage is input to the fourth input terminal,
In each unit shift register before the last three stages,
The output signal of the next two stages is input to the third input terminal,
A shift register circuit, wherein the output signal of the next stage is input to the fourth input terminal. A shift register circuit according to claim 11,
The forward start pulse generation circuit includes:
A second output terminal for outputting the forward second start pulse;
A second clock terminal to which a predetermined clock signal is input;
A sixth transistor for supplying a clock signal input to the second clock terminal to the second output terminal;
The first and second voltage signal terminals;
A seventh transistor for supplying a potential of the first voltage signal terminal to a fourth node connected to a control electrode of the sixth transistor in response to the first start pulse;
An eighth transistor for supplying the potential of the second voltage signal terminal to the fourth node in response to an output signal of the first stage unit shift register;
The reverse start pulse generation circuit includes:
A third output terminal for outputting the reverse second start pulse;
A third clock terminal to which a predetermined clock signal is input;
A ninth transistor for supplying a clock signal input to the third clock terminal to the third output terminal;
The first and second voltage signal terminals;
A tenth transistor for supplying a potential of the first voltage signal terminal to a fifth node connected to a control electrode of the ninth transistor in response to an output signal of the last unit shift register;
11. A shift register circuit comprising: an eleventh transistor that supplies the potential of the second voltage signal terminal to the fourth node in response to the first start pulse. A shift register circuit according to claim 12,
A reverse reset signal generating circuit for generating a reverse reset signal that is activated after a forward second start pulse during reverse shift;
A forward reset signal generating circuit for generating a forward reset signal that is activated after the backward second start pulse at the time of forward shift;
The forward start pulse generation circuit includes:
A twelfth transistor for discharging the fourth node in response to activation of the reverse reset signal;
The reverse start pulse generation circuit includes:
A shift register circuit, further comprising a thirteenth transistor that discharges the fifth node in response to activation of the forward reset signal. A shift register circuit according to claim 12 or claim 13,
The absolute value of the potential of the first node when the unit shift register activates the output signal is the fourth node when the forward start pulse generation circuit activates the forward second start pulse. The shift register circuit is characterized in that the absolute value of the potential of the second node is larger than the absolute value of the potential of the fifth node when the reverse direction start pulse generation circuit activates the reverse direction second start pulse. A shift register circuit according to any one of claims 11 to 14,
The first node of each of the unit shift registers is
At the time of forward shift, it is discharged in response to the activation of the output signal of one or two subsequent stages,
A shift register circuit which is discharged in response to the activation of the output signal of one or two stages before itself during reverse shift. First to fourth input terminals;
A first output terminal for outputting an output signal;
A first clock terminal to which a predetermined clock signal is input;
A first transistor for supplying a clock signal input to the first clock terminal to the first output terminal;
First and second voltage signal terminals to which first and second voltage signals complementary to each other are supplied;
A second transistor for supplying a potential of the first voltage signal terminal to a first node to which a control electrode of the first transistor is connected;
A third transistor that supplies a potential of the first voltage signal terminal to a second node connected to a control electrode of the second transistor in response to a signal input to the first input terminal;
A first MOS capacitive element coupled between the second input terminal and the second node;
A fourth transistor for supplying the potential of the second voltage signal terminal to the first node;
A fifth transistor that supplies a potential of the second voltage signal terminal to a third node connected to a control electrode of the fourth transistor in response to a signal input to the third input terminal;
A second MOS capacitive element coupled between the fourth input terminal and the third node;
A sixth transistor having a control electrode connected to the first input terminal and supplying the first voltage signal to the first node;
A shift register circuit comprising: a control electrode connected to the third input terminal; and a seventh transistor for supplying the second voltage signal to the first node. The shift register circuit according to claim 16, wherein
An inverter having the first node as an input end;
An eighth transistor having a control electrode connected to the output terminal of the inverter and discharging the output terminal;
A shift register circuit comprising: a control transistor connected to the output terminal of the inverter; and a ninth transistor for discharging the first node. The shift register circuit according to claim 16, wherein
A NOR circuit having the second and third nodes as input terminals;
An eighth transistor having a control electrode connected to the output terminal of the NOR circuit and discharging the output terminal;
A shift register circuit comprising: a control transistor connected to an output terminal of the NOR circuit; and a ninth transistor for discharging the first node.

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