JP2010033122A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device for properly preventing unauthorized copy. <P>SOLUTION: In the storage device, an address analyzing part 203 which detects whether or not the increment operation of an address is operated includes: a load signal generation part 1 for generating a load signal LD; a counter 2 for reading an address signal ADD to be supplied to a memory 100 by using the load signal LD as a trigger, and for setting the address value as its own count value, and for incrementing the count value one by one for output based on a read signal RD; and an address comparing part 3 for comparing the address signal ADD to be supplied to the memory 100 with the counter value of the counter 2, and for outputting a comparison result signal showing the matching/mismatching. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a storage device having an unauthorized copy prevention function.

Conventionally, various storage devices having an unauthorized copy prevention function have been disclosed and proposed (see, for example, Patent Document 1 and Patent Document 2). Many conventional storage devices are configured to store data encrypted using predetermined key information.
JP 2003-59178 A JP 2002-373320 A

  Certainly, in the case of the conventional storage device, even if the stored data is illegally copied, the content is unknown unless decryption processing using predetermined key information is performed. Therefore, it is difficult to use illegally copied data.

  However, the conventional storage device described above makes it difficult to use illegally copied data, and the stored data can be freely read. For this reason, when illegally copied data is analyzed using a high-speed computer and the cipher is decrypted, there is a problem that the contents are freely copied thereafter.

  In view of the above problems, an object of the present invention is to provide a storage device that can appropriately prevent unauthorized copying.

  In order to achieve the above object, a storage device according to the present invention includes a memory for storing data, and whether or not a predetermined monitoring target code accompanying an address jump operation is included in the data read from the memory A code analysis unit for detecting the address; an address analysis unit for detecting whether or not an address increment operation is performed; and executing the monitoring target code with reference to the analysis results of the code analysis unit and the address analysis unit An error detection unit that detects whether or not an address increment operation has been performed; and an output control unit that prohibits output of data stored in the memory based on a determination result of the error detection unit. The address analyzing unit includes: a load signal generating unit that generates a load signal; and the load signal is used as a trigger for the memory. A counter that reads the address signal to be read and sets the address value as its own count value, and thereafter increments the count value one by one based on the read signal; and is supplied to the memory; And an address comparison unit that compares the counter signal with the counter value of the counter and outputs a comparison result signal indicating coincidence / non-coincidence (first configuration).

  In the storage device having the first configuration, the load signal generation unit includes a one-shot generation unit that generates a one-shot signal at the start of reading of the memory; and the load signal is generated from the one-shot signal and the comparison result signal. And a logic circuit for generating a signal (second configuration).

  In the storage device having the second configuration, the one-shot generation unit receives a second pulse after the first pulse of the read signal has arrived after the reset state of the storage device is released. In the meantime, it is preferable to adopt a configuration (third configuration) for generating the one-shot signal having a predetermined logic level.

  With the storage device according to the present invention, unauthorized copying can be prevented appropriately.

  First, a first embodiment of a storage device according to the present invention will be described in detail with reference to FIG. FIG. 1 is a block diagram showing a first embodiment of a storage device according to the present invention.

  As shown in FIG. 1, the storage device of the present embodiment includes a read-only memory 100 (indicated as ROM [Random Access Memory] in FIG. 1) and an unauthorized copy prevention circuit 200. The unauthorized copy prevention circuit 200 includes a code check unit 201, a timing control unit 202, an increment check unit 203, an error detection unit 204, an initial address check unit 205, an OR calculator 206, a selector 207, , Comprising.

  The memory 100 is means for storing data D (such as a program read and executed by a CPU [Central Processing Unit]) in a nonvolatile manner.

  The code check unit 201 is a code analysis unit that analyzes a code included in the data D read from the memory 100. More specifically, the code check unit 201 monitors the data D read from the memory 100, and executes a predetermined monitoring target code (address instruction or address in addition to the jump instruction) accompanied by an address jump operation at the time of execution. And the analysis result is transmitted to the timing control unit 202 and the error detection unit 204. When the data D stored in the memory 100 is subjected to encryption processing or compression processing, the code check unit 201 performs a decryption processing function or decompression of the data D in addition to the code analysis function described above. It is necessary to have a processing function.

  The timing control unit 202 operates in response to an input of a read signal RD instructing reading of the data D, and based on the analysis result obtained by the code check unit 201, the timing check unit 202 increments the execution timing of the monitoring target code. 203 and a means for transmitting to the error detection unit 204.

  The increment check unit 203 is an address analysis unit that analyzes an address operation with respect to the memory 100. More specifically, the increment check unit 203 monitors the address signal ADD supplied to the memory 100 and performs an address increment operation (in this case, an operation for incrementing only one address). Detect whether or not

  The error detection unit 204 is a unit that refers to the analysis results of the code check unit 201 and the increment check unit 203 and determines whether an address operation that matches the code is performed. More specifically, the error detection unit 204 sets an error flag when an address increment operation is detected during execution of the monitoring target code. That is, when the error detection unit 204 detects that the address increment operation has been performed at the timing at which the address jump operation should be performed, the error detection unit 204 determines that there is a possibility of unauthorized copying, and then proceeds to the logical sum calculator 206. The output signal of the transition from low level to high level.

  The initial address check unit 205 monitors the address signal ADD given to the memory 100 to determine whether or not the initial address at the start of reading of the memory 100 matches a predetermined value set in advance. It is a means for setting an error flag when it is detected. That is, the initial address check unit 205 determines that there is a possibility of unauthorized copying when detecting that the reading of the data D is started from an address other than a predetermined value, and outputs an output signal to the logical sum calculator 206. From low level to high level.

  The logical sum calculator 206 is a means for performing a logical sum operation on the output signal of the error detection unit 204 and the output signal of the initial address check unit 205 and outputting the calculation result as a control signal for the selector 207. That is, the control signal of the selector 207 is low level only when both the output signal of the error detection unit 204 and the output signal of the initial address check unit 205 are low level, and is high level in the other cases.

  The selector 207 is an output control unit that prohibits the output of the data D stored in the memory 100 based on the output signal of the logical sum calculator 206. More specifically, the selector 207 selects and outputs the data D read from the memory 100 when the output signal of the logical sum calculator 206 is at a low level, while the output of the logical sum calculator 206. When the signal is at a high level, predetermined dummy data DD is selected and output. The dummy data DD may be a fixed value or a random value.

  Next, the protection operation of the unauthorized copy prevention circuit 200 when reading data from the storage device having the above-described configuration will be described in detail.

  When a legitimate access to the memory 100 is performed, reading of the data D is started with a predetermined value set in advance as an initial address, and an address operation for the memory 100 is also performed in a code included in the data D. Matched. Accordingly, since the output signals of the error detection unit 204 and the initial address check unit 205 are both kept at a low level, the output signal of the logical sum calculator 206 is at a low level, and the selector 207 is read from the memory 100. The data D is selected and output (that is, the data D output permission state).

  On the other hand, when the data D stored in the memory 100 is illegally copied, the address is incremented and stored in the memory 100 regardless of the contents of the code included in the data D. The data D are successively read in the order of their addresses. That is, when the data D is illegally copied, even if the address jump operation should be performed based on the monitoring target code described above, the address increment operation is performed ignoring this, so the address operation for the memory 100 is performed. Is no longer consistent with the code. In such a case, since the output signal of the error detection unit 204 transitions from the low level to the high level, the output signal of the logical sum calculator 206 becomes the high level, and the selector 207 reads the data read from the memory 100. Instead of D, predetermined dummy data DD is selected and output (data D output prohibited state).

  In addition, when illegal copying of the data D stored in the memory 100 is performed, reading of the data D may be started from an address other than a predetermined value set in advance. In such a case, since the output signal of the initial address check unit 205 is shifted from the low level to the high level, the output signal of the logical sum calculator 206 becomes the high level, and the selector 207 detects the detection result of the error detection unit 204. Without waiting for, the predetermined dummy data DD is selected and output.

  As described above, in the storage device according to the present embodiment, the output of the data D stored in the memory 100 can be prohibited under a situation where an illegal copy of the data D is suspected. Thus, unauthorized copying of data D can be prevented more appropriately.

  In the storage device having the above configuration, the code check unit 201 detects an error in the monitoring target code when it is unclear whether or not it involves an address jump operation according to the execution condition. A configuration may be adopted in which the detection unit 204 is instructed to mask an error flag obtained when the monitoring target code is executed.

  By adopting such a configuration, although the legal access to the memory 100 is performed, the monitored code does not accompany the address jump operation according to the conditions at the time of execution. However, since this is not erroneously determined as an error, unnecessary output prohibition of the data D can be avoided.

  However, the code check unit 201 may be configured to stop the subsequent mask instruction when the mask instruction to the error detection unit 204 reaches a predetermined value. By adopting such a configuration, for example, although there is an upper limit on the number of times the code is described whether it is unclear whether or not an address jump operation is involved depending on the execution condition, the upper limit is set. Since it is possible to avoid excessively masking the error flag of the error detection unit 204 beyond the value, it is possible to prevent unauthorized copying of the data D while reducing erroneous detection of errors.

  Next, a second embodiment of the storage device according to the present invention will be described in detail with reference to FIG. FIG. 2 is a block diagram showing a second embodiment of the storage device according to the present invention.

  As shown in FIG. 2, the storage device according to the present embodiment has substantially the same configuration as that of the first embodiment, and is characterized in that a decoder 208 is provided instead of the selector 207. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, thereby omitting a redundant description, and in the following, detailed description centering on the decoder 208 that is a characteristic part of the present embodiment. To do.

  In the storage device of the present embodiment, the memory 100 stores encrypted data D. Note that the encryption processing applied to the data D may be single or double.

  The decoder 208 is an output control unit that prohibits the output of the data D stored in the memory 100 based on the output signal of the logical sum calculator 206. More specifically, when outputting the data D read from the memory 100, the decoder 208 performs a correct decryption process using predetermined key information based on the output signal of the logical sum calculator 206. Whether to perform random decryption processing intentionally using dummy key information.

  With such a configuration, in a situation where an illegal copy of the data D is suspected, the decoder 208 subjects the data D read from the memory 100 to an extremely random decryption process and outputs it. Accordingly, the contents of data illegally output from the storage device (herein referred to as dummy data DD according to the first embodiment) are unknown, and cannot be used.

  Further, since the dummy data DD is created through a random decryption process by the decoder 208, it is completely different from the data D stored in the memory 100 and is used for the encryption process of the data D. It is no longer possible to perform the decryption process with the existing key information. Therefore, even if the dummy data DD is analyzed by a high speed computer, it is very difficult to read the contents of the data D. In particular, if the decoder 208 is configured to perform random decryption processing while switching a plurality of pieces of dummy key information, the analysis processing of the dummy data DD is virtually impossible.

  As described above, in the storage device according to the present embodiment, the output of the data D stored in the memory 100 can be prohibited, so that illegal copying of the data D can be more appropriately prevented as compared with the conventional configuration. It becomes possible.

  In the above description, the configuration of intentionally performing random decryption processing has been described as an example. However, the configuration of the present invention is not limited to this, and decryption different from correct decryption processing is performed. Any configuration may be used as long as processing is performed.

  Next, a third embodiment of the storage device according to the present invention will be described in detail with reference to FIG. FIG. 3 is a block diagram showing a third embodiment of the storage device according to the present invention.

  As shown in FIG. 3, the storage device according to the present embodiment has substantially the same configuration as that of the first embodiment, and is characterized in that an encoder 209 is provided instead of the selector 207. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant description is omitted. In the following, detailed description centering on the encoder 209 that is a characteristic part of the present embodiment. To do.

  The encoder 209 is an output control unit that prohibits output of the data D stored in the memory 100 based on the output signal of the logical sum calculator 206. More specifically, when outputting the data D read from the memory 100, the encoder 209 performs a correct encryption process using predetermined key information based on the output signal of the logical sum calculator 206. Whether to perform random encryption processing intentionally using dummy key information.

  By adopting such a configuration, the encoder 209 performs completely random encryption processing (in other words, reversibility thereof) on the data D read from the memory 100 under a situation where an illegal copy of the data D is suspected. Encryption processing that does not assume Accordingly, the contents of data illegally output from the storage device (herein referred to as dummy data DD according to the first embodiment) are unknown, and cannot be used. In particular, if the encoder 209 is configured to perform random encryption processing while switching a plurality of dummy key information, the decryption processing of the dummy data DD is practically impossible.

  As described above, in the storage device according to the present embodiment, the output of the data D stored in the memory 100 can be prohibited, so that illegal copying of the data D can be more appropriately prevented as compared with the conventional configuration. It becomes possible.

  In the above description, the configuration of intentionally performing random encryption processing has been described as an example. However, the configuration of the present invention is not limited to this, and encryption different from the correct encryption processing is performed. Any configuration may be used as long as processing is performed.

  Next, a fourth embodiment of the storage device according to the present invention will be described in detail with reference to FIG. FIG. 4 is a block diagram showing a fourth embodiment of the storage device according to the present invention.

  As shown in FIG. 4, the storage device according to the present embodiment has substantially the same configuration as that of the first embodiment described above, and is characterized by having an address control unit 210 instead of the selector 207. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant description is omitted. Hereinafter, the details of the address control unit 210 that is a characteristic part of the present embodiment will be mainly described. I will give a simple explanation.

  The address control unit 210 is an output control unit that prohibits the output of the data D stored in the memory 100 based on the output signal of the logical sum calculator 206. More specifically, the address control unit 210 permits an address operation to the memory 100 when the output signal of the logical sum calculator 206 is at a low level, while the output signal of the logical sum calculator 206 is at a high level. In some cases, the address operation for the memory 100 is prohibited.

  By adopting such a configuration, the address control unit 210 prohibits the address operation for the memory 100 and prohibits the reading of the data D stored in the memory 100 under a situation where unauthorized copying of the data D is suspected. Therefore, illegal copying of data D can be prevented more appropriately than in the conventional configuration.

  Next, the configuration of the increment check unit 203 and the error detection unit 204 will be described in detail with reference to FIG. FIG. 5 is a block diagram illustrating a configuration example of the increment check unit 203 and the error detection unit 204. The circuit configuration described below is based on the premise that one code D includes both a code and an address (a so-called CPU direct command is stored as data D).

  As shown in FIG. 5, the increment check unit 203 of this configuration example includes a load signal generation unit 1, an increment counter 2, and an address comparison unit 3, and the error detection unit 204 includes a D flip-flop. 4, an exclusive OR calculator 5, and a D flip-flop 5.

  The load signal generation unit 1 is a unit that generates a load signal LD for causing the increment counter 2 to read the address signal ADD supplied to the memory 100, and includes a one-shot generation unit 11 and a logical sum calculator 12. Become. The one-shot generation unit 11 is a unit that generates a one-shot signal from the read signal RD (read timing control signal for data D) when reading from the memory 100 is started. Further, the logical sum calculator 12 performs a logical sum operation between the one-shot signal generated by the one-shot generation unit 11 and the comparison result signal generated by the address comparison unit 3, and outputs the calculation result as a load signal LD. It is means to do.

  The increment counter 2 reads the address signal ADD supplied to the memory 100 using the load signal LD input from the load signal generation unit 1 as a trigger, sets the address value as its own count value, and thereafter Each time the pulse of the read signal RD arrives, the count value is incremented by one and output.

  The address comparison unit 3 is means for comparing the address signal ADD supplied to the memory 100 with the counter value of the increment counter 2 and outputting a comparison result signal indicating the match / mismatch. The comparison result signal is, for example, a binary signal that is at a low level if the address signal ADD and the counter value of the increment counter 2 match each other, and that is a high level if they do not match.

  The D flip-flop 4 is means for latching and outputting the output signal of the code check unit 201 using the read signal RD as a trigger. Note that the output signal of the code check unit 201 is, for example, a binary signal that is at a high level if the data D includes the above-described monitoring target code and is at a low level if the data D is not included.

  The exclusive OR calculator 5 is means for performing an exclusive OR operation on the output signal of the address comparator 3 and the output signal of the D flip-flop 4 and outputting the calculation result. That is, the output signal of the exclusive OR calculator 5 is low level if the logic level of the output signal of the address comparator 3 and the output signal of the D flip-flop 4 match each other, and is high level if they do not match. It becomes.

  The D flip-flop 6 is a means for latching the output signal of the exclusive OR calculator 5 using the read signal RD as a trigger and outputting this as an error flag ERR to the OR calculator 206 (not shown in FIG. 5). is there.

  In FIG. 5, the timing control unit 202 is not clearly shown as an independent circuit block. However, the operations of the one-shot generation unit 11, the increment counter 2, and the D flip-flops 4 and 6 are all read. Synchronization is based on signal RD. That is, in the configuration illustrated in FIG. 5, it can be said that the timing control unit 202 is included in these circuit blocks as means for realizing the synchronization function of the increment check unit 203 and the error detection unit 204.

  Next, operations of the increment check unit 203 and the error detection unit 204 configured as described above will be described in detail with reference to an example in which a valid access to the memory 100 is performed.

  When the one-shot signal of the one-shot signal generator 11 is raised to a high level at the start of reading from the memory 100, the load signal LD output from the OR calculator 12 also becomes a high level. The increment counter 2 uses the load signal LD as a trigger to read the address signal ADD (initial address) supplied to the memory 100, sets the address value as its own count value, and thereafter reads the read signal RD. Each time a pulse arrives, the count value is incremented by one and output.

  Therefore, if the monitoring target code is not included in the data D read from the memory 100, the address signal ADD supplied to the memory 100 is incremented one by one by the host (CPU), and the increment counter 2 Since the count value is incremented by one each time the pulse of the read signal RD arrives, both values coincide with each other, and the comparison result signal generated by the address comparison unit 3 is at a low level. At this time, the code check unit 201 sets the output signal to the low level based on the determination that the data D does not include the monitoring target code. As a result, all of the logic signals input to the exclusive OR calculator 5 have the same logic level (low level), so that the output signal (and hence the error flag ERR) becomes the low level.

  When the monitoring target code is included in the data D read from the memory 100, the address signal ADD supplied to the memory 100 is jumped to a predetermined address value by the host (CPU). As for the count value, since the same increment operation as described above is continued, the two values do not coincide with each other, and the comparison result signal generated by the address comparison unit 3 becomes high level. At this time, the code check unit 201 sets the output signal to the high level based on the determination that the monitoring target code is included in the data D. Accordingly, since all the logic signals input to the exclusive OR calculator 5 have the same logic level (high level), the output signal (and hence the error flag ERR) becomes the low level.

  Note that when the comparison result signal rises to a high level, the load signal LD output from the logical sum calculator 12 becomes a high level. The increment counter 2 uses the load signal LD as a trigger to read an address signal ADD (address after jump) supplied to the memory 100, sets the address value as its own count value, and thereafter reads the read signal. Each time an RD pulse arrives, the count value is incremented by one and output. Therefore, after the address is jumped, the address signal ADD supplied to the memory 100 is again matched with the count value of the increment counter 2, so that the subsequent address comparison operation is not hindered.

  As described above, when a legitimate access to the memory 100 is performed, an address operation that matches the code of the data D read from the memory 100 is performed, and the output signal of the code check unit 201 and the increment check unit Since the output signals 203 are at the same logic level, the error flag ERR is maintained at a low level.

  Next, a case where an illegal copy of the data D stored in the memory 100 is suspected will be described in detail. As described above, when the data D stored in the memory 100 is illegally copied, the address increment operation is performed regardless of the contents of the code included in the data D. The data D stored in the memory 100 is continuously read in the order of the addresses. That is, when the data D is illegally copied, even if the address jump operation should be performed based on the monitoring target code, the address increment operation is performed ignoring this. As a result, the address signal ADD supplied to the memory 100 and the count value of the increment counter 2 remain in agreement with each other, so that the comparison result signal generated by the address comparison unit 3 is at a low level. On the other hand, the code check unit 201 sets the output signal to a high level based on the determination that the data D includes a monitoring target code. Accordingly, since the logic signals input to the exclusive OR calculator 5 have different logic levels, their output signals (and hence the error flag ERR) are at a high level.

  As described above, when an illegal copy of the data D stored in the memory 100 is suspected, an address operation matching the code of the data D read from the memory 100 is not performed, and the output signal and the increment check of the code check unit 201 are performed. Since the output signals of the unit 203 have different logic levels, the error flag ERR is changed to a high level.

  Next, the configuration of the one-shot generation unit 11 will be described in detail with reference to FIG. FIG. 6 is a block diagram illustrating a configuration example of the one-shot generation unit 11.

  As shown in FIG. 6, the one-shot generation unit 11 of this configuration example includes an inverter 111, a D flip-flop 112 and a D flip-flop 113, and an AND operator 114. The input end of the inverter 111 is connected to the application end of the read signal RD. The clock input terminals of the D flip-flops 112 and 113 are both connected to the output terminal of the inverter 111. A data input terminal (D) of the D flip-flop 112 is connected to a high-level signal application terminal (for example, a power supply line). The data input terminal (D) of the D flip-flop 113 is connected to the output terminal (Q) of the D flip-flop 112. The reset input terminals of the D flip-flops 112 and 113 are both connected to the application terminal of the reset signal RST. One input terminal of the AND operator 114 is connected to the output terminal (Q) of the D flip-flop 112. The other input terminal of the AND operator 114 is connected to the inverting output terminal (Q bar) of the D flip-flop 113. Note that the output terminal of the AND operator 114 corresponds to the output terminal of the one-shot generator 11 (the output terminal of the one-shot signal Sd).

  Next, the operation of the one-shot generation unit 11 having the above configuration will be described in detail with reference to FIG. FIG. 7 is a timing chart for explaining the operation of the one-shot generation unit 11. From the top, the reset signal RST, the read signal RD, and the logic signals (inverted read of the inverter 111) of each part of the one-shot generation unit 11 are illustrated. The signal Sa, the output signal Sb of the D flip-flop 112, the inverted output signal Sc of the D flip-flop 113, and the one-shot signal Sd of the AND operator 114) are depicted. Note that the logic signal shown here is merely an example, and the logic level may be inverted.

  When the reset signal RST transitions from the high level to the low level and the reset state of the memory device is released, the output signal Sb of the D flip-flop 112 is set to the low level, and the inverted output signal Sc of the D flip-flop 113 is the high level. It is said. After that, when the first pulse P1 falls to the read signal RD, the D flip-flop 112 takes in the high level signal that is always applied to the data input terminal (D) with the rising edge of the inverted read signal Sa as a trigger. The output signal Sb is set to a high level. Further, the D flip-flop 113 takes the output signal Sb (low level) of the D flip-flop 112 applied to the data input terminal (D) at that time as a trigger using the rising edge of the inverted read signal Sa, and outputs the inverted output. The signal Sc is set to a high level. Accordingly, the one-shot signal Sd obtained by the logical product operation of the output signal Sb and the inverted output signal Sc becomes high level.

  When the second pulse P2 falls to the read signal RD after the one-shot signal Sd is set to the high level, the D flip-flop 112 uses the rising edge of the inverted read signal Sa as a trigger to trigger the data input terminal (D) The high level signal that is always applied to is taken in, and the output signal Sb is set to the high level. The D flip-flop 113 takes the output signal Sb (high level) of the D flip-flop 112 applied to the data input terminal (D) at that time as a trigger by using the rising edge of the inverted read signal Sa as a trigger, and outputs the inverted signal. The signal Sc is set to a low level. Therefore, the one-shot signal Sd obtained by the logical product operation of the output signal Sb and the inverted output signal Sc is at a low level.

  Thereafter, even when the pulse of the read signal RD is sequentially lowered, the signal processing similar to the above is performed, and the one-shot signal Sd is maintained at the low level. That is, in the one-shot generation unit 11, after the storage device is released from the reset state, a predetermined logic level (from the first pulse P1 of the read signal RD to the arrival of the second pulse P2) In this example, a one-shot signal Sd having a high level is generated.

  As described above, when the one-shot signal of the one-shot signal generation unit 11 is raised to a high level, the load signal LD output from the OR calculator 12 also becomes a high level. The address signal ADD (initial address) supplied to the memory 100 is read using the load signal LD as a trigger.

  With such a configuration, the one-shot generation unit 11 (and hence the increment check unit 203) can be realized with a very simple and simple circuit configuration.

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention.

  For example, in the above-described embodiment, as a method for determining whether or not an address operation that matches a code is performed, it is detected whether or not an address increment operation has been performed when executing a code that involves an address jump operation. Although the configuration has been described as an example, the configuration of the present invention is not limited to this, and other methods may be used.

  In the above embodiment, the configuration using the read-only memory 100 as an example of the storage means for the data D has been described. However, the configuration of the present invention is not limited to this, and the configuration of the data D A readable / writable flash memory or an EEPROM [Electrically Erasable and Programmable Read Only Memory] may be used.

  The present invention can be used as a technique for preventing unauthorized copying of storage devices used in game cartridges, IC cards, security devices, and the like.

These are block diagrams which show 1st Embodiment of the memory | storage device which concerns on this invention. These are block diagrams which show 2nd Embodiment of the memory | storage device based on this invention. These are block diagrams which show 3rd Embodiment of the memory | storage device based on this invention. These are block diagrams which show 4th Embodiment of the memory | storage device based on this invention. FIG. 4 is a block diagram illustrating a configuration example of an increment check unit 203 and an error detection unit 204. FIG. 3 is a block diagram illustrating a configuration example of a one-shot generation unit 11. These are timing charts for explaining the operation of the one-shot generator 11.

Explanation of symbols

100 Read only memory (ROM)
200 Unauthorized Copy Prevention Circuit 201 Code Check Unit (Code Analysis Unit)
202 Timing control unit 203 Increment check unit (address analysis unit)
204 Error detection unit 205 Initial address check unit 206 OR operation unit 207 selector 208 decoder 209 encoder 210 address control unit 1 load signal generation unit 11 one shot generation unit 111 inverter 112, 113 D flip-flop 114 AND operation unit 12 logical sum Operation unit 2 Increment counter 3 Address comparison unit 4 D flip-flop 5 Exclusive OR operator 6 D flip-flop

Claims (3)

Memory for storing data;
A code analysis unit for detecting whether or not the data read from the memory includes a predetermined monitoring target code accompanied by an address jump operation;
An address analysis unit for detecting whether or not an address increment operation is performed;
An error detection unit that refers to the analysis results of the code analysis unit and the address analysis unit and detects whether or not an address increment operation has been performed when the monitored code is executed;
An output control unit that prohibits output of data stored in the memory based on a determination result of the error detection unit;
A storage device comprising:
The address analysis unit
A load signal generator for generating a load signal;
The address signal supplied to the memory is read using the load signal as a trigger, the address value is set as its own count value, and thereafter, the count value is incremented by one based on the read signal. A counter to output;
An address comparison unit that compares an address signal supplied to the memory with a counter value of the counter and outputs a comparison result signal indicating the match / mismatch;
A storage device comprising: The load signal generator is
A one-shot generation unit that generates a one-shot signal at the start of reading of the memory; and a logic circuit that generates the load signal from the one-shot signal and the comparison result signal;
The storage device according to claim 1, further comprising:   The one-shot generation unit is configured to perform the one-shot generation at a predetermined logic level after the first pulse of the read signal arrives until the second pulse arrives after the reset state of the storage device is released. The storage device according to claim 2, wherein a shot signal is generated.

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