JP2010032458A

JP2010032458A - Circuit board inspecting device and circuit board inspection method

Info

Publication number: JP2010032458A
Application number: JP2008197285A
Authority: JP
Inventors: Takahiro Shimizu; 隆弘清水; Homare Shimodaira; 誉下平
Original assignee: Hioki EE Corp
Current assignee: Hioki EE Corp
Priority date: 2008-07-31
Filing date: 2008-07-31
Publication date: 2010-02-12
Anticipated expiration: 2028-07-31
Also published as: JP5215072B2

Abstract

【課題】電子部品が実装された回路基板や部品内蔵型の回路基板に対する絶縁検査の検査精度および検査効率を向上する。
【解決手段】電子部品（Ｅ１〜Ｅ６）を介して接続されている各導体パターン（Ｐ１〜Ｐ１８）で構成される第１導体パターン群Ｇｆ１〜Ｇｆ３内の各導体パターンを互いに同電位としつつ高電圧信号を供給する第１信号供給処理と、電子部品に接続されていない全ての導体パターン（Ｐ１９〜Ｐ２３）で構成される第２導体パターン群Ｇｓ内の各導体パターンを互いに接続した状態で低電圧信号を供給する第２信号供給処理とを実行し、第１信号供給処理が実行されている状態において高電圧信号が供給されている導体パターン間の絶縁状態を検査する第１検査を実行し、第２信号供給処理が実行されている状態において低電圧信号が供給されている導体パターン間の絶縁状態を検査する第２検査を実行する。
【選択図】図２An object of the present invention is to improve the inspection accuracy and inspection efficiency of an insulation inspection for a circuit board on which an electronic component is mounted or a circuit board with a built-in component.
SOLUTION: Each conductor pattern in a first conductor pattern group Gf1 to Gf3 composed of conductor patterns (P1 to P18) connected via electronic components (E1 to E6) is set to have the same potential while being high. The first signal supply process for supplying the voltage signal and the conductor patterns in the second conductor pattern group Gs composed of all the conductor patterns (P19 to P23) not connected to the electronic component are connected to each other. A second signal supply process for supplying a voltage signal, and a first inspection for inspecting an insulation state between conductor patterns to which a high voltage signal is supplied in a state in which the first signal supply process is performed. Then, the second inspection for inspecting the insulation state between the conductor patterns to which the low voltage signal is supplied in the state where the second signal supply processing is being executed is executed.
[Selection] Figure 2

Description

本発明は、複数の導体パターン、および導体パターンに接続された電子部品を有する回路基板における各導体パターン間の絶縁状態を検査する回路基板検査装置および回路基板検査方法に関するものである。 The present invention relates to a circuit board inspection apparatus and a circuit board inspection method for inspecting an insulation state between conductor patterns in a circuit board having a plurality of conductor patterns and electronic components connected to the conductor patterns.

この種の回路基板検査装置として、特開２００１−６６３５１号公報に開示された回路基板検査装置が知られている。この回路基板検査装置は、フィクスチャおよび接続計測部を備えて、回路基板における各導体パターン（ランドパターン）の導通検査や各導体パターン間の絶縁検査を実行可能に構成されている。この場合、フィクスチャは、回路基板の各導体パターンに対応する複数のプローブピンがその上面に突出形成された下側フィクスチャと、回路基板の他面に実装された各電子部品間の隙間に対応して複数の当接ピンがその下面に形成されると共に昇降機構によって上下方向に移動させられる上側フィクスチャとで構成されている。この回路基板検査装置では、下側フィクスチャと上側フィクスチャとの間に回路基板を挟み込むことによって下側フィクスチャのプローブピンを各導体パターンに接触させて所定のプローブピンに信号を供給した状態で、接続計測部がプローブピンを介して入力する信号に基づいて各導体パターンの導通検査や各導体パターン間の絶縁検査を行う。 As this type of circuit board inspection apparatus, a circuit board inspection apparatus disclosed in Japanese Patent Laid-Open No. 2001-66351 is known. The circuit board inspection apparatus includes a fixture and a connection measurement unit, and is configured to be able to perform a conduction inspection of each conductor pattern (land pattern) on the circuit board and an insulation inspection between the conductor patterns. In this case, the fixture is a gap between a lower fixture in which a plurality of probe pins corresponding to each conductor pattern of the circuit board are formed to protrude on the upper surface and each electronic component mounted on the other surface of the circuit board. Correspondingly, a plurality of contact pins are formed on the lower surface of the contact pin, and the upper fixture is moved up and down by an elevating mechanism. In this circuit board inspection apparatus, the circuit board is sandwiched between the lower fixture and the upper fixture so that the probe pin of the lower fixture is brought into contact with each conductor pattern and a signal is supplied to a predetermined probe pin. Thus, the continuity inspection of each conductor pattern and the insulation inspection between the conductor patterns are performed based on the signal input by the connection measuring unit via the probe pin.

この場合、各導体パターン間の絶縁検査を行う際には、各導体パターンに高電圧を供給（印加）する必要があるため、電子部品が実装された回路基板や基板内に電子部品が内蔵された部品内蔵型の回路基板に対してこの絶縁検査を行う際には、高電圧の印加によって電子部品が損傷するおそれがある。このため、発明者らは、電子部品の損傷を回避しつつ導体パターン間の絶縁検査を行うことが可能な回路基板検査装置を開発している。この回路基板検査装置では、電子部品によって互いに接続されている導体パターンを１つの導体パターン群として規定して、この導体パターン群内の各導体パターンを互いに同電位としつつ導体パターン群外の導体パターン（例えば、電子部品に接続されていない単独の導体パターン）との間に検査用信号を供給（印加）して、検査用信号が供給されている導体パターン間の絶縁検査が行われる。このため、この回路基板検査装置では、同一導体パターン群内における各導体パターン間に電位差が生じることに起因しての、導体パターン間に配設された電子部品が損傷する事態を回避することが可能となっている。
特開２００１−６６３５１号公報（第３−５頁、第１図） In this case, when conducting an insulation inspection between the conductor patterns, it is necessary to supply (apply) a high voltage to each conductor pattern, so that the electronic component is embedded in the circuit board on which the electronic component is mounted or the board. When this insulation test is performed on a circuit board with a built-in component, there is a risk that the electronic component may be damaged by the application of a high voltage. For this reason, the inventors have developed a circuit board inspection apparatus capable of performing an insulation inspection between conductor patterns while avoiding damage to electronic components. In this circuit board inspection apparatus, conductor patterns connected to each other by electronic components are defined as one conductor pattern group, and the conductor patterns outside the conductor pattern group are set to have the same potential as each conductor pattern in the conductor pattern group. An inspection signal is supplied (applied) to (for example, a single conductor pattern not connected to an electronic component), and an insulation inspection between the conductor patterns to which the inspection signal is supplied is performed. For this reason, in this circuit board inspection apparatus, it is possible to avoid a situation where an electronic component disposed between conductor patterns is damaged due to a potential difference between the conductor patterns in the same conductor pattern group. It is possible.
JP 2001-66351 A (page 3-5, FIG. 1)

ところが、発明者が既に開発している上記の回路基板検査装置にも、改善すべき以下の課題がある。すなわち、この回路基板検査装置では、導体パターン群内の各導体パターンを互いに同電位とすることで、電子部品の損傷を回避している。しかしながら、この回路基板検査装置では、導体パターン群内の導体パターンと導体パターン群外の導体パターンとの間の絶縁検査を行うことが可能なものの、電子部品を介して接続されている導体パターン群内の各導体パターン間の絶縁検査を行うことが困難である。また、この回路基板検査装置では、例えば、導体パターン群内のいずれかの導体パターンと上記した単独の導体パターンとの間の絶縁状態が不良である（短絡している）との検査結果を得たとしても、導体パターン群内のどの導体パターンが単独の導体パターンに短絡しているか、つまり導体パターン群内の個々の導体パターンと単独の導体パターンとの絶縁状態の良否を検査することは困難である。このため、この回路基板検査装置では、電子部品が実装された回路基板や部品内蔵型の回路基板を検査対象とする絶縁検査の検査精度を向上させるのが困難であり、この点の改善が望まれている。この場合、電子部品に接続されている導体パターンについては、電子部品の損傷を回避可能な低電圧を供給して絶縁検査を行う方法も考えられるが、この方法を採用した場合には、高電圧を供給しての絶縁検査に加えて、低電圧を供給しての絶縁検査を行うこととなるため、単独の導体パターンが数多く存在するときには、検査回数が増加し検査効率の向上が困難となる。 However, the circuit board inspection apparatus already developed by the inventor also has the following problems to be improved. In other words, in this circuit board inspection apparatus, each conductor pattern in the conductor pattern group is set to the same potential to avoid damage to electronic components. However, in this circuit board inspection apparatus, although it is possible to perform an insulation inspection between the conductor pattern in the conductor pattern group and the conductor pattern outside the conductor pattern group, the conductor pattern group connected via the electronic component It is difficult to perform an insulation test between the respective conductor patterns. Moreover, in this circuit board inspection apparatus, for example, an inspection result is obtained that the insulation state between any one of the conductor patterns in the conductor pattern group and the above-described single conductor pattern is poor (short-circuited). Even so, it is difficult to inspect which conductor pattern in the conductor pattern group is short-circuited to the single conductor pattern, that is, whether the insulation state between the individual conductor pattern and the single conductor pattern in the conductor pattern group is good or bad. It is. For this reason, in this circuit board inspection apparatus, it is difficult to improve the inspection accuracy of the insulation inspection on the circuit board on which the electronic component is mounted or the circuit board with a built-in component, and this point should be improved. It is rare. In this case, for the conductor pattern connected to the electronic component, a method of performing insulation inspection by supplying a low voltage capable of avoiding damage to the electronic component is conceivable. In addition to the insulation inspection by supplying low voltage, the insulation inspection is performed by supplying low voltage. Therefore, when there are a large number of single conductor patterns, the number of inspections increases and it is difficult to improve the inspection efficiency. .

本発明は、かかる改善すべき課題に鑑みてなされたものであり、電子部品が実装された回路基板や部品内蔵型の回路基板に対する絶縁検査の検査精度および検査効率を向上し得る回路基板検査装置および回路基板検査方法を提供することを主目的とする。 The present invention has been made in view of the problems to be improved, and is a circuit board inspection apparatus capable of improving the inspection accuracy and inspection efficiency of insulation inspection for a circuit board on which electronic components are mounted or a circuit board with a built-in component. And it aims at providing a circuit board inspection method.

上記目的を達成すべく請求項１記載の回路基板検査装置は、複数の導体パターンおよび当該導体パターンに接続された電子部品を有する回路基板の当該各導体パターンに対して検査用信号を供給する検査用信号供給部と、前記検査用信号の供給に伴って生じる物理量に基づいて前記導体パターン間の絶縁状態を検査する検査部とを備えた回路基板検査装置であって、前記検査用信号供給部は、前記電子部品を介して接続されている前記各導体パターンで構成される第１導体パターン群内の当該各導体パターンを互いに同電位としつつ当該第１導体パターン群外の前記導体パターンとの間に前記検査用信号としての高電圧信号を供給する第１信号供給処理と、前記電子部品に接続されていない全ての前記導体パターンで構成される第２導体パターン群内の当該各導体パターンを互いに接続した状態で当該第２導体パターン群外の前記導体パターンとの間に前記検査用信号としての低電圧信号を供給する第２信号供給処理とを実行し、前記検査部は、前記第１信号供給処理が実行されている状態において、前記高電圧信号が供給されている前記導体パターン間の絶縁状態を検査する第１検査を実行すると共に、前記第２信号供給処理が実行されている状態において、前記低電圧信号が供給されている前記導体パターン間の絶縁状態を検査する第２検査を実行する。 To achieve the above object, a circuit board inspection apparatus according to claim 1, wherein an inspection signal is supplied to each conductor pattern of a circuit board having a plurality of conductor patterns and electronic parts connected to the conductor patterns. A circuit board inspection apparatus comprising: an inspection signal supply unit; and an inspection unit that inspects an insulation state between the conductor patterns based on a physical quantity that is generated when the inspection signal is supplied. The conductor patterns in the first conductor pattern group composed of the conductor patterns connected via the electronic component are at the same potential as the conductor patterns outside the first conductor pattern group. A first signal supply process for supplying a high voltage signal as the inspection signal in between, and a second conductor pattern composed of all the conductor patterns not connected to the electronic component A second signal supply process for supplying a low voltage signal as the inspection signal between the conductor patterns outside the second conductor pattern group in a state where the conductor patterns in the conductor group are connected to each other. The inspection unit performs a first inspection for inspecting an insulation state between the conductor patterns to which the high voltage signal is supplied in a state in which the first signal supply process is being performed, and the second In a state where the signal supply process is being performed, a second inspection is performed for inspecting an insulation state between the conductor patterns to which the low voltage signal is being supplied.

また、請求項２記載の回路基板検査装置は、請求項１記載の回路基板検査装置において、前記電子部品が接続されている導体パターンを特定可能な接続データを記憶する記憶部と、前記接続データに基づいて前記第１導体パターン群および前記第２導体パターン群を特定する特定処理を実行する処理部とを備えている。 The circuit board inspection apparatus according to claim 2 is the circuit board inspection apparatus according to claim 1, wherein the storage unit stores connection data that can identify a conductor pattern to which the electronic component is connected, and the connection data. And a processing unit that executes a specifying process for specifying the first conductor pattern group and the second conductor pattern group.

また、請求項３記載の回路基板検査装置は、請求項１または２記載の回路基板検査装置において、前記検査用信号供給部は、前記第２信号供給処理において、抵抗値が所定値以下の前記電子部品を介して接続されている前記導体パターンを互いに同電位としつつ前記低電圧信号を供給する。 The circuit board inspection apparatus according to claim 3 is the circuit board inspection apparatus according to claim 1 or 2, wherein the inspection signal supply unit has a resistance value equal to or less than a predetermined value in the second signal supply processing. The low voltage signal is supplied while the conductor patterns connected via the electronic component are at the same potential.

また、請求項４記載の回路基板検査方法は、複数の導体パターンおよび当該導体パターンに接続された電子部品を有する回路基板の当該各導体パターンに対して検査用信号を供給し、前記検査用信号の供給に伴って生じる物理量に基づいて前記導体パターン間の絶縁状態を検査する回路基板検査方法であって、前記電子部品を介して接続されている前記各導体パターンで構成される第１導体パターン群内の当該各導体パターンを互いに同電位としつつ当該第１導体パターン群外の前記導体パターンとの間に前記検査用信号としての高電圧信号を供給する第１信号供給処理と、前記電子部品に接続されていない全ての前記導体パターンで構成される第２導体パターン群内の当該各導体パターンを互いに接続した状態で当該第２導体パターン群外の前記導体パターンとの間に前記検査用信号としての低電圧信号を供給する第２信号供給処理とを実行し、前記第１信号供給処理を実行している状態において、前記高電圧信号を供給している前記導体パターン間の絶縁状態を検査する第１検査を実行すると共に、前記第２信号供給処理を実行している状態において、前記低電圧信号を供給している前記導体パターン間の絶縁状態を検査する第２検査を実行する。 The circuit board inspection method according to claim 4 supplies an inspection signal to each of the conductor patterns of the circuit board having a plurality of conductor patterns and electronic components connected to the conductor patterns, and the inspection signal A circuit board inspection method for inspecting an insulation state between the conductor patterns on the basis of a physical quantity generated with the supply of a first conductor pattern comprising the conductor patterns connected via the electronic component A first signal supply process for supplying a high-voltage signal as the inspection signal between the conductor patterns outside the first conductor pattern group while keeping the conductor patterns in the group at the same potential; and the electronic component Outside the second conductor pattern group in a state in which the conductor patterns in the second conductor pattern group composed of all the conductor patterns not connected to the terminal are connected to each other Performing a second signal supply process for supplying a low voltage signal as the inspection signal between the conductor pattern and supplying the high voltage signal in a state in which the first signal supply process is being performed. Insulating state between the conductor patterns supplying the low voltage signal in a state where the first inspection for inspecting the insulating state between the conductor patterns is performed and the second signal supply process is being performed A second inspection for inspecting is performed.

請求項１記載の回路基板検査装置、および請求項４記載の回路基板検査方法では、第１導体パターン群内の各導体パターンを互いに同電位としつつ高電圧信号を供給する第１信号供給処理と、第２導体パターン群内の各導体パターンを互いに接続した状態で低電圧信号を供給する第２信号供給処理とを実行し、第１信号供給処理を実行している状態において高電圧信号を供給している導体パターン間の絶縁状態を検査する第１検査を実行すると共に、第２信号供給処理を実行している状態において低電圧信号を供給している導体パターン間の絶縁状態を検査する第２検査を実行する。このため、この回路基板検査装置および回路基板検査方法によれば、第１検査を実行することで、２つの第１導体パターン群間の絶縁の良否や、第１導体パターン群と電子部品に接続されていない単独の導体パターンとの間の絶縁状態の良否を、電子部品を破損させることなく行うことができるのに加えて、第２検査を実行することで、従来の回路基板検査装置および回路基板検査方法では困難であった第１導体パターン群内における導体パターン間の絶縁状態の良否や、第１導体パターン群内の個々の導体パターンと単独の導体パターンとの間の絶縁状態の良否を電子部品を破損させることなく確実かつ容易に行うことができる。したがって、この回路基板検査装置および回路基板検査方法によれば、絶縁検査の検査精度を十分に向上することができる。また、この回路基板検査装置および回路基板検査方法によれば、第２導体パターン群内の各導体パターンを互いに接続した状態、つまり、第２導体パターン群内の各導体パターンを１つにグループ化した状態で第２検査を実行するため、単独の導体パターンが数多く存在したとしても、少ない回数の第２信号供給処理および第２検査で全ての導体パターン間の絶縁状態を検査することができる。したがって、この回路基板検査装置および回路基板検査方法によれば、絶縁検査の検査効率を十分に向上することができる。 The circuit board inspection apparatus according to claim 1 and the circuit board inspection method according to claim 4, wherein the first signal supply process supplies a high voltage signal while keeping the conductor patterns in the first conductor pattern group at the same potential. And a second signal supply process for supplying a low voltage signal in a state where the respective conductor patterns in the second conductor pattern group are connected to each other, and a high voltage signal is supplied in a state in which the first signal supply process is being executed. The first inspection for inspecting the insulation state between the conductor patterns is performed, and the insulation state between the conductor patterns for supplying the low voltage signal in the state in which the second signal supply process is being executed 2 Perform inspection. Therefore, according to the circuit board inspection apparatus and the circuit board inspection method, by performing the first inspection, the quality of the insulation between the two first conductor pattern groups and the connection between the first conductor pattern group and the electronic component are achieved. In addition to being able to check the quality of the insulation state with a single conductor pattern that has not been performed without damaging the electronic component, the second inspection is performed, whereby a conventional circuit board inspection apparatus and circuit Whether the insulation state between the conductor patterns in the first conductor pattern group, which was difficult with the board inspection method, and the insulation state between the individual conductor patterns in the first conductor pattern group and the single conductor pattern are determined. This can be performed reliably and easily without damaging the electronic component. Therefore, according to the circuit board inspection apparatus and the circuit board inspection method, the inspection accuracy of the insulation inspection can be sufficiently improved. Further, according to the circuit board inspection apparatus and the circuit board inspection method, the conductor patterns in the second conductor pattern group are connected to each other, that is, the conductor patterns in the second conductor pattern group are grouped into one. Since the second inspection is executed in this state, even if there are a large number of single conductor patterns, the insulation state between all the conductor patterns can be inspected by a small number of times of the second signal supply processing and the second inspection. Therefore, according to this circuit board inspection apparatus and circuit board inspection method, the inspection efficiency of the insulation inspection can be sufficiently improved.

また、請求項２記載の回路基板検査装置では、処理部が記憶部に記憶されている接続データに基づいて第１導体パターン群および第２導体パターン群を特定する特定処理を実行する。このため、この回路基板検査装置によれば、どの導体パターンが電子部品によって接続されているかを調査して第１導体パターン群および第２導体パターン群を人手によって特定する作業を不要とすることができる結果、その分、検査効率を向上させることができる。 In the circuit board inspection apparatus according to the second aspect, the processing unit executes a specific process of specifying the first conductor pattern group and the second conductor pattern group based on the connection data stored in the storage unit. For this reason, according to this circuit board inspection apparatus, it is not necessary to manually identify the first conductor pattern group and the second conductor pattern group by investigating which conductor pattern is connected by the electronic component. As a result, the inspection efficiency can be improved accordingly.

また、請求項３記載の回路基板検査装置では、検査用信号供給部が、第２信号供給処理において、抵抗値が所定値以下の電子部品を介して接続されている導体パターンを互いに同電位としつつ低電圧信号を供給する。このため、この回路基板検査装置によれば、第２信号供給処理の実行時においても、電子部品を介して接続されている導体パターン間に大きな電位差が生じることに起因してその電子部品が破損する事態を確実に防止することができる。 In the circuit board inspection apparatus according to claim 3, the inspection signal supply unit sets the conductor patterns connected via electronic components having a resistance value equal to or less than a predetermined value to the same potential in the second signal supply process. While supplying a low voltage signal. Therefore, according to this circuit board inspection apparatus, even when the second signal supply process is executed, the electronic component is damaged due to a large potential difference between the conductor patterns connected via the electronic component. Can be reliably prevented.

以下、本発明に係る回路基板検査装置および回路基板検査方法の最良の形態について、添付図面を参照して説明する。 The best mode of a circuit board inspection apparatus and a circuit board inspection method according to the present invention will be described below with reference to the accompanying drawings.

最初に、回路基板検査装置１の構成について説明する。図１に示す回路基板検査装置１は、本発明に係る回路基板検査装置の一例であって、例えば、複数の導体パターンＰ１〜Ｐ２３（図２参照：以下、区別しないときには「導体パターンＰ」ともいう）および導体パターンＰに接続された電子部品Ｅ１〜Ｅ６（同図参照：以下、区別しないときには「電子部品Ｅ」ともいう）を有する回路基板１００における各導体パターンＰ間の絶縁検査を本発明に係る回路基板検査方法に従って実行可能に構成されている。具体的には、回路基板検査装置１は、図１に示すように、基板保持部１１、プローブユニット１２、移動機構１３、スキャナ部１４、検査用信号生成部１５、測定部１６、記憶部１７および制御部１８を備えて構成されている。 First, the configuration of the circuit board inspection apparatus 1 will be described. A circuit board inspection apparatus 1 shown in FIG. 1 is an example of a circuit board inspection apparatus according to the present invention. For example, a plurality of conductor patterns P1 to P23 (see FIG. 2; hereinafter referred to as “conductor pattern P” when not distinguished from each other). Insulation inspection between the conductor patterns P in the circuit board 100 having the electronic components E1 to E6 (refer to the same figure: hereinafter, also referred to as “electronic component E” if not distinguished) connected to the conductor pattern P. The circuit board inspection method according to the present invention is executable. Specifically, as shown in FIG. 1, the circuit board inspection apparatus 1 includes a substrate holding unit 11, a probe unit 12, a moving mechanism 13, a scanner unit 14, an inspection signal generation unit 15, a measurement unit 16, and a storage unit 17. And a control unit 18.

基板保持部１１は、保持板と、保持板に取り付けられて回路基板１００の端部を挟み込んで固定するクランプ機構（いずれも図示せず）とを備えて、回路基板１００を保持可能に構成されている。プローブユニット１２は、複数のプローブピン２１を備えて治具型に構成されている。この場合、プローブユニット１２は、回路基板１００の各導体パターンＰの形状や配設位置などに応じて、プローブピン２１の数や配列パターンが規定されている。移動機構１３は、制御部１８の制御に従い、上下方向にプローブユニット１２を移動させることによってプロービングを実行する。 The substrate holding unit 11 includes a holding plate and a clamp mechanism (none of which is shown) that is attached to the holding plate and sandwiches and fixes the end portion of the circuit substrate 100, and is configured to hold the circuit substrate 100. ing. The probe unit 12 includes a plurality of probe pins 21 and is configured as a jig. In this case, the number of probe pins 21 and the arrangement pattern of the probe unit 12 are defined according to the shape and arrangement position of each conductor pattern P of the circuit board 100. The moving mechanism 13 performs probing by moving the probe unit 12 in the vertical direction under the control of the control unit 18.

スキャナ部１４は、複数のスイッチ（図示せず）を備えて構成され、制御部１８の制御に従って各スイッチをオン状態またはオフ状態に移行させることにより、プローブユニット１２におけるプローブピン２１と検査用信号生成部１５との接断（接続および切断）、およびプローブピン２１と測定部１６との接断を行う。検査用信号生成部１５は、検査用信号としての高電圧信号Ｓ１および低電圧信号Ｓ２（以下、区別しないときには「電圧信号Ｓ」ともいう）を生成する。この場合、この回路基板検査装置１では、高電圧信号Ｓ１が、一例として、１０Ｖ〜１０００Ｖ程度に規定されている。一方、低電圧信号Ｓ２は、電子部品Ｅに印加しても破損しない程度の電圧（一例として、０．１Ｖ〜０．５Ｖ程度）に規定されている。測定部１６は、電圧信号Ｓを供給した際にプローブピン２１，２１（導体パターンＰ間）に流れる（生じる）電流（本発明における物理量の一例）を測定する。 The scanner unit 14 includes a plurality of switches (not shown), and switches each switch to an on state or an off state according to the control of the control unit 18, whereby the probe pin 21 and the inspection signal in the probe unit 12 are switched. Connection / disconnection (connection and disconnection) with the generation unit 15 and connection / disconnection between the probe pin 21 and the measurement unit 16 are performed. The inspection signal generator 15 generates a high voltage signal S1 and a low voltage signal S2 (hereinafter also referred to as “voltage signal S” when not distinguished) as inspection signals. In this case, in this circuit board inspection apparatus 1, the high voltage signal S1 is regulated to about 10V to 1000V as an example. On the other hand, the low voltage signal S2 is regulated to a voltage that does not break even when applied to the electronic component E (as an example, about 0.1 V to 0.5 V). The measurement unit 16 measures a current (an example of a physical quantity in the present invention) flowing (generated) through the probe pins 21 and 21 (between the conductor patterns P) when the voltage signal S is supplied.

記憶部１７は、制御部１８によって実行される検査処理５０（図５参照）において用いられる接続データＤ１および電子部品データＤ２を記憶する。この場合、接続データＤ１は、本発明における接続データの一例であって、図３に概念的に示すように、回路基板１００に実装されている各電子部品Ｅ１〜Ｅ６が接続されている導体パターンＰを特定可能な情報を含んで構成されている。また、電子部品データＤ２は、図４に概念的に示すように、各電子部品Ｅ１〜Ｅ４の抵抗値を示す情報を含んで構成されている。また、記憶部１７は、制御部１８によって生成される第１導体パターン群データＤ３（図６参照）、第２導体パターン群データＤ４（図７参照）、および第３導体パターン群データＤ５（図８参照）を記憶する。 The storage unit 17 stores connection data D1 and electronic component data D2 used in the inspection process 50 (see FIG. 5) executed by the control unit 18. In this case, the connection data D1 is an example of connection data in the present invention, and, as conceptually shown in FIG. 3, a conductor pattern to which the respective electronic components E1 to E6 mounted on the circuit board 100 are connected. It includes information that can identify P. The electronic component data D2 includes information indicating resistance values of the electronic components E1 to E4 as conceptually shown in FIG. The storage unit 17 also includes first conductor pattern group data D3 (see FIG. 6), second conductor pattern group data D4 (see FIG. 7), and third conductor pattern group data D5 (see FIG. 6) generated by the control unit 18. 8) is stored.

制御部１８は、図外の操作部から出力される操作信号に従って回路基板検査装置１を構成する各構成要素を制御する。具体的には、制御部１８は、移動機構１３によるプローブユニット１２の移動を制御する。また、制御部１８は、本発明における処理部として機能し、回路基板１００における各導体パターンＰの中から、電子部品Ｅを介して接続されている複数の導体パターンＰで構成される第１導体パターン群Ｇｆ１〜Ｇｆ３（図２参照：以下、区別しないときには「第１導体パターン群Ｇｆ」ともいう）を接続データＤ１に基づいて特定して第１導体パターン群データＤ３を生成して、生成した第１導体パターン群データＤ３を記憶部１７に記憶させる。 The control unit 18 controls each component constituting the circuit board inspection apparatus 1 according to an operation signal output from an operation unit (not shown). Specifically, the control unit 18 controls the movement of the probe unit 12 by the moving mechanism 13. Moreover, the control part 18 functions as a process part in this invention, and is comprised from the each conductor pattern P in the circuit board 100 from the 1st conductor comprised by the some conductor pattern P connected via the electronic component E. The pattern groups Gf1 to Gf3 (refer to FIG. 2; hereinafter, also referred to as “first conductor pattern group Gf” when not distinguished) are specified based on the connection data D1 to generate the first conductor pattern group data D3. The first conductor pattern group data D3 is stored in the storage unit 17.

また、制御部１８は、電子部品Ｅに接続されていない全ての導体パターンＰ（図２に示す導体パターンＰ１９〜Ｐ２３：以下、「単独の導体パターンＰ」ともいう）で構成される第２導体パターン群Ｇｓ（同図参照）を接続データＤ１に基づいて特定して第２導体パターン群データＤ４を生成して、生成した第２導体パターン群データＤ４を記憶部１７に記憶させる。なお、第１導体パターン群Ｇｆを特定する処理、および第２導体パターン群Ｇｓを特定する処理が本発明における特定処理に相当する。さらに、制御部１８は、抵抗値が所定値（一例として、１ＫΩ）以下の電子部品Ｅを介して接続されている導体パターンＰで構成される第３導体パターン群Ｇｔ（同図参照）を接続データＤ１および電子部品データＤ２に基づいて特定して第３導体パターン群データＤ５を生成して、生成した第３導体パターン群データＤ５を記憶部１７に記憶させる。 Further, the control unit 18 is a second conductor configured by all the conductor patterns P not connected to the electronic component E (conductor patterns P19 to P23 shown in FIG. 2; hereinafter, also referred to as “single conductor pattern P”). The pattern group Gs (refer to the figure) is specified based on the connection data D1, the second conductor pattern group data D4 is generated, and the generated second conductor pattern group data D4 is stored in the storage unit 17. The process for specifying the first conductor pattern group Gf and the process for specifying the second conductor pattern group Gs correspond to the specifying process in the present invention. Furthermore, the control unit 18 connects a third conductor pattern group Gt (see the same figure) composed of conductor patterns P connected via an electronic component E having a resistance value of a predetermined value (for example, 1 KΩ) or less. The third conductor pattern group data D5 is generated based on the data D1 and the electronic component data D2, and the generated third conductor pattern group data D5 is stored in the storage unit 17.

また、制御部１８は、検査用信号生成部１５およびスキャナ部１４と共に本発明における検査用信号供給部を構成し、スキャナ部１４による接断処理を制御することによって回路基板１００の導体パターンＰに対する電圧信号Ｓの供給を行う。この場合、制御部１８は、第１導体パターン群Ｇｆ内の各導体パターンＰを互いに同電位としつつ第１導体パターン群Ｇｆ外の導体パターンＰとの間に高電圧信号Ｓ１を供給する第１信号供給処理を実行する。また、制御部１８は、第２導体パターン群Ｇｓ内の各導体パターンＰを互いに接続した状態で第２導体パターン群Ｇｓ外の導体パターンＰとの間に低電圧信号Ｓ２を供給する第２信号供給処理を実行する。この場合、制御部１８は、第３導体パターン群Ｇｔが存在するときには、第２信号供給処理において、第３導体パターン群Ｇｔ内の各導体パターンＰを互いに同電位としつつ低電圧信号Ｓ２を供給する。 The control unit 18 constitutes an inspection signal supply unit in the present invention together with the inspection signal generation unit 15 and the scanner unit 14, and controls the connection / disconnection processing by the scanner unit 14, thereby controlling the conductor pattern P of the circuit board 100. The voltage signal S is supplied. In this case, the control unit 18 supplies the high voltage signal S1 between the conductor patterns P in the first conductor pattern group Gf and the conductor patterns P outside the first conductor pattern group Gf while maintaining the same potential. Execute signal supply processing. In addition, the control unit 18 supplies the low voltage signal S2 to the conductor pattern P outside the second conductor pattern group Gs in a state where the conductor patterns P in the second conductor pattern group Gs are connected to each other. Execute the supply process. In this case, when the third conductor pattern group Gt exists, the control unit 18 supplies the low voltage signal S2 while keeping the conductor patterns P in the third conductor pattern group Gt at the same potential in the second signal supply process. To do.

また、制御部１８は、測定部１６と共に本発明における検査部を構成し、測定部１６によって測定された物理量（この例では電流）に基づいて導体パターンＰ間の絶縁状態を検査する。この場合、制御部１８は、上記した第１信号供給処理を実行している状態において、第１導体パターン群Ｇｆ内の導体パターンＰと、他の第１導体パターン群Ｇｆ内の導体パターンＰとの間（高電圧信号Ｓ１を供給している導体パターンＰ間）の絶縁状態、および第１導体パターン群Ｇｆ内の導体パターンＰと、単独の導体パターンＰ（第１導体パターン群Ｇｆ外の導体パターンＰ）との間（高電圧信号Ｓ１を供給している導体パターンＰ間）の絶縁状態を検査する第１検査を実行する。また、制御部１８は、上記した第２信号供給処理を実行している状態において、第２導体パターン群Ｇｓ内の導体パターンＰと、第２導体パターン群Ｇｓ外の導体パターンＰとの間（低電圧信号Ｓ２を供給している導体パターンＰ間）の絶縁状態を検査する第２検査を実行する。 Moreover, the control part 18 comprises the test | inspection part in this invention with the measurement part 16, and test | inspects the insulation state between the conductor patterns P based on the physical quantity (in this example, electric current) measured by the measurement part 16. FIG. In this case, in the state in which the first signal supply process is performed, the control unit 18 performs the following operation on the conductor pattern P in the first conductor pattern group Gf and the conductor pattern P in the other first conductor pattern group Gf. Between the conductor patterns P between the conductor patterns P supplying the high voltage signal S1 and the conductor pattern P in the first conductor pattern group Gf and the single conductor pattern P (conductor outside the first conductor pattern group Gf) The first inspection for inspecting the insulation state between the pattern P) and the conductor pattern P supplying the high voltage signal S1 is performed. Further, the control unit 18 is in a state where the above-described second signal supply process is being performed, between the conductor pattern P in the second conductor pattern group Gs and the conductor pattern P outside the second conductor pattern group Gs ( A second inspection for inspecting the insulation state between the conductor patterns P supplying the low voltage signal S2 is executed.

次に、回路基板検査装置１を用いて本発明に係る回路基板検査方法に従い、回路基板１００における各導体パターンＰ間の絶縁状態を検査する方法、およびその際の回路基板検査装置１の動作について、図面を参照して説明する。なお、回路基板１００は、図２に示すように、一例として、２３個の導体パターンＰ１〜Ｐ２３が一面に形成されると共に、６個の電子部品が実装されて構成されているものとする。 Next, according to the circuit board inspection method according to the present invention using the circuit board inspection apparatus 1, a method for inspecting the insulation state between the conductor patterns P in the circuit board 100, and the operation of the circuit board inspection apparatus 1 at that time This will be described with reference to the drawings. As shown in FIG. 2, the circuit board 100 is configured by, for example, 23 conductor patterns P <b> 1 to P <b> 23 formed on one surface and 6 electronic components mounted thereon.

まず、検査対象の回路基板１００を基板保持部１１における保持板（図示せず）に載置し、次いで、基板保持部１１のクランプ機構（図示せず）で回路基板１００の端部を挟み込んで固定することにより、回路基板１００を基板保持部１１に保持させる。続いて、図外の操作部を用いて検査開始操作を行う。この際に、制御部１８が、操作部から出力された操作信号に従い、移動機構１３を制御してプローブユニット１２を下向きに移動させる。これにより、プローブユニット１２の各プローブピン２１の先端部が各導体パターンＰ１〜Ｐ２３に接触（プロービング）させられる。 First, the circuit board 100 to be inspected is placed on a holding plate (not shown) in the board holding part 11, and then the end part of the circuit board 100 is sandwiched by a clamping mechanism (not shown) of the board holding part 11. By fixing, the circuit board 100 is held by the board holding part 11. Subsequently, an inspection start operation is performed using an operation unit (not shown). At this time, the control unit 18 controls the moving mechanism 13 to move the probe unit 12 downward in accordance with the operation signal output from the operation unit. Thereby, the front-end | tip part of each probe pin 21 of the probe unit 12 is made to contact (probing) each conductor pattern P1-P23.

次いで、制御部１８は、図５に示す検査処理５０を実行する。この検査処理５０では、制御部１８は、記憶部１７から接続データＤ１および電子部品データＤ２を読み出す（ステップ５１）。続いて、制御部１８は、接続データＤ１に基づいて第１導体パターン群Ｇｆを特定する（ステップ５２）。この場合、制御部１８は、図６に示すように、電子部品Ｅ１，Ｅ２を介して接続されている導体パターンＰ１，Ｐ２で構成される第１導体パターン群Ｇｆ１、電子部品Ｅ３を介して接続されている導体パターンＰ３，Ｐ４で構成される第１導体パターン群Ｇｆ２、および電子部品Ｅ４〜Ｅ６を介して接続されている導体パターンＰ５〜Ｐ１８で構成される第１導体パターン群Ｇｆ３を特定する。次いで、制御部１８は、特定した各第１導体パターン群Ｇｆ１〜Ｇｆ３を識別する番号（同図に示す同電位番号「１〜３」）と各導体パターンＰとを関連付けた第１導体パターン群データＤ３を生成して、記憶部１７に記憶させる。 Next, the control unit 18 executes the inspection process 50 shown in FIG. In this inspection process 50, the control unit 18 reads the connection data D1 and the electronic component data D2 from the storage unit 17 (step 51). Subsequently, the control unit 18 specifies the first conductor pattern group Gf based on the connection data D1 (step 52). In this case, as shown in FIG. 6, the control unit 18 is connected via the first conductor pattern group Gf1 composed of the conductor patterns P1 and P2 connected via the electronic components E1 and E2, and the electronic component E3. The first conductor pattern group Gf2 composed of the conductor patterns P3 and P4, and the first conductor pattern group Gf3 composed of the conductor patterns P5 to P18 connected via the electronic components E4 to E6 are specified. . Next, the control unit 18 associates each conductor pattern P with a number (the same potential number “1 to 3” shown in the figure) for identifying each identified first conductor pattern group Gf1 to Gf3. Data D3 is generated and stored in the storage unit 17.

続いて、制御部１８は、接続データＤ１に基づいて第２導体パターン群Ｇｓを特定する（ステップ５３）。この場合、制御部１８は、図７に示すように、電子部品Ｅに接続されていない単独の導体パターンＰ１９〜Ｐ２３で構成される第２導体パターン群Ｇｓを特定する。次いで、制御部１８は、特定した第２導体パターン群Ｇｓを識別する番号（同図に示す同電位番号「４」）と各導体パターンＰとを関連付けた第２導体パターン群データＤ４を生成して、記憶部１７に記憶させる。 Subsequently, the control unit 18 specifies the second conductor pattern group Gs based on the connection data D1 (step 53). In this case, as illustrated in FIG. 7, the control unit 18 specifies the second conductor pattern group Gs including the single conductor patterns P19 to P23 that are not connected to the electronic component E. Next, the control unit 18 generates second conductor pattern group data D4 that associates each conductor pattern P with a number (the same potential number “4” shown in the figure) that identifies the specified second conductor pattern group Gs. And stored in the storage unit 17.

続いて、制御部１８は、接続データＤ１および電子部品データＤ２に基づいて第３導体パターン群Ｇｔを特定する（ステップ５４）。この場合、制御部１８は、基準値（例えば１ＫΩ）以下の抵抗値の電子部品Ｅ（この例では、電子部品Ｅ４（図４参照））を電子部品データＤ２に基づいて特定し、図８に示すように、その電子部品Ｅ４を介して接続されている導体パターンＰ７，Ｐ１４で構成される第３導体パターン群Ｇｔを接続データＤ１に基づいて特定する。次いで、制御部１８は、特定した第３導体パターン群Ｇｔを識別する番号（同図に示す同電位番号「１１」）と各導体パターンＰとを関連付けた第３導体パターン群データＤ５を生成して、記憶部１７に記憶させる。 Subsequently, the control unit 18 specifies the third conductor pattern group Gt based on the connection data D1 and the electronic component data D2 (step 54). In this case, the control unit 18 specifies an electronic component E (in this example, the electronic component E4 (see FIG. 4)) having a resistance value equal to or less than a reference value (for example, 1 KΩ) based on the electronic component data D2, and FIG. As shown, the third conductor pattern group Gt composed of the conductor patterns P7 and P14 connected via the electronic component E4 is specified based on the connection data D1. Next, the control unit 18 generates third conductor pattern group data D5 that associates each conductor pattern P with a number (the same potential number “11” shown in the figure) that identifies the specified third conductor pattern group Gt. And stored in the storage unit 17.

この場合、上記したように、この回路基板検査装置１では、制御部１８が接続データＤ１および電子部品データＤ２に基づいて第１導体パターン群Ｇｆ、第２導体パターン群Ｇｓおよび第３導体パターン群Ｇｔを特定して、第１導体パターン群データＤ３、第２導体パターン群データＤ４および第３導体パターン群データＤ５として記憶部１７に記憶させる。このため、この回路基板検査装置１では、どの導体パターンＰが電子部品Ｅによって接続されているかを調査して第１導体パターン群Ｇｆ、第２導体パターン群Ｇｓおよび第３導体パターン群Ｇｔを特定する作業や、作成した第１導体パターン群データＤ３、第２導体パターン群データＤ４および第３導体パターン群データＤ５を入力する作業が不要なため、その分、検査効率を向上させることが可能となっている。 In this case, as described above, in the circuit board inspection apparatus 1, the control unit 18 uses the first conductor pattern group Gf, the second conductor pattern group Gs, and the third conductor pattern group based on the connection data D1 and the electronic component data D2. Gt is specified and stored in the storage unit 17 as first conductor pattern group data D3, second conductor pattern group data D4, and third conductor pattern group data D5. For this reason, in this circuit board inspection apparatus 1, the first conductor pattern group Gf, the second conductor pattern group Gs, and the third conductor pattern group Gt are identified by investigating which conductor pattern P is connected by the electronic component E. And the work of inputting the created first conductor pattern group data D3, second conductor pattern group data D4, and third conductor pattern group data D5 is not necessary, and the inspection efficiency can be improved accordingly. It has become.

続いて、制御部１８は、高電圧信号Ｓ１を用いて各導体パターンＰ間の絶縁状態を検査する高電圧検査を実行する（ステップ５５）。この高電圧検査では、制御部１８は、第１信号供給処理を実行する。この場合、制御部１８は、第１信号供給処理において、検査用信号生成部１５を制御して高電圧信号Ｓ１を生成させる。また、制御部１８は、図６に示す第１導体パターン群データＤ３に基づいて各第１導体パターン群Ｇｆを特定し、次いで、スキャナ部１４を制御して、そのうちの１つの第１導体パターン群Ｇｆ（例えば、第１導体パターン群Ｇｆ１：図２参照）内の各導体パターンＰ（この例では、導体パターンＰ１，Ｐ２：同図参照）に接触しているプローブピン２１と検査用信号生成部１５とを接続する。また、制御部１８は、スキャナ部１４を制御して、上記した１つの第１導体パターン群Ｇｆ１とは異なる他の第１導体パターン群Ｇｆ（例えば、第１導体パターン群Ｇｆ２）内の各導体パターンＰ（この例では、導体パターンＰ３，Ｐ４：同図参照）に接触しているプローブピン２１をグランド電位に接続する。 Subsequently, the control unit 18 performs a high voltage inspection for inspecting the insulation state between the conductor patterns P using the high voltage signal S1 (step 55). In this high voltage inspection, the control unit 18 executes a first signal supply process. In this case, the control unit 18 controls the inspection signal generation unit 15 to generate the high voltage signal S1 in the first signal supply process. Further, the control unit 18 specifies each first conductor pattern group Gf based on the first conductor pattern group data D3 shown in FIG. 6, and then controls the scanner unit 14 so as to control one of the first conductor pattern groups Gf. Probe pin 21 in contact with each conductor pattern P (in this example, conductor patterns P1, P2: see FIG. 2) in group Gf (for example, first conductor pattern group Gf1: see FIG. 2) and generation of a test signal The unit 15 is connected. In addition, the control unit 18 controls the scanner unit 14 so that each conductor in another first conductor pattern group Gf (for example, the first conductor pattern group Gf2) different from the one first conductor pattern group Gf1 described above. The probe pin 21 that is in contact with the pattern P (in this example, the conductor patterns P3 and P4: see the figure) is connected to the ground potential.

これにより、高電圧信号Ｓ１が、第１導体パターン群Ｇｆ１内の各導体パターンＰと、第１導体パターン群Ｇｆ２内の各導体パターンＰとの間に各プローブピン２１を介して供給（印加）される。なお、この例では、第１導体パターン群Ｇｆ１内の各導体パターンＰが、第１導体パターン群Ｇｆ２側から見たときの第１導体パターン群Ｇｆ外の導体パターンＰに相当し、第１導体パターン群Ｇｆ２内の各導体パターンＰが、第１導体パターン群Ｇｆ１側から見たときの第１導体パターン群Ｇｆ外の導体パターンＰに相当する。 Thereby, the high voltage signal S1 is supplied (applied) via the probe pins 21 between the conductor patterns P in the first conductor pattern group Gf1 and the conductor patterns P in the first conductor pattern group Gf2. Is done. In this example, each conductor pattern P in the first conductor pattern group Gf1 corresponds to the conductor pattern P outside the first conductor pattern group Gf when viewed from the first conductor pattern group Gf2 side. Each conductor pattern P in the pattern group Gf2 corresponds to the conductor pattern P outside the first conductor pattern group Gf when viewed from the first conductor pattern group Gf1 side.

この場合、上記したように、第１導体パターン群Ｇｆ１内の各導体パターンＰがプローブピン２１を介して検査用信号生成部１５に接続されて各導体パターンＰが同電位（この例では、高電圧信号Ｓ１の電位）に維持され、第１導体パターン群Ｇｆ２内の各導体パターンＰがプローブピン２１を介してグランド電位に接続されて各導体パターンＰが同電位（この例では、グランド電位）に維持されている。このため、同じ第１導体パターン群Ｇｆ内の各導体パターンＰ間に大きな電位差が生じることに起因しての、各導体パターンＰ間に接続されている電子部品Ｅが破損する事態が確実に防止される。 In this case, as described above, each conductor pattern P in the first conductor pattern group Gf1 is connected to the inspection signal generator 15 via the probe pin 21 so that each conductor pattern P has the same potential (in this example, high potential). Is maintained at the potential of the voltage signal S1, and each conductor pattern P in the first conductor pattern group Gf2 is connected to the ground potential via the probe pin 21 so that each conductor pattern P has the same potential (in this example, the ground potential). Is maintained. This reliably prevents the electronic component E connected between the conductor patterns P from being damaged due to a large potential difference between the conductor patterns P in the same first conductor pattern group Gf. Is done.

続いて、制御部１８は、第１信号供給処理を実行している状態において、第１検査を実行する。この場合、制御部１８は、第１検査において、測定部１６に対して、高電圧信号Ｓ１の供給に伴って第１導体パターン群Ｇｆ１と第１導体パターン群Ｇｆ２との間に流れる電流を測定させる。次いで、制御部１８は、測定部１６によって測定された電流の測定値および高電圧信号Ｓ１の電圧値に基づいて抵抗値を算出し、その抵抗値と所定の基準値とを比較して第１導体パターン群Ｇｆ１内の導体パターンＰと第１導体パターン群Ｇｆ２内の導体パターンＰとの間（高電圧信号Ｓ１を供給している導体パターンＰ間）の絶縁状態（の良否）を検査する。 Subsequently, the control unit 18 performs the first inspection in a state where the first signal supply process is being performed. In this case, the control unit 18 measures the current flowing between the first conductor pattern group Gf1 and the first conductor pattern group Gf2 as the high voltage signal S1 is supplied to the measurement unit 16 in the first inspection. Let Next, the control unit 18 calculates a resistance value based on the measured current value measured by the measuring unit 16 and the voltage value of the high voltage signal S1, and compares the resistance value with a predetermined reference value to determine the first value. The insulation state between the conductor pattern P in the conductor pattern group Gf1 and the conductor pattern P in the first conductor pattern group Gf2 (between the conductor patterns P supplying the high voltage signal S1) is inspected.

続いて、制御部１８は、各第１導体パターン群Ｇｆおよび単独の各導体パターンＰをそれぞれ１つと数えて、これらの中からいずれか２つを選択する全ての組み合わせについて、上記した第１信号供給処理および第１検査（高電圧検査）を順次（いわゆる総当たり方式で）実行する。これにより、１つの第１導体パターン群Ｇｆ内の各導体パターンＰと他の１つの第１導体パターン群Ｇｆ内の各導体パターンＰとの間、１つの第１導体パターン群Ｇｆ内の各導体パターンＰと１つの単独の導体パターンＰとの間、および２つの単独の導体パターンＰ間の絶縁状態の検査が行われる。 Subsequently, the control unit 18 counts each first conductor pattern group Gf and each individual conductor pattern P as one, and selects the first signal described above for all combinations in which any two of them are selected. The supply process and the first inspection (high voltage inspection) are sequentially performed (so-called brute force method). Thus, each conductor in one first conductor pattern group Gf is between each conductor pattern P in one first conductor pattern group Gf and each conductor pattern P in another one first conductor pattern group Gf. The insulation state between the pattern P and one single conductor pattern P and between two single conductor patterns P is inspected.

次いで、制御部１８は、低電圧信号Ｓ２を用いて各導体パターンＰ間の絶縁状態を検査する低電圧検査を実行する（ステップ５６）。この低電圧検査では、制御部１８は、第２信号供給処理を実行する。この場合、制御部１８は、第２信号供給処理において、検査用信号生成部１５を制御して低電圧信号Ｓ２を生成させる。また、制御部１８は、図７に示す第２導体パターン群データＤ４に基づいて第２導体パターン群Ｇｓを特定し、次いで、スキャナ部１４を制御して、第２導体パターン群Ｇｓ内の各導体パターンＰ（この例では、導体パターンＰ１９〜Ｐ２３）に接触しているプローブピン２１と検査用信号生成部１５とを接続する。また、制御部１８は、図８に示す第３導体パターン群データＤ５に基づいて第３導体パターン群Ｇｔを特定し、次いで、スキャナ部１４を制御して、第３導体パターン群Ｇｔ内の各導体パターンＰ（この例では、導体パターンＰ７，Ｐ１４）に接触しているプローブピン２１とをグランド電位に接続する。これにより、低電圧信号Ｓ２が、第２導体パターン群Ｇｓ内の各導体パターンＰと、第３導体パターン群Ｇｔ内の各導体パターンＰ（第２導体パターン群Ｇｓ外の導体パターンＰ）との間に各プローブピン２１を介して供給（印加）される。 Next, the control unit 18 performs a low voltage inspection for inspecting the insulation state between the conductor patterns P using the low voltage signal S2 (step 56). In this low voltage test, the control unit 18 executes the second signal supply process. In this case, in the second signal supply process, the control unit 18 controls the inspection signal generation unit 15 to generate the low voltage signal S2. Further, the control unit 18 specifies the second conductor pattern group Gs based on the second conductor pattern group data D4 shown in FIG. 7, and then controls the scanner unit 14 to control each of the second conductor pattern group Gs. The probe pin 21 that is in contact with the conductor pattern P (conductor patterns P19 to P23 in this example) and the inspection signal generator 15 are connected. Further, the control unit 18 specifies the third conductor pattern group Gt based on the third conductor pattern group data D5 shown in FIG. 8, and then controls the scanner unit 14 to control each of the third conductor pattern group Gt. The probe pin 21 that is in contact with the conductor pattern P (in this example, the conductor patterns P7 and P14) is connected to the ground potential. As a result, the low voltage signal S2 is generated between each conductor pattern P in the second conductor pattern group Gs and each conductor pattern P in the third conductor pattern group Gt (conductor pattern P outside the second conductor pattern group Gs). It is supplied (applied) via each probe pin 21 in between.

この場合、上記したように、第３導体パターン群Ｇｔ内の各導体パターンＰがプローブピン２１を介してグランド電位に接続されて各導体パターンＰが同電位（この例では、グランド電位）に維持されている。このため、第３導体パターン群Ｇｔ内の各導体パターンＰ間に大きな電位差が生じることに起因しての、各導体パターンＰ間に接続されている電子部品Ｅが破損する事態が確実に防止されている。 In this case, as described above, each conductor pattern P in the third conductor pattern group Gt is connected to the ground potential via the probe pin 21, and each conductor pattern P is maintained at the same potential (in this example, the ground potential). Has been. For this reason, the situation where the electronic component E connected between the conductor patterns P is damaged due to the occurrence of a large potential difference between the conductor patterns P in the third conductor pattern group Gt is reliably prevented. ing.

次いで、制御部１８は、第２信号供給処理を実行している状態において、第２検査を実行する。この場合、制御部１８は、第２検査において、測定部１６に対して、低電圧信号Ｓ２の供給に伴って第２導体パターン群Ｇｓと第３導体パターン群Ｇｔとの間に流れる電流を測定させる。続いて、制御部１８は、測定部１６によって測定された電流の測定値および低電圧信号Ｓ２の電圧値に基づいて抵抗値を算出し、その抵抗値と所定の基準値とを比較して第２導体パターン群Ｇｓ内の各導体パターンＰと第３導体パターン群Ｇｔ内の各導体パターンＰ（第２導体パターン群Ｇｓ外の導体パターンＰ）との間（低電圧信号Ｓ２を供給している導体パターンＰ間）の絶縁状態（の良否）を検査する。 Next, the control unit 18 performs the second inspection while the second signal supply process is being performed. In this case, the control unit 18 measures the current flowing between the second conductor pattern group Gs and the third conductor pattern group Gt with the supply of the low voltage signal S2 to the measurement unit 16 in the second inspection. Let Subsequently, the control unit 18 calculates a resistance value based on the measured value of the current measured by the measuring unit 16 and the voltage value of the low voltage signal S2, and compares the resistance value with a predetermined reference value to calculate the resistance value. Between each conductor pattern P in the two conductor pattern group Gs and each conductor pattern P in the third conductor pattern group Gt (conductor pattern P outside the second conductor pattern group Gs) (the low voltage signal S2 is supplied) The insulation state (between conductor patterns P) is inspected.

続いて、制御部１８は、第２導体パターン群Ｇｓ、第３導体パターン群Ｇｔ、並びに第２導体パターン群Ｇｓおよび第３導体パターン群Ｇｔ外の各導体パターンＰをそれぞれ１つと数えて、これらの中からいずれか２つを選択する全ての組み合わせについて、上記した第２信号供給処理および第２検査（低電圧検査）を順次（総当たり方式で）実行する。これにより、第２導体パターン群Ｇｓ内の各導体パターンＰと第３導体パターン群Ｇｔ内の各導体パターンＰとの間、第２導体パターン群Ｇｓ内の各導体パターンＰと第２導体パターン群Ｇｓおよび第３導体パターン群Ｇｔ外の各導体パターンＰとの間、第３導体パターン群Ｇｔ内の各導体パターンＰと第２導体パターン群Ｇｓおよび第３導体パターン群Ｇｔ外の各導体パターンＰとの間、並びに第２導体パターン群Ｇｓおよび第３導体パターン群Ｇｔ外の２つの導体パターンＰ間の絶縁状態の検査が行われる。次いで、制御部１８は、第１検査および第２検査において検査した絶縁状態の良否を判別して、その結果を図外の表示部に表示させて検査処理５０を終了する。 Subsequently, the control unit 18 counts each of the second conductor pattern group Gs, the third conductor pattern group Gt, and each conductor pattern P outside the second conductor pattern group Gs and the third conductor pattern group Gt as one, The second signal supply process and the second inspection (low voltage inspection) described above are sequentially executed (by the brute force method) for all combinations in which any two are selected. Thus, between each conductor pattern P in the second conductor pattern group Gs and each conductor pattern P in the third conductor pattern group Gt, each conductor pattern P in the second conductor pattern group Gs and the second conductor pattern group. Between each conductor pattern P outside Gs and the third conductor pattern group Gt, each conductor pattern P inside the third conductor pattern group Gt, and each conductor pattern P outside the second conductor pattern group Gs and the third conductor pattern group Gt. And the insulation state between the two conductor patterns P outside the second conductor pattern group Gs and the third conductor pattern group Gt. Next, the control unit 18 determines the quality of the insulation state inspected in the first inspection and the second inspection, displays the result on a display unit outside the drawing, and ends the inspection process 50.

この場合、この回路基板検査装置１では、第２導体パターン群Ｇｓ内の各導体パターンＰ（単独の導体パターンＰ）がプローブピン２１を介して互いに接続されて１つにグループ化された状態で第２検査が行われる。このため、単独の導体パターンＰが数多くの存在したとしても、少ない回数の第２信号供給処理および第２検査（低電圧検査）で全ての導体パターンＰ間の絶縁状態を検査することが可能となっている。 In this case, in the circuit board inspection apparatus 1, the conductor patterns P (single conductor patterns P) in the second conductor pattern group Gs are connected to each other via the probe pins 21 and grouped into one. A second inspection is performed. For this reason, even if there are a large number of single conductor patterns P, it is possible to inspect the insulation state between all the conductor patterns P with a small number of times of the second signal supply processing and the second inspection (low voltage inspection). It has become.

なお、上記した低電圧検査では総当たり方式で絶縁状態を検査したが、いわゆるマルチプル方式で絶縁状態を検査することができる。ここで、マルチプル方式では、第２導体パターン群Ｇｓ、第３導体パターン群Ｇｔ、並びに第２導体パターン群Ｇｓおよび第３導体パターン群Ｇｔ外の導体パターンＰをそれぞれ１つとして取り扱って、これらを２つのグループ（Ａグループ、Ｂグループ）にグループ分けし、各グループ内において各導体パターンＰを互いに同電位としつつ各導体パターンＰに低電圧信号Ｓ２を供給して、各導体パターンＰ間の絶縁状態が良好であるか否かを検査する。そして、この検査を、グループ分けの内容（各グループに所属させる導体パターンＰやその数）を所定の規則に従って変更しつつ所定の回数行う。この場合、全ての導体パターンＰ間の絶縁状態が良好であるか否かを検査するのに必要な検査回数（グループ分けの回数）は、全ての導体パターンＰの数をＮとしたときに、ｌｏｇ_２Ｎ以上であってｌｏｇ_２Ｎに最も近い整数で規定される（例えば、Ｎ＝２０のときには５回）。このため、このマルチプル方式では、上記した総当たり方式よりもさらに少ない検査回数で全ての各導体パターンＰ間の絶縁状態を検査することができる。 In the above-described low voltage inspection, the insulation state is inspected by the round robin method, but the insulation state can be inspected by a so-called multiple method. Here, in the multiple system, the second conductor pattern group Gs, the third conductor pattern group Gt, and the conductor patterns P outside the second conductor pattern group Gs and the third conductor pattern group Gt are handled as one each, It is divided into two groups (A group and B group), and in each group, each conductor pattern P is supplied with a low voltage signal S2 while keeping each conductor pattern P at the same potential. Inspect whether the condition is good. Then, this inspection is performed a predetermined number of times while changing the contents of grouping (conductor patterns P belonging to each group and the number thereof) according to a predetermined rule. In this case, the number of inspections (number of groupings) required for inspecting whether the insulation state between all the conductor patterns P is good is as follows: a is log ₂ N or more defined by the integer closest to log ₂ N (e.g., 5 times when the N = 20). For this reason, in this multiple method, the insulation state between all the conductor patterns P can be inspected with a smaller number of inspections than the above-described round-robin method.

このように、この回路基板検査装置１および回路基板検査方法では、第１導体パターン群Ｇｆ内の各導体パターンＰを互いに同電位としつつ高電圧信号Ｓ１を供給する第１信号供給処理と、第２導体パターン群Ｇｓ内の各導体パターンＰを互いに接続した状態で低電圧信号Ｓ２を供給する第２信号供給処理を実行し、第１信号供給処理を実行している状態において、高電圧信号Ｓ１を供給している導体パターンＰ間の絶縁状態を検査する第１検査を実行すると共に、第２信号供給処理を実行している状態において、低電圧信号Ｓ２を供給している導体パターンＰ間の絶縁状態を検査する第２検査を実行する。このため、この回路基板検査装置１および回路基板検査方法によれば、第１検査を実行することで、２つの第１導体パターン群Ｇｆ間の絶縁の良否や、第１導体パターン群Ｇｆと単独の導体パターンＰとの間の絶縁状態の良否を、電子部品Ｅを破損させることなく行うことができるのに加えて、第２検査を実行することで、従来の回路基板検査装置および回路基板検査方法では困難であった第１導体パターン群Ｇｆ内における導体パターンＰ間の絶縁状態の良否や、第１導体パターン群Ｇｆ内の個々の導体パターンＰと単独の導体パターンとの間の絶縁状態の良否を電子部品Ｅを破損させることなく確実かつ容易に行うことができる。したがって、この回路基板検査装置１および回路基板検査方法によれば、絶縁検査の検査精度を十分に向上することができる。また、この回路基板検査装置１および回路基板検査方法によれば、第２導体パターン群Ｇｓ内の各導体パターンＰをプローブピン２１を介して互いに接続した状態、つまり、第２導体パターン群Ｇｓ内の各導体パターンＰを１つにグループ化した状態で第２検査を実行するため、単独の導体パターンＰが数多くの存在したとしても、少ない回数の第２信号供給処理および第２検査で全ての各導体パターンＰ間の絶縁状態を検査することができる。したがって、この回路基板検査装置１および回路基板検査方法によれば、絶縁検査の検査効率を十分に向上することができる。 As described above, in the circuit board inspection apparatus 1 and the circuit board inspection method, the first signal supply process for supplying the high voltage signal S1 while keeping the conductor patterns P in the first conductor pattern group Gf at the same potential, The second signal supply process for supplying the low voltage signal S2 is performed in a state where the conductor patterns P in the two conductor pattern group Gs are connected to each other, and the high voltage signal S1 in the state in which the first signal supply process is performed. The first inspection for inspecting the insulation state between the conductor patterns P that supply a low voltage signal S2 is performed in the state in which the first signal inspection is performed and the second signal supply process is being executed. A second inspection for inspecting the insulation state is performed. Therefore, according to the circuit board inspection apparatus 1 and the circuit board inspection method, by performing the first inspection, the quality of the insulation between the two first conductor pattern groups Gf, and the first conductor pattern group Gf alone. In addition to being able to check the quality of the insulation state with respect to the conductor pattern P without damaging the electronic component E, the conventional circuit board inspection apparatus and circuit board inspection can be performed by executing the second inspection. The insulation state between the conductor patterns P in the first conductor pattern group Gf and the insulation state between the individual conductor patterns P and the single conductor pattern in the first conductor pattern group Gf, which were difficult by the method, The quality can be reliably and easily performed without damaging the electronic component E. Therefore, according to the circuit board inspection apparatus 1 and the circuit board inspection method, the inspection accuracy of the insulation inspection can be sufficiently improved. Further, according to the circuit board inspection apparatus 1 and the circuit board inspection method, the conductor patterns P in the second conductor pattern group Gs are connected to each other through the probe pins 21, that is, in the second conductor pattern group Gs. Since the second inspection is performed in a state where the respective conductor patterns P are grouped into one, even if there are a large number of single conductor patterns P, all of the second signal supply processing and the second inspection are performed in a small number of times. The insulation state between the conductor patterns P can be inspected. Therefore, according to the circuit board inspection apparatus 1 and the circuit board inspection method, the inspection efficiency of the insulation inspection can be sufficiently improved.

また、この回路基板検査装置１および回路基板検査方法では、接続データＤ１に基づいて第１導体パターン群Ｇｆおよび第２導体パターン群Ｇｓを特定して第１導体パターン群データＤ３および第２導体パターン群データＤ４を生成する。このため、この回路基板検査装置１および回路基板検査方法によれば、どの導体パターンＰが電子部品Ｅによって接続されているかを調査して第１導体パターン群Ｇｆおよび第２導体パターン群Ｇｓを特定する作業や、作成した第１導体パターン群データＤ３および第２導体パターン群データＤ４を入力する作業を不要とすることができる結果、その分、検査効率を向上させることができる。 In the circuit board inspection apparatus 1 and the circuit board inspection method, the first conductor pattern group data D3 and the second conductor pattern are specified by specifying the first conductor pattern group Gf and the second conductor pattern group Gs based on the connection data D1. Group data D4 is generated. For this reason, according to the circuit board inspection apparatus 1 and the circuit board inspection method, the first conductor pattern group Gf and the second conductor pattern group Gs are identified by investigating which conductor pattern P is connected by the electronic component E. As a result, it is possible to eliminate the need to perform the operation of inputting the generated first conductor pattern group data D3 and the generated second conductor pattern group data D4. As a result, the inspection efficiency can be improved accordingly.

また、この回路基板検査装置１および回路基板検査方法では、第２信号供給処理において、抵抗値が所定値以下の電子部品Ｅを介して接続されている導体パターンＰを互いに同電位としつつ低電圧信号Ｓ２を供給する。このため、この回路基板検査装置１および回路基板検査方法によれば、第２信号供給処理の実行時においても、電子部品Ｅを介して接続されている導体パターンＰ間に大きな電位差が生じることに起因してその電子部品Ｅが破損する事態を確実に防止することができる。 Further, in the circuit board inspection apparatus 1 and the circuit board inspection method, in the second signal supply process, the conductor patterns P connected via the electronic component E having a resistance value equal to or lower than a predetermined value are kept at the same potential while being low in voltage. A signal S2 is supplied. Therefore, according to the circuit board inspection apparatus 1 and the circuit board inspection method, a large potential difference is generated between the conductor patterns P connected via the electronic component E even when the second signal supply process is executed. This can reliably prevent the electronic component E from being damaged.

なお、本発明は、上記した構成および方法に限定されない。例えば、第１導体パターン群Ｇｆが３つ存在すると共に、単独の導体パターンＰが５つ存在する回路基板１００に対して絶縁検査を実行する例について上記したが、第１導体パターン群Ｇｆの数や単独の導体パターンＰの数が回路基板１００とは異なる各種の回路基板に対して絶縁検査を実行する際にも、上記と同様の効果を実現することができる。 The present invention is not limited to the configuration and method described above. For example, the example in which the insulation test is performed on the circuit board 100 having three first conductor pattern groups Gf and five single conductor patterns P has been described above. The number of first conductor pattern groups Gf In addition, the same effect as described above can also be realized when performing an insulation test on various circuit boards in which the number of single conductor patterns P is different from that of the circuit board 100.

また、一面に導体パターンＰが形成された回路基板１００に対する検査を実行可能に構成した回路基板検査装置１を例に挙げて説明したが、一対のプローブユニット１２を備えて、両面に導体パターンＰが形成された回路基板に対する上記の検査を実行可能に構成した回路基板検査装置に適用することもできる。また、多層の回路基板や、基板内部に電子部品が内蔵された部品内蔵型の回路基板を検査可能に構成された回路基板検査装置に適用することもできる。さらに、プローブユニット１２を備えて各導体パターンＰにプローブピン２１を一度に接触させる構成例について上記したが、一対（または複数対）のプローブピンを移動させて、電圧信号Ｓを供給すべき導体パターンＰにのみプローブピンを接触させるフライングプローブタイプの回路基板検査装置に適用することもできる。 Further, the circuit board inspection apparatus 1 configured to be able to perform inspection on the circuit board 100 having the conductor pattern P formed on one surface has been described as an example. However, the circuit board inspection apparatus 1 includes a pair of probe units 12 and the conductor pattern P on both surfaces. It is also possible to apply the present invention to a circuit board inspection apparatus configured to execute the above-described inspection on a circuit board on which is formed. Also, the present invention can be applied to a circuit board inspection apparatus configured to be able to inspect a multilayer circuit board or a component-embedded circuit board in which an electronic component is embedded. Further, the configuration example in which the probe unit 12 is provided and the probe pin 21 is brought into contact with each conductor pattern P at the same time has been described above. The present invention can also be applied to a flying probe type circuit board inspection apparatus in which probe pins are brought into contact only with the pattern P.

また、第１検査における検査結果（絶縁状態の良否）に拘わらず第２検査を実行する例について上記したが、第１検査において絶縁状態が良好であると判別したときにのみ第２検査を実行する構成および方法を採用することもできる。また、導体パターンＰ間の絶縁検査を行う回路基板検査装置１に適用した例について上記したが、絶縁検査に加えて導体パターンＰの導通検査や電子部品Ｅの良否検査を行う回路基板検査装置に適用することもできる。 In addition, the example in which the second inspection is performed regardless of the inspection result (insulation state quality) in the first inspection has been described above, but the second inspection is performed only when it is determined that the insulation state is good in the first inspection. It is also possible to adopt a configuration and a method. Moreover, although it described above about the example applied to the circuit board test | inspection apparatus 1 which performs the insulation test between the conductor patterns P, in addition to the insulation test, the circuit board test | inspection apparatus which performs the continuity test of the conductor pattern P and the quality test of the electronic component E is applied. It can also be applied.

回路基板検査装置１の構成を示す構成図である。1 is a configuration diagram showing a configuration of a circuit board inspection device 1. FIG. 回路基板１００の構成を示す構成図である。1 is a configuration diagram showing a configuration of a circuit board 100. FIG. 接続データＤ１の構成を概念的に示すデータ構成図である。It is a data block diagram which shows notionally the structure of the connection data D1. 電子部品データＤ２の構成を概念的に示すデータ構成図である。It is a data block diagram which shows notionally the structure of the electronic component data D2. 検査処理５０のフローチャートである。5 is a flowchart of an inspection process 50. 第１導体パターン群データＤ３の構成を概念的に示すデータ構成図である。It is a data block diagram which shows notionally the structure of the 1st conductor pattern group data D3. 第２導体パターン群データＤ４の構成を概念的に示すデータ構成図である。It is a data block diagram which shows notionally the structure of 2nd conductor pattern group data D4. 第３導体パターン群データＤ５の構成を概念的に示すデータ構成図である。It is a data block diagram which shows notionally the structure of the 3rd conductor pattern group data D5.

Explanation of symbols

１回路基板検査装置
１２プローブユニット
１４スキャナ部
１５検査用信号生成部
１６測定部
１７記憶部
１８制御部
５０検査処理
１００回路基板
Ｄ１接続データ
Ｄ２電子部品データ
Ｄ３第１導体パターン群データ
Ｄ４第２導体パターン群データ
Ｄ５第３導体パターン群データ
Ｅ１〜Ｅ６電子部品
Ｇｆ１〜Ｇｆ３第１導体パターン群
Ｇｓ第２導体パターン群
Ｇｔ第３導体パターン群
Ｐ１〜Ｐ２３導体パターン
Ｓ１高電圧信号
Ｓ２低電圧信号 DESCRIPTION OF SYMBOLS 1 Circuit board inspection apparatus 12 Probe unit 14 Scanner part 15 Inspection signal generation part 16 Measurement part 17 Memory | storage part 18 Control part 50 Inspection process 100 Circuit board D1 Connection data D2 Electronic component data D3 1st conductor pattern group data D4 2nd conductor Pattern group data D5 Third conductor pattern group data E1 to E6 Electronic parts Gf1 to Gf3 First conductor pattern group Gs Second conductor pattern group Gt Third conductor pattern group P1 to P23 Conductor pattern S1 High voltage signal S2 Low voltage signal

Claims

An inspection signal supply unit for supplying an inspection signal to each conductor pattern of the circuit board having a plurality of conductor patterns and electronic components connected to the conductor pattern, and a physical quantity generated by supplying the inspection signal A circuit board inspection apparatus comprising an inspection unit for inspecting an insulation state between the conductor patterns based on
The inspection signal supply unit is arranged outside the first conductor pattern group while keeping the conductor patterns in the first conductor pattern group constituted by the conductor patterns connected via the electronic components at the same potential. A first signal supply process for supplying a high-voltage signal as the inspection signal between the conductor pattern and a second conductor pattern group configured by all the conductor patterns not connected to the electronic component A second signal supply process for supplying a low voltage signal as the inspection signal between the conductor patterns outside the second conductor pattern group in a state where the conductor patterns are connected to each other.
The inspection unit performs a first inspection for inspecting an insulation state between the conductor patterns to which the high voltage signal is supplied in a state in which the first signal supply process is being performed, and the second signal A circuit board inspection apparatus that performs a second inspection for inspecting an insulation state between the conductor patterns to which the low voltage signal is supplied in a state where a supply process is being performed.

A storage unit that stores connection data that can specify a conductor pattern to which the electronic component is connected, and a specifying process that specifies the first conductor pattern group and the second conductor pattern group based on the connection data. The circuit board inspection apparatus according to claim 1, further comprising a processing unit.

The inspection signal supply unit supplies the low voltage signal while keeping the conductor patterns connected through the electronic component having a resistance value equal to or less than a predetermined value in the second signal supply process while maintaining the same potential. Item 3. A circuit board inspection apparatus according to item 1 or 2.

An inspection signal is supplied to each conductor pattern of a circuit board having a plurality of conductor patterns and an electronic component connected to the conductor pattern, and the conductor pattern is based on a physical quantity generated by the supply of the inspection signal. A circuit board inspection method for inspecting an insulation state between
Between the conductor patterns outside the first conductor pattern group, the conductor patterns in the first conductor pattern group composed of the conductor patterns connected via the electronic component are set to the same potential. A first signal supply process for supplying a high voltage signal as the inspection signal, and the conductor patterns in the second conductor pattern group composed of all the conductor patterns not connected to the electronic component are connected to each other. A second signal supply process for supplying a low voltage signal as the inspection signal between the conductor patterns outside the second conductor pattern group in a state where
In a state where the first signal supply process is being performed, a first inspection for inspecting an insulation state between the conductor patterns supplying the high voltage signal is performed, and the second signal supply process is performed. A circuit board inspection method for executing a second inspection for inspecting an insulation state between the conductor patterns that supply the low voltage signal in a state where the low voltage signal is supplied.