JP2010029306A - Pulse generating apparatus and method, and program - Google Patents

Abstract

A processing load on a CPU is reduced.
In a clock signal generator 51 that generates a pulse signal at a variable speed based on a command from a control device, an up / down counter 71 counts up or down a counter value at a predetermined speed, The limit count generation unit 72 generates a limit count value of the counter based on the command, and the comparison unit 73 compares the limit count value with the count value of the counter, and when the count value is counted up, When the count value is larger than the limit count value, or when the count value counts down, when the count value of the counter is larger than the limit count value, a pulse signal is generated, and the clearing unit 74 generates a pulse signal. At the timing, the count value of the counter is cleared or pre- Tsu to door. The present invention can be applied to drive control of a movable accessory of a gaming machine.
[Selection] Figure 2

Description

  The present invention relates to a pulse generation device, method, and program, and more particularly, to a pulse generation device, method, and program that reduce the number of wirings and reduce the processing load of a host control device.

  A gaming machine represented by a pachinko gaming machine and a swivel type gaming machine is equipped with an effect function that appeals to the player's visual, auditory, or sensation for the purpose of improving the entertainment satisfaction of the player. For example, the production function is to perform an appropriate operation for each of the standby state, the normal game state, the reach state, and the big hit state. In recent years, even the production function itself is said to be the performance of the gaming machine. .

  In pachinko gaming machines, it has been approved to use ordinary electric and special electric instruments for a long time, and the movable body can be opened or expanded using the suction force of a game ball by a solenoid or the rotational force of a motor as a drive source, or Rotation of the start opening has been realized as a production function. Although these movable objects are directly related to games, recently, a gaming machine in which a driving source is mounted on a structure that is not directly related to games and the operation can be enjoyed has been manufactured.

  Examples of the drive source used in the rendering function of the gaming machine include a solenoid and a stepping motor.

  The solenoid attracts the metal plunger by coil excitation, and operates a so-called electric tulip, opening of a special prize opening, or two special electric accessories. In addition, the stepping motor realizes an operation of rotating the metal actuator stepwise by sequentially exciting a plurality of coils to rotate the three kinds of start ports or the specific region.

  Furthermore, recently, there are some that use a considerable number of these drive sources to realize complex movements with a movable body. As described above, the number of drive sources used per gaming machine is increasing.

  By the way, a drive signal for driving these drive sources is generated as a drive wave by a control device (CPU: Central Processing Unit) of the gaming machine.

  However, as described above, since the number of drive sources is increasing, the number of wires and the number of terminals are becoming insufficient, and the software capacity controlled by the CPU is increased, which causes secondary defects. There is. For example, when a stepping motor is driven, about 2 to 4 pulse waves with different phases are generated per motor, and the rotation speed and direction are controlled by this period, phase change angle, or generation order thereof. As a result, the software capacity itself has become enormous.

  Therefore, a technique has been proposed in which parameters such as a motor excitation method, a rotation direction, and a rotation speed are generated by a control device to simplify the hardware and reduce the software capacity (see Patent Document 1).

  In addition, there has been proposed a technique that can realize the control of the stepping motor with high resolution and high accuracy and can be realized by reducing the number of hardware points (see Patent Document 2).

Japanese Patent Laid-Open No. 6-1889597 JP 2008-54382 A

  By the way, in the latest gaming machine, in order to drive a movable accessory consisting of a movable body for production, a single control device drives a plurality of solenoids and stepping motors in a concentrated manner, and detects these driving conditions. Based on the detection result of sensors such as a position detection sensor or a limit switch, it is desired to realize a more complex operation in a movable accessory made of a movable body.

  However, in the device of a single motor represented by Patent Document 1, there is a limit to sufficiently reducing the number of wires from one control device, the number of terminals of the control device itself, and the like. There is a limit to the operation that can be realized by a movable accessory composed of a movable body driven by.

  In the technique of Patent Document 2, it is possible to control the stepping motor with high resolution and high accuracy and reduce the number of hardware, but the processing itself is very complicated. It has become.

  The present invention has been made in view of such a situation, and in controlling a plurality of drive sources to operate more sophisticated and complicated, the number of wirings is reduced, and the processing load by the host control device is reduced. It is to be able to reduce.

  A pulse generator according to one aspect of the present invention is a pulse generator that generates a pulse signal at a variable speed based on a command from a controller, and counts up or down a count value of a counter at a predetermined speed. The count means, the limit count value generating means for generating the limit count value of the counter based on the command, the limit count value and the count value of the counter are compared, and the count value is counted up Generating a pulse signal when the count value of the counter is larger than the limit count value or when the count value counts down, and when the count value of the counter is smaller than the limit count value Means and the timing at which the pulse signal is generated, Clearing the count value of the serial counter or and a clearing means for presetting.

  The pulse generator includes a frequency dividing means for generating a plurality of preset original oscillation pulse waves by frequency division, and a switching for sequentially switching the plurality of original oscillation pulse waves generated by the frequency dividing means at a predetermined time. Means for counting up the count value of the counter at a speed based on the original oscillation pulse wave switched by the switching means. Can do.

  The counting means can change the degree of counting up or down in a curved shape with the passage of time.

  The counting means causes the count value to be counted up or down to change in a pseudo curve shape formed by connecting a plurality of linear functions over time. be able to.

  The pseudo-curve-like change with the passage of time can include a pseudo-curve-like change similar to an inverse proportional function.

  The drive device of the present invention includes a receiving means for receiving a command from the control device, an operation control means for interpreting the content of the drive command based on the command, a motor, a solenoid, an LED based on the pulse signal Or a pulse generator according to any one of claims 1 to 5, further comprising output control means for driving an operating device including a sound generator.

  The operation control means retains the operation status designated by the operation status designation means until the next command is received by the reception means and the operation status designation means for designating an operation situation based on the command. It is possible to further include an operation status holding means.

  The operation control means or an output setting means for setting the output control means may be further included in the adaptive output form for each of the operation devices driven by the output control means.

  The operation control means may further include a selection means for selecting any of the plurality of output control means based on the command, and a plurality of connection means connected to the plurality of output control means. The operation status can be individually designated for each of the output control means selected by the selection means.

  Either or both of the switching means and the frequency dividing means included in the plurality of output control means can be shared by the plurality of output control means.

  A drive system comprising the control device and at least one drive device according to any one of claims 6 to 10, wherein address information for identifying each of the plurality of drive devices in a command received by the receiving means And an address identification means for identifying a plurality of the drive devices based on the address information.

  The gaming machine according to the present invention may include at least one of the pulse generation device according to claims 1 to 5, the drive device according to claims 6 to 10, or the drive system according to claim 11.

  A pulse generation method according to one aspect of the present invention is a pulse generation method of a pulse generation device that generates a pulse signal at a variable speed based on a command from a control device, and counts up a count value of a counter at a predetermined speed. Or a count step for counting down, a limit count value generating step for generating a limit count value of the counter based on the command, a comparison between the limit count value and the count value of the counter, and the count value is When counting up, when the count value of the counter is larger than the limit count value, or when the count value counts down, the pulse signal is generated when the count value of the counter is smaller than the limit count value A pulse signal generating step, and the pulse signal In timing but generated, and a clearing step of clearing the count value of the counter or preset.

  A program according to one aspect of the present invention counts up or down a count value of a counter at a predetermined speed to a computer that controls a pulse generator that generates a pulse signal at a variable speed based on a command from the controller. A count step, a limit count value generation step for generating a limit count value of the counter based on the command, a comparison between the limit count value and the count value of the counter, and the count value is counted up Generating a pulse signal when the count value of the counter is larger than the limit count value or when the count value counts down, and when the count value of the counter is smaller than the limit count value Step and the pulse signal At the timing generated, to execute a processing including a clearing step of clearing the count value or preset, the counter.

  In one aspect of the present invention, the count value of the counter is counted up or down at a predetermined speed, the limit count value of the counter is generated based on the command, the limit count value, and the count of the counter When the count value is compared, the count value is counted up, the count value of the counter is greater than the limit count value, or when the count value is counted down, the count value of the counter is When the count value is larger, the pulse signal is generated, and the count value of the counter is cleared or preset at the timing when the pulse signal is generated.

  In the pulse generator according to one aspect of the present invention, the counting means for counting up or counting down the count value of the counter at a predetermined speed is, for example, an up / down counter, and based on the command, the limit count of the counter The limit count value generation means for generating a value is, for example, a limit count generation unit, which compares the limit count value with the count value of the counter and counts up the counter when the count value is counted up. When the value is larger than the limit count value, or when the count value counts down, when the count value of the counter is smaller than the limit count value, the pulse signal generating means for generating the pulse signal is, for example, The pulse signal At a timing generated, clears the count value of the counter or The clearing means for presetting, for example, a clearing unit.

  For example, the comparison unit compares the count value of the counter counted up by the up / down counter with the limit count value generated by the limit count generation unit, and the counter count value is larger than the limit count value Generate a clock signal. When the clock signal is generated, the clearing unit clears or presets the count value of the counter, thereby initializing the count value of the counter. At this moment, the comparison unit stops generating the clock signal. That is, every time the count value counted up or down by the up / down counter is set as the limit count value, the clock signal is generated for a time corresponding to one count, whereby the pulse-shaped clock signal ( Pulse signal) is repeatedly generated.

  As a result, the pulse signal generation interval and generation time can be made variable by setting the clock speed of the up / down counter and the limit count value, so that the output signal generated based on this pulse signal It is possible to stably operate the LED, the stepping motor, the sound generator, the solenoid, and other driving sources with high control. Also, the control signal from the host control device only needs to indicate the count-up or count-down start timing, the clock speed, and the limit count value. When the drive source is actually operated, the movable body Since the drive device only needs to be self-propelled based on this control signal, it is possible to reduce the number of wires required for the distribution of the control signal and reduce the processing load of the host control device. It becomes possible to do.

  According to the present invention, when a plurality of drive sources are operated more sophisticated and complicated, it is possible to reduce the processing load of the host control device and to reduce the number of wirings according to the number of commands. .

  Embodiments of the present invention will be described below. Correspondences between the configuration requirements of the present invention and the embodiments described in the detailed description of the present invention are exemplified as follows. This description is to confirm that the embodiments supporting the present invention are described in the detailed description of the invention. Accordingly, although there are embodiments that are described in the detailed description of the invention but are not described here as embodiments corresponding to the constituent elements of the present invention, It does not mean that the embodiment does not correspond to the configuration requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  That is, the pulse generator according to one aspect of the present invention (for example, the clock signal generator 51 in FIG. 2) is a pulse generator that generates a pulse signal at a variable speed based on a command from the controller, and is a predetermined generator. Counting means (for example, up / down counter 71 in FIG. 2) for counting up the count value of the counter at a speed of, and limit count value generating means for generating the limit count value of the counter based on the command ( For example, when the limit count generation unit 72) in FIG. 2 compares the limit count value with the count value of the counter and the count value is counted up, the count value of the counter is less than the limit count value. When the count value is large or when the count value counts down, When the count value is smaller than the limit count value, the pulse signal generating means (for example, the comparison unit 73 in FIG. 2) for generating the pulse signal and the count value of the counter at the timing at which the pulse signal is generated Clearing means for clearing or presetting (for example, the clearing unit 74 in FIG. 2).

  The pulse generating means includes frequency dividing means for generating a plurality of preset original oscillation pulse waves by frequency division (for example, the frequency dividing portion 23 ′ in FIG. 16 or the frequency dividing portion 151 in FIG. 17), It further includes switching means (for example, the original oscillation selection section 91 in FIG. 16 or the frequency division switching section 174 in FIG. 17) that sequentially switches the plurality of original oscillation pulse waves generated by the frequency dividing means in a predetermined time. The counting unit can count up or down the count value of the counter at a speed based on the original oscillation pulse wave switched by the switching unit.

  The driving device of the present invention (for example, the movable body driving device 12 of FIG. 2) is driven based on receiving means (for example, the receiving unit 21 of FIG. 2) for receiving a command from the control device and the command. Operation control means for interpreting the command content (for example, the operation control unit 22 in FIG. 2) and output control means for driving an operation device including a motor, solenoid, LED, or sound generator based on the pulse signal (for example, The pulse generator according to any one of claims 1 to 5 further including an output waveform generator 53) of FIG.

  Based on the command, the operation control unit includes an operation status designating unit (for example, the operation status designating unit 43 in FIG. 2) for designating an operation status and the receiving unit until the next command is received. An operation status holding unit (for example, the operation status holding unit 52 in FIG. 2) that holds the operation status specified by the operation status specifying unit can be further included.

  The adaptive output form for each operation device driven by the output control unit is further included in the operation control unit or an output setting unit (for example, the output setting unit 83 in FIG. 2) for setting the output control unit. can do.

  The operation control means may further include a selection means (for example, a selection unit 44 in FIG. 2) for selecting any one of the plurality of output control means based on the command. The operation status can be individually designated for each of the operation devices selected by the selection unit among the plurality of operation devices connected to the output control unit.

  A drive system comprising the control device and at least one drive device according to any one of claims 6 to 10, wherein address information for identifying each of the plurality of drive devices in a command received by the receiving means And an address identifying means (for example, the address recognizing unit 42 in FIG. 2) for identifying the plurality of driving devices based on the address information.

  The gaming machine of the present invention (for example, the driving system of the gaming machine of FIG. 1) includes at least one of the pulse generators of claims 1 to 5, the driving device of claims 6 to 10, or the driving system of claim 11. Can be included.

  A pulse generation method according to one aspect of the present invention is a pulse generation method of a pulse generation device that generates a pulse signal at a variable speed based on a command from a control device, and counts up a count value of a counter at a predetermined speed. Or a count step for counting down (step S132 in FIG. 9), a limit count value generating step for generating a limit count value of the counter based on the command (step S143 in FIG. 10), the limit count value, When the count value is counted up, when the count value is larger than the limit count value, or when the count value is counted down, the count value of the counter is compared with the count value of the counter When it is smaller than the limit count value, the pulse A pulse signal generating step for generating a signal (step S147 in FIG. 10), and a clearing step (step S148 in FIG. 10) for clearing or presetting the count value of the counter at the timing at which the pulse signal is generated. Including.

  FIG. 1 is a diagram showing a configuration of an embodiment of a gaming machine drive system according to the present invention.

  This driving system is a system for driving a movable accessory made of a movable body of a gaming machine represented by a pachinko gaming machine or a spinning-type gaming machine. The drive system includes a CPU (Central Processing Unit) 11 and movable body drive devices 12-1 and 12-2. The movable body drive device 12-1 moves the motors M1-1 and M2-1 to a movable body. The driving device 12-2 includes a movable body that is driven in conjunction with the rotation of the motors M1-1, M2-1, M1-2, and M2-2 by driving the motors M2-2 and M2-2, respectively. Drive the movable accessory.

  The motors M1-1, M2-1, M1-2, and M2-2 are, for example, stepping motors, and the motors M1-1 and M2-1 are coils L1-1-1 and L2-1-1. , And the coils L1-2-1, L2-2-1, and the motors M1-2, M2-2 are rotated stepwise by switching the excitation of the coils L1-2-1, L2-2-1, respectively. The coils L1-2-2 and L2-2-2 are rotated stepwise by switching the excitation.

  The movable body driving devices 12-1, 12-2, motors M1-1, M1-2, M2-1, M2-2, and coils L1-1-1, L2-1-1, L1-2-1. , L2-2-1, L1-1-2, L2-1-2, L1-2-2, and L2-2-2, the movable body drive device 12 and the motor are simply required. M1, M2, and coils L1-1, L2-1, L1-2, and L2-2 will be referred to, and other configurations will be referred to in the same manner. Further, in FIG. 1, the CPU 11 is shown as an example of controlling the operation of the two movable body driving devices 12, but the number of the movable body driving devices 12 that the CPU 11 controls is two or more. Is also good. Further, the movable body driving device 12 will be described with respect to an example in which two motors M1 and M2 are individually driven. However, the number of motors to be controlled is not limited to two. The number of motors may be driven. Further, in FIG. 1, the movable body driving device 12 is shown as an example for driving one type of motor, but the movable body driving device 12 is not limited to a motor as long as it is a mechanism for driving a movable body. It may be.

  The CPU 11 controls the entire operation of the movable body drive system, outputs command data as serial data from the data terminal DATA in synchronization with the clock signal output from the clock terminal CK, and the movable body drive device 12-1. , 12-2, command data for driving the motors M1-1, M2-1, M1-2, and M2-2, each of which controls driving, is supplied. At this time, the CPU 11 supplies command data with address information for distinguishing which of the movable body driving devices 12-1 and 12-2 is an instruction. In addition, the CPU 11 also supplies command data with information for identifying an output system for distinguishing which of the motors M1 and M2 is an instruction. In addition, the CPU 11 supplies command data with device recognition information for identifying the device. The device recognition information is information for specifying a motor, for example, as a device. Further, for example, when a light emitting diode LED is used as a device different from the motor, information for identifying the motor is used for the motors M1 and M2. For the light emitting diode LED, command data with information for identifying the light emitting diode LED attached as device recognition information is supplied.

  In addition, the CPU 11 generates operation data indicating the drive contents as necessary according to the drive contents of the motors M1 and M2 of the movable body drive devices 12-1 and 12-2, and includes the movable body in the command data. It supplies to drive device 12-1, 12-2.

  Next, a detailed configuration example of the CPU 11 and the movable body driving device 12 will be described with reference to FIG.

  The determination unit 111 determines how to drive the stepping motors M1 and M2 corresponding to the gaming state of the gaming machine in which the movable body driving device 12 is incorporated, that is, the normal state, the reach state, and the big hit state. The determination is made, and the drive content that is the determination result is supplied to the motion data generation unit 112.

  The operation data generation unit 112 generates operation data indicating specific operation contents based on the determination result from the determination unit 111 and supplies the operation data to the command data transmission unit 113.

  The command data transmission unit 113 generates command data including the operation data supplied from the operation data generation unit 112, and serves as a destination device (as a device type, for example, a movable body drive device, LED Device recognition data for identifying (including a light emission diode) drive device) and, for example, when the movable body drive device 12 is identified as a device, address data for identifying the movable body drive device 12 is attached to the data From the output terminal DATA and the clock signal output terminal CK, command data is transmitted as serial data to all the movable body drive devices 12 in synchronization with the clock signal.

  The reception unit 21 includes a reception control unit 31 and a serial-parallel conversion unit 32. The reception unit 21 receives command data composed of serial data transmitted from the CPU 11 in synchronization with a clock signal, and converts the command data into parallel data. To the operation control unit 22. The reception control unit 31 includes a serial data reception unit 31a and a clock data reception unit 31b, and is received by the serial data reception unit 31a in synchronization with a clock signal based on the clock data received by the clock data reception unit 31b. The command data is received as serial data, and is supplied to the serial-parallel converter 32. The serial-parallel converter 32 converts serial data into parallel data and supplies the command data converted into parallel data to the operation controller 22.

  The operation control unit 22 includes a device recognition unit 41, an address recognition unit 42, an operation status designation unit 43, and a selection unit 44. When the command data supplied from the reception unit 21 is acquired, the device recognition unit built therein 41 and the address recognizing unit 42 are controlled to recognize whether or not it is command data for itself, and only when the command data is recognized for itself, the output control unit is based on the command data. Instructs output to 24-1 and 24-2.

  The device recognition unit 41 reads the device data included in the command data supplied from the CPU 11, determines whether or not the device is a device that identifies itself, and only receives the command data when the device is a device that identifies itself. This is supplied to the address recognition unit 42 in the subsequent stage. More specifically, when there are two types of devices to be identified, it is sufficient that address data for one bit is configured. For example, in the case of 0, the device is a movable body driving device, and in the case of 1, the device is an LED. A driving device may be used.

  The address recognition unit 42 reads the address data included in the command data supplied from the CPU 11 and determines whether or not the address is an address for identifying itself. This is supplied to the operation status designation unit 43 in the subsequent stage. More specifically, when there are two movable body drive devices 12 to be identified, that is, the movable body drive devices 12-1 or 12-2, address data for 1 bit may be configured. If there are, the address data has the number of bits corresponding to the number. For example, when using 3-bit address data, the movable body driving device 12-1 in FIG. 1 has its own address data setting terminals A1 to A3 (A1, A2, A3) = (Hi, Low, Low). ) Is set, the address recognition unit 42 determines that the address data (A1, A2, A3) = (Hi, Low, Low) = (1, 0, 0) and the supplied command data. Compared with the included address data, when they match, that is, when the address data is (A1, A2, A3) = (Hi, Low, Low) = (1, 0, 0), it is the address of its own Recognize. Further, for example, in the movable body driving device 12-2 in FIG. 1, the address data setting terminals A1 to A3 are (A1, A2, A3) = (Low, Hi, Low) = (0, 1, 0). ) Is set, the address recognizing unit 42 determines that the address data (A1, A2, A3) = (Low, Hi, Low) = (0, 1, 0) and the supplied command data. When the address data included is compared and coincides, that is, when the address data is (A1, A2, A3) = (Low, Hi, Low) = (0, 1, 0), it is its own address. Recognize.

  In addition, when the movable body drive device 12 is further provided, for example, when the movable body drive devices 12-1 to 12-N are provided, the data bit of the address data is set to the number of the movable body drive devices 12. Correspondingly, it is possible to cope with the problem by providing additional setting terminals correspondingly to the address identifying unit 42 and setting addresses for identifying the setting terminals.

  The frequency divider 23 includes a so-called frequency divider, and supplies a preset clock signal having a relatively high frequency f0 to the output controllers 24-1 and 24-2.

  In the case of an instruction corresponding to its own output system among the instructions from the operation control unit 22, the output control units 24-1 and 24-2 are preset by the frequency division unit 23 based on the instruction. The count values of the up / down counters 71-1 and 71-2 are sequentially counted up or down based on the clock signal having the frequency f0, and compared with the count limit value. According to the comparison result, The output waveform generation unit 53 generates an output signal having a predetermined waveform, and drives the motor M1 or M2.

  The operation status designation unit 43 designates the operation status based on the output system data and the operation data included in the command data supplied from the CPU 11, instructs the selection unit 44, and outputs the output control unit 24-1 or 24-2. To drive the stepping motors M1 and M2, respectively.

  The selection unit 44 selects either the output control unit 24-1 or 24-2 based on the output system data of the command data included in the instruction supplied from the operation status specification unit 43, and sets the operation data. Instruct the corresponding action.

  The output control units 24-1 and 24-2 are respectively from clock signal generation units 51-1 and 51-2, operation status holding units 52-1 and 52-2, and output waveform generation units 53-1 and 53-2. It is configured.

  The clock signal generation units 51-1 and 51-2 include up / down counters 71-1 and 71-2, limit count generation units 72-1 and 72-2, comparison units 73-1 and 73-2, and a settlement unit, respectively. 7, 7-4, and outputs a clock signal for generating output waveform signals for driving the stepping motors M <b> 1 and M <b> 2 to the output waveform generation unit 53.

  More specifically, as shown in FIG. 3, the up / down counter 71 counts up or counts down the count value based on a relatively high-speed clock signal f0 supplied from the frequency divider 23. And a count signal indicating the count value is supplied to the comparison unit 73. In addition, the up / down counter 71 clears the count value of the counter to 0 by the clear signal supplied from the clearing unit 74.

  The limit count generation unit 72 supplies a limit count value indicating the upper limit value (or lower limit value) of the count value of the up / down counter to the comparison unit 73 based on the limit signal supplied from the operation state holding unit 52. .

  The comparison unit 73 compares the limit count value supplied from the limit count generation unit 72 with the count value based on the count signal supplied from the up / down counter 71, and when the count value is counted up, When the count value is larger than the limit count value, a pulsed clock signal is generated and supplied to the output waveform generation unit 53.

  The operation status holding unit 52 holds the operation status supplied from the operation control unit 22, and sends the start signal and limit signal included in the operation status to the output waveform generation unit 53 and the clock signal generation unit 51, respectively. Supply.

  2 are both output waveform shaping units 81-1 and 81-2, output units 82-1 and 82-2, and output setting units 83-1 and 83-3. 2 respectively.

  The output waveform shaping unit 81 in FIG. 4 shapes the output waveform based on the setting information preset by the output setting unit 83 and supplies the output waveform to the output unit 82. The output unit 82 outputs the output waveform shaped by the output waveform shaping unit 81 from the output terminal, drives the coils L1 and L2, and drives the motor M1 or M2.

  More specifically, for example, when driving the motor M1, as shown in FIG. 4, the output setting unit 83 is provided with setting terminals SET1, SET2, and the input of these setting terminals SET1, SET2 Based on the signal, the output waveform of the output terminals V1 to V4 of the output unit 82 is set. For example, as shown in FIG. 4, when the setting terminals SET1 and SET2 are set to (SET1, SET2) = (Low, Low), respectively, a four-phase motor drive waveform is set as shown in FIG. For example, a waveform as shown at the top of FIG. 6 is output.

  Among the output waveforms of the output terminals V1 to V4 in FIG. 6, from the time t0 to t11 at the uppermost stage, the motor M1 is not driven by the coils L1 and L2 and is stopped without excitation. Further, when pre-excitation is instructed at time t11, pre-excitation is started as shown at times t11 to t20. In the preliminary excitation, the coils L1 and L2 are excited, but the drive waveform does not change and the motor M1 is stopped.

  When the rotation in the positive direction is instructed at time t20, the output waveform is sequentially shaped by the output waveform shaping unit 81 as indicated by times t20 to t38, and 90 from the output terminals V1 to V4 of the output unit 82, respectively. By outputting a square wave whose phase is shifted by °, the coils L1 and L2 are sequentially switched and excited to drive the motor M1 and rotate in the positive direction. When the stop is instructed at time t38, the outputs from the output terminals V1 to V4 of the output unit 82 are stopped and the pre-excitation state is set, but the drive waveforms of the coils L1 and L2 do not change and the motor M1 is stopped.

  Then, when rotation in the reverse direction is instructed at time t50, output waveforms are sequentially shaped by the output waveform shaping unit 81 as shown at times t50 to t76, and output from the output terminals V1 to V4 of the output unit 82. By outputting a square wave whose phase is shifted by 90 ° (the direction of shift is opposite to that at times t20 to t38), coils L1 and L2 are sequentially excited to drive motor M1 and rotate in the reverse direction. To do. At time t76, when the stop is instructed, the output from the output terminals V1 to V4 of the output unit 82 is stopped and the pre-excitation state is entered, but the motor M1 is not driven by the coils L1 and L2. Then, the motor M1 is stopped. Further, when a complete stop is instructed at time t81, the state without excitation is entered.

  For example, when the setting terminals SET1 and SET2 are set to (SET1, SET2) = (Hi, Low), respectively, a two-phase motor drive waveform is set as shown in FIG. Among the output waveforms of the output terminals V1 to V4, a waveform as shown in the middle stage is output.

  That is, when the two-phase motor is driven, since the H bridge driver is additionally connected, only the output terminals V1 and V2 are used, and the output terminals V3 and V4 are not necessary. For this reason, the output terminals V3 and V4 can be used for other purposes. In the output waveforms of the output terminals V1 to V4 in FIG. 6, the operation at the time of driving the two-phase motor shown in the middle stage is the same as that at the time of driving the four-phase motor, and the description thereof is omitted.

  Further, for example, when the setting terminals SET1, SET2 are respectively set to (SET1, SET2) = (Low, Hi), a 1-2 phase motor driving waveform is set as shown in FIG. Among the output waveforms of the output terminals V1 to V4 in FIG. 6, the waveform as shown in the lower stage is output.

  That is, when the 1-2 phase motor is driven, a waveform having an ON time: OFF time ratio of 3: 5 is output from each of the output terminals V1 to V4, and a waveform whose phase is shifted by 90 °. Since the operation at the time of driving the 1-2 phase motor shown in the lower part of FIG. 6 is the same as that at the time of driving the 4 phase motor, the description thereof is omitted.

  Further, for example, when the setting terminals SET1 and SET2 are set to (SET1, SET2) = (Hi, Hi), as shown in FIG. 5, the solenoid drive is set and each is set to ON or OFF. Is done. Since the output waveform is either ON or OFF, description of the waveform example is omitted.

  Next, the movable body drive process by the drive system of FIG. 2 will be described with reference to the flowchart of FIG.

  In step S101, the determination unit 111 sets an unprocessed device among all devices as a processing target device. Here, it is assumed that the unprocessed device is the movable body drive device 12, but other devices may be used. For example, if there is an LED drive device or the like, if it is also unprocessed, the processing target Set on the device.

  In step S <b> 102, the determination unit 111 designates an unprocessed address among all addresses for identifying the movable body driving device 12 as a processing target address.

  In step S103, the determination unit 111 determines whether one or both of the stepping motors M1 and M2 need to be driven by the output control unit 24 at the address to be processed.

  In step S103, for example, when it is determined that driving is necessary, in step S104, the operation data generation unit 112 determines the stepping motor M1 or M2 to be driven with respect to the movable body driving device 12 having the processing target address. Operation data for instructing the operation content is generated and supplied to the command data transmission unit 113. The operation data here is data for controlling generation of voltages V1-1 to V4-1 and V1-2 to V4-2 for driving the stepping motors M1 and M2 by the output waveform generation unit 53.

  In step S105, the command data transmission unit 113 instructs the operation including the supplied operation data to the movable body driving device 12 having the processing target address among the processing target devices. For example, in FIG. Command data as shown is generated and output as serial data from the data terminal DATA in synchronization with the clock signal output from the clock terminal CK.

  As shown in FIG. 8, the command data is composed of device data, address data, output system data, and operation data. For example, when generating command data addressed to the movable body driving device 12-1, device data that can identify the movable body driving device as a device is recorded in the device data. Further, address data for identifying the movable body driving device 12-1 is recorded in the address data. Further, as the output system data, data for identifying one of the output control units 24-1 and 24-2 which are output systems to be driven is recorded. As described above, the operation data includes data for controlling the generation of the voltages V1-1 to V4-1 and V1-2 to V4-2 for driving the stepping motors M1 and M2 by the output waveform generation unit 53. Is done.

  In step S111, the reception control unit 31 of the reception unit 21 determines whether or not the command data is transmitted from the CPU 11, and repeats the same processing until the command data is transmitted. In step S111, for example, when command data is transmitted from the CPU 11 by the processing in step S105, the reception control unit 31 sequentially transmits command data as serial data in synchronization with the clock signal in step S112. Is supplied to the serial-parallel converter 32. The serial-parallel conversion unit 32 converts the supplied command data including serial data into parallel data, and supplies the parallel data to the device recognition unit 41 of the operation control unit 22. The device recognition unit 41 reads the device data from the command data supplied after being converted into parallel data.

  In step S113, the device recognition unit 41 determines whether or not the read device data indicates a device for identifying itself. In step S113, for example, when it is determined that the read device data does not indicate a device for identifying itself, the device recognition unit 41 discards the supplied command data, and the process returns to step S111. . That is, in this case, the supplied command data is regarded as not being for itself, and the process is terminated. As a result, the processing is aborted in devices other than the device corresponding to the device designated as the command data destination, and only the driving device corresponding to the device designated as the command data destination performs the subsequent processing. Become.

  On the other hand, in step S113, for example, when it is determined that the read device data indicates a device for identifying itself, in step S114, the device recognition unit 41 sends the supplied command data to the address recognition unit 42. Supply. In response to this processing, the address recognition unit 42 reads the address data from the supplied command data.

  In step S115, the address recognition unit 42 determines whether or not the read address data indicates an address for identifying itself. In step S115, for example, when it is determined that the read address data does not indicate an address for identifying itself, the address recognition unit 42 discards the supplied command data, and the process returns to step S111. . That is, in this case, the supplied command data is regarded as not being for itself, and the process is terminated. As a result, except for the movable body drive device 12 corresponding to the address designated as the destination of the command data, the process is aborted, and only the movable body drive device 12 corresponding to the address designated as the destination of the command data is thereafter Will be executed.

  On the other hand, in step S115, for example, when it is determined that the read address data indicates an address for identifying itself, in step S116, the address recognition unit 42 reads all the supplied command data, and the operation status This is supplied to the designation unit 43.

  In step S117, the operation status specifying unit 43 reads the operation data from the command data, and recognizes the operation content instructed as an operation in step S118.

  In step S119, the operation state designating unit 43 reads the output system data from the command data, and recognizes the output system to which the operation data is supplied.

  In step S120, the operation status designation unit 43 designates the operation status from the operation data, designates the output control unit 24 corresponding to the recognized output system, and supplies the operation data together with the output system data to the selection unit 44. To do. In response to this, the selection unit 44 instructs the output control unit 24 to be selected on the operation status based on the output system data. At this time, the operation state holding unit 52 holds the supplied operation state by the process of step S142 described later with reference to FIG. Then, the process returns to step S111.

  On the other hand, if it is determined in step S103 that driving is not necessary, the processes in steps S104 and S105 are skipped.

  In step S <b> 106, the determination unit 111 determines whether there is an unprocessed address among all the addresses that identify the movable body driving device 12. That is, it is determined whether or not the processing has been completed for all of the movable body drive devices 12 whose operations should be managed by the CPU 11. If there is an unprocessed address in step S106, the process returns to step S102. That is, the processing of steps S102 to S106 is repeated until the processing is completed for all of the movable body driving devices 12 whose operations are to be managed by the CPU 11. If it is determined in step S106 that the process has been completed for all addresses and the process has been completed for all of the movable body drive devices 12 whose operations should be managed by the CPU 11, the process proceeds to step S107.

  In step S <b> 107, the determination unit 111 determines whether there is an unprocessed device among all devices that identify the drive device 12. That is, it is determined whether or not the processing has been completed for all the devices whose operation should be managed by the CPU 11. If there is an unprocessed device in step S107, the process returns to step S101. That is, the processing of steps S101 to S107 is repeated until the processing is completed for all of the drive devices whose operations should be managed by the CPU 11. If it is determined in step S107 that the process has been completed for all addresses and the CPU 11 has determined that the process has been completed for all of the drive devices whose operations should be managed, the process proceeds to step S108.

  In step S108, the determination unit 111 regards all addresses as unprocessed for all devices, and the process returns to step S101.

  That is, the CPU 11 cyclically monitors the operating status of all devices, that is, all the driving devices, and instructs driving as necessary. In this case, when driving the driving device, it is only necessary to indicate the operation once, so that the processing load on the CPU 11 is reduced.

  Next, the counting process of the up / down counter will be described with reference to the flowchart of FIG.

  In step S131, the up / down counter 71 resets the up / down counter to zero.

  In step S132, the up / down counter 71 counts (increments or decrements) the count value in synchronization with the clock signal having the frequency f0 generated by frequency division by the frequency divider 23, and corresponds to the count value. The count signal is supplied to the comparison unit 73.

  In step S <b> 133, the up / down counter 71 determines whether or not a clear signal is supplied from the clearing unit 74. In step S133, for example, when the clear signal is not supplied from the clearing unit 74, the process returns to step S132. That is, until the clear signal is supplied from the clearing unit 74, the up / down counter 71 continues to add or subtract the count value in synchronism with the clock signal from the frequency divider 23.

  On the other hand, when a clear signal is supplied from the clearing unit 74 in step S133, the process returns to step S131. That is, after the count value is reset, the count value is counted up or down again cumulatively.

  By the above processing, the up / down counter 71 continues to count up or count down until the clear signal is supplied from the clearing unit 74, and sequentially supplies the count value to the comparison unit 73, and the clear signal Is supplied, the count value is reset, the count value is continuously counted up or down again, and the count value is continuously supplied to the comparator 73.

  Next, output control processing by the output control unit 24 will be described with reference to the flowchart of FIG.

  In step S141, the operation status holding unit 52 determines whether an output control process is instructed to its output system, and repeats the process until it is determined that the instruction has been instructed. In step S141, for example, when operation data instructing the output control process is supplied by the process of step S120, the process proceeds to step S142.

  In step S142, the operation status holding unit 52 holds the supplied operation data.

  In step S <b> 143, the operation status holding unit 52 supplies limit count information to the limit count generation unit 72 based on the held operation data. The limit count generation unit 72 supplies a limit count signal to the comparison unit 73 based on the limit count information.

  In step S144, the operation status holding unit 52 determines whether or not it is a start timing for starting the processing based on the operation data, and repeats the same processing until it is determined that it is the start timing. If it is determined in step S144 that it is the start timing, the operation state holding unit 52 supplies the start signal to the output waveform shaping unit 81 of the output waveform generation unit 53 in step S145.

  In step S146, the comparison unit 73 compares the count value based on the count signal sequentially supplied from the up / down counter 71 with the limit count value based on the limit count signal supplied from the limit count generation unit 72. Whether or not the count value based on the count signal is larger than the limit count value based on the limit count signal is determined. In step S146, for example, when it is determined that the count value is larger than the limit count value, in step S147, the comparison unit 73 supplies a clock signal to the output waveform generation unit 53 and the settlement unit 74. In response to this clock signal, the output waveform generator 53 generates a drive signal to drive the stepping motor M1 (or M2), and drives the stepping motor M1 (or M2) by exciting the coils L1 and L2.

  In step S148, when the clearing unit 74 receives a pulse signal that is a pulsed clock signal, the clearing unit 74 supplies a clear signal to the up / down counter 71 to reset the count value of the up / down counter, and the process proceeds to step S150. . In step S147, the clock signal is generated after it is determined that the count value is larger than the limit count value and is preset by the clear signal. Since only one period until the up / down counter is counted is 1, the clock signal is a pulse signal for one count of the up / down counter.

  On the other hand, in step S146, for example, when it is determined that the count value of the up / down counter 71 is not higher than the limit count value, in step S149, the comparison unit 73 sends the output waveform generation unit 53 and the clearing unit 74 a check. In contrast, no clock signal is generated. For this reason, since the output waveform generation unit 53 does not generate a drive signal, the stepping motor M1 (or M2) is not driven.

  In step S150, the operation state holding unit 52 determines whether or not it is time to stop. If it is determined that it is not time to stop, the process returns to step S146.

  On the other hand, if it is determined in step S150 that it is time to stop, the process returns to step S141, and the subsequent processes are repeated.

  The above operation is summarized as follows.

  That is, when the upper limit value of the up / down counter 71 is 256, for example, and the count value is not set, the count value K1 indicating the count signal of the up / down counter 71 is As indicated by the solid line 11, the count value repeatedly increases from 0 to 256 repeatedly at an interval of 256 × 1 / f0 (f0 is the frequency of the clock signal supplied from the frequency divider 23). In FIG. 11, the count value K1 is expressed so as to change linearly, but strictly speaking, the count value K1 changes stepwise at intervals of 1 / f0.

  Here, as shown in FIG. 12, the count limit value K2 = 64 is set at time t1, and the count limit value K2 = 192 is set at time t2.

  In this case, from time t1 to time t2, as shown in the upper part of FIG. 13, the count value K1 reaches the count value K1 when the count value K1 of the up / down counter 71 reaches 64. Since the value K2 is exceeded by one cycle (1 / f0), the comparison unit 73 generates a pulsed clock signal K3 as shown in the lower part of FIG. 53. Therefore, the pulse signal composed of the pulse-shaped clock signal becomes a pulse signal having a width of 1 / f0 that is repeatedly generated at a cycle of 64 × 1 / f0.

  Similarly, after time t2, as shown in the upper part of FIG. 14, time C11, C12, C13... When the count signal K1 indicating the count value of the up / down counter 71 reaches 192, Since the count value exceeds the limit count signal K2 indicating the limit count value by one cycle (1 / f0) in the period, the comparison unit 73 during that period, as shown in the lower part of FIG. Is supplied to the output waveform generator 53. Therefore, this pulse signal becomes a pulse signal having a width of 1 / f0 that is repeatedly generated at a cycle of 192 × 1 / f0.

  As a result, for example, in the output waveform generator 53, as shown in FIG. 15, when the limit count value is set to 64 at time t1, each cycle of 64 × 1 / f0 from time t101 to t119 ( By repeatedly generating the pulse signal K3 at a time interval, the output terminal V1 generates a pulse waveform from time t1 to t102, t104 to t106, t108 to t110, t112 to t114, t116 to t118. Similarly, the output terminal V2 generates a pulse waveform at times t101 to t103, t105 to t107, t109 to t111, t113 to t115, and t117 to t119. Similarly, the output terminal V3 generates pulse waveforms at times t102 to t104, t106 to t108, t110 to t112, t114 to t116, and t118 to t2. Further, the output terminal V4 generates a pulse waveform from time t1 to t101, time t103 to t105, t107 to t109, t111 to t113, t115 to t117, t119 to t2.

  Further, as shown in FIG. 15, when the limit count value is set to 192 at time t2, the pulse signal K3 is repeatedly generated at each 192 × 1 / f0 period (time interval) from time t2 to t121. As a result, the output terminal V1 generates a pulse waveform at times t2 to t122, t124 to t126, and t128 to t130. Similarly, the output terminal V2 generates a pulse waveform at times t121 to t123, t125 to t127, and t129 to t130. Similarly, the output terminal V3 generates a pulse waveform at times t122 to t124 and t126 to t128. Further, the output terminal V4 generates a pulse waveform from time t2 to t121, time t123 to t125, and t127 to t129.

  As described above, during the time t1 to t2, the stepping motor is controlled to rotate at about three times the speed after the time t2. At this time, only the start timing and its limit count value are controlled, the rotation start timing and its rotation speed are controlled, and no other information is required, so only the information was supplied first. Thus, since the movable body drive device 12 is self-propelled, the control load of the control unit 11 can be extremely reduced.

  In the above description, an example in which the clock signal generated from the frequency divider 23 is one type having the frequency f0 has been described. For example, as shown in FIG. 16, two types of frequencies are generated by the frequency divider 23 ′. The clock signals f1 and f0 may be generated, and one of the clock signals may be switched and used by the original oscillation selection unit 91. By doing so, it becomes possible to change the drive pattern of the stepping motor M1 (or M2).

  Two or more types of clock signals may be generated by the frequency divider 23 '. In addition, by using the original oscillation selection unit 91 to include information instructing which clock signal is selectively switched and used in the operation data, various clock signals can be used. The stepping motor M1 (or M2) can be driven in various patterns.

  In the above description, the example in which the up / down counter 71 starts counting up or counts down and reaches the limit count value is counted up or counted down based on the same clock signal. The clock signal may be sequentially switched at predetermined time intervals until the count value reaches the limit count value after the up / down counter 71 starts counting up or counting down.

  FIG. 17 shows a movable body drive device in which the clock signal is sequentially switched at a predetermined time interval until the count value reaches the limit count value after the up / down counter 161 starts counting up or counting down. 12 configuration examples are shown. In FIG. 17, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  That is, the movable body drive device 12 in FIG. 17 differs from the movable body drive device 12 in FIG. 2 in place of the frequency divider 23 and the up / down counters 71-1 and 71-2. The up / down counters 161-1 and 161-2 are provided.

  The frequency divider 151 generates n types of clock signals of frequencies f0, f1,... Fn as the original oscillation, and supplies them to the output controllers 24-1 and 24-2, respectively.

  The up / down counter 161 is a counter that counts up or down a count value by using any one of n types of clock signals having frequencies f0, f1,... Fn supplied from the frequency divider 151. Yes, a count signal corresponding to the count value is supplied to the comparison unit 73.

  The up / down counters 161-1 and 161-2 include count units 171-1 and 171-2, switching counter control units 172-1 and 172-2, rate counter control units 173-1 and 173-2, and frequency division switching. Parts 174-1 and 174-2, and curvature setting parts 175-1 and 175-2.

  The frequency division switching unit 174 has the frequencies f0, f1, f1 at a predetermined timing according to the count rate (change rate: the number of counts per unit time) set in advance by the rate counter M controlled by the rate counter control unit 173. .. Are switched to one of the clock signals fn and supplied to the counting unit 171.

  The counting unit 171 counts the count value in synchronization with the clock signal switched by the frequency division switching unit 174 and outputs the count value to the comparison unit 73. The switching counter control unit 172 counts the switching counter C indicating the timing of switching the count rate in synchronization with the clock signal switched by the frequency division switching unit 174, and when the switching counter value corresponds to the rate counter M. The rate counter control unit 173 and the frequency division switching unit 174 are notified of the timing.

  When the rate counter control unit 173 is notified by the switching counter control unit 172 that the switching counter C has reached the switching count value, the rate counter control unit 173 increments the rate counter M by 1 at that timing.

  When the frequency division switching unit 174 is notified by the switching counter control unit 172 that the switching counter C has reached the switching count value, the frequency dividing switching unit 174 generates a clock signal having a frequency fn corresponding to the count rate corresponding to the rate counter M at that timing. Switch.

  The curvature setting unit 175 stores a preset switching count value for each rate counter M, and supplies a switching count value corresponding to the rate counter M for identifying the count rate to the switching counter control unit 172. Based on the count rate set for each rate counter M and the corresponding switching count value, a period for switching to a clock signal of a different frequency divided by the frequency divider 151 is set, and the count of the up / down counter 161 is set. The value counting speed is changed in a pseudo curve with respect to time, and the curvature of the pseudo curve is set. Here, it is assumed that the count rate decreases as the rate counter M increases. That is, the up / down counter 161 is counted up or down by a clock signal having a higher frequency as the rate counter M is smaller. Therefore, the up / down counter 161 is counted up or down at a high speed. Since it counts up or counts down by a low clock signal, it counts up or counts down at a low speed.

  Next, the up / down counter counting process will be described with reference to the flowchart of FIG.

  In step S161, the count unit 171 of the up / down counter 161 resets the counter to zero.

  In step S162, the rate counter control unit 173 initializes the rate counter M to 1.

  In step S163, the switching counter control unit 172 resets the switching counter C that switches the count rate to 0.

  In step S164, the frequency division switching unit 174 supplies the frequencies f0, f1,... Supplied from the frequency division unit 151 at the count rate preset in the curvature setting unit 175 corresponding to the rate counter M. Any one of fn is selected as a clock signal to be counted by the counting unit 171. For example, when the curvature is set so as to change steeply when the count value is small and gradually change as the count value increases, the rate counter M is the smallest in the first processing, so the clock having the fastest frequency is used. It is instructed to select a signal.

  In step S165, the counting unit 171 counts the up / down counter (increments by 1) in synchronization with the clock signal having the frequency selected by the frequency division switching unit 174, and supplies it to the comparison unit 73.

  In step S166, the switching counter control unit 172 counts the switching counter C (increments by 1) in synchronization with the clock signal having the frequency selected by the frequency division switching unit 174.

  In step S167, the counting unit 171 determines whether or not a clear signal has been supplied from the clearing unit 74. In step S167, for example, when a clear signal is supplied, the process returns to step S161. That is, by this process, the count value of the up / down counter 161 is reset to 0, and the same process is repeated.

  On the other hand, if no clear signal is supplied in step S167, in step S168, the switching counter control unit 172 sets the switching counter C for each rate counter M preset in the curvature setting unit 175. It is determined whether or not a switching count value that is a predetermined value is reached. For example, when the switching counter C is not the switching count value set for each rate counter M preset in the curvature setting unit 175, the process returns to step S164. That is, unless the clear signal is supplied until the switching counter C reaches the switching count value set for each rate counter M preset in the curvature setting unit 175 in step S168, steps S164 to S164 are performed. The processing of S168 is repeated, and the up / down counter and the switching counter C are sequentially incremented by 1 at a count rate synchronized with a clock signal having a frequency corresponding to the rate counter M.

  If it is determined in step S168 that the switching counter C is a switching count value preset in the curvature setting unit 175 for each rate counter M, the counting unit 171 counts the counted value in step S169. Is not the maximum value, and if not, the process proceeds to step S170.

  In step S170, the rate counter control unit 173 increments the rate counter M by 1, and the process returns to step S163.

  That is, when the rate counter M is incremented by 1, the process returns to step S163 again, the switching counter control unit 172 resets the switching counter C to 0, and the frequency division switching unit 74 sets the newly set rate. Based on the clock signal corresponding to the count rate corresponding to the counter M, the count value of the up / down counter 161 is counted by the counting unit 171 and the switching counter C is counted.

  By the above processing, for example, the counting of the up / down counter 161 is started at the time ta in FIG. 19, and the clock signal having the frequency counted by the clock signal having the clock frequency of the count rate corresponding to the rate counter M = 1 is obtained. When selected by the frequency division switching unit 174, the processing of steps S164 to S168 is repeated until the switching counter C1 which is a predetermined switching count value set in the curvature setting unit 175 corresponding to the rate counter M = 1. Thus, the up / down counter 161 is counted at a count rate corresponding to the rate counter M = 1. At this time, the count value of the up / down counter 161 changes linearly as shown by a one-dot chain line M1 at times ta to tb in the figure (in the figure, it is a straight line, but in detail, the value is a step. Is changing). Then, as shown at the timing of time tb in FIG. 19, when the switching counter C becomes the switching counter C1 in step S168 and is regarded as the switching count value, it is regarded as not the maximum value in step S169. In step S170, the rate counter M is incremented by 1 so that the rate counter M = 2.

  Then, steps S164 to S168 are repeated until the switching counter C2 which is a predetermined switching count value set corresponding to the rate counter M = 2, and the clock frequency of the count rate corresponding to the rate counter M = 2 is set. The count value of the up / down counter 161 is counted by the clock signal. At this time, as indicated by an alternate long and short dash line M2 at times tb to tc in FIG. 19, the count value of the up / down counter 161 changes to a gentler linear shape than at times ta to tb. Here, as shown at the timing of time tc in FIG. 19, if it is assumed in step S168 that the switching counter C has become the switching counter C2 and has reached the switching count value, it is considered in step S169 that it is not the maximum value. In step S170, the rate counter M is incremented by 1 so that the rate counter M = 3.

  Further, steps S164 to S168 are repeated until the switching counter C3 having a predetermined switching count value set corresponding to the rate counter M = 3, and the clock frequency of the count rate corresponding to the rate counter M = 3 is changed. The count value of the up / down counter 161 is counted by the clock signal. At this time, as indicated by a one-dot chain line M3 at times tc to td in FIG. 19, the value of the up / down counter changes to a gentler linear shape than at times tb to tc. Here, as indicated by the timing of time td in FIG. 19, if the switching counter C becomes the switching counter C3 in step S168 and is considered to have reached the switching count value, it is considered not to be the maximum value in step S169. In step S170, the rate counter M is incremented by 1 so that the rate counter M = 4.

  Further, steps S164 to S168 are repeated until the switching counter C4 which is a predetermined switching count value set corresponding to the rate counter M = 4, and the clock of the count rate corresponding to the rate counter M = 4. The count value of the up / down counter 161 is counted by the frequency clock signal. At this time, as indicated by an alternate long and short dash line M4 at times td to te in FIG. 19, the count value of the up / down counter 161 changes to a gentler straight line than at times tc to td. Here, as indicated by the timing te in FIG. 19, when the switching counter C becomes the switching counter C4 in step S168 and is regarded as the switching count value, it is further assumed that the maximum value is obtained in step S169. If it is regarded (the maximum value is 256 counts in FIG. 19) or a clear signal is supplied in step S167, the process returns to step S161 and the same process is repeated.

  By this processing, for example, if the time from time ta to te is 1 ms, the pseudo curve shown in FIG. 19 (a straight line with different slopes composed of linear functions set as different count rates for a plurality of sections). 19 are continuously arranged, it is possible to generate a waveform similar to the curve as shown by the solid line in FIG.

  As described above, the curvature setting unit 175 stores the clock signal of the clock frequency corresponding to the count rate, which is stored in association with the rate counter M, and the switching count value indicating the period to be counted at the count rate. The curvature of the pseudo curve indicating the change in the count value of the up / down counter 161 is set. In addition, in FIG. 19, although the example which implement | achieves a pseudo curve with four straight lines is demonstrated with respect to the curve shown with a solid line, it uses it so that the straight line shown as more linear functions may be connected. However, by switching the number of straight lines, it is possible to realize a pseudo curve that is more similar to a curve.

  With the control described above, PPS (Pulse Par Second) control of the stepping motor can be realized. PPS control is to control the progress of the phase by the number of pulses generated per second. Therefore, in general, when PPS control is performed by a counter (corresponding to the up / down counter 161), 1000PPS (1.000 ms / pulse) is assumed to be the highest speed when the counter count value = 1 (minimum value) (1 If the maximum speed is 1000 pulses per second), and the minimum value is 4PPS when the count value is the maximum value, the result is as follows.

  That is, when the count value of the counter is 1, 1000 PPS (1.000 ms / pulse), when the count value = 2, 996 PPS (1.004 ms / pulse), and when the count value is 3, 992 PPS (1.008 ms / pulse) When the count value = 4, it becomes 988PPS (1.012ms / pulse). When the count value = 254, it becomes 12PPS (83.3ms / pulse). When the count value = 255, 8PPS (125ms / pulse) When the count value = 256, 4PPS (minimum speed) (250 ms / pulse) is obtained.

  Summarizing the above relationship, the count value of the counter and the pulse period of each PPS are in a relationship proportional to the reciprocal, that is, an inversely proportional relationship. For this reason, when used for PPS control, the up / down counter 161 performs switching in a pseudo curve, so that it is not a triangular saw wave as shown in the upper part of FIG. It becomes a substantially convex hyperbolic curve.

  In FIG. 20, the count swing width is 32768 steps (0 to 32768 steps with respect to the up / down counters 1 to 256), the rising time is 250 ms and one cycle, and the count clearing operation is expressed. Has been.

  Along with this, a clock signal in the vicinity of 1 to 2 MHz is used as the frequency of the original oscillation generated by the frequency divider 151. Further, in the initial stage of counting up (0 to 128 steps in FIG. 20), the count value of the up / down counter 161 remains 0 for a period of about 1 ms, and thereafter, the set values 1, 2,... As it increases, the pulse period increases by 4 μs and increases to 1 ms, 1.004 ms, and 1.008 ms.

  Eventually, the count clock frequency is sequentially switched to the low speed direction, and the setting value 256 becomes 250 ms. Such a waveform is repeated in the same manner as the sawtooth waveform shown in the upper part of FIG.

  As a result, the rotation of the stepping motor can be controlled more smoothly. Further, by sharing the same clock signal and using it in the plurality of output control units 24, it is possible to smoothly control the rotation while synchronizing the plurality of stepping motors.

  In the above description, the comparison unit 73 has been described with respect to the example of the clock signal generation unit 51 that generates the pulse signal by comparing the count value of the up / down counter with the limit count value. It may be changed at a frequency lower than the frequency of the down counter.

  The clock signal generation unit 51 in FIG. 21 shows a configuration example of the clock signal generation unit 51 that generates the limit count value while changing it at a frequency lower than the frequency of the up / down counter. In the clock signal generation unit 51 of FIG. 21, the same components as those of the clock signal generation unit 51 of FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In other words, the clock signal generation unit 51 in FIG. 21 differs from the clock signal generation unit 51 in FIG. 3 in that instead of the frequency division unit 23, the up / down counter 71, and the limit counter 72, the frequency division unit 191 A down counter 203, a low frequency up / down counter 202, and a frequency selection unit 201 are provided.

  The high frequency up / down counter 203 is the same as the up / down counter 71, and increases or decreases the count value of the counter in response to the clock signal having the high frequency f0 supplied from the frequency divider 191. Thus, the corresponding count signal K1 is supplied to the comparison unit 73. In FIG. 21, the high frequency up / down counter 203 is simply named “high frequency” in order to distinguish the frequency of the clock signal generated by the low frequency up / down counter 202. Are the same.

  The low frequency up / down counter 202 compares the limit value in the limit count generation unit 72 with the high frequency f0, and any one of the relatively low frequencies f1, f2, and f3 generated by the frequency division unit 191. In synchronization with the clock signal selected by the selection unit 201, the count value of the counter is increased or decreased to count to the limit count value defined by the limit signal, and when the limit count value is reached, the value is maintained. In addition, the corresponding count signal K2 is supplied to the comparison unit 73.

  21 is the same as the operation in the clock signal generation unit 51 in FIG. 3, and therefore the description thereof is omitted.

  However, in the clock signal generation unit 51 in FIG. 21, the limit count value changes depending on the clock signal having a low frequency, so that, for example, as shown by the dotted line in the upper part of FIG. If the limit count value is set to increase at the timing from time t203 to t206, the time t203 to t204, the time t204 to t205, and the period at which the pulse signal is generated at the time t201 to t202 and the time t202 to t203, and From time t205 to time t206, the cycle gradually extends, and the rotation speed of the stepping motor M1 or M2 is gradually decreased with the passage of time, and is output from the low frequency up / down counter 202 again. Coun Value has reached the limit count value, when the value is constant is maintained, the interval time t206 to t207 the pulse signal while being maintained is generated.

  Thus, by changing the limit count value at a frequency lower than the frequency of the up / down counter, the pulse signal generation interval (the generation period of the drive signal by the pulse signal) can be gradually changed.

  As a result, the operation speed of the stepping motor can be controlled while gradually changing. In addition, since this speed change can be changed according to the frequency of the clock signal selected by the frequency selection unit 201, the change speed can be switched only by instructing which clock signal is selected by the command data. It becomes possible.

  In the above, an example in which a plurality of movable bodies are driven in the drive system has been described. For example, the target to be driven is not only the movable body but also, for example, a light emitting diode as shown in FIG. The drive device which combined the device to make may be sufficient.

  In the drive system of FIG. 23, an LED drive device 251 is provided in addition to the movable body drive device 12. The LED driving device 251 controls the light emission of the light emitting diodes LED1 to LED6. When driving the movable body, command data with device data and address data is supplied from the CPU 11 to instruct which speed of which stepping motor is to be rotated. If the data that can be identified by the LED driving device 251 is included, it can be recognized that it is command data for itself, and further, when controlling the rotation to the stepping motor, the rotation speed depends on the generation interval of each pulse. However, since it is possible to control the brightness of the light emitting diodes and the like by specifying the frequency of voltage application to each of the light emitting diodes, the light emission can be controlled by the same command data.

  Further, not only the light emitting diode but also a solenoid, a sound generator that generates sound, and the like can be similarly controlled by switching the generation frequency of similar pulse signals.

  With the above processing, it is possible to control advanced operations spontaneously only by receiving command data once from the CPU 11, so that it is possible to reduce the communication frequency and judgment processing of the command data of the CPU 11, and the processing of the CPU 11 The load can be reduced.

  Further, the operation forms of the driving source such as the motor, solenoid, light emission of the light emitting diode, and sound generation can be operated in various patterns by changing the output setting in advance.

  According to the present invention, it is possible to reduce the number of wirings and reduce the processing load of a host control device when controlling a plurality of drive sources to operate more sophisticated and complicated.

  Incidentally, the series of monitoring processes described above can be executed by hardware, but can also be executed by software. When a series of processing is executed by software, a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a recording medium in a general-purpose personal computer or the like.

  FIG. 24 shows a configuration example of a general-purpose personal computer. This personal computer incorporates a CPU (Central Processing Unit) 1001. An input / output interface 1005 is connected to the CPU 1001 via the bus 1004. A ROM (Read Only Memory) 1002 and a RAM (Random Access Memory) 1003 are connected to the bus 1004.

  The input / output interface 1005 includes an input unit 1006 including an input device such as a keyboard and a mouse for a user to input an operation command, an output unit 1007 for outputting a processing operation screen and an image of a processing result to a display device, a program and various data. A storage unit 1008 including a hard disk drive for storing data, a LAN (Local Area Network) adapter, and the like, and a communication unit 1009 for performing communication processing via a network represented by the Internet are connected. Also, a magnetic disk (including a flexible disk), an optical disk (including a CD-ROM (Compact Disc-Read Only Memory), a DVD (Digital Versatile Disc)), a magneto-optical disk (including an MD (Mini Disc)), or a semiconductor A drive 1010 for reading / writing data from / to a removable medium 1011 such as a memory is connected.

  The CPU 1001 is read from a program stored in the ROM 1002 or a removable medium 1011 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, installed in the storage unit 1008, and loaded from the storage unit 1008 to the RAM 1003. Various processes are executed according to the program. The RAM 1003 also appropriately stores data necessary for the CPU 1001 to execute various processes.

  In this specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in time series in the order described, but of course, it is not necessarily performed in time series. Or the process performed separately is included.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

It is a figure which shows the structure of embodiment of the drive system to which this invention is applied. It is a figure which shows the structural example of embodiment of a movable body drive device. It is a figure which shows the structural example of a clock signal generation part and an output waveform generation part. It is a figure which shows the example of a setting in the output waveform generation part of FIG. It is a figure which shows the example of a setting in the output waveform generation part of FIG. It is a figure which shows the example of a setting in the output control part of FIG. It is a flowchart explaining a movable body drive process. It is a figure which shows the structural example of command data. It is a flowchart explaining the up / down counter count process by the clock signal generation part of FIG. It is a flowchart explaining an output control process. It is a figure explaining the process of a clock signal generation part. It is a figure explaining the process of a clock signal generation part. It is a figure explaining the process of a clock signal generation part. It is a figure explaining the process of a clock signal generation part. It is a figure explaining the process of a clock signal generation part. It is a figure which shows the other structural example of a clock signal generation part. It is a figure which shows the structural example of other embodiment of a movable body drive device. It is a flowchart explaining the up / down counter count process by the clock signal generation part of FIG. It is a figure explaining the up / down counter count process by the clock signal generation part of FIG. It is a figure explaining the up / down counter count process by the clock signal generation part of FIG. It is a figure which shows a clock signal generation part other structural example. It is a figure explaining the up / down counter count process by the clock signal generation part of FIG. It is a figure which shows the structure of other embodiment of a drive system. And FIG. 11 is a diagram illustrating a configuration example of a general-purpose personal computer.

Explanation of symbols

11 CPU
12, 12-1, 12-2 Movable body drive device 21 Receiving unit 22 Operation control unit 23 Dividing unit 24, 24-1, 24-2 Output control unit 41 Device recognition unit 42 Address recognition unit 43 Operation status designation unit 44 Selection unit 51, 51-1, 51-2 Clock signal generation unit 52, 52-1, 52-2 Operation status holding unit 53, 53-1, 53-2 Output waveform generation unit 81, 81-1, 81-2 Output waveform shaping unit 82, 82-1, 82-2 Output unit 83, 83-1, 83-2 Output setting unit

Claims (14)

In a pulse generator that generates a pulse signal at a variable speed based on a command from a control device,
Counting means for counting up or down the count value of the counter at a predetermined speed;
Limit count value generating means for generating a limit count value of the counter based on the command;
When the count value of the counter is compared with the count value of the counter and the count value is counted up, when the count value of the counter is larger than the limit count value, or when the count value is counted down, Pulse signal generating means for generating the pulse signal when the count value of the counter is smaller than the limit count value;
Clearing means for clearing or presetting the count value of the counter at a timing at which the pulse signal is generated. The pulse generator is
A frequency dividing means for generating a plurality of preset original oscillation pulse waves by frequency division;
Switching means for sequentially switching the plurality of original oscillation pulse waves generated by the frequency dividing means at a predetermined time;
The pulse generation device according to claim 1, wherein the counting unit counts up or counts down a count value of the counter at a speed based on the original oscillation pulse wave switched by the switching unit. The pulse generation device according to claim 1, wherein the count unit counts up or counts down the count value and changes in a curve with the passage of time. 2. The counting means changes the count value of the count value up or down to a pseudo curve shape constructed in a pseudo manner by connecting a plurality of linear functions over time. The pulse generator according to any one of 1 to 3. The pulse generator according to claim 3 or 4, wherein the pseudo-curve-like change over time includes a pseudo-curve-like change similar to an inverse proportional function. Receiving means for receiving a command from the control device;
Based on the command, operation control means for interpreting the drive command content,
6. A drive device comprising the pulse generator according to claim 1, further comprising output control means for driving an operation device including a motor, a solenoid, an LED, or a sound generator based on the pulse signal. . The operation control means includes
Based on the command, an operation status specifying means for specifying an operation status;
The driving apparatus according to claim 6, further comprising an operation state holding unit that holds the operation state designated by the operation state designation unit until a next command is received by the reception unit. The drive device according to claim 6, further comprising an output setting unit that sets an adaptive output form for each of the operation devices driven by the output control unit in the operation control unit or the output control unit. The operation control means includes
A selection means for selecting any of the plurality of output control means based on the command;
9. The operation status is individually specified for each of the operation devices selected by the selection unit among the plurality of operation devices connected to the plurality of output control units. Drive device. The drive device according to claim 9, wherein either or both of the switching unit and the frequency dividing unit included in the plurality of output control units are shared by the plurality of output control units. The command received by the receiving means includes address information for identifying each of the plurality of drive devices,
11. A drive system comprising the control device and at least one drive device according to any one of claims 6 to 10, further comprising address identification means for identifying a plurality of the drive devices based on the address information.   A gaming machine comprising at least one of the pulse generation device according to claim 1, the drive device according to claim 6, or the drive system according to claim 11. In a pulse generation method of a pulse generator that generates a pulse signal at a variable speed based on a command from a control device,
A count step for counting up or down the count value of the counter at a predetermined speed;
A limit count value generating step for generating a limit count value of the counter based on the command;
When the count value of the counter is compared with the count value of the counter and the count value is counted up, when the count value of the counter is larger than the limit count value, or when the count value is counted down, A pulse signal generating step for generating the pulse signal when the count value of the counter is smaller than the limit count value;
A clearing step of clearing or presetting the count value of the counter at a timing at which the pulse signal is generated. Based on a command from the control device, a computer that controls a pulse generator that generates a pulse signal at a variable speed,
A count step for counting up or down the count value of the counter at a predetermined speed;
A limit count value generating step for generating a limit count value of the counter based on the command;
When the count value of the counter is compared with the count value of the counter and the count value is counted up, when the count value of the counter is larger than the limit count value, or when the count value is counted down, A pulse signal generating step for generating the pulse signal when the count value of the counter is smaller than the limit count value;
A clearing step of clearing or presetting the count value of the counter at a timing at which the pulse signal is generated.

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