JP2010027734A - Nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device including an element chip that is advantageous for reducing the area of an element chip and can be mass-produced with excellent cost efficiency.
In a nitride semiconductor device 1, a source pad 8 and a gate pad 9 formed on one surface 51 of an element chip 5 are joined to a submount 4 to be electrically connected to the submount 4. On the other hand, the aluminum wire 14 is bonded to the drain electrode 10 formed on the other surface 52 of the element chip 5. Then, the width W (width in the first direction) of the drain electrode 10 to which the aluminum wire 14 is joined is set to be twice or less the wire diameter D of the aluminum wire 14. Further, the length L (width in the second direction) of the drain electrode 10 is set to 3.5 times or less of the wire diameter D of the aluminum wire 14.
[Selection] Figure 1

Description

  The present invention relates to a nitride semiconductor device using a group III nitride semiconductor.

Conventionally, a power FET (Field Effect Transistor) using a silicon semiconductor is used for a power device mounted in a power amplifier circuit, a power supply circuit, a motor drive circuit, or the like.
As an example, the power FET includes a rectangular parallelepiped element chip, a metal support substrate that supports the element chip, and a plurality of leads (source leads and gate leads) that face the element chip and are long in the facing direction. And an aluminum wire for electrically connecting the element chip and the lead, and a resin package for sealing them.

  On one surface of the element chip, a source pad electrically connected to the source electrode in the chip and a gate pad electrically connected to the gate electrode in the chip are arranged side by side. One end of an aluminum wire is bonded to each of the source pad and the gate pad. On the other hand, a drain electrode is formed on the entire surface of the element chip opposite to the one surface. The element chip is supported on the support substrate in a posture with one surface facing upward. The drain electrode is electrically connected to the support substrate by contact with the support substrate.

The support substrate has a substantially rectangular shape in plan view, and one side in the longitudinal direction thereof is disposed in the resin package to support the element chip. On the other hand, the other side in the longitudinal direction of the support substrate is disposed outside the resin package and serves as an external terminal (drain terminal) of the power FET.
One side of the lead in the longitudinal direction is disposed in the resin package and is joined to the other end of the aluminum wire. On the other hand, the other side in the longitudinal direction of the lead is disposed outside the resin package and serves as an external terminal (source terminal and gate terminal) of the power FET.

However, in recent years, due to the theoretical limit of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of power FETs using silicon semiconductors are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of a power device using a nitride semiconductor having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and low on-resistance has been studied.
JP 2000-49184 A

Since the physical properties of nitride semiconductors are superior to silicon semiconductors, the performance required for power FETs can be sufficiently ensured even if the area of the element chip (area of the active region) is small. On the other hand, a nitride semiconductor wafer for producing a nitride semiconductor element chip is very expensive compared to a silicon wafer.
Therefore, when introducing a nitride semiconductor element chip, the area per element chip is reduced within a range in which the performance as a power FET can be maintained, so that individual element chips from one wafer can be obtained. It is preferable to increase the number of removals.

However, since the area of the source pad and the gate pad must be larger than the area necessary for bonding the aluminum wires, the reduction of the area of the element chip is limited by the area required for the source pad and the gate pad. .
Therefore, an unnecessary region that does not contribute to the transistor operation is formed in the element chip, and it is difficult to mass-produce the element chip with excellent cost efficiency.

  An object of the present invention is to provide a nitride semiconductor device including an element chip that is advantageous in reducing the area of the element chip and can be mass-produced with excellent cost efficiency.

  In order to achieve the above object, an invention according to claim 1 includes an element chip having a laminated structure of a group III nitride semiconductor layer, a source pad and a gate pad formed on one surface of the element chip, and the element chip. A drain electrode formed on the other surface opposite to the one surface, a submount joined to the gate pad and the source pad and electrically connected to the gate pad and the source pad, and the drain electrode The drain electrode has a width in the first direction that is not more than twice the wire diameter of the aluminum wire, and a width in the second direction orthogonal to the first direction is equal to the wire diameter. The nitride semiconductor device is 3.5 times or less.

According to this nitride semiconductor device, the submount is bonded to the source pad and the gate pad on one surface of the element chip. On the other hand, an aluminum wire is bonded to the drain electrode on the other surface of the element chip. Further, the width of the drain electrode in the first direction and the second direction is not more than twice and not more than 3.5 times the wire diameter of the aluminum wire, respectively.
Since the source pad and gate pad on the element chip are bonded to the submount, the number of aluminum wires bonded to the element chip can be reduced to one. Further, since the area of the element chip can be determined according to the size (width) of the drain electrode, the area of the element chip can be reduced, and unnecessary regions that do not contribute to transistor operation can be reduced.

The drain electrode has a region necessary for bonding the aluminum wire, and the width in the first direction and the second direction is, for example, a width greater than the wire diameter of the aluminum wire, and preferably in the first direction. Is about 1.5 to 2 times the wire diameter of the aluminum wire, and the width about the second direction is about 3 to 3.5 times the wire diameter of the aluminum wire.
As a result, the number of element chips taken from one wafer can be increased, so that the element chips can be mass-produced with excellent cost efficiency.

  The drain electrode is formed in a rectangular shape in plan view covering the entire other surface when the element chip has a rectangular parallelepiped shape, for example, and the one surface and the other surface are formed in a rectangular shape in plan view. May be. In this case, the length of one side of two adjacent sides of the drain electrode is not more than twice the wire diameter of the aluminum wire, and the length of the other side of the two sides is the wire diameter of the aluminum wire. It may be 3.5 times or less.

  According to a second aspect of the present invention, there is provided an element chip having a laminated structure of a group III nitride semiconductor layer, a source pad and a gate pad formed on one surface of the element chip, and the one surface of the element chip. A drain electrode formed on the other surface opposite to the substrate, a submount bonded to the gate pad and the source pad and electrically connected to the gate pad and the source pad, and an aluminum bonded to the drain electrode The nitride semiconductor device includes a wire, and the area of the other surface of the element chip is not more than 7 times the bonding surface with the aluminum wire.

According to this nitride semiconductor device, the submount is bonded to the source pad and the gate pad on one surface of the element chip. On the other hand, an aluminum wire is bonded to the drain electrode on the other surface of the element chip.
Since the source pad and gate pad on the element chip are bonded to the submount, the number of aluminum wires bonded to the element chip can be reduced to one. Furthermore, the area of the other surface of the element chip (surface on which the drain electrode is formed) is 7 times or less than the bonding surface of the aluminum wire to the drain electrode. Since the upper limit of the area of the other surface of the element chip is 7 times or less than the above bonding surface, the transistor operation can be achieved by designing (reducing) the area of the element chip within a range that can maintain the performance as a power FET. It is possible to reduce unnecessary areas that do not contribute to.

As a result, the number of element chips taken from one wafer can be increased, so that the element chips can be mass-produced with excellent cost efficiency.
According to a third aspect of the present invention, in the submount, a first wiring pattern bonded to the source pad and a second wiring pattern bonded to the gate pad are formed in an insulated state. The nitride semiconductor device according to claim 1 or 2.

In this nitride semiconductor device, since the first wiring pattern and the second wiring pattern are formed in an insulating state on the submount, by bonding an aluminum wire to each of them, The connection between the aluminum wire and the source pad and the connection between the aluminum wire and the gate pad can be achieved in a state where they are insulated from each other.
According to a fourth aspect of the present invention, there is provided an n-type first layer, a second layer containing a p-type impurity, and an n-type, wherein the laminated structure is laminated in order from the other surface side to the one surface side of the element chip. A gate insulating layer formed on the wall surface and straddling the first, second, and third layers, and a wall surface straddling the first, second, and third layers. A gate electrode opposed to the second layer across the gate insulating film, and a source electrode formed on the third layer, the gate electrode and the source electrode being the gate pad and the gate electrode The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is electrically connected to a source pad.

  In this nitride semiconductor device, the element chip has an npn structure composed of first, second and third layers, and a gate insulating film is formed on a wall surface extending over the npn structure. A gate electrode facing the second layer is formed on the gate insulating film with the gate insulating film interposed therebetween. Thereby, a MOS (Metal Oxide Semiconductor) structure is formed in the element chip. That is, the element chip may be an element chip having a vertical MOS structure as described in claim 4.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic perspective view of a nitride semiconductor device according to an embodiment of the present invention. 2 is a cross-sectional view taken along the cutting line II-II in FIG.
The nitride semiconductor device 1 includes a rectangular parallelepiped resin package 2. The resin package 2 is made of a thermosetting resin such as an epoxy resin or polyimide, for example.

The resin package 2 includes a die pad 3, a submount 4 supported by the die pad 3, and an element chip 5 supported by the submount 4.
The die pad 3 is made of, for example, a thin metal plate having a rectangular shape in plan view.
The submount 4 is a member that relays a part of the electric signal from the element chip 5 to an external terminal outside the resin package 2, and has a heat expansion coefficient of, for example, 90 to 110% of the thermal expansion coefficient of the group III nitride semiconductor. A substrate having an expansion coefficient is provided. As such a substrate, for example, an insulating substrate such as an aluminum nitride (AlN) substrate or a sapphire substrate can be used. Further, the submount 4 is cut into a rectangular shape in plan view having a size smaller than that of the die pad 3. A source wiring pad 6 and a gate wiring pad 7 are formed on one surface 41 of the submount 4.

The source wiring pad 6 and the gate wiring pad 7 can be configured using aluminum, for example.
The source wiring pad 6 is formed in a rectangular shape in plan view having a pair of opposing sides having the same length as the short side of the submount 4.
Similarly to the source wiring pad 6, the gate wiring pad 7 is formed in a rectangular shape in plan view having a pair of opposing sides having the same length as the short side of the submount 4, and is slightly smaller than the source wiring pad 6. It is formed in size.

  The source wiring pad 6 and the gate wiring pad 7 are arranged so that one side of the pair of sides overlaps the short side of the submount 4. Further, the source wiring pad 6 and the gate wiring pad 7 are insulated and separated from each other by providing an appropriate interval therebetween. The source wiring pad 6 and the gate wiring pad 7 can be formed by a known technique such as sputtering.

Then, the submount 4 has a posture in which the other surface 42 facing the one surface 41 (pad forming surface) and the surface of the die pad 3 are opposed to each other, for example, silver so that the long side thereof is along the long side of the die pad 3. Bonded to the die pad 3 by a bonding material such as paste.
The element chip 5 is a semiconductor chip having a vertical MOS structure using a group III nitride semiconductor, and is formed in a rectangular parallelepiped shape smaller than the submount 4. A source pad 8, a gate pad 9, and a drain electrode 10 are respectively formed on one surface 51 and the other surface 52 of the element chip 5 that are rectangular in plan view and facing each other. The source pad 8 and the gate pad 9 are formed separately from each other.

The drain electrode 10 is formed so as to cover the entire other surface 52 of the element chip 5 and is formed in a rectangular shape in plan view.
In the element chip 5, the one surface 51 and one surface 41 of the submount 4 are opposed to each other, and the long side thereof is orthogonal to the short side of the submount 4 (specifically, the source pad 8 and the source wiring pad). 6, and the gate pad 9 and the gate wiring pad 7 are opposed to each other). Due to the joining form of the element chip 5 and the submount 4, the submount 4 having a size larger than the element chip 5 protrudes from the element chip 5 in a plan view. The source wiring pad 6, the drain electrode 10, and the gate wiring pad 7 are arranged side by side toward the other side.

  The nitride semiconductor device 1 includes three leads 11. The leads 11 are made of, for example, a rectangular thin metal plate in plan view, and are arranged at equal intervals along the long side of the submount 4 so that one short side faces the long side of the submount 4. ing. The lead 11 is classified into a source lead 11S facing the source wiring pad 6, a drain lead 11D facing the drain electrode 10, and a gate lead 11G facing the gate wiring pad 7 according to the arrangement position.

Each lead 11 extends over the inside and outside of the resin package 2, a flat plate-like inner lead 12 disposed in the resin package 2, and a crank that is disposed outside the resin package 2 and is bent in two stages in the middle. The outer lead 13 having a shape is integrally provided.
The lead 11 and the submount 4 are connected by two aluminum wires 14, and the lead 11 and the element chip 5 are connected by one aluminum wire 14. Specifically, the source lead 11S and the gate lead 11G are connected to the source wiring pad 6 and the gate wiring pad 7 of the submount 4 via the aluminum wires 14, respectively, and the drain lead 11D is connected to the drain electrode 10 of the element chip 5. Are connected to each other via an aluminum wire 14.

  Thereby, the source pad 8 and the gate pad 9 of the element chip 5 and the source lead 11S and the gate lead 11G are conducted through the source wiring pad 6 and the gate wiring pad 7 formed in the submount 4, respectively. It will be. On the other hand, the drain electrode 10 of the element chip 5 and the drain lead 11 </ b> D are directly connected via the aluminum wire 14.

  The aluminum wire 14 is a flexible wire and has, for example, a wire diameter D of 100 to 150 μm (as a specific example, 125 μm). The aluminum wires 14 are arched from the source wiring pad 6, drain electrode 10 and gate wiring pad 7 on the element chip 5 side (submount 4 side) to the source lead 11S, drain lead 11D and gate lead 11G on the lead side, respectively. It is stretched and joined to each joining object (each lead 11, each wiring pad 6, 7 and drain electrode 10) by, for example, ultrasonic joining. A joining portion 15 of the aluminum wire 14 joined by ultrasonic joining is formed in a bell shape in a sectional view with a diameter extending from a cylindrical body portion 16.

  In the element chip 5 to which one aluminum wire 14 is bonded, the drain electrode 10 having a rectangular shape in plan view, which is an object to be bonded, has a length L (related to the second direction) of 3.5 times or less of the wire diameter D. Width) and a width W (width in the first direction) that is not more than twice the wire diameter D. The specific range of the length L and the width W of the drain electrode 10 is as follows. For example, when the wire diameter D is 125 μm, the length L is 375 to 437.5 μm and the width W is 187.5 to 250 μm. is there.

In addition, the area S of the other surface 52 where the drain electrode 10 is formed in the element chip 5 is 7 times or less with respect to the bonding surface between the drain electrode 10 and the aluminum wire 14. , Approximately 70,000 to 110,000 μm ² .
FIG. 3 is a schematic plan view of the element chip. FIG. 4 is a schematic bottom view of the element chip. FIG. 5 is a cross-sectional view taken along the cutting line indicated by VV in FIG. 3 to 5, parts corresponding to those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1.

The element chip 5 having a vertical MOS structure includes a GaN substrate 21 and a laminated structure portion 22 made of a group III nitride semiconductor formed on the GaN substrate 21.
The stacked structure unit 22 includes an n-type GaN layer 23, a p-type GaN layer 24 containing a p-type impurity, and an n-type GaN layer 25, and the GaN layers are stacked in this order. More specifically, each GaN layer is formed on the GaN substrate 21 by, for example, a MOCVD (Metal Organic Chemical Vapor Deposition) method, an LPE (Liquid Phase Epitaxy) method, or a VPE (VPE) method. It is formed by epitaxially growing a group III nitride semiconductor by a method such as Vapor Phase Epitaxy (vapor phase epitaxy) or MBE (Molecular Beam Epitaxy).

  Near the middle in the width direction of the multilayer structure portion 22, a trench 26 is formed having a depth that extends from the n-type GaN layer 25 through the p-type GaN layer 24 and in the middle of the n-type GaN layer 23 in the layer thickness direction. By forming the trench 26, the stacked structure portion 22 is formed in a substantially trapezoidal shape in sectional view extending in the width direction of the element chip 5. The side surface of the laminated structure portion 22 (trapezoid) forms a wall surface 27 straddling the n-type GaN layer 23, the p-type GaN layer 24, and the n-type GaN layer 25.

A plurality of trapezoidal stacked structure portions 22 are formed in the length direction of the element chip 5 with a predetermined interval (interval of the trenches 26), and each stacked structure portion 22 constitutes a unit cell. A trench 26 between adjacent stacked structure portions 22 is a boundary of each unit cell.
The wall surface 27 is a surface inclined with respect to the main surface of the GaN substrate 21. For example, when the main surface of the GaN substrate 21 is the c-plane (0001), the n-type GaN layer 23, the p-type GaN layer 24, and the n-type GaN layer 25 grown on the GaN substrate 21 by epitaxial growth are The c-plane (0001) is laminated as the main surface. Therefore, the wall surface 27 that is a surface inclined with respect to the main surface (c-plane) is, for example, non-m-plane (10-10) or a-plane (11-20) when inclined at 90 °. Polar surface. Further, in the vicinity of the wall surface 27 in the p-type GaN layer 24, an inversion layer (channel) that electrically conducts between the n-type GaN layers 23 and 25 by applying an appropriate bias voltage to a gate electrode 30 (described later). Is formed.

On the n-type GaN layer 25, a source electrode 28 is formed in contact with the n-type GaN layer 25. The source electrode 28 is electrically connected (ohmic connection) with the n-type GaN layer 25.
On the other hand, the back surface of the GaN substrate 21 opposite to the formation surface of the stacked structure portion 22 forms the other surface 52 of the element chip 5, and the entire surface is formed on the back surface (other surface 52) of the GaN substrate 21. A covering drain electrode 10 is formed. The drain electrode 10 is electrically connected (ohmic connection) with the n-type GaN layer 23 via the GaN substrate 21. Note that the drain electrode 10 is shared among the plurality of stacked structure portions 22.

  The source electrode 28 is preferably configured using a metal containing at least aluminum (Al), and can be configured using, for example, a titanium-aluminum alloy (Ti-Al alloy). Similarly to the source electrode 28, the drain electrode 10 is also preferably made of a metal containing aluminum (Al), and can be made of, for example, a titanium-aluminum alloy (Ti-Al alloy).

  In addition, as long as the drain electrode 10 and the source electrode 28 are materials that can form an ohmic junction with the GaN substrate 21 and the n-type GaN layer 25, molybdenum (Mo) or a molybdenum compound (for example, molybdenum silicide), titanium (Ti) or You may comprise using a titanium compound (for example, titanium silicide) or tungsten (W) or a tungsten compound (for example, tungsten silicide).

Further, a gate insulating film 29 is formed on the surface of the laminated structure portion 22. The gate insulating film 29 is formed across the n-type GaN layer 23, the p-type GaN layer 24, and the n-type GaN layer 25 on the wall surface 27.
The gate insulating film 29 can be configured using, for example, an oxide or a nitride. More specifically, silicon oxide (SiO ₂ ), gallium oxide (Ga ₂ O ₃ ), magnesium oxide (MgO), scandium oxide (Sc ₂ O ₃ ), silicon nitride (SiN), or the like may be used. it can.

A gate electrode 30 is formed on the gate insulating film 29. The gate electrode 30 faces the wall surface 27 with the gate insulating film 29 interposed therebetween.
The gate electrode 30 is made of, for example, platinum (Pt), aluminum (Al), nickel-gold alloy (Ni-Au alloy), nickel-titanium-gold alloy (Ni-Ti-Au alloy), palladium-gold alloy (Pd- An Au alloy), a palladium-titanium-gold alloy (Pd-Ti-Au alloy), a palladium-platinum-gold alloy (Pd-Pt-Au alloy), and a conductive material such as polysilicon can be used.

  On the gate insulating film 29, an interlayer insulating film 31 covering the source electrode 28 and the gate electrode 30 is laminated. The interlayer insulating film 31 can be configured using, for example, silicon nitride or silicon oxide. A gate contact hole 32 is formed in the interlayer insulating film 31 at a portion facing the gate electrode 30. A gate contact electrode 33 for contact with the gate electrode 30 is embedded in the gate contact hole 32.

The gate contact electrode 33 can be configured using, for example, the same material (for example, aluminum) as the gate pad 9.
A gate wiring 34 having a predetermined pattern is formed on the interlayer insulating film 31. The gate wiring 34 can be formed using the same material (for example, aluminum) as the gate pad 9. The gate wiring 34 is in contact with the gate contact electrode 33, whereby the gate wiring 34 is electrically connected (ohmic connection) to the gate electrode 30 through the gate contact electrode 33.

  On the interlayer insulating film 31, an interlayer insulating film 35 covering the gate wiring 34 is laminated. The interlayer insulating film 35 can be configured using, for example, silicon nitride or silicon oxide. In the interlayer insulating film 31 and the interlayer insulating film 35, a source contact hole 36 penetrating therethrough is formed in a portion facing the source electrode 28. A source contact electrode 37 for contact with the source electrode 28 is embedded in the source contact hole 36.

The source contact electrode 37 can be formed using the same material (for example, aluminum) as the source pad 8.
The surface of the interlayer insulating film 35 forms one surface 51 of the element chip 5, and the source pad 8 and the gate pad 9 are formed on the surface (one surface 51) of the interlayer insulating film 35. The source pad 8 is in contact with the source contact electrode 37, whereby the source pad 8 is electrically connected (ohmic connection) with the source electrode 28 via the source contact electrode 37.

On the other hand, the gate pad 9 is routed on the interlayer insulating film 31 at a position not shown, and comes into contact with the gate wiring 34 penetrating the interlayer insulating film 35, so that the gate pad 9 passes through the gate wiring 34. The gate electrode 30 is electrically connected (ohmic connection).
Next, a method for manufacturing the element chip 5 will be described.

In order to manufacture the element chip 5, first, the n-type GaN layer 23, the p-type GaN layer 24, and the n-type GaN layer 25 are sequentially grown on the wafer-like GaN substrate 21 by the epitaxial growth method described above. . Thus, the laminated structure portion 22 is formed on the GaN substrate 21.
As the n-type dopant for growing the n-type GaN layer 23 and the n-type GaN layer 25, for example, Si may be used. On the other hand, as a p-type dopant for growing the p-type GaN layer 24, for example, Mg or C may be used.

  After the formation of the multilayer structure 22, the multilayer structure 22 is etched in a stripe shape. That is, a trench 26 is formed by etching from the n-type GaN layer 25 through the p-type GaN layer 24 to the middle layer thickness of the n-type GaN layer 23. Thereby, a plurality of trapezoidal laminated structure portions 22 having a trapezoidal cross-sectional shape are shaped in a stripe shape on the GaN substrate 21, and a wall surface 27 is formed in each shaped laminated structure portion 22.

The trench 26 can be formed, for example, by dry etching (anisotropic etching) using a chlorine-based gas. In addition, after the dry etching, a wet etching process for improving the wall surface 27 of the laminated structure 22 damaged by the dry etching may be performed as necessary. Note that wet etching, KOH (potassium hydroxide), _NH 4 OH (ammonia water), it is preferable to use a basic solution such as TMAH (tetramethylammonium hydroxide).

Next, a gate insulating film 29 that covers the surface of the multilayer structure portion 22 is formed. The gate insulating film 29 is formed by a method such as an ECR (Electron Cyclotron Resonance) sputtering method or a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
Subsequently, the gate electrode 30 facing the wall surface 27 is formed on the gate insulating film 29 by a known photolithography technique and sputtering technique.

Next, an opening exposing the upper surface of the n-type GaN layer 25 is formed from the gate insulating film 29 by a known photolithography technique. Then, the source electrode 28 is formed on the n-type GaN layer 25 exposed from the gate insulating film 29 by sputtering.
Thereafter, the interlayer insulating film 31 is stacked on the stacked structure portion 22 by, for example, PECVD. Next, a gate contact hole 32 is formed in the interlayer insulating film 31 by a known photolithography technique and etching technique. Then, a material (electrode material) of the gate contact electrode 33 is deposited in the gate contact hole 32 and on the interlayer insulating film 31. Next, unnecessary portions of the electrode material existing outside the gate contact hole 32 are removed by CMP polishing.

Next, a gate wiring 34 having a predetermined pattern is formed on the interlayer insulating film 31 by a known photolithography technique and sputtering technique.
After the formation of the gate wiring 34, the interlayer insulating film 35 is laminated on the interlayer insulating film 31 by, for example, PECVD. Next, a contact hole (not shown) exposing the source contact hole 36 and the gate wiring 34 is simultaneously formed by a known photolithography technique and etching technique. Then, a material (electrode material) of the source contact electrode 37 is deposited in the contact holes and on the interlayer insulating film 35. Next, unnecessary portions of the electrode material outside the contact holes are removed by CMP polishing.

Then, the source pad 8 and the gate pad 9 are formed on the surface (one surface 51) of the interlayer insulating film 35 by a known photolithography technique and etching technique.
Thereafter, the drain electrode 10 is formed on the back surface (the other surface 52) of the GaN substrate 21 by sputtering. After the drain electrode 10 is formed, the wafer-like GaN substrate 21 is divided to obtain individual pieces of the element chip 5. Note that before the drain electrode 10 is formed, a step of polishing the GaN substrate 21 to reduce the thickness of the substrate may be performed.

In order to manufacture the nitride semiconductor device 1 (see FIGS. 1 and 2) in which the separated element chip 5 is built, first, the source pad 8 and the gate pad 9 of the element chip 5 are used in advance or newly. The element chip 5 and the submount 4 are joined in a state where the source wiring pad 6 and the gate wiring pad 7 of the submount 4 manufactured in the above are abutted.
Next, the submount 4 is bonded to a lead frame having the die pad 3 and the leads 11 integrally. Then, each wiring pad 6, 7 and the drain electrode 10 are connected to each lead 11 by an aluminum wire 14.

Thereafter, the structure on the lead frame is sealed with a sealing resin (for example, epoxy resin). After sealing with the sealing resin, the sealing resin is divided together with the lead frame, whereby the nitride semiconductor device 1 that is separated into pieces is obtained.
In order to operate the nitride semiconductor device 1, first, a bias is applied between the source lead 11S and the drain lead 11D so that the drain lead 11D side is positive. Thereby, a reverse voltage is applied to the pn junction at the interface between the n-type GaN layer 23 and the p-type GaN layer 24 in the element chip 5 via the drain electrode 10 and the source wiring pad 6 and the source pad 8. As a result, between the n-type GaN layer 25 and the n-type GaN layer 23, that is, between the source electrode 28 and the drain electrode 10 (between the source and drain) is in a cut-off state (reverse bias state).

From this state, when a bias equal to or higher than the gate threshold voltage, which is positive with the source lead 11S as a reference potential, is applied to the gate lead 11G, the p-type GaN layer 24 near the interface with the gate insulating film 29 Electrons are induced to form an inversion layer (channel).
The n-type GaN layer 23 and the n-type GaN layer 25 are electrically connected via the inversion layer. Thus, conduction between the source and the drain is established. In this way, the transistor operation of the nitride semiconductor device 1 is realized. As described above, in nitride semiconductor device 1 packaged with resin package 2, source pad 8 and gate pad 9 on one surface 51 of element chip 5 are the source wiring pads on one surface 41 of submount 4. 6 and the gate wiring pad 7, respectively.

  The element chip 5 and the external terminals (leads 11) of the nitride semiconductor device 1 are electrically connected to the drain electrode 10 and the drain lead 11D of the element chip 5, the source wiring pad 6 and the source lead 11S of the submount 4, In addition, this is achieved by joining the gate wiring pad 7 and the gate lead 11G of the submount 4 with aluminum wires 14, respectively.

  That is, in this nitride semiconductor device 1, only one aluminum wire 14 is bonded to the element chip 5, and the drain electrode 10 to which the aluminum wire 14 is bonded is 3. A length W of 5 times or less and a width W of 2 times or less of the wire diameter D (specifically, when the wire diameter D is 125 μm, the length L is 375 to 437.5 μm and the width W is 187 .5 to 250 μm).

Further, the area S of the other surface 52 of the element chip 5 on which the drain electrode 10 is formed is 7 times or less with respect to the bonding surface between the drain electrode 10 and the aluminum wire 14 (specific values are about 70000 to 110000 μm ² ).
The number of aluminum wires 14 bonded to the element chip 5 can be reduced to one, and the length L and the width W of the drain electrode 10 necessary for bonding the aluminum wires 14 are the above-mentioned sizes. . Further, the area S of the other surface 52 (surface on which the drain electrode 10 is formed) of the element chip 5 is 7 times or less than the bonding surface of the aluminum wire 14 to the drain electrode 10.

  Therefore, the area of the element chip 5 may be designed in a range in which the length L and the width W of the drain electrode 10 can be secured and in a range in which the performance as the power MOSFET can be maintained in the element chip 5. The area can be reduced. Thereby, an unnecessary region that does not contribute to transistor operation can be reduced. As a result, it is possible to increase the number of element chips 5 to be taken from one wafer, and it is possible to mass-produce element chips with excellent cost efficiency.

As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form.
For example, the drain electrode 10 does not need to have a rectangular shape in plan view, and may have a square shape in plan view, a circular shape, a rhombus shape, a parallelogram shape, or the like. For example, the laminated structure portion 22 is generally made of a group III nitride semiconductor other than GaN, such as aluminum nitride (AlN), indium nitride (InN), or the like, and generally Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1). , 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

  In addition, various design changes can be made within the scope of matters described in the claims.

1 is a schematic perspective view of a nitride semiconductor device according to an embodiment of the present invention. It is sectional drawing when cut | disconnecting by the cutting line shown by II-II of FIG. It is a schematic plan view of an element chip. It is a schematic bottom view of an element chip. It is sectional drawing when cut | disconnecting by the cutting line shown by VV of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nitride semiconductor device 4 Submount 5 Element chip 6 Source wiring pad (1st wiring pattern)
7 Gate wiring pad (second wiring pattern)
8 Source pad 9 Gate pad 10 Drain electrode 14 Aluminum wire 22 Multilayer structure 23 n-type GaN layer (first layer)
24 p-type GaN layer (second layer)
25 n-type GaN layer (third layer)
27 Wall surface 28 Source electrode 29 Gate insulating film 30 Gate electrode 51 One surface (one surface of the element chip)
52 Other surface (other surface of element chip)

Claims (4)

An element chip having a laminated structure of group III nitride semiconductor layers;
A source pad and a gate pad formed on one surface of the element chip;
A drain electrode formed on the other surface facing the one surface of the element chip;
A submount bonded to the gate pad and the source pad and electrically connected to the gate pad and the source pad;
An aluminum wire joined to the drain electrode,
The drain electrode has a width in the first direction not more than twice the wire diameter of the aluminum wire, and a width in the second direction orthogonal to the first direction is not more than 3.5 times the wire diameter. Semiconductor device. An element chip having a laminated structure of group III nitride semiconductor layers;
A source pad and a gate pad formed on one surface of the element chip;
A drain electrode formed on the other surface facing the one surface of the element chip;
A submount bonded to the gate pad and the source pad and electrically connected to the gate pad and the source pad;
An aluminum wire joined to the drain electrode,
The nitride semiconductor device, wherein an area of the other surface of the element chip is 7 times or less with respect to a bonding surface with the aluminum wire.   3. The nitriding according to claim 1, wherein a first wiring pattern bonded to the source pad and a second wiring pattern bonded to the gate pad are formed in the submount in an insulated state. Semiconductor device. The stacked structure includes an n-type first layer, a second layer containing a p-type impurity, an n-type third layer, and the first and first layers stacked in order from the other surface side to the one surface side of the element chip. Having wall surfaces straddling 2 and 3rd layers,
The element chip includes a gate insulating film formed on the wall surface across the first, second, and third layers, a gate electrode that faces the second layer across the gate insulating film, and the first A source electrode formed on three layers,
4. The nitride semiconductor device according to claim 1, wherein the gate electrode and the source electrode are electrically connected to the gate pad and the source pad, respectively.

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