JP2010027687A - Semiconductor integrated circuit device and its inspecting apparatus - Google Patents

Abstract

A semiconductor integrated circuit device capable of easily specifying a device failure portion of a semiconductor integrated circuit device and an inspection device therefor are realized.
A semiconductor integrated circuit device and an inspection device thereof according to the present invention include photoelectric conversion elements (Di1 to Di1) having a cathode connected to an internal signal line (node to be measured) of a circuit to be measured 11 and an anode connected to a fixed potential. 10), and the photoelectric conversion elements (Di1 to 10) are irradiated with laser light to generate a potential difference between the internal signal line and the fixed potential.
[Selection] Figure 1

Description

The present invention relates to a semiconductor integrated circuit device and an inspection device therefor, and more particularly to device failure location identification.

Conventionally, in order to identify a device failure location of a semiconductor integrated circuit device, first, a test program is executed by an evaluation system such as an LSI tester, and a signal is input to a control pin of a device under test connected to a test head. . In that case, various analysis test patterns are prepared and evaluated because signals cannot be directly input to each circuit in the device under test and analyzed individually.
These are executed on the analysis system (EB tester, EMS, etc.) to gradually narrow down the failure points (see, for example, “Patent Document 1”). In preparing these various test patterns for analysis, test patterns are created in cooperation with the person in charge of the device. Therefore, it takes time to prepare for analysis in order to identify the device failure location in the past. And there was a problem of spending money.

As another technology for identifying the device failure location, an analysis pad is created by FIB processing.
Although there is a method of performing waveform observation and the like analysis using a tester, there is a problem that it takes time and cost for FIB processing. In some cases, an observation pad is prepared for each circuit in the device in advance. However, there is a problem that the chip area is greatly increased and the manufacturing cost is increased.
JP 2004-301526 A

The present invention provides a semiconductor integrated circuit device that can easily identify a device failure location of a semiconductor integrated circuit device, and an inspection device therefor.

According to an aspect of the present invention, the internal signal line includes a photoelectric conversion element having a cathode connected to an internal signal line and an anode connected to a fixed potential, and the photoelectric conversion element is irradiated with a laser beam to thereby generate the internal signal line. A semiconductor integrated circuit device is provided in which a potential difference is generated between the semiconductor integrated circuit device and the fixed potential.

According to another aspect of the present invention, there is provided an apparatus for inspecting a semiconductor integrated circuit device having a photoelectric conversion element connected to a measured node, based on a first control signal from a laser pulse control means. Laser generating means for generating laser light, and laser scanning for controlling to irradiate the position of the photoelectric conversion element with the laser light from the laser generating means based on the second control signal from the laser pulse control means An inspection apparatus for a semiconductor integrated circuit device is provided.

According to the present invention, an arbitrary test signal can be directly input to each circuit in the semiconductor integrated circuit device, so that it is possible to greatly reduce the analysis time for identifying a device failure location, shorten the chip development period, and the manufacturing cost. Can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention.
Here, as an example, a portion related to signal input of the circuit under test 11 to be measured in failure analysis or the like is shown.

In the semiconductor integrated circuit device according to the first embodiment of the present invention, pads 1 to 6 (hereinafter referred to as “Pad 1 to 6”) to which signals from the outside are input, optional function switching (so-called bonding option), and a wafer are provided. Reduction pad 7 (hereinafter referred to as “OP7”) used for test signal input in the state, two inverters 1 and 2 (hereinafter referred to as “Inv1 and 2”)
That's it. ), Six 2-input AND circuits 1 to 6 (hereinafter referred to as “And 1 to 6”), three 2-input OR circuits 1 to 3 (hereinafter referred to as “Or 1 to 3”), and 10 photoelectric conversions Elements 1 to 10 (light emitting diodes, hereinafter referred to as “Di1 to 10”) are provided.

The first input of And1 is connected to Pad1, the first input of And2 is connected to Pad2, the first input of And3 is connected to Pad3, the first input of And4 is connected to Pad4, and the input of And5 The first input is connected to Pad5, and the first input of And6 is Pad
6 is connected.

The anode of Di1 is connected to the ground potential (hereinafter referred to as “GND”), the cathode of Di1 is connected to the output of And1, the anode of Di2 is connected to GND, the cathode of Di2 is connected to the output of And2, The anode of Di3 is connected to GND, the cathode of Di3 is connected to the output of And3, the anode of Di4 is connected to GND, the cathode of Di4 is connected to the output of And4, the anode of Di5 is connected to GND, and Di5 Are connected to the output of And5, the anode of Di6 is connected to GND, and the cathode of Di6 is connected to the output of And6.

The first input of Or1 is connected to the output of And1, the second input of Or1 is connected to the output of And2, the first input of Or2 is connected to the output of And3, and the second input of Or2 is And4. The first input of Or3 is connected to the output of And5, and the second input of Or3 is connected to the output of And6.

The anode of Di7 is connected to GND, the cathode of Di7 is connected to the output of Or1,
The anode of Di8 is connected to GND, the cathode of Di8 is connected to the output of Or2, and D
The anode of i9 is connected to GND, the cathode of Di9 is connected to the output of Or3, and Di
The anode of 10 is connected to GND, and the cathode of Di10 is connected to OP7.

The input of Inv1 is connected to OP7, and the output of Inv1 is And1, And3, and A
connected to the second input of nd5, the input of Inv2 is connected to the output of Inv1, and Inv2
Are connected to the second inputs of And2, And4, and And6.

Di1-10 generate an electromotive force when irradiated with laser light, and generate a voltage between GND and an internal signal line to which the cathode is connected.

FIG. 2 is an image diagram showing the configuration of the inspection apparatus for a semiconductor integrated circuit device according to the first embodiment of the present invention. Here, as an example, the laser generator 2 in the case of performing failure analysis while irradiating the semiconductor integrated circuit device having the above-described photoelectric conversion elements (Di1 to 10) with laser light.
1 and the part related to its control are shown.

The inspection apparatus for a semiconductor integrated circuit device according to the first embodiment of the present invention includes a laser generator 21 having a laser generator 22 and a laser scanner 23, a laser pulse controller 25 for generating a control signal 24 of the laser generator 21, A control PC 26 for controlling the laser pulse control device 25, a test board 28 to which an analysis device 27 to be measured is attached, a test head 29 for transmitting / receiving signals to / from the analysis device 27 via the test board 28, and a test pattern for failure analysis L is generated and supplied to the test head 29 as an input signal 31
An SI tester 32 is provided.

The laser generator 22 generates laser light based on the first control signal 24 from the laser pulse control device 25, and the laser scanner 23 converts this laser light into the second control signal 24 from the laser pulse control device 25. Based on this, the desired position of the analysis device 27, specifically the positions Di1 to 10 shown in FIG. As a result, the test signal can be directly input to the internal signal line (measured node) of the circuit under test 11.

The LSI tester 32 is provided with a photoelectric conversion element (D
A test pattern 30 created on the assumption that a desired voltage is generated in i1 to 10) is supplied to the test head 29 as an input signal 31. Then, the output signal from the analysis device 27 corresponding to the input signal 31 is analyzed, and failure analysis such as identification of the failure location is performed.

As a specific failure location identification method, first, an analysis device 27 is prepared in which photoelectric conversion elements (Di1 to 10) are added in advance to the internal signal lines of the circuit under test 11 when designing a semiconductor device. Then, after the semiconductor integrated circuit device is manufactured, the test pattern 30 is executed by a normal LSI tester 32, and a rough failure location is specified using an analysis device such as EMS. Focusing on the circuit related around the rough failure detected here, the failure location is examined and narrowed down based on CAD navigation or the like.

Next, a control signal 24 is input from the laser pulse controller 25 to the laser generator 22 and the laser scanner 23 so as to generate a desired laser pulse, and laser light is irradiated to Di 1 to 10 of the analysis device 27.

Utilizing the electromotive force generated in Di1 to 10 by being irradiated with the laser light, level pulse input (test signal) is performed to the internal signal line to which they are connected. Then, the failure location is identified by checking the signal waveform output from the output pad of the analysis device 27 corresponding to these level and pulse inputs. It is also possible to specify the failure location by proceeding while checking the presence or absence of failure for each circuit under test 11 using an EB tester.

According to the first embodiment, an arbitrary test signal can be directly input to the circuit under test 11 in the semiconductor integrated circuit device, so that the analysis time for specifying a device failure location can be greatly shortened. For this reason, it is possible to shorten the development period and the manufacturing cost of the semiconductor integrated circuit device.

FIG. 3 is an image diagram showing a configuration of an inspection apparatus for a semiconductor integrated circuit device according to the second embodiment of the present invention. Here, as an example, a portion related to laser light control when the failure analysis of the semiconductor integrated circuit device shown in the first embodiment is performed in a wafer state is shown. Since the configuration of the circuit under test 11 to be measured is the same as that in FIG. 1 of the first embodiment, the description is omitted and the same reference numerals are used.

The semiconductor integrated circuit device inspection apparatus according to the second embodiment of the present invention includes a tester having a tester head 42 to which a laser generator 41 is attached, a laser irradiation position control mechanism 43, a laser irradiation unit 44, and a laser irradiation unit 44. A probe card 46 having an opening 45 through which the laser beam passes, a prober having a wafer stage 48 for fixing the wafer 47, a control having a laser controller 49, a main body controller 50, and a laser use signal information input device 51. Device.

The first output of the laser control device 49 is supplied to the laser generator 41 as the first control signal 52, and the second output of the laser control device 49 is supplied to the first input of the main body control controller 50 to control the main body. The output of the laser use signal information input device 51 is input to the second input of the controller 50, and the output of the main body controller 50 is supplied to the laser irradiation position control mechanism 43 as the second control signal 53.

The laser generator 41 generates laser light based on the first control signal 52 from the laser controller 49, and the laser irradiation position control mechanism 43 converts this laser light into the second control signal 53 from the main body controller 50. Based on the wafer 47 via the laser irradiation unit 44
Irradiation is performed on the desired position above, specifically, the positions of Di1 to 10 shown in FIG. This
A test signal can be directly input to the internal signal line (measured node) of the circuit under test 11.

When an actual wafer test is performed, a first signal that generates a fixed-level or low-frequency pulse signal at the measured node (usually an operation test using a high-speed signal is not practical in the wafer test). The control signal 52 is supplied from the laser control device 49 and the laser generator 41 generates laser light.

Then, the position information of the corresponding measured node is inputted in advance from the laser use signal information input device 51, and the second control signal 53 is supplied from the main body controller 50 in synchronization with the first control signal 52. The irradiation position is determined by the laser irradiation position control mechanism 43, and laser light is irradiated from the laser irradiation unit 44 to Di 1 to 10 on the wafer 47 through the opening 45 of the probe card 46.

Using the electromotive force generated in Di1 to 10 by the irradiated laser light, a fixed level voltage or low frequency pulse is input to the measured node, and the device is controlled and tested.

According to the second embodiment, the failure location in the wafer state can be identified and the failure analysis can be performed, so that feedback such as a circuit failure can be performed at an early stage of the development process, and the development period of the semiconductor integrated circuit device can be further shortened. be able to.

Also, according to the second embodiment, the pad area can be further reduced by providing the photoelectric conversion element (Di10) on the test reduction pad (for example, OP7 in FIG. 1) used only in the wafer test. Therefore, the chip size can be reduced, and the manufacturing cost can be further reduced.

1 is a circuit block diagram showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention. 1 is an image diagram showing a configuration of an inspection apparatus for a semiconductor integrated circuit device according to Embodiment 1 of the present invention; FIG. 6 is an image diagram showing a configuration of an inspection apparatus for a semiconductor integrated circuit device according to a second embodiment of the present invention.

Explanation of symbols

11 Circuit to be Measured 21 Laser Generator 22 Laser Generator 23 Laser Scanner 24 Control Signal 25 Laser Pulse Controller 26 Control PC
27 Analysis Device 28 Test Board 29 Test Head 30 Test Pattern 31 Input Signal 32 LSI Tester

Claims (4)

A photoelectric conversion element having a cathode connected to an internal signal line and an anode connected to a fixed potential, and a potential difference between the internal signal line and the fixed potential by irradiating the photoelectric conversion element with laser light. A semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the cathode of the photoelectric conversion element is connected to an input signal line from an input pad. An apparatus for inspecting a semiconductor integrated circuit device in which a photoelectric conversion element is connected to a measured node,
Laser generating means for generating laser light based on a first control signal from the laser pulse control means;
A semiconductor integrated circuit comprising laser scanning means for controlling the laser light from the laser generating means to irradiate the position of the photoelectric conversion element based on a second control signal from the laser pulse control means. Equipment inspection device. 4. The semiconductor integrated circuit device inspection apparatus according to claim 3, wherein the semiconductor integrated circuit device is inspected in a wafer state.

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