JP2010021393A - Integrated circuit design method and integrated circuit design apparatus - Google Patents

Abstract

An integrated circuit design method and an integrated circuit design apparatus capable of reliably reducing the influence of a plurality of wirings around a predetermined macroblock while suppressing an increase in processing load.
An integrated circuit design method includes: a wiring grid change area setting step for setting a given area as a wiring grid change area; and the inside of the area set as the wiring grid change area in the wiring grid change area setting step A wiring grid changing step for changing the wiring grid interval more greatly, and in the region, a given wiring is arranged on the wiring grid whose spacing is changed in the wiring grid changing step, and the wiring grid changing step And a placement and routing step of placing cells whose configuration is designated at a cell grid interval corresponding to the interval of the wiring grid changed in step, on the wiring grid whose interval has been changed in the wiring grid changing step.
[Selection] Figure 1

Description

  The present invention relates to an integrated circuit design method and an integrated circuit design apparatus.

  In recent years, the market demand for higher functionality and higher performance of semiconductor integrated circuits (in a broad sense, integrated circuits) is high. For this reason, while higher integration of semiconductor integrated circuits has progressed rapidly due to the multilayered wiring and advances in manufacturing process technology, semiconductor integrated circuits have increased due to the mounting of special macroblocks such as analog circuits and a significant increase in circuit scale. The arrangement of cells and wiring is becoming more difficult. Accordingly, the design period of the semiconductor integrated circuit is lengthened, and shortening of the design period is one of the major issues.

  In order to provide such a semiconductor integrated circuit to users in a short period of time, a design method for a semiconductor integrated circuit including a gate array, an embedded array, and a standard cell has been prepared. For example, in a semiconductor integrated circuit composed of standard cells, the functions required by the user are optimally designed internal logic cells, ROM (Read Only Memory), RAM (Random Access Memory), CPU (Central Processing Unit) and analog. A macro block such as a circuit is connected by wiring to form one chip. At that time, after determining the placement position of the macroblock as a floor plan, the automatic placement and routing tool places the cell terminals on the wiring grid defined in the layout possible area on the chip, and performs wiring according to the netlist. Be placed.

  However, even when the automatic placement and routing tool is used, digital signal wiring and analog signal wiring may run in parallel or cross each other around the analog macroblock. The impact on analog signals may be significant. For example, even if the periphery of an analog macroblock is set as a cell placement and routing prohibition area so that cells and wiring are not placed, if there is not enough wiring area, this cell placement and routing prohibition area is also Wiring is placed. In this case, since the wiring grid interval is the same, the digital signal wiring and the analog signal wiring may be arranged adjacent to each other.

  For example, Patent Document 1 discloses a technique for regenerating a wiring grid based on a wiring pitch corresponding to a margin of the number of wiring grids based on a result of a schematic wiring in order to prevent crosstalk due to coupling capacitance. Has been.

JP 2004-133638 A

  By the way, in the automatic placement and routing tool, wiring is arranged on a wiring grid defined in a lattice shape, and cells are arranged so that terminals are arranged on lattice points of the wiring grid. However, in Patent Document 1, based on the wiring pitch according to the margin of the number of wiring grids, the wiring grid is simply regenerated, and the types of cells that can be placed on the regenerated wiring grid are limited. End up. Therefore, it is necessary to perform a special wiring process without using a wiring grid, and there is a problem that the processing load becomes heavy.

  As described above, even if the technique disclosed in Patent Document 1 is used, a wiring grid having an arbitrary wiring pitch cannot be regenerated, and a wiring grid having a wiring pitch that can substantially place the original cell is used. It must be regenerated. Therefore, with the technique disclosed in Patent Document 1, the processing load due to special wiring processing becomes heavy or the effect of high integration of the integrated circuit cannot be obtained sufficiently.

  The present invention has been made in view of the above technical problems, and one of its purposes is to reliably reduce the influence of a plurality of wirings around a predetermined macroblock while suppressing an increase in processing load. Another object is to provide an integrated circuit design method and an integrated circuit design apparatus.

  To solve the above problems, the present invention provides a wiring grid change area setting step for setting a given area as a wiring grid change area, and the area set as the wiring grid change area in the wiring grid change area setting step. A wiring grid changing step for changing the interval between the wiring grids in the area to a greater extent, and in the region, a given wiring is arranged on the wiring grid whose spacing has been changed in the wiring grid changing step, and the wiring grid changing A placement and routing step of placing cells whose configuration is designated at a cell grid interval corresponding to the interval of the wiring grid changed in the step, in the wiring grid in which the interval is changed in the wiring grid changing step Related to circuit design method.

  According to the present invention, the wiring grid interval is locally increased, and the cells defined by the cell grid corresponding to the enlarged wiring grid are arranged, so that the processing load can be reduced without performing special wiring processing. For example, the influence of crosstalk between a signal wiring for transmitting an analog signal and a signal wiring for transmitting a digital signal can be reduced in the vicinity of a predetermined macroblock while suppressing an increase in the number of signals.

  Further, in the integrated circuit design method according to the present invention, the wiring grid changing step includes a wiring grid extending in at least one of first and second directions intersecting each other in an area set as the wiring grid changing area. The interval can be changed.

  According to the present invention, in addition to the above effect, by changing the interval of the wiring grid extending in at least one direction, an increase in processing load can be suppressed even in a region where the influence between the wirings is caused by crosstalk. However, the influence of a plurality of wirings can be reliably reduced around a predetermined macroblock.

  In the integrated circuit design method according to the present invention, the wiring grid changing step can greatly change the interval between the wiring grids so that the wiring grid is set outside the region.

  According to the present invention, in addition to the above-described effects, it is possible to reliably prevent cells and wirings from being arranged on the wiring grid changed outside the area within the wiring grid change area.

  According to the present invention, a wiring grid changing area setting step for setting a given area as a wiring grid changing area, and a wiring grid in the area set as the wiring grid changing area in the wiring grid changing area setting step are eliminated. Integrated circuit design including a wiring grid changing step to be performed, and a placement and wiring step for arranging cells and wirings in the wiring grid after processing in the wiring grid changing step, excluding the region set as the wiring grid changing region Related to the method.

  According to the present invention, even when the influence of crosstalk has been exerted between the wirings so far, since the wiring grid has disappeared in the wiring grid change area, no cells or wirings are arranged, and the wiring in this area is not arranged. It is possible to reliably reduce the influence of the crosstalk.

  Further, in the integrated circuit design method according to the present invention, the wiring grid changing step includes a wiring grid extending in at least one of first and second directions intersecting each other in an area set as the wiring grid changing area. Can be extinguished.

  According to the present invention, in addition to the above-described effects, by eliminating the wiring grid extending in at least one direction, even in a region where the influence between the wirings is caused by crosstalk, while suppressing an increase in processing load, The influence of a plurality of wirings can be reliably reduced around a predetermined macroblock.

  In the integrated circuit design method according to the present invention, the first direction is an active region continuous arrangement direction in which the active regions of the first conductivity type of all the cells among the cells constituting the standard cell are arranged adjacent to each other. There may be.

  In the integrated circuit design method according to the present invention, the area set as the wiring grid change area may be a peripheral area of an analog macroblock.

  According to the present invention, even if a digital signal wiring is arranged in the wiring grid change area, for example, it is arranged away from the analog signal wiring input or output to the macroblock in advance, so that crosstalk to the wiring is performed. The influence by can be reduced.

  In the integrated circuit design method according to the present invention, the peripheral area of the analog macroblock may be an area provided outside the analog macroblock by a given length.

  According to the present invention, the wiring grid is extinguished in a region provided outside the analog macroblock by a given length, so that, for example, a digital signal wiring is input to or output from the analog macroblock. It is possible to reliably reduce the influence of crosstalk on the analog signal wiring.

  The present invention also relates to an integrated circuit design apparatus that arranges wiring and cells on a wiring grid, and stores information on a plurality of cells that respectively specify the configuration of a plurality of cells having the same function at different cell grid intervals. A cell information storage unit; a wiring grid change region setting unit for setting a given region as a wiring grid change region; and a wiring grid in the region set as the wiring grid change region by the wiring grid change region setting unit A wiring grid change processing unit that changes the interval more greatly, and a placement wiring processing unit that arranges a given wiring and cell in the wiring grid in which the spacing is changed by the wiring grid change processing unit within the region; And the placement and routing processing unit changes the wiring grid based on the cell information stored in the cell information storage unit. An integrated circuit design apparatus that arranges cells whose configuration is designated at a cell grid interval corresponding to the interval of the wiring grid changed by the processing unit on the wiring grid whose interval has been changed by the wiring grid change processing unit Related to.

  According to the present invention, the wiring grid interval is locally increased, and the cells defined by the cell grid corresponding to the enlarged wiring grid are arranged, so that the processing load can be reduced without performing special wiring processing. For example, the influence of crosstalk between a signal wiring for transmitting an analog signal and a signal wiring for transmitting a digital signal can be reduced in the vicinity of a predetermined macroblock while suppressing an increase in the number of signals.

  Moreover, in the integrated circuit design device according to the present invention, the wiring grid change processing unit has a wiring extending in at least one of the first and second directions intersecting each other in the region set as the wiring grid changing region. The grid interval can be changed.

  According to the present invention, in addition to the above effect, by changing the interval of the wiring grid extending in at least one direction, an increase in processing load can be suppressed even in a region where the influence between the wirings is caused by crosstalk. However, the influence of a plurality of wirings can be reliably reduced around a predetermined macroblock.

  Moreover, in the integrated circuit design device according to the present invention, the wiring grid change processing unit can greatly change the interval between the wiring grids so as to set the wiring grid outside the region.

  According to the present invention, in addition to the above-described effects, it is possible to reliably prevent cells and wirings from being arranged on the wiring grid changed outside the area within the wiring grid change area.

  The present invention also relates to an integrated circuit design apparatus for arranging wirings and cells on a wiring grid, the wiring grid changing area setting unit for setting a given area as a wiring grid changing area, and the wiring grid changing area setting unit The wiring grid change processing unit that eliminates the wiring grid in the region set as the wiring grid change region by the above, and the processing by the wiring grid change processing unit excluding the region set as the wiring grid change region The present invention relates to an integrated circuit design apparatus including a placement and routing processing unit that places cells and wirings on a later wiring grid.

  According to the present invention, even when the influence of crosstalk has been exerted between the wirings so far, since the wiring grid has disappeared in the wiring grid change area, no cells or wirings are arranged, and the wiring in this area is not arranged. It is possible to reliably reduce the influence of the crosstalk.

  Moreover, in the integrated circuit design device according to the present invention, the wiring grid change processing unit has a wiring extending in at least one of the first and second directions intersecting each other in the region set as the wiring grid changing region. The grid can be extinguished.

  According to the present invention, in addition to the above-described effects, by eliminating the wiring grid extending in at least one direction, even in a region where the influence between the wirings is caused by crosstalk, while suppressing an increase in processing load, The influence of a plurality of wirings can be reliably reduced around a predetermined macroblock.

  In the integrated circuit design apparatus according to the present invention, the first direction is an active region continuous arrangement direction in which the active regions of the first conductivity type of all the cells of the standard cells are arranged adjacent to each other. There may be.

  In the integrated circuit design device according to the present invention, the area set as the wiring grid change area may be a peripheral area of an analog macroblock.

  According to the present invention, even if a digital signal wiring is arranged in the wiring grid change area, for example, it is arranged away from the analog signal wiring input or output to the macroblock in advance, so that crosstalk to the wiring is performed. The influence by can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

  In the following embodiment, the integrated circuit in the embodiment according to the present invention will be described as being composed of standard cells and macroblocks, but the present invention is not limited to this, and a gate array or an embedded array It may be comprised.

[Embodiment 1]
1A and 1B schematically show an outline of processing of the integrated circuit design apparatus according to the first embodiment of the present invention. FIG. 1A schematically shows an outline of an integrated circuit layout using the integrated circuit design apparatus in the comparative example of the first embodiment. FIG. 1B schematically shows an outline of an integrated circuit layout using the integrated circuit design apparatus of the first embodiment. 1A and 1B, the same portions are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The integrated circuit design apparatus according to the first embodiment or the comparative example arranges cells and wirings on a grid-like wiring grid defined in a layout possible area according to a net list having connection information between cells and macroblocks. Perform the placement process. As a result, in FIGS. 1A and 1B, in the integrated circuit 100, the macro block 102, the logic circuit cells, and the wirings connecting them are arranged on the wiring grid.

  In FIG. 1A, the first layer wiring ML1, the second layer wiring ML2 above the first layer wiring ML1, the first layer wiring ML1, and the second layer wiring ML2 are arranged on the wiring grid GR provided in a grid pattern. A via cell VC for electrically connecting the two is disposed. A wiring grid interval GD1, which is an interval between adjacent wiring grids GR, is defined by a design rule depending on the manufacturing process. For example, the wiring grid interval GD1 is defined so as to be equal to or greater than the minimum pitch m1 between the edges of adjacent via cells VC. The first layer wiring ML1 is disposed on the wiring grid GR extending in the vertical direction, for example, and the second layer wiring ML2 is disposed on the wiring grid GR extending in the horizontal direction, for example, and the via cell VC is on the lattice point of the wiring grid. Placed in.

  In FIG. 1A, it has been described that the interval between the wiring grids extending in the horizontal direction is the same as the interval between the wiring grids extending in the vertical direction, but the interval between the wiring grids in both directions may be different.

  By the way, in the integrated circuit design apparatus in the comparative example of the first embodiment, as shown in FIG. 1A, the wiring grid interval GD1 between adjacent wiring grids extending in the same direction is the same. Therefore, in the peripheral area of the macro block 102, the wirings are arranged close to each other. For example, when the macro block 102 is an analog macro block, the analog signal wiring and the digital signal wiring are arranged so as to run parallel to each other with a wiring grid interval GD1 therebetween, or arranged so as to intersect with each other. As a result, the possibility of superimposing noise on the analog signal is increased.

  In order to prevent such wiring, it is conceivable that, for example, the entire wiring grid interval is largely changed around the macroblock. However, in a general automatic placement and routing tool, even if it is a cell placement and routing prohibition area, if the margin of wiring is lost, wiring is placed on the wiring grid in which the wiring grid interval is greatly changed in that area. Sometimes. However, in order to simplify the wiring process, it is desirable to place the cell terminals on the grid points of the wiring grid. If the wiring grid interval is simply changed, the cell terminals cannot be arranged or changed. The wiring process for connecting the terminal of the cell that does not exist on the subsequent wiring grid and the wiring on the changed wiring grid becomes complicated.

  Therefore, in the first embodiment, the crosstalk between the wirings in the region can be easily achieved by locally increasing the wiring grid interval and arranging the cells defined by the cell grid corresponding to the enlarged wiring grid. The influence by can be reduced. More specifically, in the first embodiment, as shown in FIG. 1B, an area where the influence of crosstalk between arranged wirings is to be reduced is set as the wiring grid change area BA, and the wiring grid change area BA is set. In the wiring grid change area BA, the cell grid corresponding to the wiring grid intervals GD2x and GD2y is changed so that the wiring grid intervals GD2x and GD2y (GD2x> GD1, GD2y> GD1) Place the specified cell.

  In this way, in FIG. 1A, even if there is an influence due to crosstalk between the wirings arranged in the area set as the cell placement and wiring prohibition area, the complicated wiring process is performed as the wiring grid change area. Thus, it is possible to reliably reduce the influence of crosstalk between wirings wired in this region.

  Hereinafter, the configuration and operation of an integrated circuit design apparatus that realizes such processing will be described.

  FIG. 2 shows a block diagram of a configuration example of the integrated circuit design system according to the first exemplary embodiment.

  The integrated circuit design system 10 according to the first embodiment includes an integrated circuit design device 20 and a display device 40. The integrated circuit design apparatus 20 performs cell and wiring on a grid-like wiring grid defined in the layout possible area according to a net list having connection information between cells and macroblocks by a given automatic placement and routing algorithm. Perform the placement process. The result of the cell and wiring arrangement processing by the integrated circuit design device 20 is displayed on the display device 40. The function of the integrated circuit design device 20 is realized by a personal computer, a network terminal (client terminal connected to a server), or the like, and the display device 40 is realized by a CRT (Cathode Ray Tube) device, a liquid crystal display device, or the like.

  The integrated circuit design device 20 includes a net list storage unit 22, a wiring grid change area setting unit 24, a wiring grid change processing unit 26, a cell information storage unit 28, and a placement and routing processing unit 30. The net list storage unit 22 stores a net list. The integrated circuit design device 20 performs processing for arranging cells and wirings based on the net list.

  The wiring grid change area setting unit 24 sets a given area in the layout possible area as the wiring grid change area. In the wiring grid change area, it is desirable that the priority of cell arrangement in the area is set lower than the priority of cell arrangement in other areas. This wiring grid changing area is desirably set to an area where it is desired to reduce the influence of crosstalk between arranged wirings.

  The wiring grid change processing unit 26 performs a process of changing the interval between the wiring grids provided in a lattice shape. That is, the wiring grid change processing unit 26 changes the interval between the wiring grids extending in at least one of the first and second directions intersecting each other in the wiring grid changing area set as the wiring grid changing area. At this time, the wiring grid change processing unit 26 changes the interval between the wiring grids in the wiring grid change area more greatly. That is, the first wiring grid interval GD1 before the changing process by the wiring grid changing processing unit 26 becomes the second wiring grid interval GD2 (GD2> GD1) by the changing process.

  The cell information storage unit 28 stores a plurality of cell information. Here, the cell information includes information necessary for the arrangement of cells and wirings such as the shape of the cell, the number of terminals, and the terminal position for each cell. Each cell is designated with a layout shape in the cell with reference to a cell grid defined in each cell. The cell information storage unit 28 stores cell information for each of a plurality of types of cell grid intervals for each of a plurality of cell configurations having the same function. For example, for a cell corresponding to an inverter circuit, the cell information storage unit 28 includes cell information of a cell specified by a first cell grid interval and cell information of a cell specified by a second cell grid interval. Remembered. The first cell grid interval is a cell grid interval corresponding to the first wiring grid interval (wiring grid interval before change processing), and the second cell grid interval (wiring grid interval after change processing) is the second interval. This is the cell grid interval corresponding to the wiring grid interval.

  Based on the net list stored in the net list storage unit 22, the placement / wiring processing unit 30 arranges cells so that the terminals are arranged on the grid points of the wiring grid, and arranges wirings on the wiring grid. To do.

  FIG. 3 is an operation explanatory diagram of the wiring grid change processing unit 26 of FIG. In FIG. 3, it is assumed that the integrated circuit 100 is composed of standard cells, and only the P-type (for example, first conductivity type) active area PA and the N-type (for example, second conductivity type) active area NA of each cell are schematically illustrated. Represents.

  In the wiring grid change area set by the wiring grid change area setting unit 24, the wiring grid change processing unit 26 changes the interval between the wiring grids extending in at least one of the first and second directions intersecting each other. be able to.

  As shown in FIG. 3, a P-type active area PA and an N-type active area NA are arranged in each cell. In the integrated circuit 100, like the cells C10 to C13, active regions of the same conductivity type of all the cells in a given direction are arranged adjacent to each other. The active region continuous arrangement direction in which active regions of the same conductivity type of all the cells are arranged adjacent to each other is defined as an X direction. In the Y direction intersecting with the X direction, when the P-type active areas PA and N-type active areas NA are alternately arranged as in the cells C10 and C20, or in the mirror arrangement as in the cells C13 and C24, the P-type is activated. One of the active area PA and the N-type active area NA may be arranged adjacent to each other.

  As described above, the wiring grid change processing unit 26 can change the interval between the wiring grids extending in at least one of the X direction and the Y direction defined as shown in FIG. 3 in the wiring grid changing region. This simplifies the generation of the cells defined by the cell grid interval corresponding to the wiring grid interval that has been changed greatly, and simplifies the wiring process in the wiring grid change region.

  FIG. 4 schematically shows an operation explanatory diagram of the placement and routing processing unit 30 of FIG.

  In FIG. 4, a wiring grid extending in the X direction (first direction) at the wiring grid interval yd1 and a wiring grid extending in the Y direction (second direction) at the wiring grid interval xd1 are provided in a grid pattern. . That is, a wiring grid extending in the X direction and a wiring grid extending in the Y direction intersecting the X direction are provided.

  The placement and routing processing unit 30 places the terminal XC1 of the cell CL having a given shape on a given grid point of the wiring grid. In addition, the placement and wiring processing unit 30 places the wiring CN1 on a given wiring grid.

  Therefore, outside the wiring grid change area, the cells are arranged so that the terminals are arranged on the grid points of the wiring grid before the change processing, and the wiring is arranged on the wiring grid before the change processing. In the wiring grid change area, the terminals are arranged on the grid points of the wiring grid whose intervals are changed by the wiring grid change processing unit 26, and the wiring is arranged on the wiring grid after the change processing. . At this time, a cell (designated by the second cell grid interval) whose configuration is designated on the basis of the cell grid corresponding to the wiring grid interval (second wiring grid interval) changed by the wiring grid change processing unit 26. Are arranged on the grid points of the wiring grid after the change processing.

  FIG. 5 shows an outline of cell information stored in the cell information storage unit 28 of FIG.

  The cell information storage unit 28 stores a plurality of types of cell information defined at different cell grid intervals for cells having the same function. For example, the cell information storage unit 28 stores the cell information of the inverter circuits INV-1 and INV-2 defined by two types of cell grid intervals for the inverter circuit having the same function. The cell of the inverter circuit INV-1 is a cell defined by a first cell grid interval cg1 corresponding to the first wiring grid interval GD1, for example. The cell of the inverter circuit INV-2 is a cell defined by, for example, a second cell grid interval cg2 (cg2> cg1) corresponding to the second wiring grid interval DG2.

  When the wiring grid change processing unit 26 in FIG. 2 performs a change to increase only the wiring grid interval in the X direction among the wiring grids provided in the X direction and the Y direction (see FIG. 4), the cell information storage unit 28 The cell information of the cell defined by the original cell grid interval and the cell information of the cell defined by the cell grid interval which is larger only in the X direction than the original cell grid interval are stored. Then, the placement and routing processing unit 30 reads out cell information of a cell whose cell grid interval is increased only in the X direction from the cell information storage unit 28, places the cell on the wiring grid in the wiring grid change area, and the wiring grid. A process of connecting to the wiring arranged above is performed.

  6A and 6B are explanatory diagrams of cell information stored in the cell information storage unit 28 when only the wiring grid interval in the X direction is greatly changed. FIG. 6A shows an explanatory diagram of cell information of the inverter circuit INV-1. FIG. 6B shows an explanatory diagram of cell information of the inverter circuit INV-2. In FIG. 6B, the same portions as those in FIG. 6A are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The inverter circuit INV-1 extends in the X direction and the Y direction, and its layout shape is defined with reference to a cell grid provided in a lattice shape with a cell grid interval cg1. That is, in the inverter circuit INV-1, a wiring layer M1 to which the high potential side power supply voltage VDD is applied, a wiring layer M2 to which the low potential side power supply voltage VSS is applied, and a P type active region in which a P type channel region is formed. A region PA and an N-type active region NA in which an N-type channel region is formed are provided. Wiring layer M1 and P-type active area PA are electrically connected by via cell VC1 in the source area. The wiring layer M2 and the N-type active area NA are electrically connected by a via cell VC2 in the source area. In addition, in the inverter circuit INV-1, a polysilicon layer PL is provided above the P-type active area PA and the N-type active area NA (via an insulating film). An input terminal A arranged on the grid point of the grid is provided. A wiring layer M3 is provided and electrically connected to a region serving as a drain region in the P-type active region PA and a region serving as a drain region in the N-type active region NA via via cells VC3 and VC4. The wiring layer M3 is provided with an output terminal X arranged on the lattice point of the cell grid.

  The cell information of the inverter circuit INV-1 is information in which the shape shown in FIG. 6A is specified by the cell grid interval, the coordinate position of the cell grid coordinate system, and the like.

  On the other hand, the inverter circuit INV-2 is based on the cell grid CG extending in the X direction and provided at the cell grid interval cg1, or on the basis of the cell grid CG extending in the Y direction and provided at the cell grid interval cg2. The layout shape is specified. That is, the inverter circuit INV-2 has the same length in the Y direction as the inverter circuit INV-1, and the length in the X direction is longer. Therefore, the inverter circuit INV-2 has a shape that is longer by a length d1 in the X direction than the inverter circuit INV-1. On the other hand, in the inverter circuit INV-2, the input terminal A and the output terminal X are arranged on the grid points of the cell grid corresponding to the wiring grid interval that the wiring grid change processing unit 26 changes more greatly.

  The cell information of the inverter circuit INV-2 is information in which the shape shown in FIG. 6B is specified by the cell grid interval, the coordinate position of the cell grid coordinate system, and the like.

  As a result, the wiring grid interval can be increased in a region that is easily affected by crosstalk between adjacent wirings, so that the influence of crosstalk between adjacent wirings can be reduced in this region. . In addition, since the cells defined by the cell grid interval corresponding to the increased wiring grid interval can be arranged in this region, it is not necessary to perform complicated wiring processing.

  Further, when the wiring grid change processing unit 26 in FIG. 2 performs a change to increase only the wiring grid interval in the Y direction among the wiring grids provided in the X direction and the Y direction, the cell information storage unit 28 stores the original information. The cell information of the cell defined by the cell grid interval and the cell information of the cell defined by the cell grid interval which is increased only in the Y direction with respect to the original cell grid interval are stored. Then, the placement and wiring processing unit 30 reads out cell information of the cell with the cell grid interval reduced only in the Y direction from the cell information storage unit 28, places the cell on the wiring grid in the wiring grid change area, and the wiring grid. A process of connecting to the wiring arranged above is performed.

  7A and 7B are explanatory diagrams of cell information stored in the cell information storage unit 28 when only the wiring grid interval in the Y direction is significantly changed. FIG. 7A shows an explanatory diagram of cell information of the inverter circuit INV-1. FIG. 7B is an explanatory diagram of cell information of the inverter circuit INV-2. 7A, the same portions as those in FIG. 6A are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In FIG. 7B, the same portions as those in FIG. 7A are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The layout of the inverter circuit INV-1 is specified with reference to a cell grid that extends in the X direction and the Y direction and is provided in a grid pattern with a cell grid interval cg1. The inverter circuit INV-1 illustrated in FIG. 7A has the same shape as the inverter circuit INV-1 illustrated in FIG. The cell information of the inverter circuit INV-1 is information in which the shape shown in FIG. 7A is specified by the cell grid interval, the coordinate position of the cell grid coordinate system, and the like.

  On the other hand, the inverter circuit INV-2 is based on the cell grid CG extending in the X direction and provided with the cell grid interval cg3, or on the basis of the cell grid CG extending in the Y direction and provided with the cell grid interval cg1. A layout shape is specified. Here, although the length in the X direction of the inverter circuit INV-2 is the same as that of the inverter circuit INV-1, the length in the Y direction is the same as that of the inverter circuit INV-1, thereby simplifying the cell arrangement process. ing. On the other hand, in the inverter circuit INV-2, the input terminal A and the output terminal X are arranged on the grid points of the cell grid corresponding to the wiring grid interval that the wiring grid change processing unit 26 changes more greatly.

  The cell information of the inverter circuit INV-2 is information in which the shape shown in FIG. 7B is specified by the cell grid interval, the coordinate position of the cell grid coordinate system, and the like.

  As a result, the wiring grid interval can be increased in a region that is easily affected by crosstalk between adjacent wirings, so that the influence of crosstalk between adjacent wirings can be reduced in this region. . In addition, since the cells defined by the cell grid interval corresponding to the increased wiring grid interval can be arranged in this region, it is not necessary to perform complicated wiring processing.

  Further, when the wiring grid change processing unit 26 in FIG. 2 performs a change to increase the wiring grid interval in the X direction and the wiring grid interval in the Y direction, the cell information storage unit 28 defines the original cell grid interval. The cell information of the cell and the cell information of the cell defined by the cell grid interval that is larger in the X direction and the Y direction than the original cell grid interval are stored. Then, the placement and wiring processing unit 30 reads the cell information of the cell with the cell grid interval increased in the X direction and the Y direction from the cell information storage unit 28, arranges the cell on the wiring grid in the wiring grid change area, A process of connecting to the wiring arranged on the wiring grid is performed.

  8A and 8B are explanatory diagrams of cell information stored in the cell information storage unit 28 when the wiring grid interval is greatly changed in the X direction and the Y direction. FIG. 8A shows an explanatory diagram of cell information of the inverter circuit INV-1. FIG. 8B shows an explanatory diagram of cell information of the inverter circuit INV-2. In FIG. 8A, the same portions as those in FIG. 6A are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In FIG. 8B, the same portions as those in FIG. 8A are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The inverter circuit INV-1 extends in the X direction and the Y direction, and its layout shape is specified on a cell grid provided in a lattice shape with a cell grid interval cg1. The inverter circuit INV-1 illustrated in FIG. 8A has the same shape as the inverter circuit INV-1 illustrated in FIG. The cell information of the inverter circuit INV-1 is information in which the shape shown in FIG. 8A is specified by the cell grid interval, the coordinate position of the cell grid coordinate system, and the like.

  On the other hand, the inverter circuit INV-2 is based on the cell grid CG extending in the X direction and provided with the cell grid interval cg3, or on the basis of the cell grid CG extending in the Y direction and provided with the cell grid interval cg2. A layout shape is specified. Here, the inverter circuit INV-2 has a shape that is longer by a length d1 in the X direction than the inverter circuit INV-1, and the length in the Y direction is the same as that of the inverter circuit INV-1. The arrangement process is simplified. On the other hand, in the inverter circuit INV-2, the input terminal A and the output terminal X are arranged on the grid points of the cell grid corresponding to the wiring grid interval that the wiring grid change processing unit 26 changes more greatly.

  The cell information of the inverter circuit INV-2 is information in which the shape shown in FIG. 8B is specified by the cell grid interval, the coordinate position of the cell grid coordinate system, and the like.

  As a result, the wiring grid interval can be increased in a region that is easily affected by crosstalk between adjacent wirings, so that the influence of crosstalk between adjacent wirings can be reduced in this region. . In addition, since the cells defined by the cell grid interval corresponding to the increased wiring grid interval can be arranged in this region, it is not necessary to perform complicated wiring processing.

  As described above, the integrated circuit design device 20 according to the first exemplary embodiment includes the cell information storage unit 28 that stores information on a plurality of cells that specify the configuration of cells having the same function at different cell grid intervals, A wiring grid change area setting unit 24 that sets an area as a wiring grid change area, and a wiring grid change process that changes the interval between wiring grids in the area set as the wiring grid change area by the wiring grid change area setting unit 24 And an arrangement wiring processing unit 30 that arranges a given wiring and cell in the wiring grid whose interval is changed by the wiring grid change processing unit 26 in the area set as the wiring grid change area. . Then, the arrangement and wiring processing unit 30 is configured with the cell grid interval corresponding to the interval of the wiring grid changed by the wiring grid change processing unit 26 based on the cell arrangement information stored in the cell information storage unit 28. The designated cell can be arranged on the wiring grid whose interval is changed by the wiring grid change processing unit 26.

  By the way, in the first embodiment, it is desirable to locally set one or a plurality of wiring grid change areas in the layout possible area. For example, the wiring grid change area of the first embodiment is set in the following areas. Is desirable.

  FIG. 9 shows an example of the wiring grid change area in the first embodiment. FIG. 9 schematically illustrates an example of a floor plan of the integrated circuit 100 in which cells and wirings are arranged by automatic placement and routing in the integrated circuit design device 20 of the first exemplary embodiment.

  In the integrated circuit 100, I / O cell areas IA1 to IA4 having a certain width are provided adjacent to each side of the rectangular layout available area LA. In each I / O cell region, a pad and an I / O cell corresponding to the pad are arranged along the edge of the chip. This pad is electrically connected to a terminal of the IC package via a bonding wire.

  Automatic placement and routing of cells and wirings by the integrated circuit design apparatus 20 is performed in the layout possible area LA. In FIG. 9, it is assumed that macroblocks MB1 to MB3 are arranged in the layout available area LA. The macro blocks MB1 to MB3 are analog macro blocks each having an analog circuit (for example, an oscillation circuit, a power supply circuit, a RAM, an A / D converter, a D / A converter, etc.), and the integrated circuit design apparatus 20 according to the first embodiment. Before the cell and wiring arrangement process according to, signal lines for transmitting analog signals input or output to analog macroblocks in advance are arranged in a physical layout.

  In the first embodiment, as shown in FIG. 9, it is desirable to set the peripheral area of the analog macro block as a wiring grid change area. In FIG. 9, the peripheral areas MC1 to MC3 of the macroblocks of the macroblocks MB1 to MB3 are set as the wiring grid change area.

  FIG. 10 is an explanatory diagram of the wiring grid change area set in the peripheral area of the analog macroblock. FIG. 10 is an explanatory diagram of the region MC3. 10, the same parts as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  Here, it is assumed that the macroblock MB3 has a rectangular shape in which the length in the X direction is D1 and the length in the Y direction is D2. At this time, the area MC3 as the wiring grid change area is an area provided outside the macro block MB3 by a given length. More specifically, an area that is evenly provided on the outside by the length W1 from the edge of the macroblock MB3 is set as the wiring grid change area. Therefore, in the area MC3 as the wiring grid change area in FIG. 10, the priority of the cell arrangement is lowered and the wiring grid interval is changed to be larger than that in the other areas.

  As a result, as shown in FIG. 9, even if the digital signal wiring CND is arranged in the wiring grid changing area MC3, the digital signal wiring CND is arranged away from the analog signal wiring CNA input or output to the macroblock MB3 in advance. Therefore, it is possible to reduce the influence of crosstalk on the wiring CNA.

  The functions of the integrated circuit design apparatus 20 as described above may be realized by hardware or may be realized by software. In the following, it is assumed that the function of the integrated circuit design device 20 is realized by software processing.

  FIG. 11 shows a block diagram of a hardware configuration example of the integrated circuit design device 20 of FIG.

  The integrated circuit design apparatus 20 includes a CPU 50, an I / F circuit 52, a read only memory (ROM) 54, a random access memory (RAM) 56, and a bus 58. The CPU 50, the I / F circuit 52, the ROM 54, and the RAM 56 are electrically connected.

  For example, the ROM 54 or the RAM 56 stores a program that realizes the function of the integrated circuit design apparatus 20. The CPU 50 can implement the functions of the integrated circuit design apparatus 20 described above by software processing by reading a program stored in the ROM 54 or the RAM 56 and executing processing corresponding to the program. That is, the function of each unit of the integrated circuit design device 20 of FIG. 2 is realized by the CPU 50 that reads a program stored in the ROM 54 or the RAM 56 and performs processing corresponding to the program.

  The RAM 56 is used as a work area for processing by the CPU 50 or used as a buffer area for the I / F circuit 52 or the ROM 54. The I / F circuit 52 performs an output interface process (display process, display drive process) to the display device 40 in FIG. 2, an input interface process of a signal that designates a wiring grid change area from an input interface (not shown), and the like.

  FIG. 12 shows a flowchart of a processing example of the integrated circuit design apparatus 20 of FIG. For example, the ROM 54 or RAM 56 in FIG. 11 stores a program for realizing the processing shown in FIG. 12, and the CPU 50 reads the program stored in the ROM 54 or RAM 56 and executes processing corresponding to the program. Thus, the processing shown in FIG. 12 can be realized by software processing.

  First, the integrated circuit design apparatus 20 reads the floor plan setting information generated in advance or takes in the floor plan setting information designated from the outside, and puts the analog macro block in the layout possible area of the integrated circuit 100. Is performed (step S10).

  Next, the integrated circuit design apparatus 20 integrates, for example, the wiring grid change area designated from the outside by the function of the wiring grid change area setting unit 24 as the wiring grid change area step. A process of setting the layout possible area of the circuit 100 is performed (step S12). The wiring grid change area set in step S12 is, for example, the peripheral area of the analog macro block described with reference to FIG.

  Here, the integrated circuit design device 20 once performs a cell and wiring arrangement process by the function of the arrangement and wiring processing unit 30 (step S14). That is, in step S14, in order to confirm the influence of the crosstalk between the wirings arranged in the wiring grid change area, the cells and the cells and the wiring grid intervals in the wiring grid change area set in step S12 are not changed. Wiring placement processing is performed.

  In step S14, after the cell and wiring arrangement processing is performed once, the integrated circuit design device 20 checks the degree of influence caused by the crosstalk of the wiring input or output to the analog macroblock (step S16). . At this time, for example, in the wiring grid change area, for example, when both wirings are arranged on the adjacent wiring grid, or when both wirings intersect, the analog signal wiring input or output to the analog macroblock, It is determined that the wiring of the digital signal is determined to be affected by the crosstalk, and a region other than the wiring grid change region in which the display device 40 notifies that effect or the wiring that may be affected by the crosstalk is arranged. Is notified by the display device 40.

  In step S16, as a result of checking the influence degree of both wirings, when it is determined that the wiring of the digital signal does not affect the wiring of the analog signal input or output to the analog macroblock due to the crosstalk (step S16: Y) The integrated circuit design device 20 ends the series of processing (end).

  In step S16, as a result of checking the influence degree of both wirings, when it is determined that the wiring of the digital signal affects the wiring of the analog signal input to or output from the analog macroblock (step S16: N The integrated circuit design apparatus 20 performs a change process for increasing the wiring grid interval in the wiring grid change area by the function of the wiring grid change processing unit 26 as a wiring grid changing step (step S18).

  Subsequently, the integrated circuit design device 20 uses the function of the placement and routing processing unit 30 to change the cells in the wiring grid change area to cells having the same function defined by the cell grid interval corresponding to the wiring grid interval changed in step S18. (Step S20), the process returns to step S14 again to perform the placement and routing process. That is, step S20 and subsequent step S14 are arranged in the wiring grid change area, as a placement and routing step, placing a given wiring on the wiring grid whose wiring grid interval has been changed in the wiring grid changing step. Then, the cells whose configuration is designated based on the cell grid corresponding to the interval between the wiring grids changed in the wiring grid changing step are arranged in the wiring grid whose wiring grid interval has been changed in the wiring grid changing step.

  In step S20 and step S14 performed subsequently thereto, in a region other than the wiring grid change region, a given wiring is arranged at the wiring grid interval before the change process, and the wiring grid interval before the change process. A cell whose configuration is designated with reference to the cell grid corresponding to is arranged in the wiring grid at the wiring grid interval before the change processing.

  If cell information corresponding to a plurality of types of cell grid intervals is stored in the cell information storage unit 28, the wiring of the digital signal crosses the wiring of the analog signal input or output to the analog macroblock in step S16. Until it is determined that there is no influence from the talk, the wiring grid in the wiring grid change area is greatly changed and the replacement of cells having the same function defined by the cell grid interval corresponding to the changed wiring grid interval is repeated. Can do.

  Further, while greatly changing the wiring grid in the wiring grid changing area and repeating the replacement of the cells having the same function, the wiring grid interval changed in step S18 becomes larger, and the wiring grid set in step S12 is increased. It will be repeated until it is set outside the change area.

  In FIG. 12, it has been described that the cell and wiring arrangement / wiring process is performed in step S14 following step S20, but the present invention is not limited to this. For example, as a result of checking the influence of both wires in step S16, when an area other than the wiring grid change area in which the wiring that may be affected by crosstalk is specified is specified, the process returns to step S12 following step S20. Then, after the wiring grid change area is newly added and set, the arrangement wiring process of cells and wirings may be performed in step S14.

  In step S18, when the wiring grid interval is changed, the wiring grid interval may be greatly changed so that the wiring grid is set outside the wiring grid changing region as it is. By doing so, it becomes possible to reliably prevent the arrangement of cells and wirings on the wiring grid changed outside the area within the wiring grid change area.

  As described above, in the first embodiment, the wiring grid change area setting step for setting a given area as the wiring grid change area, and the wiring grid in the area set as the wiring grid change area in the wiring grid change area setting step In the wiring grid changing step for changing the interval of the wiring to a larger extent, and in the area set as the wiring grid changing area, the given wiring is arranged on the wiring grid whose interval was changed in the wiring grid changing step, and the wiring grid A placement and routing step of placing cells whose configuration is specified at a cell grid interval corresponding to the interval of the wiring grid changed in the changing step on the wiring grid whose interval is changed in the wiring grid changing step. it can.

  According to the first embodiment, for example, a signal wiring that transmits an analog signal and a signal wiring that transmits a digital signal around a predetermined macroblock while suppressing an increase in processing load without performing special wiring processing. The effect of crosstalk with can be reduced.

[Modification of Embodiment 1]
In the integrated circuit design apparatus 20 according to the first embodiment, a description has been given assuming that a plurality of pieces of cell information in which cells having the same function are defined by a plurality of types of cell grid intervals are stored in the cell information storage unit 28. It is not limited to this. For example, when the wiring grid interval is changed more greatly, cell information defined by the cell grid interval corresponding to the changed wiring grid interval may be newly generated.

  FIG. 13 shows a block diagram of a configuration example of an integrated circuit design apparatus in a modification of the first embodiment. In FIG. 13, the same parts as those in FIG.

  The integrated circuit design device 80 according to the modification of the first embodiment includes a net list storage unit 22, a wiring grid change area setting unit 24, a wiring grid change processing unit 26, a cell information storage unit 28, a placement and routing processing unit 30, and cell information generation. Part 90 is included.

  Since the configurations and functions of the net list storage unit 22, the wiring grid change area setting unit 24, the wiring grid change processing unit 26, the cell information storage unit 28, and the placement and routing processing unit 30 are the same as those in the first embodiment, they will be described. Is omitted.

  The cell information generation unit 90 newly generates information on a cell whose layout shape is defined at a cell grid interval corresponding to the wiring grid interval changed by the wiring grid change processing unit 26. For this reason, when the change process which makes a wiring grid space | interval larger is performed by the wiring grid change process part 26, the cell information production | generation part 90 is in the wiring grid change area | region among the cells memorize | stored in the cell information storage part 28. FIG. Read the information of the cells placed in the. Then, the cell information generation unit 90 changes the cell grid interval of the read cell information more greatly so that the cell grid interval corresponding to the wiring grid interval changed by the wiring grid change processing unit 26 is obtained. Information specifying the shape of the corresponding cell is generated. At this time, the cell information generation unit 90 generates information specifying the shape of the cell so that the terminals are arranged on the lattice points of the cell grid after the change even when the cell grid interval is increased.

  The placement and wiring processing unit 30 performs processing for placing cells and wirings on the wiring grid whose wiring grid interval has been changed based on the cell information generated by the cell information generation unit 90 within the wiring grid change region. Do.

  Note that the cell information generation unit 90 may generate cell information every time the wiring grid interval is changed by the wiring grid change processing unit 26, or a plurality of changes after the change by the wiring grid change processing unit 26 in advance. If the wiring grid interval is known, cell information of the cell grid interval corresponding to each wiring grid interval may be generated prior to the change processing by the wiring grid change processing unit 26.

  According to this modification, the wiring grid change processing unit 26 can change to an arbitrary wiring grid interval, so that the high integration of the integrated circuit 100 can be further promoted.

[Embodiment 2]
The integrated circuit design apparatus 20 according to the first embodiment or the integrated circuit design apparatus 80 according to the modification of the first embodiment increases the wiring grid interval in the wiring grid change area, for example, an analog input or output to an analog macroblock. Although the influence of the crosstalk on the signal wiring is reduced, the present invention is not limited to this. In the second embodiment according to the present invention, the influence of crosstalk on the wiring of the analog signal is surely reduced by eliminating the wiring grid in the wiring grid change area.

  14A and 14B schematically show an outline of processing of the integrated circuit design apparatus according to the second embodiment. FIG. 14A schematically shows an outline of an integrated circuit layout using the integrated circuit design apparatus in the comparative example of the second embodiment. FIG. 14B schematically shows an outline of an integrated circuit layout using the integrated circuit design apparatus of the second embodiment. 14A and 14B, the same portions are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The integrated circuit design apparatus according to the second embodiment or the comparative example arranges cells and wirings on a grid-like wiring grid defined in the layout possible area according to a net list having connection information between cells and macroblocks. Process. As a result, in FIGS. 14A and 14B, in the integrated circuit 100, the macro block 102, the logic circuit cells, and the wirings connecting them are arranged on the wiring grid.

  In FIG. 14A, the first layer wiring ML1, the second layer wiring ML2 above the first layer wiring ML1, the first layer wiring ML1, and the second layer wiring ML2 are arranged on the wiring grid GR provided in a lattice shape. A via cell VC for electrically connecting the two is disposed. A wiring grid interval GD1, which is an interval between adjacent wiring grids GR, is defined by a design rule depending on the manufacturing process. For example, the wiring grid interval GD1 is defined so as to be equal to or greater than the minimum pitch m1 between the edges of adjacent via cells VC. For example, the first layer wiring ML1 is disposed on the wiring grid GR extending in the vertical direction, and the second layer wiring ML2 is disposed on the wiring grid GR extending in the horizontal direction. Placed on a point.

  In FIG. 14A, it has been described that the interval between the wiring grids extending in the horizontal direction is the same as the interval between the wiring grids extending in the vertical direction, but the interval between the wiring grids in both directions may be different.

  By the way, also in the integrated circuit design apparatus in the comparative example of the second embodiment, the wirings are arranged close to each other in the peripheral region of the macro block 102. For example, when the macro block 102 is an analog macro block, the analog signal wiring and the digital signal wiring are arranged so as to run in parallel or cross each other with a wiring grid interval GD1, and the analog signal has noise. Is likely to be superimposed.

  In order to surely prevent such wiring, in the second embodiment, processing for locally erasing the wiring grid is performed. More specifically, in the second embodiment, as shown in FIG. 14B, an area in which the influence of crosstalk between arranged wirings is to be reduced is set as the wiring grid change area BA, and the wiring grid change area BA is set. The wiring grid inside disappears.

  In this way, in FIG. 14A, even if there is an influence due to crosstalk between the wirings arranged in the area set as the cell placement wiring prohibition area, the wiring grid disappears in the wiring grid change area. Therefore, cells and wirings are not arranged, and the influence of crosstalk between wirings in this region can be reliably reduced.

  Hereinafter, the configuration and operation of an integrated circuit design apparatus that realizes such processing will be described.

  FIG. 15 is a block diagram illustrating a configuration example of the integrated circuit design system according to the second embodiment. In FIG. 15, the same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The integrated circuit design system 200 according to the second embodiment includes an integrated circuit design device 210 and a display device 40. Similar to the integrated circuit design apparatus 20 of FIG. 2, the integrated circuit design apparatus 210 uses a given automatic placement and routing algorithm to place cells and macroblocks on a grid-like wiring grid defined in the layout possible area. A process of arranging cells and wirings is performed according to a net list having connection information. The result of the cell and wiring arrangement processing by the integrated circuit design device 210 is displayed on the display device 40. The functions of the integrated circuit design apparatus 210 are realized by a personal computer, a network terminal (client terminal connected to a server), or the like.

  The integrated circuit design device 210 includes a net list storage unit 22, a wiring grid change area setting unit 212, a wiring grid change processing unit 214, a cell information storage unit 216, and a placement and routing processing unit 30. The net list storage unit 22 stores a net list. The integrated circuit design device 210 performs processing for arranging cells and wirings based on the net list.

  The wiring grid change area setting unit 212 sets a given area in the layout possible area as the wiring grid change area. In the wiring grid change area, as will be described later, the arrangement of cells and wirings is prohibited. This wiring grid changing area is desirably set to an area where it is desired to reduce the influence of crosstalk between arranged wirings.

  The wiring grid change processing unit 214 performs a process of changing the interval between the wiring grids provided in a lattice shape. That is, the wiring grid change processing unit 214 performs a process of eliminating a wiring grid extending in at least one of the first and second directions intersecting each other in the wiring grid changing area set as the wiring grid changing area. . Here, the first direction can be the X direction defined as shown in FIG. 3, and the second direction can be the Y direction defined as shown in FIG.

  The cell information storage unit 216 stores a plurality of pieces of cell information. Here, the cell information includes information necessary for the arrangement of cells and wirings such as the shape of the cell, the number of terminals, and the terminal position for each cell. For each cell, the shape of the layout in the cell is designated based on the cell grid. Unlike the cell information storage unit 28 of the first embodiment, the cell information storage unit 216 stores cell information defined by one type of cell grid interval.

  Based on the net list stored in the net list storage unit 22, the placement / wiring processing unit 30 arranges cells so that the terminals are arranged on the grid points of the wiring grid, and arranges wirings on the wiring grid. To do. The placement and routing processing unit 30 performs the same processing as in the first embodiment described in FIG.

  As described above, the integrated circuit design device 210 according to the second exemplary embodiment uses the wiring grid change area setting unit 212 that sets a given area as the wiring grid change area and the wiring grid change area setting unit 212 as the wiring grid change area. The wiring grid change processing unit 214 that eliminates the wiring grid in the set area and the area set as the wiring grid change area are excluded, and cells and wirings are added to the wiring grid processed by the wiring grid change processing part 214. And a placement and routing processing unit 30 to be placed.

  In the second embodiment, it is desirable to set one or a plurality of wiring grid change regions locally in the layout possible region, as in the first embodiment or the modification thereof, for example, in the region shown in FIG. It is desirable to set the wiring grid change area of the second embodiment. That is, also in the second embodiment, it is desirable to set the peripheral area of the analog macro block as the wiring grid change area.

  As a result, as shown in FIG. 9, even if the digital signal wiring CND is arranged in the wiring grid change area MC3, the analog signal wiring input or output to the macro block MB3 in advance is not arranged. The influence of the crosstalk on the wiring CNA can be surely reduced.

  The functions of the integrated circuit design apparatus 210 as described above may be realized by hardware or may be realized by software. In the following, it is assumed that the function of the integrated circuit design device 210 is realized by software processing.

  Here, the hardware configuration example of the integrated circuit design device 210 is the same as the integrated circuit design device 20 of the first embodiment shown in FIG. 11 or the integrated circuit design device 80 of the modification of the first embodiment. Is omitted. Also in the second embodiment, for example, the ROM 54 or the RAM 56 stores a program for realizing the function of the integrated circuit design device 210. The CPU 50 can implement the functions of the integrated circuit design device 210 described above by software processing by reading a program stored in the ROM 54 or the RAM 56 and executing processing corresponding to the program. That is, the function of each unit of the integrated circuit design device 210 is realized by the CPU 50 that reads a program stored in the ROM 54 or the RAM 56 and performs processing corresponding to the program.

  FIG. 16 shows a flowchart of a processing example of the integrated circuit design apparatus 210 of FIG. For example, the ROM 54 or RAM 56 in FIG. 11 stores a program for realizing the processing shown in FIG. 16, and the CPU 50 reads the program stored in the ROM 54 or RAM 56 and executes processing corresponding to the program. Thus, the processing shown in FIG. 16 can be realized by software processing.

  First, the integrated circuit design device 210 reads the floor plan setting information generated in advance or takes in the designated floor plan setting information from the outside, so that the analog macro block is placed in the layout possible area of the integrated circuit 100. Is performed (step S30).

  Next, the integrated circuit design device 210 performs, as a wiring grid change area step, for example, a wiring grid change area designated from the outside by the function of the wiring grid change area setting unit 212, in which the above analog macroblocks are arranged. A process of setting the layout possible area of the circuit 100 is performed (step S32). The wiring grid change area set in step S32 is, for example, the peripheral area of the analog macro block described with reference to FIG.

  Subsequently, as a wiring grid changing step, the integrated circuit design apparatus 210 performs a changing process for erasing the wiring grid in the wiring grid changing area by the function of the wiring grid changing processing unit 214 (step S34).

  Subsequently, the integrated circuit design apparatus 210 excludes the area set as the wiring grid change area by the function of the placement and routing processing unit 30 as the placement and routing step, and performs cell processing on the wiring grid after the processing in the wiring grid change step. Then, the wiring is arranged (step S36), and the series of processing is ended (end).

  In step S36, when only the X-direction wiring grid disappears in the wiring grid change area, the cells and wirings are arranged on the Y-direction wiring grid in this area, and the wiring grid change is performed. Cells and wirings are arranged on a grid-like wiring grid outside the region. In addition, when only the Y-direction wiring grid is erased in the wiring grid change area, cells and wirings are arranged on the X-direction wiring grid in this area, and a grid-like pattern outside the wiring grid change area is displayed. Cells and wirings are arranged on the wiring grid. Furthermore, in the wiring grid change area, when the wiring grids in the X direction and the Y direction are eliminated, the cells and wiring are not arranged in this area, and the cells and wiring are only outside the wiring grid change area. Be placed.

  As described above, in the second embodiment, the wiring grid change area setting step for setting a given area as the wiring grid change area, and the wiring grid in the area set as the wiring grid change area in the wiring grid change area setting step A wiring grid changing step for eliminating the area and an arrangement wiring step for excluding the area set as the wiring grid changing area and arranging cells and wirings in the wiring grid after the processing in the wiring grid changing step.

  According to the second embodiment, for example, a signal wiring for transmitting an analog signal and a signal wiring for transmitting a digital signal around a predetermined macroblock while suppressing an increase in processing load without performing special wiring processing. It is possible to reliably reduce the influence of crosstalk with the.

  As described above, the integrated circuit design apparatus and the integrated circuit design method according to the present invention have been described based on the above-described embodiment or the modification thereof, but the present invention is not limited to the above-described embodiment or the modification. The present invention can be implemented in various modes without departing from the gist thereof, and for example, the following modifications are possible.

  (1) In the first embodiment or its modification, it has been described that the peripheral area of the analog macroblock is adopted as the wiring grid change area, but the present invention is not limited to this. In the layout possible region, it is only necessary to locally set a region where the wiring grid interval is changed to be larger as the wiring grid change region.

  (2) In the second embodiment, the peripheral area of the analog macro block is used as the wiring grid change area. However, the present invention is not limited to this. It suffices if the area where the wiring grid disappears can be locally set as the wiring grid change area in the layout possible area.

  (3) In the above-described embodiment or its modification, it has been mainly described that the integrated circuit to be designed for layout is composed of standard cells, but the present invention is not limited to this. For example, an integrated circuit constituted by a gate array or an embedded array may be a layout design target.

  (4) In the above embodiment or its modification, the example applied to the layout design of the integrated circuit formed on the semiconductor substrate has been described, but the present invention is not limited to this. For example, the present invention can be applied to a layout design of an integrated circuit in which a circuit is formed on a substrate that is not a semiconductor substrate.

  (5) In the above embodiment or its modification, the P type is described as the first conductivity type and the N type as the second conductivity type. However, the N type may be the first conductivity type and the P type may be the second conductivity type. Good.

  (6) In the above embodiment or its modification, the example in which the wiring of the digital signal affects the wiring of the analog signal input or output to the analog macroblock due to the crosstalk has been described. It is not limited. For example, the present invention can also be applied to the case where the influence of crosstalk given to the clock signal wiring of another system on the wiring of the clock signal input or output to the macroblock is reduced. Further, for example, the present invention can also be applied to a case where the wirings of two types of clock signals of different systems simply run side by side or intersect to reduce the influence of crosstalk that one side has on the other.

  (7) Although the present invention has been described as an integrated circuit design apparatus and an integrated circuit design method in the above embodiment or its modification, the present invention is not limited to this. For example, it may be a program in which a processing procedure of an integrated circuit design method for realizing the present invention is described, or a recording medium on which the program is recorded.

1A and 1B are diagrams schematically showing an outline of processing of an integrated circuit design apparatus according to Embodiment 1 of the present invention. 1 is a block diagram of a configuration example of an integrated circuit design system in Embodiment 1. FIG. Operation | movement explanatory drawing of the wiring grid change process part of FIG. Operation | movement explanatory drawing of the arrangement | positioning wiring process part of FIG. The figure which shows the outline | summary of the cell information which the cell information storage part of FIG. 2 memorize | stores. 6A and 6B are explanatory diagrams of cell information stored in the cell information storage unit when only the wiring grid interval in the X direction is greatly changed. FIGS. 7A and 7B are explanatory diagrams of cell information stored in the cell information storage unit when only the wiring grid interval in the Y direction is significantly changed. 8A and 8B are explanatory diagrams of cell information stored in the cell information storage unit when the wiring grid interval is greatly changed in the X direction and the Y direction. FIG. 3 is a diagram illustrating an example of a wiring grid change area in the first embodiment. Explanatory drawing of the wiring grid change area | region set to the peripheral area | region of an analog macroblock. FIG. 3 is a block diagram of a hardware configuration example of the integrated circuit design device of FIG. 2. FIG. 3 is a flowchart of a processing example of the integrated circuit design apparatus of FIG. 2. The block diagram of the structural example of the integrated circuit design apparatus in Embodiment 1 modification. FIGS. 14A and 14B are diagrams schematically showing an outline of processing of the integrated circuit design apparatus according to Embodiment 2 of the present invention. FIG. 4 is a block diagram of a configuration example of an integrated circuit design system according to a second embodiment. FIG. 16 is a flowchart of a processing example of the integrated circuit design device of FIG. 15.

Explanation of symbols

10, 200 ... integrated circuit design system, 20, 80, 210 ... integrated circuit design device,
22 ... net list storage unit, 24, 212 ... wiring grid change area setting unit,
26, 214 ... wiring grid change processing unit, 28, 216 ... cell information storage unit,
30 ... Place and route processing unit, 40 ... Display device, 50 ... CPU, 52 ... I / F circuit,
54 ... ROM, 56 ... RAM, 58 ... bus, 90 ... cell information generator,
100: Integrated circuit, 102, MB1 to MB3: Macroblock,
BA ... wiring grid change area, C10 to C13, C20, C24, CL ... cell,
CG ... cell grid, CN1 ... wiring, CNA ... analog signal wiring,
CND: Digital signal wiring,
GD1, GD2x, GD2y, xd1, yd1 ... wiring grid interval,
GR ... wiring grid, IA1-IA4 ... I / O cell area,
INV-1, INV-2 ... inverter circuit, LA ... layout possible area,
M1 to M3 ... wiring layer, MC1 to MC3 ... region, ML1 ... first layer wiring,
ML2 ... second layer wiring, NA ... N-type active region, PA ... P-type active region,
PL ... polysilicon layer, VC, VC1 to VC4 ... via cell, XC1 ... terminal,
cg1, cg2, cg3 ... cell grid interval, m1 ... minimum pitch

Claims (15)

A wiring grid change area setting step for setting a given area as a wiring grid change area;
A wiring grid changing step for changing the wiring grid interval in the area set as the wiring grid changing area in the wiring grid changing area setting step to a greater extent;
Within the region, a given wiring is arranged on the wiring grid whose spacing has been changed in the wiring grid changing step, and at a cell grid spacing corresponding to the spacing of the wiring grid changed in the wiring grid changing step. And a placement and routing step of placing a cell whose configuration is designated on the wiring grid whose spacing has been changed in the wiring grid changing step. In claim 1,
The wiring grid changing step includes
An integrated circuit design method, wherein an interval between wiring grids extending in at least one of first and second directions intersecting each other is changed in an area set as the wiring grid changing area. In claim 1 or 2,
The wiring grid changing step includes
An integrated circuit design method, wherein an interval between the wiring grids is greatly changed so that a wiring grid is set outside the region. A wiring grid change area setting step for setting a given area as a wiring grid change area;
A wiring grid changing step for eliminating the wiring grid in the area set as the wiring grid changing area in the wiring grid changing area setting step;
An integrated circuit design method comprising: an arrangement wiring step of arranging cells and wirings in a wiring grid after processing in the wiring grid changing step, excluding the region set as the wiring grid changing region. In claim 4,
The wiring grid changing step includes
A method of designing an integrated circuit, wherein a wiring grid extending in at least one of first and second directions intersecting each other in an area set as the wiring grid changing area is extinguished. In claim 2 or 5,
The first direction is:
A method for designing an integrated circuit, wherein among the cells constituting a standard cell, the active region continuous arrangement direction in which the first conductivity type active regions of all the cells are adjacently arranged is provided. In any one of Claims 1 thru | or 6.
The area set as the wiring grid change area is
A method for designing an integrated circuit, which is a peripheral region of an analog macroblock. In claim 7,
The peripheral area of the analog macroblock is
A method of designing an integrated circuit, characterized in that it is a region provided outside a predetermined length around the analog macroblock. An integrated circuit design apparatus for arranging wiring and cells on a wiring grid,
A cell information storage unit that stores information of a plurality of cells that specify the configuration of a plurality of cells having the same function at different cell grid intervals, and
A wiring grid change area setting unit for setting a given area as a wiring grid change area;
A wiring grid change processing unit that changes the interval of the wiring grid in the region set as the wiring grid change region by the wiring grid change region setting unit;
In the region, including a placement and routing processing unit that arranges a given wiring and cells in the wiring grid that has been changed by the wiring grid change processing unit,
The placement and routing processing unit
Based on the cell information stored in the cell information storage unit, a cell whose configuration is designated by a cell grid interval corresponding to the interval of the wiring grid changed by the wiring grid change processing unit is used as the wiring grid. An integrated circuit design apparatus, wherein the arrangement is arranged on the wiring grid whose interval is changed by a change processing unit. In claim 9,
The wiring grid change processing unit
An integrated circuit design apparatus, wherein an interval between wiring grids extending in at least one of first and second directions intersecting each other is changed in an area set as the wiring grid changing area. In claim 9 or 10,
The wiring grid change processing unit
An integrated circuit design apparatus, wherein the interval between the wiring grids is greatly changed so as to set a wiring grid outside the region. An integrated circuit design apparatus for arranging wiring and cells on a wiring grid,
A wiring grid change area setting unit for setting a given area as a wiring grid change area;
A wiring grid change processing unit for eliminating the wiring grid in the region set as the wiring grid change region by the wiring grid change region setting unit;
An integrated circuit design comprising: an arrangement wiring processing unit that arranges cells and wirings in a wiring grid after processing by the wiring grid change processing unit, excluding the region set as the wiring grid change region apparatus. In claim 12,
The wiring grid change processing unit
An integrated circuit design apparatus, wherein a wiring grid extending in at least one of a first direction and a second direction intersecting each other in an area set as the wiring grid change area is extinguished. In claim 10 or 13,
The first direction is:
An integrated circuit design apparatus, wherein among the cells constituting a standard cell, the active region continuous arrangement direction in which the active regions of the first conductivity type of all the cells are adjacently arranged is provided. In any of claims 9 to 14,
The area set as the wiring grid change area is
An integrated circuit design apparatus characterized by being a peripheral region of an analog macroblock.

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