JP2010016705A - Transmission system and transmission method - Google Patents

Abstract

An optical transmission system having a deskew function applicable to long-distance parallel transfer of a plurality of high-speed channels is realized.
A transmission apparatus 300 includes a multi-frame synchronization circuit 330 that supplies a synchronization signal to each channel, and a frame addition circuit 316 that synchronizes and generates a new overhead having a multi-frame counter bit using the synchronization signal as a trigger. The receiving device 350 includes a deskew function unit 380 that aligns the phase of each channel with reference to the phase generated from the multi-frame counter bit of the signal received by the master channel that is one of the transmitted channels. It was.
[Selection] Figure 3

Description

  The present invention relates to an optical transmission system that divides data into a plurality of channels and transfers them in parallel. More specifically, the present invention relates to a delay due to dispersion of a transmission path, a transmission delay when each channel passes another path, and a circuit component. The present invention relates to an optical transmission system that restores large-capacity data by adjusting a delay difference generated between channels due to a delay due to an inherent deviation and aligning and coupling phases between channels.

  Conventionally, an optical virtual concatenation (OVC) technique has been proposed in order to realize an application requiring a transmission capacity of terabit (Tbit / s) or more and low delay. The OVC technology is a technology that handles a plurality of wavelengths as one group, divides a large volume of data, assigns the data to each wavelength, and transfers the divided data. In the OVC technique, bulk data is divided into n data blocks, assigned to n wavelengths, and transferred as parallel channels. In the receiving unit, n blocks are combined to restore the original bulk data.

  One of the advantages of the OVC technology is that the restriction on the distance determined by the transmission speed can be relaxed. Transmission due to degradation of signal-to-noise ratio (Signal to Noise ratio) and waveform distortion due to transmission loss and nonlinear effects in optical fibers, group velocity dispersion (GVD), polarization mode dispersion (PMD), etc. The higher the speed, the shorter the transmission distance. In the OVC technique, data is divided into a plurality of pieces and transferred, so the transmission speed per wavelength is slowed down, and if the number of divisions is increased, the data can be transmitted over a longer distance. Another advantage is that a transmission rate that is n times the transmission rate at one wavelength can be realized with low delay. For example, if data channels are transferred in parallel using 25 channels (25 wavelengths) having a transmission rate of 40 gigabits per wavelength, a 1 terabit throughput can be realized. On the other hand, one of the problems of the OVC technology is that a delay difference is generated in n parallel channels. The following points can be cited as causes of the delay difference.

  One is a delay difference generated in a process in which a signal passes through a transmission medium such as an optical fiber. When the parallel channels are transferred by the same fiber, the group velocity dispersion becomes a major factor of the transmission delay difference. Further, a delay difference is caused by LD (Laser Diode) oscillation delay in the transmission unit, input power dependency of PD (Photo Diode) in the reception unit, individual deviation of circuit components, and the like. Alternatively, a delay difference is generated for each wavelength by wavelength conversion processing, regenerative relay processing, or the like at the relay node.

  In view of the above factors, a method of performing optical signal processing and a method of performing electrical signal processing are conceivable as methods for absorbing a phase difference between a plurality of channels treated as one group. The optical signal processing can be realized by a method using a dispersion compensation fiber (DCF), a fiber having a different length, or a fiber grating. However, the method using fiber or fiber grating only gives a fixed length delay to each channel. Therefore, for example, it cannot cope with a change in transmission path length due to path switching. Therefore, it is difficult to apply a delay difference absorption technique based on optical signal processing to a network for transferring future large-capacity data.

  Until now, several methods for absorbing a delay difference between channels by electric signal processing have been proposed (for example, see Non-Patent Documents 1 to 3). These techniques are summarized as follows. The transmitter performs framing of the data signal with a specially prepared bit or pattern, and the receiver adjusts the phase by detecting the special bit or pattern. This technique requires increasing the bit rate or adding a special channel. These conventional techniques are based on the assumption that the same route is transferred at a low speed and with a short transfer distance. When a 12-channel 10 Gb Ethernet signal is transferred by 40 km, a delay adjustment of up to 88 nanoseconds (ie, 880 bits) can be achieved. However, these techniques are difficult to apply to terabit class applications that are expected to have a high transmission rate, a long transfer distance, and a large delay difference between channels.

T. Sakamoto et al., “Skew-Compensation Technique for Parallel Optical Interconnections”, IEICE TRANS. COMMUN., VOL.E82-B, NO.8, pp. 1162-1168, AUGUST 1999, (Fig.4) N. Fujimoto et al., “Skew-Free Parallel Optical Transmission Systems”, IEEE JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 16, NO.10, OCTOBER 1998, pp. 1822-1831 N. Toyoda et al., “100-Gb / s Physical-Layer Architecture for Next-Generation Ethernet”, IEICE TRANS. COMMUN., VOL.E89-B, NO.3, pp. 696-703, MARCH 2006

  As described above, it is difficult to apply the conventional delay difference compensation technique based on optical signal processing to a future network that requires a terabit class application. In addition, delay difference compensation technology using electrical signal processing has a low operating speed and a small amount of delay difference compensation, so it can be used for terabit-class applications where the transmission speed is high, the transfer distance is long, and the delay difference between channels is expected to increase. Application is difficult.

  The present invention has been made in view of such problems, and an object thereof is to realize an optical transmission system having a deskew function applicable to long-distance parallel transfer of a plurality of high-speed channels. .

  In order to achieve such an object, according to a first aspect of the present invention, there is provided a transmission system that includes a transmission device and a reception device and divides data into a plurality of channels and transmits the data in parallel. A multi-frame synchronization circuit that supplies a synchronization signal to the frame, and a frame addition circuit that synchronizes and generates a new overhead having a multi-frame counter bit using the synchronization signal from the multi-frame synchronization circuit as a trigger, And a deskew function unit that defines one of the transmitted channels as a master channel and aligns the phases of the channels with reference to the phase generated from the multiframe counter bits. .

  In one embodiment, the deskew function unit distributes, for each channel, a multi-frame pulse phase detection circuit that generates a reference phase signal from the phase of a multi-frame counter bit of a received signal, and the reference phase signal and the master channel. A phase difference detection circuit that detects a phase difference from the reference phase signal that is generated, and a phase difference absorption FIFO memory that adjusts the phase of the channel according to the phase difference detected by the phase difference detection circuit. Features.

  In another embodiment, the deskew function unit includes, for each channel, a multi-frame pulse phase detection circuit that generates a reference phase signal from a phase of a multi-frame counter bit of a received signal, and the reference distributed from the master channel. A delay adjustment circuit that generates a reference phase information signal that gives a predetermined delay to the phase signal, a phase difference detection circuit that detects a phase difference between the reference phase signal and the reference phase information signal, and the phase difference detection circuit And a phase difference absorption FIFO memory that adjusts the phase of the channel according to the detected phase difference.

  In still another embodiment, in the deskew function unit, the rest of each channel excluding the master channel is defined as a slave channel, and the master channel is based on the phase of the multiframe counter bit of the received signal of the master channel. A multi-frame pulse phase detection circuit for generating a phase signal; a delay adjustment circuit for generating a reference phase information signal obtained by giving a predetermined delay to the reference phase signal generated by the master channel; and the reference phase signal and the reference phase A phase difference detection circuit that detects a phase difference from the information signal; and a phase difference absorption FIFO memory that adjusts the phase of the channel according to the phase difference detected by the phase difference detection circuit. The multi-frame counter bit of the received signal of the slave channel. A second multi-frame pulse phase detection circuit for generating a second reference phase signal from the phase; a second phase difference detection circuit for detecting a phase difference between the second reference phase signal and the reference phase information signal; And a second phase difference absorption FIFO memory that adjusts the phase of the channel according to the phase difference detected by the second phase difference detection circuit.

  In still another embodiment, in the deskew function unit, the remainder of each channel excluding the master channel is defined as a slave channel, and the master channel obtains a reference phase signal from the phase of the multiframe counter bit of the received signal. A second multi-frame for generating a second reference phase signal from the phase of a multi-frame counter bit of a received signal for each channel and transmitting the second reference phase signal to the master channel. A pulse phase detection circuit, wherein the master channel compares the phase of the second reference phase signal generated in each of the slave channels with the reference phase signal generated in the master channel, and the reference having the longest delay A group that selects and distributes the phase signal to each channel. And a signal selector circuit, wherein each channel detects a phase difference between the reference signal having the longest delay distributed from the master channel and the first or second reference phase signal generated in each channel. A phase detection circuit and a phase difference absorption FIFO memory that adjusts the phase of the channel according to the phase difference detected by the phase difference detection circuit are provided.

  A second aspect of the present invention is a transmission method in which data is divided into a plurality of channels and transmitted in parallel in a transmission system including a transmission device and a reception device, and the transmission device transmits a synchronization signal to each channel. A step of synchronizing and generating a new overhead having a bit for a multiframe counter using a synchronization signal from the multiframe synchronization circuit as a trigger; and the receiver is defined as a master channel A step of detecting a phase of the bit for the multi-frame counter of a signal received on one of the channels, and a deskewing step in which the receiving device aligns the phases of the channels based on the detected phase It is characterized by including.

  In one embodiment, the receiving device generates a reference phase signal from the detected phase for each channel, and the receiving device is distributed from the reference phase signal and the master channel for each channel. Detecting a phase difference from the reference phase signal, and the deskew step includes: the receiving device, for each channel, the reference phase signal distributed from the master channel and the reference phase signal; This is a step of aligning the phases of the respective channels on the basis of the phase difference of.

  In another embodiment, the receiving device generates a reference phase signal from the detected phase for each channel, and the receiving device has a predetermined delay in the reference phase signal distributed from the master channel. Generating a reference phase information signal that is given, and a step in which the receiving device detects a phase difference between the reference phase signal and the reference phase information signal for each channel, and the deskew step includes The receiving device is a step of aligning the phases of the channels with reference to the phase difference between the detected reference phase signal and the reference phase information signal.

  In yet another embodiment, the receiving device generates a reference phase signal from the detected phase, and the receiving device generates a reference phase information signal that gives a predetermined delay to the detected phase. The receiving device detects a phase difference between the reference phase signal and the reference phase information signal, and the receiving device is provided for each slave channel that is the remaining of each channel except the master channel, Detecting a phase of a multi-frame counter bit of the received signal of the slave channel, and generating a second reference phase signal from the detected phase of the multi-frame counter bit of the received signal of the slave channel; The receiver detects a phase difference between the second reference phase signal and the reference phase information signal. The deskew step is a step in which the receiving device aligns the phase of each channel with reference to the phase difference between the reference phase signal and the reference phase information signal in the detected master channel. It is characterized by that.

  In yet another embodiment, the receiving device generates a reference phase signal from the detected phase, and the receiving device is configured for each slave channel that is the remainder of each channel except the master channel. Detecting a phase of a multi-frame counter bit of the received signal of the slave channel, and generating a second reference phase signal from the detected phase of the multi-frame counter bit of the received signal of the slave channel; The receiver compares the phase of the second reference phase signal generated in each of the slave channels with the reference phase signal generated in the master channel, and selects the reference phase signal having the longest delay. Distributing to each of the channels; and A step of detecting a phase difference between the reference signal having a large delay and the first or second reference phase signal generated in each channel, wherein the deskew step detects the longest delay detected by the receiver. The phase of each channel is adjusted with reference to the phase difference phase difference between the reference signal having a large value and the first or second reference phase signal generated in each channel.

  In one embodiment, the new overhead may be a synchronous digital hierarchy (SDH) frame overhead or an optical transport network (OTN) frame overhead.

  As described above, according to the present invention, it is possible to provide parallel transfer of data with a simple configuration. Therefore, an application that requires a transmission capacity of the future terabit (Tbit / s) or more and low delay. Can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a network architecture to which the OVC technology is applied. The embodiment of the present invention can be applied to the network architecture shown in FIG. In FIG. 1, the server computer 10 and the supercomputer 20 are shown as a transmission source node or a destination node of large-capacity data transmitted / received via a network. In FIG. 1, a network including an edge node 30 connected to the server computer 10 and the supercomputer 20 and a core node 40 connected to the edge node is shown as a core network. The core node has a multiplexing (ADM: Add / Drop Multiplexer) function for a wavelength division multiplexing (WDM) signal, etc. The edge node implements an embodiment of the present invention described below.

  In FIG. 1, the server computer 10T is described as a large-volume data transmission source node, and the server computer 10R is described as a large-volume data destination node.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram illustrating a configuration of the transmission / reception device 30 including the transmission unit 300 and the reception unit 350 according to the embodiment of the present invention. The transmission unit 300 and the reception unit 350 may be configured separately as a transmission device and a reception device, respectively.

  The transmission unit 300 of the transmission / reception device 30 receives a large amount of data stored in the transmission server 10T in parallel, frames each of the received data, modulates it to a predetermined wavelength, and modulates a plurality of modulated wavelengths. Transfer channels in parallel. The number of divisions (n: an integer of 2 or more) is the same as the number of channels to be transferred in parallel.

  Referring to FIG. 3, the transmission unit 300 (or the transmission device) is an optical / electrical conversion as a data reception unit that receives in parallel data (also referred to as divided data in this specification) divided from the transmission server 10T. (O / E) circuit 312-k (k: integer between 1 and n) and a serial / parallel conversion (S / P) circuit that converts a serial signal output from O / E circuit 312-k into a parallel signal 314-k, a frame addition circuit 316-k that frames the parallel signal output from the S / P circuit 314-k, a multi-frame synchronization circuit 330 that supplies a control signal to n frame addition circuits, A parallel / serial conversion (P / S) circuit 318-k that converts a frame signal, which is a parallel signal output from the additional circuit 316-k, into a serial signal, and a P / S conversion An optical / optical conversion (E / O) circuit 320-k that converts a frame signal converted into a serial signal into an optical signal in a path 318-k, and an optical signal having a plurality of wavelengths modulated by the frame signal; And a wavelength division multiplexing (MUX) circuit 340 for transferring to the core network. The number n of sets including the O / E circuit 312-k, the S / P circuit 314-k, the frame addition circuit 316-k, the P / S circuit 318-k, and the E / O circuit 310-k is determined by the transmission server 10T. It is configured to be equal to the number of divisions of large-capacity data, and the division data input for each set is converted into a frame signal, modulated to a corresponding wavelength channel, and transferred.

  Further, the receiving unit 350 (or receiving device) receives a wavelength-multiplexed optical signal from the core network, and wavelength-separates it into optical signals of a plurality of wavelengths each of which is modulated by a frame signal (DEMUX). 360, an optical / electrical conversion circuit (O / E) 372-k that converts each optical signal having a plurality of wavelengths into an electrical signal and outputs a frame signal, and an output from the optical / electrical conversion circuit (O / E) A phase adjustment circuit 374-k that adjusts the phase of each of the frame signals, and a frame termination circuit 376 that terminates the frame signal whose phase has been adjusted by the phase adjustment circuit 374-k and extracts the divided data stored in the frame -K, a parallel / serial conversion circuit (P / S) 378-k that converts the divided data that is parallel signals into serial signals, and the amount converted into serial signals It converts the data into an optical signal, an electrical / optical conversion circuit for transferring to the receiving server 10R (E / O) and a 380-k. The number n of sets including the O / E circuit 372-k, the phase adjustment circuit 374-k, the frame termination circuit 376-k, the P / S circuit 378-k, and the O / E circuit 380-k is received from the core network. It is configured to be equal to the number of wavelength channels multiplexed in the wavelength multiplexed signal (that is, the number of divisions of large-capacity data), and divided data is extracted from the wavelength channels input for each set and transferred to the receiving server 10R. Has been.

  In the above configuration, each frame addition circuit 316 of the transmission unit 300 generates a frame signal by adding new overhead to the divided data. At that time, each frame adding circuit 316 generates the frame signals of the respective channels in synchronism with each other by the control signal from the multi-frame synchronizing circuit 330, that is, with the phases aligned. For example, the multi-frame synchronization circuit 330 and the frame addition circuits 316-1 to 316 -n are connected by equal-length wiring, and the multi-frame synchronization circuit 330 indicates the timing of framing to the frame addition circuits 316-1 to 316 -n. A synchronization control signal (shown as a multiframe synchronization signal in FIG. 2) is supplied, and the frame addition circuits 316-1 to 316-n add new overhead to the divided data in response to reception of the synchronization control signal. N frame signals having the same phase are generated.

  Next, a processing flow in the transmission unit 300 will be described. The large-capacity data 50 (FIG. 1) of the transmission server 10T is, for example, blocked by 64B / 66B code or 512B / 514B code, and transmitted almost simultaneously in parallel by round robin as divided data (51 to 53). Received at 300. The 64B / 66B code is a block in which 2-bit header information is added to 64-bit user information or control information. Similarly, the 512B / 514B code is a block in which 2-bit header information is added to 512-bit user information or control information. Since the 64B / 66B code and the 512B / 514B code are well known to those skilled in the art, a detailed description thereof will be omitted.

  Each of the plurality of divided data received in parallel by the transmitting unit 300 is converted from a serial signal to a parallel signal for each divided data by the S / P circuit 314 and supplied to the frame adding circuit 316, and the FIFO memory in the frame adding circuit Is remembered.

  Each of the frame addition circuits 316 reads one or a plurality of divided data from the FIFO memory in response to a synchronization control signal (multiframe synchronization signal) from the multiframe synchronization circuit 330, adds a new overhead, and outputs it.

  A multi-frame counter bit is defined in a new overhead (a position known to the receiving unit 350) added to data by each frame addition circuit 316, and the frame addition circuits 316-1 to 316 -n respectively serve as multi-frame counter bits. 1 to p (2 ≦ p ≦ (an integer satisfying the maximum value that can be counted by a new overhead multiframe counter bit)) is entered, and the length obtained by concatenating p frames is defined as one frame (this specification) (Also referred to as multi-frame in the book) (Fig. 2). Each data signal (that is, a frame signal) to which a new overhead is added is converted into an optical signal having a corresponding wavelength and transmitted to the network. Each wavelength channel may be wavelength-multiplexed by the MUX circuit 340 and pass through the same path, or may pass through a different path for each wavelength channel.

  Next, a processing flow in the receiving unit 350 will be described. Each wavelength channel transmitted from the transmission unit 300 is optical / electrically converted in the E / O circuit 372 of the reception unit 350 and supplied to the corresponding phase adjustment circuit 374. When each wavelength channel is wavelength-multiplexed and transmitted in the transmission unit 300, the wavelength is separated in the DMUX circuit 360 and then electrically converted in the E / O circuit 372 of the reception unit 350.

  The phase adjustment circuit 374 detects the position of the multi-frame counter bit added to the known position of the new overhead in each transmission unit. Each channel is affected by the delay difference due to the characteristics of the transmission medium such as group velocity dispersion and polarization dispersion, and the delay difference due to the inherent deviation of the circuit components. The delay difference is the phase difference of the multi-frame counter bits detected at the receiver. Appears as Therefore, if the delay for each channel is adjusted (deskewed) so that the positions of the multiframe counter bits of each channel are aligned based on the position of the detected multiframe counter bits, the phases of the channels can be aligned. The phase adjustment circuits 374-1 to 374-n collectively operate as a deskew function unit, whereby the phases of the respective channels can be aligned. The deskew function unit will be described later.

  The frame signal having the same phase is terminated (removed) by the new overhead added by the transmission unit in the frame termination circuit 376-1, converted into a serial signal, modulated into an optical signal, and transferred to the receiving server 10R. The

  The receiving server 10R can restore the original large-capacity data by combining the divided data received via each channel. Here, the new overhead may be, for example, a Synchronous Digital Hierarchy (SDH) frame overhead or an optical transport network (OTN) frame overhead.

(Second embodiment)
A second embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. 4 shows a block configuration of the deskew function unit 400 of this embodiment. 4 is the phase adjustment circuit 374-1 in FIG. 3, and the phase adjustment circuits 410-1 to 410- (n−1) in FIG. 4 are the phase adjustment circuit 374 in FIG. 2 to 374-n, respectively.

  As shown in FIG. 4, in this embodiment, by measuring the delay amount of each wavelength channel in advance, the channel with the largest delay among the plurality of wavelength channels is defined as the master channel, and the remaining channels are defined. Assume that a channel is defined as a slave channel.

  Referring to FIG. 4, the phase adjustment circuit 410-k detects the phase of a multiframe counter bit from the electrical signal converted in the E / O circuit 372-k, and outputs a reference phase signal MFP (Multi Frame Pulse) A phase detection circuit 412-k, a phase absorption FIFO memory 414-k for storing an electrical signal converted in the E / O circuit 372-k via the MFP phase detection circuit, and an MFP phase detection circuit 412-n for the master channel The output timing of the electrical signal (frame signal) stored in the phase absorption FIFO memory 414-k is controlled based on the reference phase signal output from and distributed and the reference phase signal output from the MFP phase detection circuit 412-k. And a phase difference detection circuit 416-k for supplying a control signal to the phase absorption FIFO memory 414-k. The wiring connecting the MFP phase detection circuit 412-k and the phase difference detection circuit 416-k is the same length regardless of k. Further, the reference phase signal distributed from the MFP phase detection circuit 412-n corresponding to the master channel to the phase detection circuit 416-k is distributed via the equal-length wiring and is connected to the MFP phase detection circuit 412-k. It is configured to be longer than the wiring length connecting the phase difference detection circuit 416-k (for the phase detection circuit 416-n, the reference phase signal from the MFP phase detection circuit 412-n has two different lengths). Supplied through one wiring.)

  The MFP phase detection circuit 412-k detects, for example, the rising edge of the pulse corresponding to the multiframe counter bit given to a known position in the new overhead, so that the phase of the multiframe counter bit (ie, the multiframe counter bit) is detected. Is detected and the reference phase signal is output.

  The phase difference detection circuit 416-k is based on the reference phase signal output from the master channel MFP phase detection circuit 412-n and the reference phase signal output from the MFP phase detection circuit 412-k. The phase difference absorption amount at -k is determined, and the determined phase difference absorption amount is supplied to the phase absorption FIFO memory 414-k as a control signal. That is, the phase difference detection circuit 416-k can know the relative delay difference of the channel k when the phase detected by the MFP phase detection circuit 412-n of the master channel is used as a reference.

  FIG. 5 is a diagram for explaining the operation of the skew function unit 400. In FIG. 5, channel n is defined as the master channel. Also, two reference phase signals input to the phase difference detection circuit 416 are shown as inputs 1 and 2, respectively. For example, input 1 in channel 1 defined as a slave channel is a reference phase signal output from MFP phase detection circuit 412-1. The input 2 in the channel 1 defined as the slave channel is a reference phase signal distributed from the MFP phase detection circuit 412 -n of the channel defined as the master channel, and the phase difference absorbed by the phase absorption FIFO memory 414 This is a reference point for determining the quantity. The phase difference absorbed in the phase absorption FIFO memory 414 of each channel is shown as a phase difference absorption amount.

  The phase absorption FIFO memory 414-k outputs a signal stored therein at a timing delayed by the supplied phase difference absorption amount. That is, the phase absorption FIFO memory 414-k reads the signal at a timing delayed by the number of write / read clocks corresponding to the phase absorption amount supplied from the timing at which the signal was written.

  Therefore, each channel adjusts the delay amount when reading the data signal in the phase absorption FIFO memories 410-1 to 410-k based on the phase difference detected by the phase difference detection circuits 416-1 to 416-n, respectively. Thus, the phases between the channels are aligned and transferred in synchronization.

(Third embodiment)
The third embodiment of the present invention will be described with reference to FIGS. FIG. 6 shows a block configuration of the deskew function unit 600 of this embodiment. Phase adjustment circuits 610-1 to 610-n shown in FIG. 6 correspond to the phase adjustment circuits 374-1 to 374-n of FIG.

  As shown in FIG. 6, in the present embodiment, it is assumed that any one channel 1 among the plurality of wavelength channels is defined as a master channel, and the remaining channels 2 to n are defined as slave channels. .

  Referring to FIG. 6, the phase adjustment circuit 610-k detects the phase of the multiframe counter bit from the electrical signal converted in the E / O circuit 372-k, and outputs a reference phase signal. k, the phase absorption FIFO memory 614-k for storing the electrical signal converted in the E / O circuit 372-k via the MFP phase detection circuit, and the master channel MFP phase detection circuit 612-1 for output and distribution. A delay adjustment circuit 618-k for outputting a reference phase information signal obtained by giving a predetermined delay adjustment amount to the reference phase signal, a reference phase information signal output from the delay adjustment circuit 618-k, and an MFP phase detection circuit 612-k Of the electrical signal (frame signal) stored in the phase absorption FIFO memory 614-k based on the reference phase signal output from A control signal for controlling the timing and a phase difference detecting circuit 616-k is supplied to the phase absorption FIFO memories 614-k. The wirings connecting the MFP phase detection circuit 612-k and the phase difference detection circuit 616-k have the same length regardless of k. Further, the reference phase signal distributed from the MFP phase detection circuit 612-1 corresponding to the master channel to the delay adjustment circuit 618-k is configured to be distributed through the equal length wiring. Furthermore, the wiring connecting the delay adjustment circuit 618-k and the phase detection circuit 616-k has the same length regardless of k.

  The MFP phase detection circuit 612-k detects the phase of the multi-frame counter bit and outputs a reference phase signal in the same manner as the MFP phase detection circuit 412-k.

  The delay adjustment circuit 618-k has a predetermined delay adjustment amount, that is, the phase of the reference phase information signal detected by the MFP phase detection circuit 612-k of each channel (input 2 in FIG. 7) (FIG. 7). 1) The delay adjustment amount that is slower than any one (however, the same delay adjustment amount for all channels is given to the reference phase signal detected by the MFP phase detection circuit 612-k to obtain the reference phase information signal). The delay adjustment amount set in the delay adjustment circuit 618-k is set in advance by predicting or actually measuring the delay difference of the transmission path and the difference in path length from the optical characteristics of the fiber and the network configuration.

  The phase difference detection circuit 616-k is provided in the phase absorption FIFO memory 614-k based on the reference phase information signal output from the delay adjustment circuit 618-k and the reference phase signal output from the MFP phase detection circuit 612-k. The phase difference absorption amount is determined, and the determined phase difference absorption amount is supplied as a control signal to the phase absorption FIFO memory 614-k. That is, the phase difference detection circuit 616-k can know the relative delay difference of the channel k when the phase detected by the MFP phase detection circuit 412-n of the master channel is used as a reference, and the phase absorption FIFO memory. A reference point (Reference Point) for determining the amount of phase difference absorbed at 614-k can be determined.

  FIG. 7 is a diagram for explaining the operation of the skew function unit 600. In FIG. 7, channel 1 is defined as the master channel. Further, the reference phase signal input to the phase difference detection circuit 616 is indicated as input 1, and the reference phase information signal input to the phase difference detection circuit 616 is indicated as input 2. For example, input 1 in channel 2 defined as a slave channel is a reference phase signal output from MFP phase detection circuit 612-2, and input 2 is channel 1 defined as a master channel in delay adjustment circuit 618-2. The reference phase information signal is output by giving a predetermined delay adjustment amount to the reference phase signal distributed from the MFP phase detection circuit 612-1. The phase difference absorbed in the phase absorption FIFO memory 614 of each channel is shown as a phase difference absorption amount.

  Similarly to the phase absorption FIFO memory 414-k, the phase absorption FIFO memory 614-k outputs a signal stored therein at a timing delayed by the supplied phase difference absorption amount.

  Therefore, each channel adjusts the delay amount when reading the data signal in the phase absorption FIFO memories 610-1 to 610-k based on the phase difference detected by the phase difference detection circuits 616-1 to 616-n, respectively. Thus, the phases between the channels are aligned and transferred in synchronization.

(Fourth embodiment)
With reference to FIG. 8 and FIG. 9, a fourth embodiment of the present invention will be described. FIG. 8 shows a block configuration of the deskew function unit 800 of the present embodiment. Phase adjustment circuits 810-1 to 810-n shown in FIG. 8 respectively correspond to the phase adjustment circuits 374-1 to 374-n of FIG. 3.

  As shown in FIG. 8, in this embodiment, it is assumed that any one channel 1 among the plurality of wavelength channels is defined as a master channel, and the remaining channels 2 to n are defined as slave channels. .

  Referring to FIG. 8, the phase adjustment circuit 810-1 (k = 1) detects the phase of the multi-frame counter bit from the electrical signal converted in the E / O circuit 372-1 and outputs a reference phase signal. The phase detection circuit 812-1, the phase absorption FIFO memory 814-1 for storing the electrical signal converted in the E / O circuit 372-1 via the MFP phase detection circuit, and the MFP phase detection circuit 812-1 are output. A delay adjustment circuit 818 for outputting a reference phase information signal obtained by giving a predetermined delay adjustment amount to the distributed reference phase signal, a reference phase information signal output from the delay adjustment circuit 818, and an output from the MFP phase detection circuit 812-1 The output timing of the electrical signal (frame signal) stored in the phase absorption FIFO memory 814-1 is controlled based on the reference phase signal That includes a phase difference detecting circuit 816-1 supplies the phase absorption FIFO memory 814-1 control signal.

  The phase adjustment circuit 810-k (k ≠ 1) detects the phase of the multiframe counter bit from the electrical signal converted in the E / O circuit 372-k and outputs a reference phase signal. -K, a phase absorption FIFO memory 814-k for storing an electrical signal converted in the E / O circuit 372-k via the MFP phase detection circuit, and a reference outputted and distributed from the delay adjustment circuit 818 of the master channel Based on the phase information signal and the reference phase signal output from the MFP phase detection circuit 812-k, the phase absorption of the control signal for controlling the output timing of the electrical signal (frame signal) stored in the phase absorption FIFO memory 814-k And a phase difference detection circuit 816-k for supplying to the FIFO memory 814-k.

  The wirings connecting the MFP phase detection circuit 812-k (hereinafter, k = 1 to n) and the phase difference detection circuit 816-k are equal in length regardless of k. Also, the wiring connecting the delay adjustment circuit 818 of the master channel and the phase detection circuit 816-k has the same length regardless of k.

  The MFP phase detection circuit 812-k detects the phase of the multiframe counter bit and outputs a reference phase signal, as in the MFP phase detection circuit 412-k.

  Similarly to the delay adjustment circuit 618-1, the delay adjustment circuit 818 gives a predetermined delay adjustment amount to the reference phase signal detected by the MFP phase detection circuit 812-1 and outputs a reference phase information signal. The output reference phase information signal is distributed to the phase detection circuit 816-k. The delay adjustment amount set in the delay adjustment circuit 818 predicts or actually measures the delay difference and path length difference of the transmission path from the optical characteristics of the fiber and the network configuration, and the reference phase information signal is the reference of all other channels. It is set in advance so as to be slower than the phase signal.

  The phase difference detection circuit 816-k is configured to output a phase difference in the phase absorption FIFO memory 814-k based on the reference phase information signal output from the delay adjustment circuit 818 and the reference phase signal output from the MFP phase detection circuit 812-k. The absorption amount is determined, and the determined phase difference absorption amount is supplied to the phase absorption FIFO memory 814-k as a control signal.

  FIG. 9 is a diagram for explaining the operation of the skew function unit 800. In FIG. 9, channel 1 is defined as the master channel. Further, a reference phase signal input to the phase difference detection circuit 816 is indicated as input 1, and a reference phase information signal input to the phase difference detection circuit 816 is indicated as input 2. For example, input 1 in channel 2 defined as a slave channel is a reference phase signal output from MFP phase detection circuit 812-2, and input 2 is output from MFP phase detection circuit 812-1 in delay adjustment circuit 818. The reference phase information signal is output and distributed by giving a predetermined delay adjustment amount to the reference phase signal. The input 2 is at a position delayed from the output of the reference phase information signal in the delay adjustment circuit 818 by a time interval required for distribution. The phase difference absorbed in the phase absorption FIFO memory 814 of each channel is shown as a phase difference absorption amount.

  Similarly to the phase absorption FIFO memory 414-k, the phase absorption FIFO memory 814-k outputs a signal stored therein at a timing delayed by the supplied phase difference absorption amount.

  Therefore, each channel adjusts the delay amount when reading out the data signal in the phase absorption FIFO memories 814-1 to 814-k based on the phase difference detected by the phase difference detection circuits 816-1 to 816-n. Thus, the phases between the channels are aligned and transferred in synchronization.

(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIGS. 10 and 11. FIG. 10 shows a block configuration of the deskew function unit 1000 of this embodiment. Phase adjustment circuits 1010-1 to 1010-n illustrated in FIG. 10 correspond to the phase adjustment circuits 374-1 to 374-n illustrated in FIG.

  As shown in FIG. 10, in the present embodiment, it is assumed that any one channel 1 among a plurality of wavelength channels is defined as a master channel, and the remaining channels 2 to n are defined as slave channels. .

  Referring to FIG. 10, the phase adjustment circuit 1010-1 (k = 1) detects the phase of the multiframe counter bit from the electrical signal converted in the E / O circuit 372-1 and outputs a reference phase signal. A phase detection circuit 1012-1, a phase absorption FIFO memory 1014-1 for storing an electrical signal converted in the E / O circuit 372-1 via the MFP phase detection circuit, and an MFP phase detection circuit 1012-k (k = , N), a reference signal selector circuit 1018 that selects and outputs the reference phase signal having the longest delay from the reference phase signals output from 1, 2,..., N), and the most output and distributed reference signal selector circuit 1018. A phase absorption FIFO memory based on the reference phase signal having a large delay and the reference phase signal output from the MFP phase detection circuit 1012-1 And a phase difference detecting circuit 1016-1 is supplied to the phase absorption FIFO memories 1014-1 a control signal for controlling the output timing of 014-1 on the stored electrical signal (frame signal).

  The phase adjustment circuit 1010-k (k ≠ 1) detects the phase of the multiframe counter bit from the electrical signal converted in the E / O circuit 372-k and outputs a reference phase signal. -K, a phase absorption FIFO memory 1014-k for storing an electrical signal converted in the E / O circuit 372-k via the MFP phase detection circuit, and a reference signal selector circuit 1018 for the master channel. Control for controlling the output timing of the electrical signal (frame signal) stored in the phase absorption FIFO memory 1014-k based on the reference phase signal having the largest delay and the reference phase signal output from the MFP phase detection circuit 1012-k. A phase difference detection circuit 1016-k for supplying a signal to the phase absorption FIFO memory 1014-k That. Wirings connecting the MFP phase detection circuit 1012-k (hereinafter, k = 1 to n) and the phase difference detection circuit 1016-k have the same length regardless of k. Also, the wiring connecting the reference signal selector circuit 1018 for the master channel and the phase difference detection circuit 1016-k for each channel is the same length regardless of k.

  The MFP phase detection circuit 1012-k detects the phase of the multiframe counter bit and outputs a reference phase signal in the same manner as the MFP phase detection circuit 1012-k.

  The reference signal selector circuit 1018 selects and outputs the reference signal with the longest delay from the reference phase signals output from the MFP phase detection circuit 1012-k (k = 1, 2,..., N). The outputted reference signal with the longest delay is distributed to the phase difference detection circuit 1016-k.

  Similarly to the phase difference detection circuit 416-k, the phase difference detection circuit 1016-k outputs the reference phase signal having the longest delay output from the reference signal selector circuit 1018 and the reference phase output from the MFP phase detection circuit 812-k. Based on the signal, the phase difference absorption amount in the phase absorption FIFO memory 1014-k is determined, and the determined phase difference absorption amount is supplied to the phase absorption FIFO memory 1014-k as a control signal.

  FIG. 11 is a diagram for explaining the operation of the skew function unit 1000. In FIG. 11, channel 1 is defined as the master channel. Also, FIG. 11 shows a plurality of reference phase signals input to the master channel reference signal selector circuit 1018, and the reference phase signal of channel 2 defined as slave 2 is the reference phase signal with the longest delay. The state of being selected and distributed to the phase detection circuit 1016-k of each channel is shown. Further, the reference phase signal input from the MFP phase detection circuit 1012-k to the phase difference detection circuit 1016-k is indicated as input 1, and the most delayed input from the reference signal selector circuit 1018 to the phase difference detection circuit 1016-k. A large reference phase signal is shown as input 2. For example, input 1 in channel 2 defined as a slave channel is a reference phase signal output from MFP phase detection circuit 1012-2, and input 2 is output from reference signal selector circuit 1018 and has the longest delay distributed. Reference phase signal. The input 2 is at a position delayed by a time interval required for processing and distribution in the reference signal selector circuit 1018. The phase difference absorbed in the phase absorption FIFO memory 1014 of each channel is shown as a phase difference absorption amount.

  Similarly to the phase absorption FIFO memory 414-k, the phase absorption FIFO memory 1014-k outputs a signal stored therein at a timing delayed by the supplied phase difference absorption amount.

  Therefore, each channel adjusts the delay amount when reading the data signal in the phase absorption FIFO memories 1014-1 to 1014-k based on the phase differences detected by the phase difference detection circuits 1016-1 to 1016 -n, respectively. Thus, the phases between the channels are aligned and transferred in synchronization.

(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIGS. If the delay difference between the channels becomes large and exceeds half of the multiframe period, it becomes difficult to identify the context of the delay difference between the channels. FIG. 12 shows the time relationship of the reference phase signal when the delay difference between the channels does not exceed 1/2 of the multiframe period. As shown in FIG. 12, the m-th reference phase signal of the master channel is compared with the m-th reference phase signal of the slave channel, so that a delay difference between the channels is detected, and the phase between each channel is appropriately adjusted accordingly. Can be aligned.

  On the other hand, FIG. 13 shows an example when the phase difference between channels exceeds 1/2 of the multiframe period. In FIG. 13, since the delay difference between the master channel and the slave channel exceeds a ½ frame period, the m−1th reference phase signal of the master channel and the mth reference phase signal of the slave channel are mistakenly generated. Will be compared. In the case of the example shown in FIG. 13, the phase difference is detected to be smaller than the actual delay difference, and when the delay amount of each channel signal is adjusted by the phase absorption FIFO memory according to the erroneously detected phase difference, The m−1th multiframe of the channel is adjusted in phase, and is synchronized with the mth multiframe of the slave channel shifted by one frame. In order to avoid the erroneous detection of the delay amount between channels as shown in FIG. 13, the delay difference between channels should not exceed 1/2 of the multiframe period. What is necessary is just to be able to make a frame period more than twice as long as it.

  FIG. 14 shows H4 byte coding standardized as SDH (ITU-T G.707). In SDH, a multiframe is a combination of 4 bits 5 to 8 of multiframe MFI1 (Multiframe Indicator-1) and a total of 8 bits including bits 1 to 4 of two adjacent MFI2s, which are bits 1 to 8. It is a counter. Specifically, MFI1 and MFI2 bits are incremented from 0 to 15 for each frame from 0 to 15 from the state that all bits of MFI1 and MFI2 are 0, and MFI2 is incremented by 1 in the next frame that becomes 15. At the same time, MFI1 is returned to zero. Since MFI2 is 8 bits long, it can be added from 0 to 255. Therefore, by combining MFI1 and MFI2, it is possible to count up to 16 x 256 = 4096 frames. If this is 1 multiframe, 1 frame is 125 microseconds, so 1 multi The maximum frame period is 4096 (frames) × 125 (microseconds) = 512 milliseconds. Therefore, according to the present embodiment, it is possible to cope with a delay difference between channels of 256 milliseconds which is 1/2 of 512 milliseconds.

  In the above, an example using standardized overhead bytes has been explained, but undefined overhead may be used as a counter, or a longer multiframe may be configured by combining standardized bytes and undefined bytes. good.

(Seventh embodiment)
A seventh embodiment of the present invention will be described with reference to FIGS. As described above in the sixth embodiment, the longer the multiframe period, the larger the phase difference between channels that can be handled.

  15 shows an OTUk (Optical Transport Unit-k) frame structure standardized as OTN (ITU-T G.709), FIG. 16 shows an OPUk-Xv (Optical channel Payload Unit-k Xv) frame structure, and FIG. Indicates an OPUk-Xv overhead structure. FIG. 17 shows a specific allocation method for the 15th column, VCOH (Virtual Concatenation Overhead) in the first to third rows, and PSI (Payload Structure Identifier) in the fourth row in the frame structure of FIG. Counting from 0 to 255 using 8 bits of bits 1 to 8 of the MFAS byte in the seventh row and first column of FIG. By combining this with a count from 0 to 65535 using 16 bits that are a combination of MFI1 and MFI2 defined in VCOH1 in the 15th row and 1st column of FIG. 17, 256 × 65536 = 16777216 frame length is 1 It can be handled as a multi-frame. Assuming a transmission rate of 40 Gbps (ODU3), one frame is about 3 microseconds, so one multiframe is a maximum of 3 (microseconds) × 16777216 (frames) = 50.331648 seconds. Therefore, according to the present embodiment, it is possible to cope with a delay difference between channels of about 25.1 seconds, which is 1/2 of 50.3 seconds.

  In the above, an example using standardized overhead bytes has been explained, but undefined overhead may be used as a counter, or a longer multiframe may be configured by combining standardized bytes and undefined bytes. good.

It is a figure which shows the network architecture to which OVC technique is applied. It is a figure which shows the multi-frame structure in one Embodiment of this invention. 1 shows a configuration of a transmission / reception device according to an embodiment of the present invention. It is a figure which shows the structure of the deskew function part concerning one Embodiment of this invention. It is a figure for demonstrating operation | movement of the deskew function part concerning one Embodiment of this invention. It is a figure which shows the structure of the deskew function part concerning one Embodiment of this invention. It is a figure for demonstrating operation | movement of the deskew function part concerning one Embodiment of this invention. It is a figure which shows the structure of the deskew function part concerning one Embodiment of this invention. It is a figure for demonstrating operation | movement of the deskew function part concerning one Embodiment of this invention. It is a figure which shows the structure of the deskew function part concerning one Embodiment of this invention. It is a figure for demonstrating operation | movement of the deskew function part concerning one Embodiment of this invention. It is a figure for demonstrating the multi-frame phase difference detection concerning one Embodiment of this invention. It is a figure for demonstrating the multi-frame phase difference detection concerning one Embodiment of this invention. It is a figure which shows the SDH overheader which sets a multi-frame counter bit in one Embodiment of this invention. It is a figure which shows the frame structure of the OTUk frame which sets a multi-frame counter bit in one Embodiment of this invention. It is a figure which shows the frame structure of the OPUk-Xv frame which sets a multi-frame counter bit in one Embodiment of this invention. It is a figure which shows the structure of the OPUk-Xv overhead of the OPU frame which sets a multi-frame counter bit in one Embodiment of invention.

Explanation of symbols

300 Transmitter, Transmitter 316 Frame Addition Circuit 330 Multiframe Synchronous Circuit 350 Receiver, Receiver 374, 410, 610, 810, 1010 Phase Adjustment Circuit 380, 400, 600, 800, 1000 Deskew Function Unit

Claims (12)

In a transmission system that includes a transmitter and a receiver and divides data into a plurality of channels for parallel transmission,
The transmitter is
A multi-frame synchronization circuit for supplying a synchronization signal to each channel;
A frame addition circuit that synchronizes and generates a new overhead having a multiframe counter bit triggered by a synchronization signal from the multiframe synchronization circuit,
The receiving device is:
One of the transmitted channels is defined as a master channel, and a deskew function unit is provided that aligns the phases of the channels with reference to the phase generated from the multiframe counter bits. Transmission system. The deskew function unit includes:
For each channel,
A multi-frame pulse phase detection circuit that generates a reference phase signal from the phase of the multi-frame counter bit of the received signal;
A phase difference detection circuit for detecting a phase difference between the reference phase signal and the reference phase signal distributed from the master channel;
The transmission system according to claim 1, further comprising: a phase difference absorption FIFO memory that adjusts a phase of the channel according to a phase difference detected by the phase difference detection circuit. The deskew function unit includes:
For each channel,
A multi-frame pulse phase detection circuit that generates a reference phase signal from the phase of the multi-frame counter bit of the received signal;
A delay adjustment circuit that generates a reference phase information signal obtained by giving a predetermined delay to the reference phase signal distributed from the master channel;
A phase difference detection circuit for detecting a phase difference between the reference phase signal and the reference phase information signal;
The transmission system according to claim 1, further comprising: a phase difference absorption FIFO memory that adjusts a phase of the channel according to a phase difference detected by the phase difference detection circuit. In the deskew function unit,
Define the rest of each channel except the master channel as a slave channel,
The master channel is
A multi-frame pulse phase detection circuit that generates a reference phase signal from the phase of the multi-frame counter bit of the reception signal of the master channel;
A delay adjusting circuit that generates a reference phase information signal obtained by giving a predetermined delay to the reference phase signal generated by the master channel;
A phase difference detection circuit for detecting a phase difference between the reference phase signal and the reference phase information signal;
A phase difference absorption FIFO memory that adjusts the phase of the channel according to the phase difference detected by the phase difference detection circuit, and the slave channel for each channel,
A second multi-frame pulse phase detection circuit for generating a second reference phase signal from the phase of the multi-frame counter bit of the received signal of the slave channel;
A second phase difference detection circuit for detecting a phase difference between the second reference phase signal and the reference phase information signal;
A second phase difference absorption FIFO memory that adjusts the phase of the channel according to the phase difference detected by the second phase difference detection circuit;
The transmission system according to claim 1, further comprising: In the deskew function unit,
Define the rest of each channel except the master channel as a slave channel,
The master channel is
A multi-frame pulse phase detection circuit that generates a reference phase signal from the phase of the multi-frame counter bit of the received signal,
The slave channel is for each channel,
A second multi-frame pulse phase detection circuit that generates a second reference phase signal from the phase of the multi-frame counter bit of the received signal and transmits the second reference phase signal to the master channel;
The second reference phase signal generated in each of the slave channels is compared with the reference phase signal generated in the master channel, and the reference phase signal having the longest delay is selected and distributed to each channel. A reference signal selector circuit;
Each channel is
A phase detection circuit for detecting a phase difference between the reference signal having the longest delay distributed from the master channel and the first or second reference phase signal generated in each channel;
The transmission system according to claim 1, further comprising: a phase difference absorption FIFO memory that adjusts a phase of the channel according to a phase difference detected by the phase difference detection circuit.   6. The transmission system according to claim 1, wherein the new overhead is an overhead of a synchronous digital hierarchical frame.   The transmission system according to claim 1, wherein the new overhead is an overhead of an optical transport network frame. In a transmission method in which data is divided into a plurality of channels and transmitted in parallel in a transmission system including a transmission device and a reception device,
The transmission apparatus includes a multi-frame synchronization circuit for supplying a synchronization signal to each channel, and generates a new overhead having a multi-frame counter bit in synchronization with the synchronization signal from the multi-frame synchronization circuit as a trigger; ,
Detecting the phase of the multi-frame counter bit of a signal received by one of the channels defined as a master channel by the receiving device;
And a deskew step in which the receiving apparatus aligns the phases of the channels with the detected phase as a reference. The receiving device generating a reference phase signal from the detected phase for each channel;
The receiving apparatus further comprises: detecting, for each channel, a phase difference between the reference phase signal and the reference phase signal distributed from the master channel, and the deskew step includes: 9. The transmission according to claim 8, wherein, for each channel, the phase of each channel is aligned based on a phase difference between the reference phase signal and the reference phase signal distributed from the master channel. Method. The receiving device generating a reference phase signal from the detected phase for each channel;
The receiver generates a reference phase information signal obtained by giving a predetermined delay to the reference phase signal distributed from the master channel;
The receiving apparatus further includes detecting a phase difference between the reference phase signal and the reference phase information signal for each channel;
9. The deskew step is a step in which the receiving device aligns the phases of the respective channels with reference to a phase difference between the detected reference phase signal and the reference phase information signal. Transmission method. The receiver generates a reference phase signal from the detected phase;
The receiver generates a reference phase information signal in which a predetermined delay is given to the detected phase;
The receiver detects a phase difference between the reference phase signal and the reference phase information signal;
The receiving device detecting a phase of a multi-frame counter bit of a received signal of the slave channel for each slave channel that is the remaining of each channel except the master channel; and
The receiver generates a second reference phase signal from the phase of the detected multi-frame counter bit of the received signal of the slave channel;
The receiver further includes detecting a phase difference between the second reference phase signal and the reference phase information signal;
The deskew step is a step in which the receiving apparatus aligns the phases of the channels with reference to a phase difference between the reference phase signal and the reference phase information signal in the detected master channel. Item 9. The transmission method according to Item 8. The receiver generates a reference phase signal from the detected phase;
The receiving device detecting a phase of a multi-frame counter bit of a received signal of the slave channel for each slave channel that is the remaining of each channel except the master channel; and
The receiver generates a second reference phase signal from the phase of the detected multi-frame counter bit of the received signal of the slave channel;
The receiver compares the phase of the second reference phase signal generated in each of the slave channels with the reference phase signal generated in the master channel, selects the reference phase signal having the largest delay, and Distributing to each channel;
The receiver further comprising, for each channel, detecting a phase difference between the reference signal having the longest delay and the first or second reference phase signal generated in each channel;
In the deskew step, the receiving device uses the phase difference phase difference between the detected reference signal having the longest delay and the first or second reference phase signal generated in each channel as a reference. The transmission method according to claim 8, wherein the phase is adjusted.

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