JP2010015233A - Integrated circuit and electronic apparatus - Google Patents

Abstract

An integrated circuit suitable for a multifunctional electronic device to which a peripheral device as an interface is connected.
An integrated circuit in which a main processing unit and a peripheral connection port for connecting a peripheral device are connected by an internal bus controls the peripheral connection port, and interrupts and data transfer from the peripheral device connected to the peripheral connection port The main processing unit uses memory resources of the auxiliary processing unit as part of the internal memory space of the main processing unit.
[Selection] Figure 1

Description

  The present invention relates to an integrated circuit and an electronic apparatus in which a main processing unit and a peripheral connection port for connecting a peripheral device are connected by an internal bus.

  With recent rapid progress in digital technology, moving image data and audio data compression / decompression technology and miniaturization of semiconductor integrated circuits, digital television (DTV), digital video recorders (DVR) such as DVD recorders, mobile phones, Video / audio equipment such as video cameras is becoming more sophisticated. The operability of equipment has become more complex with higher functionality. In addition, since the device is required to be smaller and thinner, the area between the frame of the device and the display is small regardless of the size of the device. For this reason, a large number of operation buttons as input interfaces cannot be arranged on the device.

  In this way, since the input interface such as buttons and keys that can be operated intuitively by the user cannot be sufficiently arranged in the device, it is a guide function or a support function that guides the user how to operate or necessary functions, Realization of a man-machine interface that does not require keys or keys is required.

  In order to realize the above request, for example, a touch panel is provided on the display as a man-machine interface that does not require buttons or keys. In addition, instead of using the buttons to enter the front, back, left, and right directions, tilting the electronic device works in conjunction with that direction, or turning the camera lens on the device downwards causes the camera to enter an idle state or switch off state. In the same manner as a gesture for photographing a subject, switching is performed such that the camera is activated when the camera lens is leveled. Further, a speaker provided in the device for receiving wirelessly transmitted audio data by the wireless headphones is excluded from the device.

  As described above, it is required to combine and integrate various functions in an electronic device, and also to reduce the size and thickness of the device. Furthermore, there is not much space for arranging input interfaces such as buttons and keys on the device in order to realize a reduction in size and thickness of the device. For this reason, utilization of a high-performance graphical user interface (GUI) or an intelligent man-machine interface is expected.

  An object of the present invention is to provide an integrated circuit suitable for a multifunctional electronic device to which a peripheral device as an interface is connected.

  The present invention is an integrated circuit in which a main processing unit and a peripheral connection port for connecting a peripheral device are connected by an internal bus, and controls the peripheral connection port from the peripheral device connected to the peripheral connection port. An auxiliary processing unit that controls the interruption and data transfer of the main processing unit instead of the main processing unit, and the main processing unit uses memory resources of the auxiliary processing unit as a part of the internal memory space of the main processing unit. An integrated circuit to be used is provided.

  The present invention comprises a main processing unit that performs both control of the entire system and media processing, and an auxiliary processing unit that controls interrupts and data transfer from peripheral devices connected to the main processing unit, The auxiliary processing unit includes a data storage unit that stores data transferred from the peripheral device, and provides an integrated circuit that performs intermediate processing on the data stored in the data storage unit and collectively transfers the data to an external memory .

  In the integrated circuit, the data storage unit included in the auxiliary processing unit is accessed as a part of the internal memory of the main processing unit from the main processing unit, and the auxiliary processing unit is the same memory of the data storage unit. In the case where a read access from the main processing unit and a write access from the auxiliary processing unit occur simultaneously with respect to the address, when an operation corresponding to the write access from the auxiliary processing unit is awaited, the main processing A flag register that informs the main processing unit that an update occurs in a part of data read by the unit, and the auxiliary processing unit is configured to read the main processing unit during or after the main processing unit. Is processed with respect to the main processing unit so as to match the coherency of the data read.

  In the integrated circuit, when the main processing unit is in an idle state, supply of a clock to the main processing unit is stopped, the power supply voltage of the main processing unit is stepped down, and the auxiliary processing unit is connected to the main processing unit. In the idle state, an interrupt or data input from the peripheral device or a data output process to the peripheral device is performed without going through the main processing unit.

  In the integrated circuit, the auxiliary processing unit operates at an operating frequency lower than the operating frequency of the main processing unit or operates in an asynchronous mode.

  In the integrated circuit, the operating frequency of the auxiliary processing unit is changed for each processing mode or operating condition, and the auxiliary processing unit operates in an asynchronous mode.

  In the integrated circuit, when the main processing unit is in an idle state, the auxiliary processing unit operates in the asynchronous mode.

  In the integrated circuit, data input from the peripheral device is captured by the auxiliary processing unit, and the auxiliary processing unit compares the captured data with the data stored in the data storage unit in the past, When the difference in data amount is less than or equal to a predetermined value, the captured data is not stored in the data storage unit, and when the difference in data amount is greater than the predetermined value, the captured data is stored in the data Accumulate in the accumulator.

  In the integrated circuit, the auxiliary processing unit increases the operating frequency stepwise when the frequency of data capture from the peripheral device is greater than a predetermined value, and when the data storage size of the data storage unit exceeds a predetermined value, Data is collectively transferred to the external memory, and the main processing unit is notified that the data has been transferred to the external memory.

  The present invention provides an electronic apparatus comprising the above integrated circuit and having an external device connected to the integrated circuit.

  According to the present invention, it is possible to realize a high-performance graphical user interface, an intelligent man-machine interface, and a user support function that matches the time, place, and situation of using an electronic device. The operability and convenience of the equipment can be improved.

  In addition, by realizing a device to be miniaturized with a keyless and buttonless design, it is possible to realize a device having excellent design properties, such as configuring all one plane of the device with a display device.

  In addition, when connecting peripheral devices to an integrated circuit, signal processing for low-speed bus communication and frequent operation without reducing the processing efficiency of the main processing unit and the bandwidth performance of the bus connecting the external memory and the main processing unit The interrupt processing that occurs can be performed efficiently.

  In addition, while the operating frequency of the main processing unit is further improved due to higher performance, power consumption can be reduced by offloading the high-performance main processing unit from interrupt processing and low-speed bus control processing. Leakage current, which is a problem in a fine process, can be reduced by clock control and power supply control linked with standby control by the processing unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the video / audio processing integrated circuit described below can be applied to server electronic devices such as a digital television (DTV) and a digital video recorder (DVR), or mobile electronic devices such as a mobile phone and a video camera.

  FIG. 1 is a block diagram showing an internal configuration and a peripheral configuration of a related video / audio processing integrated circuit. A video / audio processing integrated circuit 10 shown in FIG. 1 is a system LSI that processes stream data related to video and audio, and includes a microcomputer block 101, a media processing block 102, a stream I / O block 103, and an AVIO (Audio Visual). Input Output) block 104 and memory IF block 105 are provided.

  The microcomputer block 101 performs non-real-time general-purpose processing, and is connected to the memory I / F block 105 via the data bus 107a. The media processing block 102 performs real-time general-purpose processing, and is connected to the memory I / F block 105 via the data bus 107b. The stream I / O block 103 performs non-real time I / O processing and is connected to the memory I / F block 105 via the data bus 107c. The AVIO block 104 performs real-time I / O processing and is connected to the memory I / F block 105 via the data bus 107d.

  An external memory device 111 provided outside the video / audio communication processing integrated circuit 10 is connected to the memory I / F block 105. In addition, a sensor device 109 and a wireless communication device 110 are connected to the microcomputer block 101. The microcomputer block 101 performs low-speed I / O processing according to the interrupt signal 112 output from the sensor device 109 or the wireless communication device 110.

  It is assumed that the electronic device including the video / audio processing integrated circuit 10 is connected to a broadband network such as the Internet. A general-purpose OS (basic software) is mounted on a memory (not shown) of the microcomputer block 101, and the video / audio processing integrated circuit 10 performs processing for reproducing streaming data downloaded via the Internet.

  If the video / audio processing integrated circuit 10 does not recognize the codec format of the downloaded streaming data, the codec execution software is downloaded and the application software is executed on the general-purpose OS, and then the media processing block 102 performs real-time general-purpose processing. Do. However, in the video / audio processing integrated circuit 10, an environment for operating the general-purpose OS may not always be prepared. In order to meet the required specifications even in such a situation, the microcomputer block 101 is designed to have a relatively high operation clock frequency sufficient for performing real-time processing.

  However, the microcomputer block 101 that operates with a high-frequency operation clock is connected to the sensor device 109 and the wireless communication device 110 that need to perform I / O processing at a speed lower than that of the operation clock. O processing becomes a significant deterioration factor of processing performance in the microcomputer block 101. Furthermore, the power consumption efficiency in the microcomputer block 101 also decreases.

  Specifically, in order for the video / audio processing integrated circuit 10 to recognize the current position of the electronic device or the situation where the electronic device is placed, position detection information from the GPS or beacon transmitted from a nearby electronic device Information from the wireless communication device 110 or the sensor device 109 that receives the signal needs to be input to the microcomputer block 101 regularly or at a high frequency. At this time, if the data obtained from the sensor device 109 or the wireless communication device 110 frequently occupies the data bus 107a, the bus memory bandwidth decreases.

  FIG. 2 is a block diagram showing an internal configuration and peripheral configuration of the integrated circuit for video / audio processing according to the embodiment of the present invention. The video / audio processing integrated circuit 100 shown in FIG. 2 is different from the video / audio processing integrated circuit 10 shown in FIG. 1 in that a microcomputer block 151 is provided instead of the microcomputer block 101 and a sub-computer block 153 is further provided. It is. A sub-con block 153 is connected to the sensor device 109 and the wireless communication device 110. The low-speed I / O processing performed by the microcomputer block 101 of the video / audio processing integrated circuit 10 is performed by the sub-con block 153, and the interrupt signal 112 output from the sensor device 109 or the wireless communication device 110 is input to the sub-con block 153. .

  The sub control block 153 performs low-speed I / O processing with the sensor device 109 or the wireless communication device 110 in response to the interrupt signal 112, and is connected to the memory I / F block 105 via the data bus 107e.

  FIG. 3 is a block diagram showing the internal configuration of the microcomputer block 151 and the sub-computer block 153 and the peripheral configuration. The microcomputer block 151 includes a CPU 201, a DMA unit 203, and a microcomputer peripheral unit 205. The sub computer block 153 includes a coprocessor 301, a data storage unit 303, an I / O control unit 305, a clock control unit 307, a power supply control unit 309, and an interrupt control unit 311.

  The I / O control unit 305 monitors the status of data input from the sensor device 109 or the wireless communication device 110, and takes input data into the data storage unit 303 only when a change amount equal to or greater than a threshold value occurs. Under other conditions, the operation of the sub control block 153 is stopped to reduce the power consumption.

  In the sub control block 153, except for the regular data monitoring mode, only the interrupt control unit 311 operates with an ultra-low-speed clock having a frequency of 32 KHz or 12 MHz, for example. Otherwise, the clock is stopped. When the interrupt signal 112 is input in this state, the clock control unit 307 supplies a clock, and the coprocessor 301 starts operation.

  However, the 12 MHz clock signal is a reference clock for the PLL, and until the clock can be supplied to the CPU 201 and the entire system LSI of the microcomputer block 151, the PLL lock-up time (stable waiting time), etc. A time lag of several hundred microseconds is required. Therefore, when the coprocessor 301 detects an interrupt, it operates with a source clock of 12 MHz, and when the supply of the clock is started after the PLL is stabilized, a frequency that is a fraction of the operation clock frequency of the CPU 201, for example, a peripheral of the CPU 201 The operation is switched to a clock having the same operation clock frequency as that of the port bus, or a frequency of 1/2 or 1/4 of the operation clock frequency.

  In addition, when the interrupt signal 112 is input when the PLL is stopped and the power saving mode is lower than the normal power supply voltage, the power supply control unit 309 immediately outputs a command to boost the power supply voltage when the interrupt signal 112 is detected. However, it may take several milliseconds for the power supply voltage to return to the normal voltage and stabilize. In this case, since the power supply voltage gradually rises, the circuit operation at this stage has a high possibility of causing a malfunction, and great care must be taken in circuit design.

  Therefore, in this case, the coprocessor 301 is operated in the asynchronous mode. Asynchronous coprocessor is a circuit with excellent noise immunity, so even within a few milliseconds until the power supply voltage recovers, it receives an interrupt signal and executes device driver processing such as an interrupt handler and the CPU 201 can operate. The coprocessor 301 can perform pre-processing until it reaches a certain state. As described above, the video / audio processing integrated circuit 100 can realize low power consumption and high-speed response performance because it can stand by in the power saving mode until the interrupt signal 112 is input.

  Next, the internal configuration of the sub control block 153 will be described with reference to FIG. FIG. 4 is a block diagram showing the internal configuration of the sub-con block 153 and the peripheral configuration. Data input from the sensor device 109 or the wireless communication device 110 is received by the signal input / output unit 521 included in the I / O control unit 305. Note that the signal input / output unit 521 can output data, but basically is often used as an input.

  The signal input / output unit 521 has a function of detecting the interrupt signal 112 and capturing data, a function of capturing or not capturing data constantly according to the setting made from the processor to the register 524, and a timer 525. The function is selected from the function of fetching data for each set value cycle. When the signal input / output unit 521 fetches data, the comparison unit 522 compares the value of the data buffer 523 with the size. The data buffer 523 stores data that has passed through the comparator 522 among the previously acquired data. If the difference between the data captured by the signal input / output unit 521 and the data stored in the data buffer 523 is equal to or greater than the value set in the threshold setting register 526, the comparison unit 522 is captured by the signal input / output unit 521. Data is output and the data is written into the data buffer 523 and the data storage unit 303. At this time, the comparison unit 522 outputs a signal 527 notifying that the data update has occurred to the coprocessor control circuit 531 included in the coprocessor 301.

  The coprocessor 301 is set to either the asynchronous operation mode or the synchronous operation mode. When the coprocessor 301 is set to the asynchronous operation mode, the coprocessor control circuit 531 includes, for example, a memory I / F control unit 532, a fetch control unit 533, a decode unit 534, an arithmetic unit control circuit 535, a calculation unit 536, The pipeline stage circuits such as the general-purpose register 537 and the data storage unit 303 operate while handshaking using the request signal 538 and the acknowledge signal 539.

  On the other hand, when the coprocessor 301 is set to the synchronous operation mode, the asynchronous mode switching control unit 540 included in the coprocessor 301 is configured so that the circuits 501 to 507 and the data storage unit operate so as to operate in clock synchronization without handshaking. A control signal is transmitted to 303. The mode switching can also be set by a register, but when the amount of data stored in the data storage unit 303 exceeds the threshold and approaches immediately before FULL, the mode change request signal 542 is sent from the data storage unit 303 to the asynchronous mode. Notification is made to the switching control unit 540.

  The data storage unit 303 is provided with an instruction memory area 543 of the coprocessor 301 so that instructions can be fetched by a dedicated bus. Further, the coprocessor 301 is provided with a memory management unit 544. The memory management unit 544 performs coherency control on the contents of the data storage unit 303 and the internal memory of the CPU 201, for example, a secondary cache, or is obtained from an external device. The stored information can be stored in the data storage unit 303 and the stored data can be directly transferred to the internal memory of the CPU 201.

  In the integrated circuit for video / audio processing 10 shown in FIG. 1, DMA transfer is performed from the periphery of the microcomputer to the external memory using the DAM unit 203, and then the CPU 201 accesses the external memory. However, according to the present embodiment, The data can be directly transferred to the internal memory of the CPU 201. In this transfer, there is a large amount of single access or small burst size data, which solves the memory bandwidth performance problem in the memory I / F block.

  As for the operation in which a single access from the CPU 201 to the external memory occurs when an interrupt occurs, when the operation clock frequency of the CPU 201 increases, a pipeline register is not inserted between the CPU 201 and the external bus to the external bus for speeding up. However, in this embodiment, since this portion is processed by the coprocessor 301, the number of man-machine interfaces increases and the frequency of occurrence of interrupts is remarkably high. Even if it increases, high responsiveness can be maintained. As a result, it is possible to realize an agile movement in realizing a highly responsive graphical user interface (GUI) or an electronic device that operates the device by shaking, tilting, or touching with a sensor device.

  The integrated circuit according to the present invention is useful as a system LSI for an electronic device that handles video and audio, particularly as a mobile LSI such as a mobile phone, an AVC mobile such as a digital camera, and a system LSI in an AVC server such as a DTV or DVD recorder. is there.

The block diagram which shows the internal structure and peripheral structure of a related audio-video processing integrated circuit 1 is a block diagram showing an internal configuration and peripheral configuration of an integrated circuit for video / audio processing according to an embodiment of the present invention. Block diagram showing each internal configuration and peripheral configuration of microcomputer block and sub-computer block The block diagram which shows the internal configuration of the sub control block and the peripheral configuration

Explanation of symbols

10, 100 Integrated circuit for video / audio processing 101, 151 Microcomputer block 102 Media processing block 103 Stream I / O block 104 AVIO block 105 Memory IF block 109 Sensor device 110 Wireless communication devices 107a to 107e Data bus 153 Sub-con block 201 CPU
203 DMA unit 205 Microcomputer peripheral unit 301 Coprocessor 303 Data storage unit 305 I / O control unit 307 Clock control unit 309 Power supply control unit 311 Interrupt control unit

Claims (10)

An integrated circuit in which a main processing unit and a peripheral connection port for connecting a peripheral device are connected by an internal bus,
An auxiliary processing unit that controls the peripheral connection port and performs control of interrupt and data transfer from the peripheral device connected to the peripheral connection port instead of the main processing unit;
The integrated circuit according to claim 1, wherein the main processing unit uses a memory resource of the auxiliary processing unit as a part of an internal memory space of the main processing unit. A main processing unit that performs both overall system control and media processing;
An auxiliary processing unit that controls interrupts and data transfer from peripheral devices connected to the main processing unit,
The auxiliary processing unit includes a data storage unit that stores data transferred from the peripheral device, performs intermediate processing on the data stored in the data storage unit, and collectively transfers the data to an external memory. Integrated circuit. An integrated circuit according to claim 2, wherein
The data storage unit included in the auxiliary processing unit is accessed from the main processing unit as a part of the internal memory of the main processing unit,
The auxiliary processing unit performs write access from the auxiliary processing unit when a read access from the main processing unit and a write access from the auxiliary processing unit occur simultaneously for the same memory address of the data storage unit. When waiting for a corresponding operation, the main processing unit has a flag register that notifies the main processing unit that an update occurs in a part of the data read,
The integrated processing circuit, wherein the auxiliary processing unit performs processing on the main processing unit so that the coherency of data read by the main processing unit coincides during or after the read operation of the main processing unit. An integrated circuit according to any one of claims 1-3,
When the main processing unit is in an idle state, the supply of the clock to the main processing unit is stopped, the power supply voltage of the main processing unit is stepped down,
The auxiliary processing unit performs processing of interrupt or data input from the peripheral device or data output to the peripheral device without passing through the main processing unit when the main processing unit is in an idle state. Integrated circuit. An integrated circuit according to any one of claims 1 to 4,
The integrated circuit, wherein the auxiliary processing unit operates at an operating frequency equal to or lower than an operating frequency of the main processing unit, or operates in an asynchronous mode. An integrated circuit according to any one of claims 1 to 4,
The operating frequency of the auxiliary processing unit is changed for each processing mode or each operating condition,
The integrated circuit, wherein the auxiliary processing unit operates in an asynchronous mode. An integrated circuit according to claim 5 or 6,
The integrated circuit according to claim 1, wherein when the main processing unit is in an idle state, the auxiliary processing unit operates in the asynchronous mode. An integrated circuit according to any one of claims 1 to 7,
Data input from the peripheral device is taken into the auxiliary processing unit,
The auxiliary processing unit compares the captured data with data captured in the past and stored in the data storage unit. When the difference in data amount is equal to or less than a predetermined value, the auxiliary processing unit stores the captured data in the data storage unit. The integrated circuit is characterized in that when the difference in the amount of data is larger than the predetermined value, the captured data is stored in the data storage unit. An integrated circuit according to claim 8, comprising:
The auxiliary processing unit increases the operating frequency stepwise when the data fetching frequency from the peripheral device is greater than a predetermined value, and when the data storage size of the data storage unit exceeds a predetermined value, An integrated circuit, wherein the main processing unit is notified that data has been transferred to the external memory. An integrated circuit according to any one of claims 1 to 9, comprising:
An electronic apparatus, wherein an external device is connected to the integrated circuit.

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