JP2010010963A - Input interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive input interface circuit having a wide allowable range of input signal voltage, for responding to a different input signal voltage, and having a simple structure. <P>SOLUTION: This input interface circuit I1 includes a CMOS inverter C1 where a P-channel MOS transistor M1 and an N-channel MOS transistor M2 are serially connected to each other between a power (VCC) terminal and a ground (GND) terminal. The input interface circuit I1 is structured such that the gate terminal of the N-channel MOS transistor M2 is used as an input terminal; a semiconductor element L1 having a threshold voltage is connected between the gate terminal of the P-channel MOS transistor M1 and the gate terminal of the N-channel MOS transistor M2; and the potential of the gate terminal of the P-channel MOS transistor M1 is set higher than that of the gate terminal of the N-channel MOS transistor M2 by the threshold voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to an input interface circuit comprising a CMOS inverter in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply terminal and a ground terminal.

  In an automobile, a large number of electronic control devices (so-called ECUs, Electronic Control Units) are mounted to control in-vehicle devices, and these electronic control devices share control data and perform integrated control of the vehicle. They are connected to each other via a communication bus such as a CAN (Controller Area Network) so as to be able to communicate with each other (for example, refer to Patent Documents 1 and 2).

  FIG. 7 is a diagram schematically showing the in-vehicle device network 100 based on the CAN communication.

As shown in FIG. 7, a CAN communication network 100 is a differential communication network using two bus lines (differential communication lines) 10a and 10b, and various electronic control devices (nodes) 11 mounted on a vehicle. -14 are networks connected in parallel by buses. Each of the nodes 11 to 14 includes, for example, an ECU that controls an actuator based on information from a sensor that detects a state of the vehicle, and includes a CAN transceiver T10 for communicating with other nodes. Each of the CAN transceivers T10 is provided with a circuit that converts output signals from the control microcomputers M11 to M14 or input signals from other nodes into transmission data and reception data according to a communication protocol.
JP 2007-243317 A JP-T-2006-521052 gazette

  In the network 100 shown in FIG. 7, as described above, input / output signals are converted via the CAN transceiver T10, and data communication is possible between the control microcomputers M11 to M14 of the different nodes 11 to 14.

  Here, in a network device constituting conventional CAN communication, a signal voltage 5 V system is generally used for both the microcomputer and the CAN transceiver. However, with the recent decrease in the voltage of microcomputers, as shown in the network 100 in FIG. 7, 5V microcomputers M13 and M14 and 3V microcomputers M11 and M12 are mixed in the network. . On the other hand, the CAN transceivers T10 of the nodes 11 to 14 are all 5V systems because they are general-purpose components. Therefore, at the nodes 11 and 12, the 3V signal voltage of the microcomputers M11 and M12 is input to the CAN transceiver T10 designed with the signal voltage of 5V. For this reason, the following problems occur.

  FIG. 8 is a diagram showing a conventional representative input interface circuit I9 of the CAN transceiver T10 connected to the microcomputer.

  An input interface circuit I9 surrounded by a broken line in FIG. 8 is an input interface circuit having a CMOS inverter C1 in which a P-channel MOS transistor M1 and an N-channel MOS transistor M2 are connected in series between a power supply terminal and a ground terminal. . The gate terminal of the P-channel MOS transistor M1 and the gate terminal of the N-channel MOS transistor M2 are commonly connected, and the commonly connected gate terminal is the input terminal of the input interface circuit I9. The resistor R1 is a pull-up resistor, and a CMOS inverter C2 for buffering is connected after the CMOS inverter C1.

  Since the CAN transceiver T10 of FIG. 8 is designed in the 5V system as described above, the input signal voltage to the input interface circuit I9 must be at the same 5V level as the power supply voltage VCC. However, since the microcomputer M11 is designed with a 3V system as described above, a signal voltage of 3V is input to the input interface circuit I9. This 3V input signal voltage is a value close to 2.5V, which is the input threshold voltage 1 / 2VCC of the CMOS transistor C1, and is therefore used in a state where the margin with respect to the threshold voltage is very small compared to the original design value. Will be. For this reason, a malfunction is likely to occur. Even in the Hi input signal state, the sneak current Is indicated by the dotted arrow in the drawing flows to the microcomputer M11 via the pull-up resistor R1.

  In recent years, signal transmission / reception between different voltage operation ICs as shown in FIG. 7 is not uncommon, not limited to microcomputers and CAN transceivers. Therefore, in order to solve the problem described with reference to FIG. 8, in many cases, the voltage is boosted (or stepped down) in the output-side IC to exchange signals. For example, in the case of a 3V microcomputer and a driver IC, the voltage is converted from 3V to 5V at the interface (I / F) portion of the microcomputer, and a signal of 0V-5V is input to the driver IC. However, for example, when the driver IC is changed to 3V, it is necessary to change the I / F circuit of the microcomputer at the same time. As a result, both ICs are changed, and development costs and man-hours are increased.

  Therefore, the present invention is an input interface circuit having a CMOS inverter in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply terminal and a ground terminal, and has a wide allowable range of input signal voltage, An object of the present invention is to provide an inexpensive input interface circuit that can cope with different input signal voltages and has a simple configuration.

  The input interface circuit according to claim 1, wherein the input interface circuit includes a CMOS inverter in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply terminal and a ground terminal, and the N-channel The gate terminal of the MOS transistor is used as the input terminal of the input interface circuit, and a semiconductor element having a threshold voltage is connected between the gate terminal of the P-channel MOS transistor and the gate terminal of the N-channel MOS transistor. The transistor is configured such that the potential of the gate terminal of the transistor is higher than the potential of the gate terminal of the N-channel MOS transistor by the threshold voltage.

  In the conventional input interface circuit having a CMOS inverter, the gate terminals of the P-channel MOS transistor and the N-channel MOS transistor connected in series between the power supply terminal and the ground terminal are input terminals of the input interface circuit. . Therefore, when the power supply potential is VCC, the input threshold voltage of the input interface circuit (CMOS inverter) is about ½ VCC, and the same input signal voltage as the power supply potential VCC is input to the input terminal. The N-channel MOS transistor was switched on and off. For this reason, in the conventional input interface circuit, when the input signal voltage becomes lower than the power supply potential VCC, it approaches the input threshold voltage of 1/2 VCC, and the margin of ON / OFF switching of the P-channel MOS transistor is reduced. Malfunction is likely to occur.

  On the other hand, the input interface circuit according to claim 1 is the same as the conventional one in that the P-channel MOS transistor and the N-channel MOS transistor constituting the CMOS inverter are connected in series between the power supply terminal and the ground terminal. is there. However, in the input interface circuit, unlike the prior art, a semiconductor element having a threshold voltage is connected between the gate terminal of the P-channel MOS transistor and the gate terminal of the N-channel MOS transistor. The potential of the gate terminal of the P channel MOS transistor is configured to be higher than the potential of the gate terminal of the N channel MOS transistor by the threshold voltage.

  In the input interface circuit, the gate terminal of the N-channel MOS transistor constituting the CMOS inverter is the input terminal of the input interface circuit, and the N-channel MOS transistor has an input signal voltage applied to the input terminal, Similarly, turn on and off. On the other hand, the P channel MOS transistor, which is the other component of the CMOS inverter, has a gate terminal potential increased by the threshold voltage of the semiconductor element by the above configuration. For this reason, even when the input signal voltage at the input terminal is lower than the specified power supply potential VCC, the level of the gate terminal of the P-channel MOS transistor is shifted by the threshold voltage of the semiconductor element and the potential of the gate terminal of the P-channel MOS transistor is set. Can be approached. From the viewpoint of this effect, it can be said that the input threshold voltage of the CMOS inverter as a whole is lowered as compared with the conventional input interface circuit in which no semiconductor element is inserted. As a result, even when operating with an input signal voltage lower than the specified voltage, it is possible to secure a margin for ON / OFF switching of the P-channel MOS transistor as compared with the conventional case, so that malfunction can be prevented. it can.

  Further, the input interface circuit uses a semiconductor element having a threshold voltage as a level shift element of the gate potential of the P-channel MOS transistor, thereby suppressing a sneak current to the input terminal as compared with, for example, a resistance element. be able to.

  The input interface circuit can be configured only by adding a semiconductor element having a threshold voltage to the conventional input interface circuit. Therefore, in order to cope with the case where the input signal voltage is lower than the prescribed power supply potential VCC, for example, an increase in manufacturing cost can be suppressed as compared to adding a signal voltage conversion circuit.

  As described above, the input interface circuit is an input interface circuit having a CMOS inverter in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply terminal and a ground terminal. It is possible to provide an inexpensive input interface circuit that has a wide voltage tolerance range, can handle different input signal voltages, and has a simple configuration.

  In the input interface circuit, it is preferable that a resistor is connected between the gate terminal of the P-channel MOS transistor and the power supply terminal.

  The resistor functions as a pull-up resistor. As a result, the gate potential of the P-channel MOS transistor constituting the CMOS inverter is fixed, so that the circuit operation can be stabilized.

  In the input interface circuit, as described in claim 3, the semiconductor element may be constituted by a plurality of elements connected in series. According to this, since the sum of the threshold voltages of the respective elements becomes the threshold voltage of the semiconductor element, it is possible to obtain a large threshold voltage as a whole as compared with the case where the element is constituted by one element.

  According to a fourth aspect of the present invention, the semiconductor element may be composed of a plurality of elements connected in parallel. According to this, since the threshold voltage as a whole becomes smaller than the threshold voltage of the individual elements constituting the semiconductor element, it is possible to set a fine threshold voltage.

  As the semiconductor element in the input interface circuit, for example, a P-channel MOS transistor element can be adopted as described in claim 5, and a gate terminal of the P-channel MOS transistor element constitutes the CMOS inverter. It is configured to be connected to the gate terminal of the channel MOS transistor. Thus, the threshold voltage between the gate and the source of the P channel MOS transistor element can be used for the level shift of the gate potential of the P channel MOS transistor constituting the CMOS inverter described above.

  Similarly, as described in claim 6, an N-channel MOS transistor element is adopted as the semiconductor element, and a gate terminal of the N-channel MOS transistor element is connected to a gate terminal of a P-channel MOS transistor constituting the CMOS inverter. You may comprise so that it may be connected. Thereby, the threshold voltage between the gate and the source of the N channel MOS transistor element can be used for the level shift of the gate potential of the P channel MOS transistor constituting the CMOS inverter described above.

  When a P-channel MOS transistor element or an N-channel MOS transistor element is adopted as the semiconductor element, it is the same type of element as a P-channel MOS transistor and an N-channel MOS transistor that constitute a CMOS inverter, and therefore has a temperature characteristic. It is the same. Therefore, temperature dependency of the input interface circuit (CMOS inverter) can be suppressed as compared with the case where other types of elements are employed as the semiconductor elements. In addition, the P-channel MOS transistor element and the N-channel MOS transistor element employed as the semiconductor element are always in an ON state due to the connection, but as described above, for example, compared with the case where a resistance element is used, the input terminal It is possible to suppress the sneak current into the.

  As the semiconductor element in the input interface circuit, for example, a diode element can be adopted as described in claim 7, and a cathode terminal of the diode element is a gate terminal of a P-channel MOS transistor constituting the CMOS inverter. And the anode terminal of the diode element is connected to the gate terminal of the N-channel MOS transistor constituting the CMOS inverter. Thereby, the threshold voltage between the anode and the cathode of the diode element can be used for the level shift of the gate potential of the P-channel MOS transistor constituting the CMOS inverter described above. When a diode element is employed as the semiconductor element, the sneak current to the input terminal can be further reduced as compared with the case where a P-channel MOS transistor element or an N-channel MOS transistor element is employed as the semiconductor element. it can.

  As described above, the input interface circuit is an input interface circuit having a CMOS inverter in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply terminal and a ground terminal. The input interface circuit has a wide voltage tolerance range, can handle different input signal voltages, and has a simple configuration and is inexpensive.

  Therefore, as described in claim 8, the input interface circuit is suitable for use in the CAN transceiver connected to the control microcomputer in an in-vehicle electronic control apparatus having a CAN transceiver and a control microcomputer. As a result, even in a vehicle-mounted electronic control device network in which 3V and 5V control microcomputers coexist, stable operation of each electronic control device can be realized at low cost.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing an input interface circuit I1 according to an example of the present invention. In addition, in each input interface circuit illustrated below, the same code | symbol was attached | subjected about the part similar to the input interface circuit I9 shown in FIG.

  An input interface circuit I1 shown in FIG. 1 includes an input interface having a CMOS inverter C1 in which a P-channel MOS transistor M1 and an N-channel MOS transistor M2 are connected in series between a power supply (VCC) terminal and a ground (GND) terminal. Circuit. The input interface circuit I1 uses the gate terminal of the N-channel MOS transistor M2 as an input terminal.

  Further, between the gate (G) terminal of the P-channel MOS transistor M1 and the gate (G) terminal of the N-channel MOS transistor M2 constituting the CMOS inverter C1, a P-channel MOS transistor element L1 is provided as a semiconductor element having a threshold voltage. Is connected. The gate terminal of the P channel MOS transistor element L1 is connected to the gate terminal of the N channel MOS transistor M2 constituting the CMOS inverter C1. Therefore, in the input interface circuit I1, the gate terminal of the N-channel MOS transistor M2 has a potential at the gate terminal of the P-channel MOS transistor M1 constituting the CMOS inverter C1 by the threshold voltage Vt between the gate and source of the P-channel MOS transistor element L1. It is configured to be higher than the terminal potential.

  In the conventional input interface circuit I9 shown in FIG. 8, the commonly connected gate terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 connected in series between the power supply terminal and the ground terminal are connected to the input interface circuit I9. It was an input terminal. Accordingly, when the power supply potential is VCC, the input threshold voltage of the input interface circuit I9 (CMOS inverter C1) is about 1/2 VCC, and the same input signal voltage as the power supply potential VCC is input to the input terminal, so that the P channel MOS The transistor M1 and the N-channel MOS transistor M2 are switched on and off. For this reason, in the conventional input interface circuit I9, when the input signal voltage becomes lower than the power supply potential VCC, it approaches the input threshold voltage of ½ VCC, and the margin for switching ON / OFF of the P-channel MOS transistor M1 becomes small. It was easy for malfunctions to occur.

  On the other hand, in the input interface circuit I1 shown in FIG. 1, the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the CMOS inverter C1 are serially connected between the power supply (VCC) terminal and the ground (GND) terminal. This is the same as in the past. However, in the input interface circuit I1, unlike the prior art, a P-channel MOS transistor element L1 is connected as a semiconductor element having a threshold voltage between the gate terminal of the P-channel MOS transistor M1 and the gate terminal of the N-channel MOS transistor M2. ing. The potential of the gate terminal of the P-channel MOS transistor M1 constituting the CMOS inverter C1 is configured to be higher than the potential of the gate terminal of the N-channel MOS transistor M2 by the threshold voltage.

  In the input interface circuit I1 of FIG. 1, the gate terminal of the N-channel MOS transistor M2 constituting the CMOS inverter C1 is an input terminal of the input interface circuit I1, and the N-channel MOS transistor M2 is connected to the input terminal. The signal voltage is turned ON / OFF similarly to the case of the conventional input interface circuit I9 shown in FIG. On the other hand, in the P channel MOS transistor M1, which is another component of the CMOS inverter C1, the potential of the gate terminal is increased by the threshold voltage Vt of the P channel MOS transistor element L1 by the above configuration. For this reason, even when the input signal voltage at the input terminal is lower than the specified power supply potential VCC, the level of the threshold voltage Vt of the P channel MOS transistor element L1 is shifted and the potential at the gate terminal of the P channel MOS transistor M1 is changed. It can be close to the specified input signal voltage. From a different viewpoint, it can be said that the input threshold voltage of the CMOS inverter C1 as a whole is lowered as compared with the conventional input interface circuit I9 in which the P-channel MOS transistor element L1 is not inserted. As a result, even when operating with an input signal voltage lower than the specified voltage, it is possible to secure a margin for switching the ON / OFF of the P-channel MOS transistor M1 as compared with the conventional input interface circuit I9. Therefore, malfunction can be prevented.

  More specifically, assuming that the power supply potential VCC is 5V and the input signal voltage Vin from the microcomputer M11 is 3V, the input interface circuit I1 of FIG. 1 operates as follows. The threshold voltage Vt of the P channel MOS transistor element L1 is generally 1 to 1.1V.

  When the input “IN” is 0V, the N-channel MOS transistor M2 is OFF, the P-channel MOS transistor M1 is ON, and the output “OUT” is 0V output. When the input “IN” is 3V (H level), the N-channel MOS transistor M2 is ON, and the gate potential of the P-channel MOS transistor M1 is 4 to 4.1V at (Vin + Vt), and the potential difference from the power supply potential VCC is 0.9 to 1V. If the potential difference between the gate potential of the P channel MOS transistor M1 and the power supply potential VCC is equal to or lower than the threshold voltage Vt of the P channel MOS transistor M1, the P channel MOS transistor M1 is turned off. 5V is output. The threshold voltage Vt of the semiconductor element connected between the gate terminal of the P-channel MOS transistor M1 and the gate terminal of the N-channel MOS transistor M2 can be appropriately set as will be described later. The potential difference between the gate potential and the power supply potential VCC can also be set as appropriate. On the other hand, in the conventional input interface circuit I9 shown in FIG. 8, when the input "IN" is 3V, the gate potential of the P-channel MOS transistor M1 is 3V and the potential difference from the power supply potential VCC is 2V. Therefore, not only the N-channel MOS transistor M2 but also the P-channel MOS transistor M1 is turned on, and malfunctions. Note that the input interface circuit I1 of FIG. 1 can be operated not only with a 3V input signal voltage but also with a normal 5V input signal voltage that is the same as the power supply potential VCC. Accordingly, the input interface circuit I1 of FIG. 1 is an input interface circuit having a wide input signal voltage range that can handle output signals from the 3V and 5V microcomputers as input signals.

  As in the input interface circuit I9 shown in FIG. 8, the input interface circuit I1 shown in FIG. 1 has a resistor R1 connected between the gate terminal of the P-channel MOS transistor M1 and the power supply (VCC) terminal. The resistor R1 functions as a pull-up resistor, which fixes the gate potential of the P-channel MOS transistor M1 that constitutes the CMOS inverter C1, thereby stabilizing the circuit operation.

  The input interface circuit I1 shown in FIG. 1 can suppress a sneak current to the input terminal as compared with the conventional input interface circuit I9 shown in FIG. More specifically, in the conventional input interface circuit I9 shown in FIG. 8, a sneak current Is of (VCC-Vin) / R1 is generated. For example, when R1 = 30 kΩ, the sneak current Is is about 66 μA. On the other hand, the input interface circuit I1 shown in FIG. 1 has a sneak current of (VCC−Vin−Vt) / R1, and is about 20 μA when R1 = 30 kΩ. Further, in the input interface circuit I1 of FIG. 1, a semiconductor element (P channel MOS transistor M1) having a threshold voltage is used as a level shift element of the gate potential of the P channel MOS transistor M1, for example, compared to the case of using a resistance element. However, the sneak current to the input terminal can be suppressed.

  The input interface circuit I1 of FIG. 1 can be configured only by adding a semiconductor element (P channel MOS transistor M1) having a threshold voltage to the conventional input interface circuit I9 shown in FIG. Therefore, in order to cope with the case where the input signal voltage is lower than the prescribed power supply potential VCC, for example, an increase in manufacturing cost can be suppressed as compared to adding a signal voltage conversion circuit.

  As described above, the input interface circuit I1 shown in FIG. 1 includes the CMOS inverter C1 in which the P-channel MOS transistor M1 and the N-channel MOS transistor M2 are connected in series between the power supply (VCC) terminal and the ground (GND) terminal. The input interface circuit has a wide allowable range of input signal voltage, can handle different input signal voltages, and can be an inexpensive input interface circuit with a simple configuration.

  FIG. 2 is a diagram showing an input interface circuit I2 as another example.

  In the input interface circuit I1 of FIG. 1, a P-channel MOS transistor element L1 is employed as a semiconductor element having a threshold voltage, and is connected between two gate (G) terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2. It had been. The gate terminal of the P-channel MOS transistor element L1 is connected to the gate terminal of the N-channel MOS transistor M2.

  On the other hand, in the input interface circuit I2 of FIG. 2, an N-channel MOS transistor element L2 is adopted as a semiconductor element having a threshold voltage, and two of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the CMOS inverter C1. Connected between two gate terminals. The gate terminal of the N channel MOS transistor element L2 is connected to the gate terminal of the P channel MOS transistor M1 constituting the CMOS inverter C1. With the above connection, the threshold voltage Vt between the gate and the source of the N-channel MOS transistor element L2 is set to the P-channel constituting the CMOS inverter C1 as in the case of the P-channel MOS transistor element L1 in the input interface circuit I1 of FIG. It can be used for level shift of the gate potential of the MOS transistor M1.

  Therefore, the input interface circuit I2 in FIG. 2 also has a wide allowable range of input signal voltages, can handle different input signal voltages, and is inexpensive with a simple configuration, similar to the input interface circuit I1 in FIG. It can be an input interface circuit.

  When the P-channel MOS transistor element L1 or the N-channel MOS transistor element L2 is employed as the semiconductor element having the threshold voltage as in the input interface circuits I1 and I2 shown in FIGS. 1 and 2, the CMOS inverter C1 Is the same type of element as the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the same, and therefore has the same temperature characteristics. Therefore, temperature dependency of the input interface circuits I1 and I2 (CMOS inverter C1) can be suppressed as compared with the case where other types of elements are employed as the semiconductor elements.

  Also, the N-channel MOS transistor element L2 in the input interface circuit I2 in FIG. 2 is always in the ON state by the above connection, similarly to the P-channel MOS transistor element L1 in the input interface circuit I1 in FIG. However, as described above, for example, a sneak current to the input terminal can be suppressed as compared with a case where a resistance element is connected between two gate terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2. is there.

  FIG. 3 is a diagram showing an input interface circuit I3 as another example.

  In the input interface circuit I3 of FIG. 3, unlike the input interface circuits I1 and I2 of FIGS. 1 and 2, a diode element L3 is used as a semiconductor element having a threshold voltage, and two P-channel MOS transistors M1 and N-channel MOS transistors M2 are used. It is connected between the gate (G) terminals. The cathode terminal (C) of the diode element L3 is connected to the gate terminal of the P-channel MOS transistor M1 constituting the CMOS inverter C1, and the anode terminal (A) of the diode element L3 is connected to the N-channel MOS transistor M2. Connected to the gate terminal. With the above connection, the threshold voltage Vf between the anode and the cathode of the diode element L3 can be used for the level shift of the gate potential of the P-channel MOS transistor M1 constituting the CMOS inverter C1 described above. When the diode element is employed as the semiconductor element having the threshold voltage as in the input interface circuit I3 in FIG. 3, the P-channel MOS transistor element L1 or the N-channel MOS transistor element L2 shown in FIGS. As compared with the case of adopting, the sneak current to the input terminal can be further reduced.

  4 and 5 are diagrams showing input interface circuits I4 and I5, respectively, as another example.

  In the input interface circuit I4 of FIG. 4, two P-channel MOS transistor elements connected in series between two gate (G) terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the CMOS inverter C1. L4a and L4b are connected. The gate terminals of the two P-channel MOS transistor elements L4a and L4b are connected in common to the gate (G) terminal of the N-channel MOS transistor M2 constituting the CMOS inverter C1.

  In the input interface circuit I5 of FIG. 5, two diode elements L5a connected in series between the two gate (G) terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the CMOS inverter C1. , L5b are connected.

  Like the input interface circuits I4 and I5 shown in FIGS. 4 and 5, the threshold voltage is inserted between the two gate terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the CMOS inverter C1. The semiconductor element may be composed of a plurality of elements connected in series. According to this, since the sum of the threshold voltages of the respective elements becomes the threshold voltage of the semiconductor element, it is possible to obtain a large threshold voltage as a whole as compared with the case where the element is constituted by one element. Due to the configuration of this circuit, the semiconductor element inserted between the two gate terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 has a higher margin for malfunction as the threshold voltage increases, and wraps around to the input terminal side. It is preferable because the current is reduced. For example, in the input interface circuit I4 of FIG. 4, when R1 = 30 kΩ, the input threshold voltage as a whole of the CMOS inverter C1 is around 1 V, and a margin for malfunction of the P-channel MOS transistor M1 can be secured. Also, the sneak current Is to the input terminal side can be reduced to about 13 μA. Needless to say, a plurality of N-channel MOS transistor elements can be similarly connected in series to obtain a large threshold voltage as a whole.

  FIG. 6 is a diagram showing an input interface circuit I6 as another example.

  In the input interface circuit I4 of FIG. 4, two P-channel MOS transistor elements L4a and L4b connected in series have two gates (G) of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the CMOS inverter C1. Connected between terminals. On the other hand, in the input interface circuit I6 in FIG. 6, two P-channel MOS transistor elements L6a and L6b connected in parallel are two P-channel MOS transistors M1 and N-channel MOS transistors M2 constituting the CMOS inverter C1. Connected between two gate (G) terminals.

  As described above, a semiconductor element having a threshold voltage inserted between the two gate terminals of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 constituting the CMOS inverter C1 is constituted by a plurality of elements connected in parallel. You may make it do. According to this, since the threshold voltage as a whole becomes smaller than the threshold voltage of the individual elements constituting the semiconductor element, it is possible to set a fine threshold voltage. Needless to say, a plurality of N-channel MOS transistor elements and diode elements can be similarly connected in parallel to obtain a large threshold voltage as a whole.

  Each of the input interface circuits I1 to I6 exemplified above has an input interface circuit having a CMOS inverter C1 in which a P-channel MOS transistor M1 and an N-channel MOS transistor M2 are connected in series between a power supply terminal and a ground terminal. The input signal voltage has a wide allowable range, can be applied to different input signal voltages, and is an inexpensive input interface circuit with a simple configuration.

  Accordingly, the input interface circuits I1 to I6 are suitable for use in the CAN transceiver connected to the control microcomputer in the in-vehicle electronic control apparatus having the CAN transceiver and the control microcomputer illustrated in FIG. As a result, even in a vehicle-mounted electronic control device network in which 3V and 5V control microcomputers coexist, stable operation of each electronic control device can be realized at low cost.

FIG. 3 is a diagram illustrating an input interface circuit I1 according to an example of the present invention. In another example, it is a diagram showing an input interface circuit I2. In another example, it is a diagram showing an input interface circuit I3. In another example, it is a figure which shows the input interface circuit I4. In another example, it is a diagram showing an input interface circuit I5. In another example, it is a diagram showing an input interface circuit I6. It is the figure which showed typically the network 100 of the vehicle equipment by CAN communication. It is the figure which showed the conventional typical input interface circuit I9 of CAN transceiver T10 connected to a microcomputer.

Explanation of symbols

I1 to I6, I9 Input interface circuit C1 CMOS inverter M1 P channel MOS transistor M2 N channel MOS transistor L1, L4a, L4b, L6a, L6b P channel MOS transistor element L2 N channel MOS transistor element L3, L5a, L5b Diode element 11 14 Electronic control unit T10 CAN transceiver M11 to M14 Control microcomputer

Claims (8)

An input interface circuit having a CMOS inverter in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply terminal and a ground terminal,
The gate terminal of the N-channel MOS transistor is used as the input terminal of the input interface circuit,
A semiconductor element having a threshold voltage is connected between the gate terminal of the P-channel MOS transistor and the gate terminal of the N-channel MOS transistor,
An input interface circuit, wherein the potential of the gate terminal of the P-channel MOS transistor is configured to be higher than the potential of the gate terminal of the N-channel MOS transistor by the threshold voltage.   2. The input interface circuit according to claim 1, wherein a resistor is connected between the gate terminal of the P-channel MOS transistor and the power supply terminal.   The input interface circuit according to claim 1, wherein the semiconductor element includes a plurality of elements connected in series.   3. The input interface circuit according to claim 1, wherein the semiconductor element is composed of a plurality of elements connected in parallel. The semiconductor element comprises a P-channel MOS transistor element;
5. The input interface circuit according to claim 1, wherein a gate terminal of the P channel MOS transistor element is connected to a gate terminal of an N channel MOS transistor constituting the CMOS inverter. . The semiconductor element comprises an N-channel MOS transistor element;
5. The input interface circuit according to claim 1, wherein a gate terminal of the N-channel MOS transistor element is connected to a gate terminal of a P-channel MOS transistor constituting the CMOS inverter. . The semiconductor element comprises a diode element;
A cathode terminal of the diode element is connected to a gate terminal of a P-channel MOS transistor constituting the CMOS inverter;
5. The input interface circuit according to claim 1, wherein an anode terminal of the diode element is connected to a gate terminal of an N-channel MOS transistor constituting the CMOS inverter. The input interface circuit is
The input interface circuit according to any one of claims 1 to 7, wherein the input interface circuit is used in the CAN transceiver connected to the control microcomputer in an in-vehicle electronic control device having a CAN transceiver and a control microcomputer. .

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