JP2010098700A5

JP2010098700A5 -

Info

Publication number: JP2010098700A5
Application number: JP2008270291A
Authority: JP
Filing date: 2008-10-20
Publication date: 2011-12-08
Anticipated expiration: 2028-10-20

Description

本発明は、上述した課題を解決するために、入力された画像データの水平方向の画素数を所定の変換比で変換する画像処理装置であって、入力された前記画像データに同期した入力クロックに基づき、前記入力クロックにそれぞれ同期する、前記入力クロックより高い周波数の第１のクロックと、前記第１のクロックより周波数が高い第２のクロックとを発生する同期クロック発生手段と、入力された前記画像データを前記第１のクロックに応じてサンプリングすることにより前記画像データの画素数を増加する第１のサンプリング手段と、所定のカウント値までを巡回的にカウントするカウンタであって、前記第２のクロックに応じて、前記変換比と、前記第２のクロックおよび前記入力クロックの周波数の比とに基づく値を順次加算するカウンタと、前記カウンタのカウント値が前記所定のカウント値になる毎に前記第２のクロックをゲートすることにより第３のクロックを生成するクロック生成手段と、前記第１のサンプリング手段によりサンプリングされた前記画像データを、前記クロック生成手段により生成された前記第３のクロックに応じてサンプリングすることにより、前記第１のサンプリング手段によりサンプリングされた前記画像データの画素数を減少する第２のサンプリング手段とを有することを特徴とする画像処理装置である。 The present invention, in order to solve the problems described above, the number of pixels in the horizontal direction of the input image data by an image processing apparatus for converting a predetermined conversion ratio, the input clock synchronized with the inputted said image data the basis, synchronized respectively with the input clock, a first clock of a frequency higher than the input clock, a synchronizing signal generating means for said first frequency from the clock to generate a high second clock, is input A first sampling means for increasing the number of pixels of the image data by sampling the image data according to the first clock; and a counter for cyclically counting up to a predetermined count value, depending on the second clock, sequentially adding said conversion ratio, a value based on the ratio of the frequency of the second clock and the input clock A counter, and a clock generating means for generating a third clock by the count value of the counter gating the second clock each time becomes the predetermined count value, it is sampled by the first sampling means Second sampling means for reducing the number of pixels of the image data sampled by the first sampling means by sampling the image data according to the third clock generated by the clock generating means And an image processing apparatus.

また、本発明は、入力された画像データの水平方向の画素数を所定の変換比で変換する画像処理装置における画像処理方法であって、前記画像処理装置の同期クロック発生手段が、入力された前記画像データに同期した入力クロックに基づき、前記入力クロックにそれぞれ同期する、前記入力クロックより高い周波数の第１のクロックと、前記第１のクロックより周波数が高い第２のクロックとを発生する同期クロック発生ステップと、前記画像処理装置の第１のサンプリング手段が、入力された前記画像データを前記第１のクロックに応じてサンプリングすることにより前記画像データの画素数を増加する第１のサンプリングステップと、前記画像処理装置のカウンタが、所定のカウント値までを巡回的にカウントするカウントステップであって、前記第２のクロックに応じて、前記変換比と、前記第２のクロックおよび前記入力クロックの周波数の比とに基づく値を順次加算するカウントステップと、前記画像処理装置のクロック生成手段が、前記カウント値が前記所定のカウント値になる毎に前記第２のクロックをゲートすることにより第３のクロックを生成するクロック生成ステップと、前記画像処理装置の第２のサンプリング手段が、前記第１のサンプリングステップによりサンプリングされた前記画像データを、前記クロック生成ステップにより生成された前記第３のクロックに応じてサンプリングすることにより前記第１のサンプリングステップによりサンプリングされた前記画像データの画素数を減少する第２のサンプリングステップとを有することを特徴とする画像処理方法である。 The present invention is also an image processing method in an image processing apparatus for converting the number of pixels in the horizontal direction of input image data at a predetermined conversion ratio, wherein the synchronization clock generating means of the image processing apparatus receives the input based on said input clock synchronized with the image data, synchronized respectively with the input clock, a first clock of a frequency higher than the input clock, synchronization of the first frequency from the clock to generate a high second clock And a first sampling step in which the first sampling means of the image processing apparatus increases the number of pixels of the image data by sampling the input image data in accordance with the first clock. When the counter of the image processing apparatus, the count step of counting cyclically until a predetermined count value What the second in response to the clock, and the conversion ratio, the second clock and a count step of sequentially adding a value based on the ratio of the frequency of the input clock, the clock generating means of the image processing apparatus but before a clock generation step of generating a third clock by hear count value to gate the second clock each time becomes the predetermined count value, the second sampling means of the image processing apparatus The image data sampled by the first sampling step is sampled according to the third clock generated by the clock generation step, and the image data sampled by the first sampling step is sampled. and having a second sampling step of reducing the number of pixels An image processing method.

また、本発明は、入力された画像データの画素数を変換する画像処理装置であって、入力された前記画像データに同期した入力クロックに基づき、前記入力クロックに同期し且つ前記入力クロックより高い周波数の第１のクロックと、前記入力クロックに同期し且つ前記第１のクロックより高い周波数の第２のクロックとを発生する同期クロック発生手段と、入力された前記画像データを前記第１のクロックに応じてサンプリングすることにより前記画像データの画素数を増加すると共に画素数が増加された前記画像データに対してフィルタ処理を施すフィルタを含む第１のサンプリング手段と、所定のカウント値までを巡回的にカウントするカウンタであって、前記第２のクロックに従い所定の調整値を順次加算するカウンタと、前記カウンタのカウント値に従って前記第２のクロックに同期し且つ変換後の画素数に応じた周波数の第３のクロックを生成するクロック生成手段と、前記第１のサンプリング手段によりサンプリングされフィルタ処理が施された前記画像データを、前記クロック生成手段により生成された前記第３のクロックに応じてサンプリングすることにより、前記第１のサンプリング手段によりサンプリングされフィルタ処理が施された前記画像データの画素数を減少する第２のサンプリング手段とを有することを特徴とする画像処理装置である。
また、本発明は、入力された画像データの画素数を変換する画像処理装置における画像処理方法であって、前記画像処理装置の同期クロック発生手段が、入力された前記画像データに同期した入力クロックに基づき、前記入力クロックに同期し且つ前記入力クロックより高い周波数の第１のクロックと、前記入力クロックに同期し且つ前記第１のクロックより高い周波数の第２のクロックとを発生する同期クロック発生ステップと、前記画像処理装置の第１のサンプリング手段が、入力された前記画像データを前記第１のクロックに応じてサンプリングすることにより前記画像データの画素数を増加すると共に画素数が増加された前記画像データに対してフィルタ処理を施す第１のサンプリングステップと、前記画像処理装置のカウンタが、所定のカウント値までを巡回的にカウントするカウントステップであって、前記第２のクロックに従い所定の調整値を順次加算するカウントステップと、前記画像処理装置のクロック生成手段が、前記カウント値に従って前記第２のクロックに同期し且つ変換後の画素数に応じた周波数の第３のクロックを生成するクロック生成ステップと、前記画像処理装置の第２のサンプリング手段が、前記第１のサンプリングステップによりサンプリングされフィルタ処理が施された前記画像データを、前記クロック生成ステップにより生成された前記第３のクロックに応じてサンプリングすることにより、前記第１のサンプリングステップによりサンプリングされフィルタ処理が施された前記画像データの画素数を減少する第２のサンプリングステップとを有することを特徴とする画像処理方法である。 The present invention is also an image processing apparatus for converting the number of pixels of input image data, and is based on an input clock synchronized with the input image data and is synchronized with the input clock and higher than the input clock. Synchronous clock generating means for generating a first clock having a frequency and a second clock having a higher frequency than the first clock in synchronization with the input clock; and the input image data as the first clock. cyclic a first sampling means including a filter performs a filtering process on the image data in which the number of pixels is increased with increasing the number of pixels of the image data by sampling, up to a predetermined count value in response to A counter that sequentially counts a predetermined adjustment value in accordance with the second clock, and the counter A clock generating means for generating a third clock having a frequency corresponding to the number of pixels after synchronization to and converted into the second clock in accordance with the count value of the data are sampled filtering into force by said first sampling means Further, by sampling the image data according to the third clock generated by the clock generation means, the number of pixels of the image data sampled and filtered by the first sampling means is reduced. And a second sampling means.
The present invention is also an image processing method in an image processing apparatus for converting the number of pixels of input image data, wherein a synchronization clock generating means of the image processing apparatus synchronizes with the input image data. Generating a first clock having a higher frequency than the input clock and a second clock having a higher frequency than the first clock and a second clock having a higher frequency than the first clock. And the first sampling means of the image processing apparatus increases the number of pixels of the image data and increases the number of pixels by sampling the input image data according to the first clock. A first sampling step for performing a filtering process on the image data, and a counter of the image processing apparatus, A counting step of cyclically counting up to a predetermined count value, wherein a predetermined adjustment value is sequentially added according to the second clock, and the clock generation means of the image processing device is configured to perform the counting according to the count value. A clock generation step of generating a third clock having a frequency corresponding to the number of pixels after conversion in synchronization with the second clock; and a second sampling means of the image processing device performs sampling by the first sampling step. The image data that has been sampled and filtered by the first sampling step is sampled according to the third clock generated by the clock generation step. A second sampling step that reduces the number of data pixels. The image processing method characterized in that it comprises and.

Claims

An image processing apparatus for converting the number of pixels in the horizontal direction of input image data at a predetermined conversion ratio,
Based on synchronized with the inputted image data input clock, synchronized respectively with the input clock, a first clock of a frequency higher than the input clock, and the frequency is higher than the first clock the second clock A synchronous clock generating means for generating;
First sampling means for increasing the number of pixels of the image data by sampling the input image data according to the first clock;
A counter that counts cyclically until a predetermined count value in response to said second clock, sequentially adding said conversion ratio, a value based on the ratio of the frequency of the second clock and the input clock Counter to
A clock generating means for generating a third clock by gating the second clock each time the count value of said counter reaches said predetermined count value,
The image data sampled by the first sampling unit is sampled in accordance with the third clock generated by the clock generating unit, whereby the image data sampled by the first sampling unit is sampled. the image processing apparatus according to claim and Turkey which have a second sampling means for reducing the number of pixels.

An image processing device that converts the number of pixels of input image data,
Based on synchronized with the inputted image data input clock, a first clock having a frequency higher than the synchronous and the input clock to the input clock, a frequency higher than the synchronous and the first clock to the input clock Synchronous clock generating means for generating a second clock;
A first filter including a filter that increases the number of pixels of the image data by sampling the input image data in accordance with the first clock and performs a filtering process on the image data with the increased number of pixels . Sampling means ,
A counter that cyclically counts up to a predetermined count value, the counter sequentially adding a predetermined adjustment value according to the second clock;
Clock generation means for generating a third clock having a frequency in accordance with the number of pixels after conversion in synchronization with the second clock according to the count value of the counter;
The image data filtered sampled is facilities by the first sampling means, by sampling in accordance with the generated third clock by said clock generating means, is sampled by the first sampling means the image processing apparatus according to claim and Turkey which have a second sampling means for filtering reduces the number of pixels of the image data subjected.

Said first sampling means, an image processing apparatus according to claim 1 or 2, characterized in that it comprises an FIR filter tap coefficients are set for each tap.

The first sampling unit may change the tap coefficient for each first clock so that only one of a plurality of samples sampled at the same phase in the input clock is used. The image processing apparatus according to claim 3 .

The counter is an image processing apparatus according to claim 1, any one of 4, wherein the reset to Turkey the count value for each horizontal line of the image data.

Imaging means for outputting the image data to the first sampling means;
Display means for displaying image data from the second sampling means;
The image processing apparatus according to claim 1, further comprising:

An image processing method in an image processing apparatus for converting the number of pixels in the horizontal direction of input image data at a predetermined conversion ratio,
Synchronizing signal generating means of said image processing apparatus based on an input clock synchronized with the inputted said image data, and synchronization to each of the input clock, a first clock of a frequency higher than the input clock, the first A synchronous clock generating step for generating a second clock having a higher frequency than the clock;
A first sampling step in which a first sampling unit of the image processing apparatus increases the number of pixels of the image data by sampling the input image data according to the first clock;
Counter of the image processing apparatus, a counting step of counting cyclically until a predetermined count value in response to said second clock, and the conversion ratio, the second clock and the frequency of the input clock A count step for sequentially adding values based on the ratio of
A clock generation step of generating a third clock by clock generation means of the image processing apparatus, prior to hear count value to gate the second clock each time becomes the predetermined count value,
The image second sampling means of the processing apparatus, the image data sampled by said first sampling step, the first by sampling in accordance with the generated third clock by the clock generating step image processing method comprising the Turkey second having a sampling step of reducing the number of pixels of the image data sampled by the sampling step.

  An image processing method in an image processing apparatus for converting the number of pixels of input image data,
  The synchronization clock generating means of the image processing device is synchronized with the input clock based on the input clock synchronized with the input image data and with the first clock having a higher frequency than the input clock. And a synchronous clock generating step for generating a second clock having a higher frequency than the first clock;
  The first sampling means of the image processing apparatus samples the input image data in accordance with the first clock, thereby increasing the number of pixels of the image data and increasing the number of pixels. A first sampling step for applying a filtering process to
  A counting step in which the counter of the image processing device cyclically counts up to a predetermined count value, and sequentially adds a predetermined adjustment value according to the second clock;
  A clock generation step in which the clock generation means of the image processing apparatus generates a third clock having a frequency according to the number of pixels after conversion in synchronization with the second clock according to the count value;
  The second sampling means of the image processing device samples the image data sampled and filtered by the first sampling step according to the third clock generated by the clock generation step. A second sampling step for reducing the number of pixels of the image data sampled and filtered by the first sampling step;
An image processing method comprising: