JP2010098176A - Method of manufacturing semiconductor device - Google Patents

Abstract

A device pattern having a desired dimension can be easily formed by etching in each of a sparse part and a dense part.
A step of forming two mask layers 13 and 14 on a metal layer 12 and a sparse part or densely forming device patterns sparsely for each layer with respect to the two mask layers 13 and 14 Forming a mask pattern 13-1 to 13-4, 14-1 to 14-4 by changing one kind of etching parameter for adjusting the CD shift amount in the dense portion to be formed, and mask pattern; The metal layer 12 is etched using 13-1 to 13-4 to form gate electrodes 12-1 to 12-4.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for patterning wirings, electrodes, and the like.

  In a semiconductor device such as a system LSI (Large Scale Integrated circuit), complicated circuits having different wiring densities are formed on one chip. With the progress of miniaturization of semiconductor devices, high processing accuracy is required in the patterning process of device patterns to be densified.

  In the lithography process, etching is performed according to a mask pattern formed on the substrate. The device pattern dimensions (width and aperture) after etching generally differ from the mask pattern dimensions due to CD (Critical Dimension) shift. Although the CD shift amount can be controlled by the etching conditions, it varies depending on whether the device pattern is formed sparsely in the chip (sparse part) or densely formed region (dense part). The phenomenon in which the CD shift amount changes depending on the pattern density and the etching results are different is known as a microloading effect.

  2. Description of the Related Art Conventionally, in etching a mask base film, a method is known in which etching conditions are adjusted to reduce a difference in CD shift amount between a sparse part and a dense part (hereinafter referred to as sparse / dense difference) (for example, see Patent Document 1) .)

Further, a method of controlling the CD shift amount in the sparse part and the dense part by controlling the temperature of the wafer and the flow rate of O ₂ (oxygen) is known (for example, see Patent Document 2).
In addition, a method is known in which the flow rate ratio of the etching gas, SO ₂ (sulfur dioxide) / O ₂ , and the amount of overetching are optimized to eliminate dimensional variations due to mask pattern density ( For example, see Patent Document 3.)
JP-A-8-286381 JP 2007-81216 A JP 2005-26292 A

  However, in the conventional technique, in order to obtain device patterns having desired dimensions in the sparse part and the dense part, it is necessary to simultaneously change two kinds of etching parameters. For this reason, it is difficult to set etching conditions, and it takes man-hours such as detailed investigation in advance on the dependency of the CD shift amount on two types of etching parameters.

  In view of the above points, the present inventors have an object to provide a method of manufacturing a semiconductor device in which a device pattern having a desired dimension can be easily formed in each of a sparse part and a dense part.

  In order to achieve the above object, a semiconductor device manufacturing method including the following steps is provided. This method of manufacturing a semiconductor device includes a step of forming two mask layers on a patterning target layer, and a sparse part or a densely forming device pattern for each layer with respect to the two mask layers. Etching by changing one kind of etching parameters for adjusting the CD shift amount in the dense part to be formed, forming a mask pattern, etching the patterning target layer using the mask pattern, and forming the device pattern Forming.

  A device pattern having a desired dimension can be easily formed in each of the sparse part and the dense part.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 1 is a diagram schematically showing a method for manufacturing a semiconductor device according to the present embodiment.
In the following description, an example in which a gate electrode of a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) is formed by etching will be described.

  First, an insulating layer 11 for a gate insulating film is formed on a semiconductor substrate (for example, a silicon wafer) 10, and a metal layer 12 for forming a gate electrode is formed thereon as a patterning target layer. Then, two mask layers 13 and 14 are formed on the metal layer 12. Further, resist patterns 15-1, 15-2, 15-3, and 15-4 are formed thereon by a lithography technique (FIG. 1A). The resist patterns 15-1 to 15-4 are patterned in the shapes of gate electrodes 12-1, 12-2, 12-3, and 12-4, which are device patterns to be formed (see FIG. 1D). .

  In addition, the resist pattern 15-1 is formed in a sparse part away from the adjacent resist pattern 15-2, and the resist patterns 15-2 to 15-4 are close to each other and formed in a dense part. For example, the distance between the dense resist patterns 15-2 to 15-4 is 70 to 100 nm, and the distance between the sparse resist patterns 15-1 and 15-2 is about 0.7 to 1.0 μm. It is. Here, the dimension of the resist pattern 15-1 in the sparse part is x1, and the dimension of the resist patterns 15-2 to 15-4 in the dense part is x2.

  By using the resist patterns 15-1 to 15-4 as a mask, the mask layer 14 is etched and the resist patterns 15-1 to 15-4 are removed, whereby the mask patterns 14-1, 14-2, and 14- 3, 14-4 are formed (FIG. 1B). The mask layers 13 and 14 are films made of different materials, and the etching of the mask layer 14 is performed under a condition having a high selectivity with respect to the mask layer 13. Details will be described later.

  Next, using the mask patterns 14-1 to 14-4 as a mask, the mask layer 13 is etched, and the mask patterns 14-1 to 14-4 are removed, whereby the mask patterns 13-1, 13-2, 13- are removed. 3 and 13-4 are formed (FIG. 1C). At this time, the mask layer 13 is etched under a condition having a high selectivity with respect to the metal layer 12 so that the metal layer 12 is not etched.

  Finally, using the mask patterns 13-1 to 13-4 as a mask, the metal layer 12 and the insulating layer 11 are etched, and the mask patterns 13-1 to 13-4 are removed. Thereby, gate electrodes 12-1 to 12-4 and gate insulating films 11-1, 11-2, 11-3, and 11-4 are formed (FIG. 1D). Thereafter, although not shown, the drain and source regions are formed by a known doping process or the like to complete the MOSFET.

  When the dimension of the gate electrode 12-1 in the sparse part formed in the step of FIG. 1D is y1, and the dimension of the gate electrodes 12-2 to 12-4 in the dense part is y2, the CD shift amount in the sparse part is x1-y1 and the CD shift amount of the dense part are x2-y2.

  When the dimension of the sparse part gate electrode 12-1 is t1, and the dimension of the dense part gate electrodes 12-2 to 12-4 is t2, the mask layer 13 is set so that the dimensions y1, y2 approach the dimensions t1, t2. , 14 is adjusted in the CD shift amount.

  In the method of manufacturing a semiconductor device according to the present embodiment, when etching the mask layers 13 and 14, one kind of etching parameter for adjusting the CD shift amount in the sparse part or the dense part is changed for each layer. For example, as will be described in detail below, the amount of overetching is changed when the mask layer 14 is etched, and the gas flow rate is changed when the mask layer 13 is etched.

  As described above, when the mask layers 13 and 14 are etched, one kind of etching parameter is changed to control the CD shift amount, so that the etching conditions can be easily set. Therefore, it is possible to easily form the gate electrodes 12-1 to 12-4 having desired dimensions in the sparse part and the dense part.

Next, details of the manufacturing method of the semiconductor device of the present embodiment will be described.
First, the result of examining the change of the CD shift amount when the over-etching amount and the gas flow rate are used as the etching parameters for controlling the CD shift amount is shown.

  Note that polysilicon was used as the metal layer 12 in FIG. 1 described above, and a carbon-based resist film was deposited to 120 nm as the mask layer 13 formed thereon. Furthermore, as a mask layer 14 formed on the mask layer 13, siloxane which is a SiO-based film was formed with a thickness of 30 nm. Upper resist patterns 15-1 to 15-4 were formed with a thickness of 130 nm.

The plasma etching conditions for the metal layer 12 and the mask layers 13 and 14 are shown below.
(Etching conditions for metal layer 12)
Gas flow rate: HBr (hydrogen bromide) / O ₂ = 170/4 sccm
Etching chamber pressure: 6 mTorr
RF (Radio Frequency) power: 385W
Applied voltage: 65V
Overetching amount: 50 sec (fixed)
(Etching conditions for mask layer 13)
Gas flow rate: SO ₂ / O ₂ / He (helium) = x / 30−x / 60 sccm (x is a variable parameter)
Etching chamber pressure: 5 mTorr
RF power: 330W
Applied voltage: 100V
Overetching amount: 20%
(Etching conditions for mask layer 14)
Gas flow rate: CF ₄ (carbon tetrafluoride) / CHF ₃ (methane trifluoride) = 100/20 sccm
Etching chamber pressure: 5 mTorr
RF power: 330W
Applied voltage: 100V
Overetching amount: y% (y is a variable parameter)
Incidentally, in the etching of the mask layer 13 is to change the flow rate of SO _2, for a total flow rate is constant, the flow rate of O ₂ is also changed at the same time.

  The overetching amount is an etching time added after the end point is detected by etching the mask layer 14, and is expressed as a ratio to the time until the end point is detected. The end point is automatically determined using plasma emission analysis.

  The dimensions y1 and y2 of the gate electrodes 12-1 to 12-4 obtained after etching under the above conditions are measured using an SEM (Scanning Electron Microscope) or the like, and the dimensions of the resist patterns 15-1 to 15-4 are measured. From x1 and x2, the etching parameter dependency of the CD shift amount x1-y1 of the sparse part and the CD shift amount x2-y2 of the dense part was obtained.

2A and 2B are diagrams showing the dependency of the CD shift amount on each etching parameter, where FIG. 2A shows the dependency of the CD shift amount on the sparse portion and FIG. 2B shows the dependency of the CD shift amount on the etching parameter.
2A and 2B, the XY axis indicates the SO ₂ flow rate (Sccm) and the overetching amount (%), and the Z axis indicates the CD shift amount (nm).

As shown in FIGS. 2A and 2B, the change in the CD shift amount with respect to the change in the SO ₂ flow rate and the overetching amount, which are etching parameters, is different between the sparse part and the dense part. The increase in the CD shift amount with respect to the increase in the overetching amount is larger in the dense portion than in the sparse portion. Further, the increase in the CD shift amount with respect to the decrease in the SO ₂ flow rate is larger in the sparse part.

Note that, in both the sparse part and the dense part, the surface in the graph showing the dependency of the CD shift amount on the etching parameter is almost flat and can be expected to have a linear correlation. This means that an equation for calculating the optimum etching parameter value is obtained by a linear expression. Therefore, the model can be easily constructed, and from the viewpoint of dimensional control, the SO ₂ flow rate and the overetching amount can be said to be ideal etching parameters.

FIG. 3 is a diagram showing the dependence of the CD shift amount on the respective etching parameters.
The XY axis shows the SO ₂ flow rate (Sccm) and the overetching amount (%), and the Z axis shows the CD shift amount (nm) density difference (difference in CD shift amount between the sparse part and the dense part). Yes.

It was found that the change range of the density difference of the CD shift amount is about −3 to +3 nm with respect to the change region of the selected etching parameters (SO ₂ flow rate and overetch amount). This is a value that is almost satisfactory as a range for correcting the density difference, which is expected to be necessary in the current semiconductor device manufacturing process.

  From the results shown in FIG. 2 and FIG. 3, a model for obtaining an etching condition necessary for obtaining a desired dimension is obtained by linearly approximating the dependence of the CD shift amount and the density difference of the sparse part on the etching parameter. The following equation was constructed.

The overetching amount of the SiO film that is the mask layer 14 is a (%), and the SO ₂ flow rate in the etching of the mask layer 13 is b (sccm). Assuming that the CD shift amount of the sparse part is si (nm) and the density difference of the CD shift amount is ds (nm), si and ds can be expressed by the following approximate expression from the results shown in FIGS.

si = 0.0465 * a-1.265 * b + 41.73 (1)
ds = −0.0135 × a−0.414 × b + 8.37 (2)
From these equations (1) and (2), the overetching amount a and the SO ₂ flow rate b can be calculated by the following equations.

a = −0.371 × si−1.281 × ds + 26.21 (3)
b = 11.41 * si-34.81 * ds-184.5 (4)
By setting the etching parameters using such equations (3) and (4), gate electrodes 12-1 to 12-4 having desired dimensions can be obtained in the sparse part and the dense part, respectively.

In the above description, the formulas (3) and (4) are constructed based on the CD shift amount of the sparse part, but it may be based on the CD shift amount of the dense part.
FIG. 4 is a diagram showing a configuration example of an etching apparatus to which the semiconductor device manufacturing method of the present embodiment is applied and its control system.

  The etching apparatus 20 includes gas supply units 21a, 21b, and 21c that supply gas used for etching, a flow rate control unit 22 that controls a gas flow rate, and an etching chamber 23.

The etching chamber 23 has gas inlets 24 a, 24 b, 24 c through which gas is introduced into the etching chamber 23, and an upper electrode 25 and a lower electrode 26.
The upper electrode 25 is connected to the RF power source 27, and the lower electrode 26 is connected to the bias power source 28. The RF power source 27 and the bias power source 28 are grounded.

  Furthermore, the etching apparatus 20 includes an etching control unit 29 that controls the flow rate control unit 22, the RF power source 27, or the bias power source 28 in accordance with the input etching conditions.

  As the control system, for example, a control computer 30 that performs calculation of optimum etching conditions using equations (3) and (4) stored in the recording medium 30a and a production integrated system 31 are provided.

  The production integrated system 31 includes one or a plurality of computers, and the dimensions x1 and x2 of the resist patterns 15-1 to 15-4 measured by the length measuring device 32 and the gate electrodes 12-1 to 12-4. , Y1 and y2 are input and transferred to the control computer 30. In addition, the etching control unit 29 is notified of the etching conditions calculated by the control computer 30 and other etching conditions.

The length measuring device 32 is, for example, an SEM.
Hereinafter, the flow of the etching process will be described.
FIG. 5 is a flowchart for explaining the flow of the etching process.

First, the lengths x1 and x2 of the resist patterns 15-1 to 15-4 formed as shown in FIG. 1A are measured by the length measuring device 32 (step S1).
Next, the control computer 30 receives, for example, input of target values (the above-described dimensions t1 and t2) of the gate electrodes 12-1 to 12-4 of the sparse part and the dense part from the user (step S2). The control computer 30 determines the CD shift amount (si = x1−t1) of the sparse part necessary to obtain the input target value and the density difference (ds = (x1−t1) − (x2−2) between the CD shift amounts. t2)) is calculated (step S3).

Then, the control computer 30 substitutes si and ds obtained in the process of step S3 into the equations (3) and (4) to obtain the optimum overetching amount a ( %) And the SO ₂ flow rate (sccm) are calculated (step S4).

  The production integration system 31 sets the etching conditions calculated in step S4 in the etching control unit 29 together with the other etching conditions described above such as the pressure in the etching chamber and the RF power (step S5).

Thereafter, the etching process as shown in FIG. 1 is performed by the etching apparatus 20 (step S6). In the etching process of the mask layer 14 shown in FIG. 1A to FIG. 1B, the etching control unit 29 controls the RF power source 27 so that the over-etching amount a obtained by Expression (3) is obtained. Like that. Further, in the etching process of the mask layer 13 shown in FIGS. 1B to 1C, the etching control unit 29 controls the flow rate control unit 22 to obtain the SO ₂ flow rate obtained by the equation (4). b. Thereafter, the etching of the metal layer 12 and the insulating layer 11 is performed under the above-described etching conditions (gas flow rate: HBr / O ₂ = 170/4 sccm, etching chamber pressure: 6 mTorr, RF power: 385 W).

With the above etching process, it is possible to form the gate electrodes 12-1 to 12-4 having desired dimensions t1 and t2 after the etching in both the sparse part and the dense part.
As described above, in the semiconductor device manufacturing method of the present embodiment, even if the dimensions of the resist patterns 15-1 to 15-4 formed in the lithography process are not constant, the etching conditions are optimized. It becomes possible to process the gate electrodes 12-1 to 12-4 in the sparse part and the dense part into desired dimensions. As a result, process tolerance is increased in the lithography process, and the operation rate of the lithography apparatus can be improved and the maintenance process can be reduced.

  In addition, since only one etching parameter is changed when etching one layer, a desired etching condition is easily and quickly obtained as compared with a case where a plurality of etching parameters are changed simultaneously in one layer. be able to.

  This is because in the case where a plurality of etching parameters are changed in one layer, it is necessary to perform preliminary verification by trial manufacture under all etching conditions in consideration of the influence of changes in the respective etching parameters. Specifically, assuming five conditions as the set value of one etching parameter, a prototype of 5 × 5 is required when changing two types of etching parameters in one layer. On the other hand, in the manufacturing method of the semiconductor device of this embodiment, 5 × 2 trial manufactures for two layers are sufficient.

  Although it is conceivable that the etching characteristics fluctuate due to maintenance of the etching apparatus or the like, since only one etching parameter is changed per layer, the etching conditions can be easily adjusted. Therefore, the product processing stoppage period in the etching apparatus can be shortened.

  Further, the layers for changing the etching conditions are only the mask layers 13 and 14, and the etching of the metal layer 12 is performed using the constant etching conditions regardless of the dimensions to be controlled. For this reason, the etching damage to the metal layer 12 can be suppressed, and the shape of the side walls of the gate electrodes 12-1 to 12-4, the etching selectivity with respect to the base, and the thickness reduction of the base due to excessive etching can be stably maintained. .

  By the way, the etching characteristics for the processing between lots fluctuate due to the influence of the deposited film on the inner wall of the etching chamber 23 as shown in FIG. Further, even within a lot, etching characteristics may vary from wafer to wafer due to a phenomenon such as an increase in wafer temperature during plasma processing. Such a variation caused by a change in the state of the process apparatus is called a process drift.

  6A and 6B are diagrams illustrating an example of a change over time of a CD shift amount and a density difference of the CD shift amount, in which FIG. 6A shows a change over time in a CD shift amount between a sparse part and a dense part, and FIG. It is a figure which shows the time-dependent change of the density difference of shift amount.

In FIG. 6A, the vertical axis represents the CD shift amount, and the horizontal axis represents the date and time. The solid line shows the change over time in the CD shift amount at the sparse part, and the dotted line shows the change over time in the CD shift amount at the dense part.
In FIG. 6B, the vertical axis represents the CD shift amount density difference, and the horizontal axis represents the date and time.

As shown in FIG. 6A, the CD shift amount changes with time in both the sparse part and the dense part, the change amount is different between the sparse part and the dense part, and the density difference is a graph as shown in FIG. 6B. Indicated.
An etching method in consideration of the change over time of the CD shift amount as described above will be described below.

FIG. 7 is a flowchart for explaining the flow of the etching process in consideration of the change with time of the CD shift amount.
First, as shown in FIG. 6, the change over time of the CD shift amount and the density difference of the CD shift amount is recorded on the recording medium 30a (step S10). When optimizing the etching conditions for each lot, when optimizing for each lot and for each wafer, the CD shift amount at the sparse part and the dense part is obtained for each wafer. Record changes in density over time.

Next, the control computer 30 predicts the next value based on the CD shift amount and the temporal change in the density difference of the CD shift amount (step S11).
For example, the moving average is obtained for each of the CD shift amount and the density difference of the CD shift amount in the processing from the recent processing result back to the processing of a plurality of lots or a plurality of wafers. Also, a weighted average that weights recent processing results may be used. The predicted value thus obtained is the density difference between the CD shift amount and the CD shift amount when a certain etching condition is assumed. It is desirable that the assumed etching conditions are a central condition when changing the etching parameters or an etching condition frequently used in actual processing.

  Next, the control computer 30 adjusts the correlation model of the CD shift amount and the density difference of the CD shift amount with respect to the etching parameter as shown in FIGS. 2 and 3 using the predicted value obtained in the process of step S11. (Step S12).

  For example, from FIG. 2 and FIG. 3, the CD shift amount and the density difference of the CD shift amount under the constant etching conditions used for recording the change over time are obtained, and these values and the predicted value obtained in the process of step S11 are obtained. To adjust the constructed correlation model. At that time, the intercept is adjusted on the assumption that the inclination in the graphs of FIGS. 2 and 3 does not change. In accordance with this, the equations (3) and (4) are corrected. Or you may make it rebuild the correlation model of FIG. 2, FIG. 3 obtained by the preliminary | backup investigation according to the newest process result.

The processing of steps S13 to S18 is the same as the processing of steps S1 to S6 in FIG.
As described above, by adjusting the correlation model in consideration of the CD shift amount and the change in density of the CD shift amount with time, the representative value of each lot for each lot and the representative of each wafer for each wafer. The dimensions of the sparse part and dense part as values can be controlled with high accuracy. As a result, not only the lithography but also the process tolerance in etching is expanded, and an improvement in the apparatus operating rate and a reduction in maintenance man-hours can be expected also in the etching apparatus.

  In the above description, the case where the etching conditions are changed in consideration of the CD shift amount and the temporal change in the density difference of the CD shift amount has been described. However, in consideration of the electrical characteristics of the device in which the dimension after etching affects. Etching conditions may be set.

  For example, for gate electrode etching, as the gate length decreases, the threshold voltage of the transistor decreases and the on and off currents increase. Regarding the etching in the wiring process, the wiring resistance decreases as the hole diameter or the line width increases. Based on such a correlation between the electrical characteristics and dimensions of the device, a processing dimension for obtaining desired electrical characteristics is obtained.

  Specifically, the electrical characteristics of the device having a correlation with the sparse part and / or the dense part are extracted in advance. Based on the difference between the target value for the extracted electrical characteristic and the actual measurement value, an optimum dimension after etching is obtained. Then, the CD shift amount necessary for obtaining the optimum dimension in the next lot processing or wafer processing and the density difference of the CD shift amount are calculated, and the calculated values are substituted into the equations (3) and (4) to obtain the etching parameters. To decide.

By changing the etching conditions according to the electrical characteristics of the device, the electrical characteristics of the device can be stabilized.
In the above description, as shown in FIG. 1, the case where the mask layers 13 and 14 to be etched are two layers on the metal layer 12 has been described. However, the number of layers to be etched is three or more. May be. If the dimensions of the sparse and dense gate electrodes 12-1 to 12-4 can be controlled using the two mask layers 13 and 14, the dimensions can be selected by selecting appropriate etching conditions when etching the other layers. It is possible to improve the distribution in the wafer surface other than the above. In addition, when the range in which the CD shift amount changes with respect to the usable etching parameter change region is small, the range in which the CD shift amount changes can be widened by changing the etching conditions of other layers.

In the above description, the etching parameters for adjusting the CD shift amount are the over-etching amount when the mask layer 14 is etched and the SO ₂ flow rate when the mask layer 13 is etched. However, the present invention is not limited to this. Depending on the etching conditions and the material of the film to be etched, other etching parameters (pressure during etching, wafer temperature, power of bias power source, etc.) may be used so that the CD shift amount can be controlled effectively. .

  In order to select an etching parameter effective for dimensional control, it is necessary that the CD shift amounts of the sparse part and the dense part change according to the increase or decrease of the etching parameter. In addition, it is desirable that the amount of change in the CD shift amount in the sparse part is different from the amount of change in the CD shift amount in the dense part so that the density difference in the CD shift amount changes.

  FIG. 8 is a diagram illustrating an example of a change in the CD shift amount of the sparse portion and the dense portion with respect to a change in one etching parameter. 8A, 8B, and 8C show the relationship between the three types of etching parameters and the CD shift amount. The vertical axis represents the CD shift amount, and the horizontal axis represents the etching parameter. The solid line indicates the relationship between the etching parameter and the CD shift amount in the sparse part, and the dotted line indicates the relationship between the etching parameter and the CD shift amount in the dense part.

  FIG. 8A shows a case where straight lines representing the relationship between the CD shift amount of the sparse part and the dense part and the etching parameter intersect within the effective change range of the etching parameter.

  When such an etching parameter is used, it is possible to control whether the density difference is positive or negative by selecting an etching parameter smaller than the intersection or an etching parameter larger than the intersection.

  FIG. 8B shows a case where the straight line representing the relationship between the CD shift amount of the sparse part and the dense part and the etching parameter does not intersect within the effective change range of the etching parameter. In addition, as the etching parameter increases, the change amount of the CD shift amount is larger in the sparse part.

  When such an etching parameter is changed during the etching of a certain layer and used for adjusting the CD shift amount, in other layers, the change amount of the CD shift amount is increased as the etching parameter increases. An etching parameter is selected so that the portion becomes larger. By using the two types of etching parameters obtained in this way, the dimensions of the device pattern to be formed can be controlled in each of the sparse part and the dense part.

  FIG. 8C shows a case where straight lines representing the relationship between the CD shift amount of the sparse part and the dense part and the etching parameter are parallel to each other. When etching a certain layer, the density difference of the CD shift amount cannot be controlled only by adjusting the etching parameters showing the dependency as shown in FIG. Therefore, when the other layers are etched, the difference in density of the CD shift amount can also be controlled by adjusting the etching parameters showing dependency as shown in FIG. 8B. However, it is effective only when the controlled density difference is either positive or negative.

  In the above description, the case where the gate electrode in the MOSFET is formed by etching has been described as an example. However, the present invention is not limited to this. For example, the present invention is applicable to all etching processes that can find an etching parameter that can change the CD shift amount, such as a wiring formation process.

It is a figure which shows the outline of the manufacturing method of the semiconductor device of this Embodiment. It is a figure which shows each etching parameter dependence of CD shift amount, (A) is a figure which shows the etching parameter dependence of CD shift amount in a sparse part, and (B). It is a figure which shows the dependence with respect to each etching parameter of the density difference of CD shift amount. It is a figure which shows the structural example of the etching apparatus and its control system to which the manufacturing method of the semiconductor device of this Embodiment is applied. It is a flowchart explaining the flow of an etching process. It is a figure which shows an example of a time-dependent change of CD shift amount and the density difference of CD shift amount, (A) shows the time-dependent change of CD shift amount in a sparse part and a dense part, (B) is the density of CD shift quantity. It is a figure which shows the time-dependent change of a difference. It is a flowchart explaining the flow of the etching process which considered the time-dependent change of CD shift amount. It is a figure which shows the example of the change of CD shift amount of a sparse part and a dense part with respect to the change of one etching parameter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Insulating layer 11-1 to 11-4 Gate insulating film 12 Metal layer 12-1 to 12-4 Gate electrode 13, 14 Mask layer 13-1 to 13-4, 14-1 to 14-4 Mask pattern 15-1 to 15-4 resist pattern

Claims (6)

Forming two mask layers on the patterning target layer;
For each of the two mask layers, for each layer, etching is performed by changing one kind of etching parameter for adjusting the CD shift amount in a sparse part where a device pattern is sparsely formed or a dense part where a device pattern is densely formed, Forming a mask pattern;
Etching the patterning target layer using the mask pattern to form the device pattern; and
A method for manufacturing a semiconductor device, comprising:   Based on the step of receiving an input of a target value of the dimensions of the device pattern in each of the sparse part and the dense part, the input target value, and the dimension of the resist pattern formed on the uppermost mask layer The method of manufacturing a semiconductor device according to claim 1, further comprising: calculating the required CD shift amount.   In order to obtain the required CD shift amount by obtaining in advance a change in the CD shift amount or a difference between the sparse portion and the dense portion of the CD shift amount with respect to a change in the etching parameter by measurement with a length measuring device. The method for manufacturing a semiconductor device according to claim 1, wherein an equation for obtaining the etching parameter is constructed, and the etching parameter is determined based on the equation.   A step of recording a change with time of the difference between the sparse part and the dense part of the CD shift amount or the CD shift amount, and the CD shift amount or the CD shift in the next etching process based on the change with time. Predicting the difference between the sparse part and the dense part of the amount, and based on the predicted CD shift amount or the difference between the sparse part and the dense part of the CD shift amount next time The method for manufacturing a semiconductor device according to claim 1, wherein the etching conditions are adjusted.   The CD shift amount or the difference between the sparse part and the dense part of the CD shift amount is calculated so as to be the size of the device pattern necessary for obtaining desired electrical characteristics, and the CD shift amount or 5. The method of manufacturing a semiconductor device according to claim 1, wherein the etching parameter is determined based on a difference between the sparse part and the dense part of the CD shift amount. 6.   The method of manufacturing a semiconductor device according to claim 1, wherein the etching parameter is an overetching amount or a gas flow rate.

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