JP2010098064A - Laminated wiring board and method for manufacturing the same - Google Patents

Abstract

To provide a laminated wiring board suitable for obtaining a thin package structure that incorporates a thin semiconductor element having a low contact resistance and is easy to assemble, and a method for manufacturing the same.
In a laminated wiring board in which a semiconductor element is embedded and bonded and sealed between a first substrate material and a second substrate material arranged facing each other, the first substrate material is disposed on one surface of an insulating substrate. A wiring board on which a wiring layer is formed, and a conductive paste penetrating electrode that penetrates the insulating substrate, has one end surface connected to the wiring layer and the other end surface exposed on the other surface of the insulating substrate. An electrode pad formed on a part of the surface, an inorganic insulating film on the surface of the semiconductor substrate having a contact hole for the electrode pad, a rewiring layer thereon, and a contact hole for the inorganic insulating film formed on the surface of the rewiring layer The organic insulating film and a protective conductive layer covering the surface of the rewiring layer in the contact hole are provided, and the other end face of the through electrode is connected to the rewiring layer through the protective conductive layer.
[Selection] Figure 1

Description

  The present invention relates to a multilayer wiring board and a method for manufacturing the same, and more particularly to a multilayer wiring board suitable for reducing the thickness of a built-in semiconductor element and package substrate and a method for manufacturing the same.

  In the printed circuit board field, a package substrate for electrically connecting an element and an external circuit or device is used to transmit a signal or supply power to an element manufactured by a wafer process such as a semiconductor IC / LSI element. ing. A conventional package substrate has been used in which an individualized IC chip is mounted on a circuit substrate larger than the IC chip on which the rewiring layer is formed and wire-bonded. With the recent increase in the number of functions of portable electronic devices, further miniaturization of semiconductor devices is required, and the demand for higher integration of IC / LSI has been focused on miniaturization of packages. .

  Under such circumstances, in recent years, a wafer level chip scale package (WLCSP) constituted only by a built-up method has been developed as an ultimate small package. This WLCSP is a method of building up wiring directly on an IC using a Si wafer as a base, and the package size is minimized to the same extent as the IC chip size. However, since the number of terminals that can be arranged on the package is restricted by the rule of the terminal pitch of the mounting board, the application of WLCSP is limited to an element having a small number of pins.

  As a technique for solving the restriction of WLCSP, for example, a package substrate technique called EWLP (Embedded Wafer Level Package) as disclosed in Patent Document 1 is known. However, this EWLP uses a built-up method based on repeated processes such as a resist mask and plating, which requires a large number of processes and a high manufacturing cost. There is a problem that a large amount of heat history is applied to the insulating substrate resin layer, and the resin is liable to deteriorate.

  On the other hand, as seen in Patent Document 2, a circuit wiring layer and an adhesive layer are provided on both surfaces of an insulating substrate, and a large number of wiring substrates are provided with through electrodes made of conductive paste serving as interlayer conductive vias. There is a technique for obtaining a multilayer wiring board structure by batch-bonding the wiring boards by thermocompression bonding.

  The present inventors have developed a package type multilayer wiring board capable of incorporating components using such a conductive paste through electrode and a batch thermocompression bonding technique. An example of the developed technology will be described with reference to FIGS.

  The structure of this prior art will be schematically described with reference to FIG. 6. An upper wiring substrate 71 is made of an insulating substrate 71a, a circuit wiring layer 71b on the upper surface thereof, and a conductive paste made through the insulating substrate 71a. A through electrode 71c is provided. The lower wiring substrate 72 includes an insulating substrate 72a and a circuit wiring layer 72b on the lower surface thereof. The semiconductor element 73 between the upper and lower wiring substrates 71 and 72 is electrically connected to the wiring layer 71b through the through electrode 71c and embedded in an adhesive layer 74 that bonds the wiring substrates.

  A detailed structure of the semiconductor element 73 and a manufacturing method thereof will be described with reference to FIG. First, in the process of FIG. 7A, a large number of element regions (not shown) corresponding to the semiconductor elements 73 are formed on the upper surface of the semiconductor wafer 73A by a selective diffusion technique or the like. An electrode pad 73b is formed. Further, an inorganic insulating film 73c made of silicon oxide or silicon nitride having contact holes for the electrode pads 73b is formed on the upper surface of the wafer 73A. Next, as shown in FIG. 7B, a liquid photosensitive polyimide precursor is spin-coated, and a first contact hole 73d exposing the pad 73b is formed by photolithography, followed by baking to form a first organic insulating film 73e. Form. Then, as shown in FIG. 7C, a rewiring layer 73f patterned by, for example, a copper plating layer is formed on each electrode pad 73b and the first organic insulating film 73e by a semi-additive method. In FIG. 7D, similarly to the case of forming the first organic insulating film 73e, the liquid photosensitive polyimide precursor is spin-coated again on the upper surface of the wafer, and the second contact corresponding to a part of the rewiring layer 73f. A second organic insulating film 73h having a hole 73g is formed. Next, after polishing the back surface of the wafer 73A to thin the wafer, a plurality of individual semiconductor elements 73 having a semiconductor substrate 73a that has been thinned by dicing as shown in FIG. Take out. The thinning of the semiconductor element is indispensable with the market demand for thinning the package substrate.

  By the way, although an assembly process diagram of the package substrate incorporating the semiconductor element 73 is omitted, in this assembly process, each semiconductor element 73 picked up one by one by the vacuum chuck of the mounter equipment is re-wired. The layer 73f is temporarily fixed to the upper wiring substrate 71 with an adhesive layer material in a state where the layer 73f is pressed against the through electrode 71c (see FIG. 6). After that, the upper wiring board 71 with the semiconductor element 73 is aligned and laminated on the lower wiring board 72 with the adhesive layer 74 interposed therebetween, and the element is formed by batch thermocompression bonding in a direction sandwiching the laminated body. A built-in package substrate is formed.

  In such a prior art, many organic insulating films, that is, the first and second organic insulating films 73e and 73h are formed on the inorganic insulating film 73c, and these organic insulating films are cured and contracted in the formation process. Therefore, tensile stress is generated on the upper surface side of the semiconductor substrate 73a. Accordingly, if the semiconductor substrate 73a is sufficiently thick, it can maintain flatness against the tensile stress, but if the semiconductor substrate 73a is thinned, the semiconductor substrate 73a cannot withstand the tensile stress and easily causes chip warpage.

  If there is such a chip warp, the vacuum chuck cannot attract (pick up) the element during the package substrate assembling process, which may increase the number of cases that hinder the mounting operation. Even if it can be picked up, when the semiconductor element 73 is positioned and pressed against the through electrode 71c and mounted as described above, there is a possibility that the alignment accuracy may be lowered or the semiconductor element 73 may be broken by the pressing force. is there. As described above, it is difficult to obtain both a thin semiconductor device and a package substrate and a reliable and stable mounting operation.

  In addition, a portion of the surface of the rewiring layer 73f exposed from the second contact hole 73g of the second organic insulating film 73h, that is, a contact portion surface for connection to the through electrode 71c is subjected to various heating and chemical treatments. During the package substrate assembling process including the above processes, the package substrate is exposed, and is liable to be oxidized and corroded to increase the contact resistance. When the surface oxidation and corrosion are significant, there is a problem that an abnormal increase in circuit resistance value or poor conduction may occur.

This problem also occurs in the techniques of Patent Documents 1 and 2.
Japanese Patent Laid-Open No. 2004-95836 Japanese Patent Laid-Open No. 2003-318546

  The present invention solves the above-mentioned conventional problems, and in particular, has a thinned package structure that incorporates a thinned semiconductor element with reduced contact resistance and excellent flatness, and is easy to assemble. It is an object of the present invention to provide a laminated wiring board suitable for obtaining and a manufacturing method thereof.

  The present invention according to claim 1 is a multilayer wiring board in which a semiconductor element is embedded and sealed between a first substrate material and a second substrate material that are arranged facing each other, wherein the first substrate material is A wiring substrate having a wiring layer formed on one surface of the insulating substrate, and a conductive paste that penetrates the insulating substrate, has one end connected to the wiring layer, and the other end exposed on the other surface of the insulating substrate. The semiconductor element includes an electrode pad formed on a part of the surface of the semiconductor substrate, an inorganic insulating film formed on the surface of the semiconductor substrate having a contact hole for the electrode pad, A rewiring layer formed on an inorganic insulating film and connected to the electrode pad, an organic insulating film having a contact hole for the rewiring layer and formed on a surface of the rewiring layer, and the contact of the organic insulating film Redistribution in the hole It is configured to include a protective conductive layer covering the layer surface, the other end face of the through electrode, characterized in that connected to the redistribution layer through the protective conductive layer.

  According to a second aspect of the present invention, in the multilayer wiring board according to the first aspect, the protective conductive layer is at least one selected from nickel, gold, silver, platinum, tin, palladium, and alloys thereof. It is characterized by including one.

According to a third aspect of the present invention, in the multilayer wiring board according to the first or second aspect,
The multilayer wiring board according to claim 1, wherein the rewiring layer is formed of a copper plating layer, and the organic insulating film is formed using a photosensitive organic material as a material.

  The present invention according to claim 4 is a method of manufacturing a laminated wiring board in which a semiconductor element is built in and bonded and sealed between a first substrate material and a second substrate material that are disposed facing each other, and the semiconductor element (A-1) forming a plurality of element regions corresponding to a plurality of semiconductor elements on the surface of the semiconductor wafer, forming electrode pads for each of the element areas, and forming first contact holes for the electrode pads. Forming an inorganic insulating film on the wafer surface; (A-2) forming a rewiring layer connected to the electrode pad through the first contact hole on the inorganic insulating film; 3) a step of forming a photosensitive organic material film on the wafer so as to cover the inorganic insulating film and the rewiring layer; and (A-4) subjecting the photosensitive organic material film to photolithography to perform the rewiring. Second contact for the layer A step of forming an organic insulating film having a second contact hole on the surface of the wafer by forming a hole and performing a baking process; and (A-5) protecting the rewiring layer surface in the second contact hole. A step of coating with a layer, and (A-6) a step of performing dicing after each wafer inspection of each element region and taking out each semiconductor element separated corresponding to each element region. The step of incorporating and sealing the semiconductor element between the substrate material and the second substrate material includes (B) a wiring layer patterned on one surface of the insulating substrate, an adhesive layer formed on the other surface, And a first substrate material having a through electrode made of a conductive paste that penetrates the insulating substrate and the adhesive layer, has one end face connected to the wiring layer, and the other end face corresponding to a protective conductive layer on the rewiring layer of the semiconductor element. And (C) the process of preparing Aligning and connecting the other end surface of the electrode to the rewiring layer of the semiconductor element, and temporarily bonding the semiconductor element to the adhesive layer to integrate with the first substrate material; and (D) Providing a second substrate material facing the first substrate material; and (E) aligning and superimposing the semiconductor element integrated with the first substrate material on the second substrate material; (F) a step of collectively heating and pressing the first substrate material and the second substrate material in an overlapping direction, surrounding the semiconductor element with the adhesive layer, and bonding the first and second substrate materials to each other; It is characterized by that.

  According to the structure and the manufacturing method of the multilayer wiring board of the present invention, since the contact portion of the rewiring layer with respect to the through electrode is covered with the protective conductive layer, it is oxidized by various heating and chemical treatment in the package substrate assembly process. Further, it is possible to prevent the occurrence of corrosion and corrosion, to maintain a flatness and to incorporate a thinned semiconductor element, and to obtain a thin package substrate structure that can be easily assembled.

  Hereinafter, an embodiment of the multilayer wiring board of the present invention will be schematically described with reference to FIG.

  The first substrate material 1 constituting the upper surface side of the package type laminated wiring substrate is a first insulating substrate 1a made of, for example, a polyimide resin film and a first copper foil patterning formed on one surface (upper surface) thereof. A first wiring board having a wiring layer 1b and a plurality of first through holes made of a conductive paste provided through the first insulating substrate 1a and having one end (upper end) connected to a part of the first wiring layer 1b. An electrode 1c is provided.

  The second substrate material 2 constituting the lower surface side of the multilayer wiring board is disposed facing the lower side of the first substrate material 1 so as to face the second insulating substrate 2a made of, for example, a polyimide resin film and one surface (lower surface). ) And a second wiring substrate having a second wiring layer 2b made of copper foil patterned, and one end (lower end) connected to a part of the second wiring layer 2b provided through the second insulating substrate 2a. A plurality of second through-electrodes 2c made of the conductive paste formed are provided.

  The semiconductor element 3 disposed between the first substrate material 1 and the second substrate material 2 is composed of, for example, a semiconductor IC chip located at the center of the left and right in the figure, and is an upper surface of a semiconductor substrate 3a made of silicon, for example. The electrode pad 3b formed on the substrate, the inorganic insulating film 3c made of an inorganic insulator made of silicon oxide or silicon nitride having a contact hole for the electrode pad 3b, and patterned on the electrode pad 3b and the inorganic insulating film 3c, for example A plurality of copper rewiring layers 3d and an organic insulating film 3f covering the surface of the inorganic insulating film 3c and having contact holes 3e for the rewiring layer 3d are provided. A protective conductive layer 3g is covered on the surface of the contact portion (also referred to as a land portion) exposed in the contact hole 3e in the surface of the rewiring layer 3d. The protective conductive layer 3g is made of a material having a good conductivity and serving as an antioxidant conductive layer and a corrosion-resistant conductive layer for preventing oxidation and corrosion of the surface of the rewiring layer 3d. As the material, a material containing at least one selected from nickel, gold, silver, platinum, tin, palladium, and alloys thereof can be used. More specifically, in the protective conductive layer 3g, electroless nickel (Ni) plating is applied to the contact portion surface of the rewiring layer 3d made of, for example, copper plating, and then a gold (Au) plating layer is formed. Can be obtained. Of the plurality of first through electrodes 1c of the first substrate material 1, two first through electrodes 1c at the left and right central portions in the drawing are arranged at a pitch that can face the respective rewiring layers 3d. The lower end portions of the contact holes 3e are electrically connected to the redistribution layer 3d through the protective conductive layer 3g.

  The third substrate material 4 disposed between the first substrate material 1 and the second substrate material 2 is, for example, a wiring layer 4b, 4c made of copper foil, which is patterned on both surfaces of the insulating substrate 4a. The wiring layer 4b is composed of a double-sided wiring type intermediate wiring board having a through-hole type interlayer conductive path 4d between the wiring layers 4b and 4c. And the said 3rd board | substrate material 4 (intermediate wiring board) has the opening part 4e in which the said semiconductor element 3 is inserted. The opening 4e is formed to penetrate the insulating substrate 4a with a slightly larger diameter than the outer diameter of the semiconductor element, and has a shape and size that surrounds the entire periphery of the semiconductor element 3 with a gap. Has been.

  The adhesive layer material 5 filled in the gaps between the first to third substrate materials 1, 2, 4 and the opening 4e is formed by bonding these members 1, 2, 4 together. The semiconductor element 3 is embedded and sealed in the adhesive layer material 5 (details of materials and forming methods will be described later).

  The wiring layers 4b and 4c on the upper and lower surfaces of the third substrate material 4 (intermediate wiring substrate) are formed on the through electrodes 1c of the first substrate material 1 and the second substrate material 2 which are opposed to each other at the left and right positions in the drawing. Each is connected to the through electrode 2c.

  In this way, each of the first to third substrate materials 1, 2, and 4 is formed of a circuit wiring board, and the first and second substrate materials 1 and 2 are included in a package type multilayer wiring substrate. For internal circuit elements including semiconductor elements, interlayer conductive vias to the wiring layers 1b and 2b on the upper and lower surfaces of the package can be formed through the through electrodes 1c and 2c. Therefore, the package can be reduced in thickness and size, and can easily cope with an increase in the number of wirings accompanying an increase in the functionality of the semiconductor element and an increase in the number of built-in elements. Further, when each of the insulating substrates having an area that is as wide as possible than the chip area of the semiconductor element 3 is used, the wiring layers of the first to third substrate materials 1, 2, and 4 are arranged in the outer direction of the semiconductor element 3. Therefore, it is easy to cope with the higher functionality and the increase in the number of built-in elements.

  The thickness of the third substrate material 4 is approximately the same as the thickness of the semiconductor element 3 and is parallel to the first and second substrate materials 1 and 2 in a batch thermocompression bonding process to be described later. It can also serve as a spacer for performing adhesion by the adhesive layer material 5 while maintaining the properties.

  By the way, the semiconductor element 3 has various electrode pads according to the number of built-in elements and the number of circuit functions. Therefore, each wiring layer formed on each of the substrate materials 1, 2, 4 corresponding to the type of the semiconductor element 3 to be incorporated has the number of wiring layers, the wiring pitch, the wiring length, etc. according to the type. It can also be referred to as a redistribution layer formed in a defined manner.

  In the embodiment of the present invention, the first and second substrate materials 1 and 2 are constituted by so-called single-sided wiring substrates, and the third substrate material 4 is constituted by a double-sided wiring substrate. The board materials 1 and 2 may be appropriately changed such as a double-sided wiring board, or the third board material 4 may be a single-sided wiring board. Each of the board materials 1, 2, and 4 may be at least one surface of an insulating substrate. It is sufficient that a wiring layer is formed on the substrate.

  Although not shown, the third substrate material 4 has a shape having an extended portion obtained by extending the insulating substrate 4a to the outside of the package type multilayer wiring board. By providing an external terminal layer connected to the wiring layer in the package, a structure that can be electrically connected to an external connector or the like can be provided. In this case, the third substrate material 4 functions not only as an intermediate wiring board for circuit configuration in the package, but also as a flat cable having input / output terminals for external circuits such as power supply terminals and electronic devices. Can have.

  Next, the manufacturing method of the said multilayer wiring board in one Embodiment of this invention is demonstrated with reference to FIGS. 2 is a cross-sectional view illustrating the manufacturing process of the semiconductor element 3, FIG. 3 is a cross-sectional view illustrating the manufacturing process of the first substrate material 1, FIG. 4 is a cross-sectional view illustrating the manufacturing process of the third substrate material 4, and FIG. It is sectional drawing for demonstrating the assembly method of this multilayer wiring board.

  Referring to FIG. 2, the method of manufacturing the semiconductor element 3 will be described. In the step of FIG. 2A, for example, an IC / LSI or the like is formed on the upper surface of a semiconductor wafer 3A made of silicon by a selective diffusion technique or the like. A large number of unit element regions (not shown) corresponding to the semiconductor element 3 are formed, and a plurality of element electrode pads 3b are formed for each element region. In addition, an inorganic insulating film 3c made of silicon oxide or silicon nitride having a contact hole for each electrode pad 3b is formed on the upper surface of the wafer 3A.

  Next, as shown in FIG. 2B, a rewiring layer 3d as a conductor circuit patterned by, for example, a copper plating layer is formed on each electrode pad 3b and the inorganic insulating film 3c by a semi-additive method.

  Thereafter, as shown in FIG. 2C, for example, a liquid photosensitive polyimide precursor is spin-coated over the entire upper surface of the wafer 3A, and a part of the surface of each rewiring layer 3d is exposed by photolithography. After the contact hole 3e is formed, it is baked to form an organic insulating film 3f made of a photosensitive organic material. The organic insulating film serves as a surface protective film for a semiconductor element, and when a photosensitive organic material is used, it serves for patterning processing such as contact hole formation.

  In forming the organic insulating film 3f, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like can be used as another photosensitive resin material. Further, the photosensitive resin is not necessarily applied by spin coating, and curtain coating, screen printing, spray coating, or the like may be used. Further, the photosensitive resin is not limited to liquid, and a film-like resin may be laminated on the wafer 3A.

  Next, as shown in FIG. 2 (d), a contact portion (also referred to as a land portion) exposed in the contact hole 3e (see FIG. 2 (c)) in the surface of the rewiring layer 3d. The surface is covered with 3 g of the protective conductive layer. The protective conductive layer 3g is highly conductive and plays a role as an antioxidant conductive layer and a corrosion-resistant conductive layer for preventing oxidation and corrosion of the surface of the rewiring layer 3d. As a suitable material, a material containing at least one selected from nickel, gold, silver, platinum, tin, palladium, and alloys thereof can be used. More specifically, the protective conductive layer 3g is formed by performing electroless nickel (Ni) plating on the contact portion surface of the rewiring layer 3d made of, for example, copper plating, followed by gold (Au) plating. .

  Next, for each unit element region corresponding to the semiconductor element 3, a probing inspection is performed through the protective conductive layers 3g and the rewiring layers 3d to determine whether the characteristics are good or bad. The determination result can be marked on the wafer as necessary to facilitate the classification of chips.

  Thereafter, the back surface of the wafer 3A is polished to thin the wafer, and then, as shown in FIG. 2E, a plurality of individual semiconductor elements 3 each having a semiconductor substrate 3a thinned by dicing are obtained. Take out. The semiconductor element 3 can be applied to various semiconductor products such as a semiconductor IC or LSI, and can include circuit elements such as an inductor, a capacitor, and a resistor in addition to a normal conductive circuit.

  In the semiconductor element 3, since the rewiring layer 3d is formed directly on the surface of the inorganic insulating film 3c and the first organic insulating film 73e in the prior art shown in FIG. Further, the material cost is reduced, and the shrinkage of curing in the process of forming the organic insulating film and the tensile stress on the upper surface side of the semiconductor substrate 3a are remarkably reduced. Accordingly, the semiconductor substrate 3a can be further thinned, and even if the semiconductor substrate 3a is made thinner, chip warpage of the semiconductor substrate 3a can be avoided and the flatness thereof can be maintained. Thinning can be achieved.

  Here, in the present invention, the reason why the first organic insulating film 73e in the prior art is omitted and the structure of the semiconductor element 3 as in the first embodiment is adopted will be described. Conventionally, in this field, as is also seen in Patent Document 1, the interlayer conductive via is formed of a metal column having a relatively large rigidity and is connected to the electrode layer (pad portion) of the semiconductor element in a butted state. Therefore, in general, it has been considered necessary to provide the first organic insulating film 73e as a buffer layer against the butt pressing stress. Thus, as a result of various studies by the inventor in the development process of the multilayer wiring board of the present invention, when a through electrode made of a conductive paste having a relatively low rigidity as in Patent Document 2 is used, conventionally, as a buffer layer, The reason is that even if the desired first organic insulating film 73e is omitted, damage such as surface damage of the semiconductor element can be avoided.

Next, the manufacturing method of the 1st board | substrate material 1 is demonstrated with reference to FIG. First, FIG. 3 (a)
In the step shown in FIG. 1, a single-sided copper-clad plate (CCL) in which a wiring material layer 1B made of copper foil is provided on one surface (upper surface) of a flexible first insulating substrate 1a made of, for example, a polyimide resin film is prepared. As the first insulating substrate 1a and the wiring material layer 1B, those having thicknesses of 25 μm and 12 μm were used, respectively.

  The CCL is prepared by a so-called casting method in which a polyimide varnish is applied to a copper foil and the varnish is cured, or a copper seeding layer is sputtered on a polyimide film to grow a copper electrolytic plating, In addition, one obtained by bonding a copper foil by rolling or electrolysis with a polyimide film can be used. For the first insulating substrate 1a, a plastic film such as a liquid crystal polymer may be used instead of the polyimide resin.

  In the step shown in FIG. 3B, an etching resist pattern (etching mask) corresponding to a desired circuit pattern is formed on the surface of the wiring material layer 1B by photolithography, and then chemical selective etching is performed on the wiring material layer 1B. By performing, the 1st wiring board which has the 1st wiring layer 1b patterned by the desired circuit was obtained. For the etching, for example, an etchant mainly containing ferric chloride is used, but an etchant mainly containing cupric chloride can also be used.

  In the step shown in FIG. 3C, the adhesive layer 5a and the resin film F are sequentially stacked on the other surface (lower surface) opposite to the first wiring layer 1b of the first insulating substrate 1a and bonded by thermocompression bonding. Match. An epoxy thermosetting resin film adhesive having a thickness of 25 μm was used for the adhesive layer 5a, and a polyimide resin film having a thickness of 25 μm was used for the resin film F. The thermocompression bonding was performed by using a vacuum laminator and pressing with a pressure of 0.3 MPa at a temperature equal to or lower than the curing temperature of the adhesive in an atmosphere under reduced pressure.

  As the material of the adhesive layer 5a, an adhesive such as an acrylic resin or a thermoplastic adhesive represented by thermoplastic polyimide can be used instead of the epoxy thermosetting resin. The adhesive layer 5a may be formed by applying a varnish-like resin adhesive on the lower surface of the first insulating substrate 1a instead of the film material.

  As the resin film F, a plastic film such as PET or PEN may be used instead of polyimide, and a film that can be bonded or peeled off by UV irradiation may be formed on the surface of the adhesive layer 5a.

  Next, in the step shown in FIG. 3D, a via hole having a diameter of 100 μm is formed by drilling the first insulating substrate 1a, the adhesive layer 5a and the resin film F with a YAG laser so as to penetrate from the lower surface side. A plurality of through holes 1d (four places in the figure) are formed. Thereafter, plasma desmear treatment with a mixed gas of CF4 and O2 is performed.

  During the laser processing, a small hole (not shown) having a diameter of about 30 μm may be formed in the central portion corresponding to each through hole 1d in the wiring layer 1b. The through-hole 1d and the small hole can be formed by laser processing using a carbonic acid laser or excimer laser, drilling, or chemical etching, or can be formed by drilling or chemical etching.

  In addition, the plasma desmear process is not limited to CF4 and O2 mixed gas as the type of gas used, and other inert gas such as Ar can be used, and a wet desmear process is applied instead of the dry process. May be.

  In the step shown in FIG. 3E, a plurality of through electrodes 1c are formed by filling each through hole 1d with a conductive paste by screen printing until the space of each through hole 1d is filled. To do. Thereafter, the resin film F is peeled off. As a result, the portion of the other end surface (lower surface) of each through electrode 1c is exposed in a state of projecting to the lower surface side of the adhesive layer 5a with a height corresponding to the thickness dimension of the resin film F. Thus, the resin film F adjusts the protruding height of the through electrode by appropriately selecting the thickness thereof, and press connection between the through electrode 1c, the rewiring layer 3d of the semiconductor element 3, and the protective conductive layer 3g. At this time, the pressing force can be adjusted so that the mutual low resistance connection and element damage avoidance can be obtained.

  In particular, when the small hole communicating with the through hole 1d is formed in the first wiring layer 1b, one end surface (upper side) of the through electrode 1c is the inner surface (lower surface) of the first wiring layer 1b and Engaging with a relatively large area over the inner wall of the small hole, the connection is made even stronger. The first substrate material 1 is formed through the above steps.

  By the way, the conductive paste of the through electrode 1c is selected from the group of at least one kind of low electrical resistance metal particles selected from the group of nickel, silver and copper and the group of tin, bismuth, indium and lead. It comprised at least 1 type of low melting metal particle, and comprised with the paste which mixed the binder component which has an epoxy resin as a main component. Further, by adjusting the viscosity or the like of the binder component, when the through-electrode 1c and the protective conductive layer 3g on the rewiring layer 3d are pressed and connected, the connection resistance can be lowered and damage to the element can be reduced. . The conductive paste has a metal composition that is easy to be alloyed at a low temperature, such as the curing temperature of the adhesive layer 5a, so that the metal particles can be diffusion bonded to each other or diffusion bonded to the metal of the rewiring layer 3d. By using, it is possible to secure connection reliability equivalent to interlayer connection by bulk metal or plating. In addition, since the said electrically conductive paste is excellent also in heat conductivity, it can also acquire the effect which heat-generates and dissipates generated heat outside.

  By the way, although the manufacturing method of the second substrate material 2 is not shown, one surface of a flexible second insulating substrate 2a made of, for example, a polyimide resin film (in FIG. 1), like the first substrate material 1. A single-sided copper clad plate (CCL) provided with a wiring material layer for the second wiring layer 2b made of copper foil on the lower surface is used. An adhesive layer and a resin film similar to the adhesive layer 5a and the resin film F of the first substrate material 1 are bonded to the other surface (the upper side in FIG. 1) of the second insulating substrate 2a. Further, the patterning of the second wiring layer 2b, the method of forming the through hole and the through electrode 2c, and the materials used for each member are the same as in the case of the first substrate material 1.

Next, the manufacturing method of the said 3rd board | substrate material 4 is demonstrated with reference to FIG. First, in the process shown in FIG. 4A, for example, a double-sided copper clad plate (CCL) in which wiring material layers 4B and 4C made of copper foil are respectively provided on both sides of an insulating substrate 4a made of a polyimide resin film is prepared. Therefore, as shown in FIG. 4B, a through hole TH penetrating the double-sided CCL is formed by, for example, a drill, and a plasma desmear process using a CF 4 and O ₂ mixed gas is performed.

  Thereafter, as shown in FIG. 4C, copper plating is grown on both surfaces of the double-sided CCL and the inner wall of the through hole TH to form a wiring material layer 4BC. At this time, an interlayer conductive path (via) 4d is formed on the inner wall of the through hole TH.

  Then, as shown in FIG. 4D, circuit patterning is performed on the material layer 4BC on both surfaces of the double-sided CCL by the same method as the formation of the first substrate material 1, and one wiring layer 4b. The other wiring layer 4c is formed on both upper and lower surfaces of the insulating substrate 4a. During the patterning, the central portion 4a1 of the insulating plate 4a is exposed on both surfaces by removing the portion corresponding to the semiconductor element 3 in the material layer 4BC. That is, the wiring layer 4b and the wiring layer 4c are patterned at a pitch so that the semiconductor element 3 after mounting is not in contact.

  Next, as shown in FIG. 4E, an opening 4e that is penetrated by a drill, for example, is formed in the central portion 4a1 of the insulating plate 4a. The opening 4 e has a shape / dimension that is slightly larger than the outer diameter of the semiconductor element 3 so as to surround and surround the outer wall of the semiconductor element 3.

  The through hole TH and the opening 4e can be formed by YAG laser, carbonic acid laser, excimer laser or chemical etching. The plasma desmear process is not limited to CF4 and O2 mixed gas as the type of gas used, but other inert gases such as Ar can be used, and a wet desmear process can be applied instead of a dry process. Also good.

  The first to third substrate materials 1, 2, and 4 are subjected to quality screening as a package assembly part after manufacturing, by quality inspection, as in the case of inspection and selection of semiconductor elements.

  Next, a manufacturing method related to the assembly of the package type wiring board of the embodiment will be described with reference to FIG. In addition, about the part which is the same as that of each part shown by FIGS. 1-4, the same referential mark is attached | subjected and the detailed description is abbreviate | omitted.

  First, in the process shown in FIG. 5A, a semiconductor element (chip) 3 corresponding to a non-defective product that has been inspected and selected in the process related to FIG. 2C is prepared. The non-defective chip 3 is aligned with the first substrate material (first wiring board) 1 manufactured in the process shown in FIG. 3E by the semiconductor element chip mounter, and the material of the adhesive layer 5a is obtained. Further, the adhesive paste is temporarily bonded by thermocompression bonding at a temperature equal to or lower than the curing temperature of the conductive paste of the through electrode 1c. Specifically, the protective conductive layer 3g on the rewiring layer 3d of the semiconductor element 3 is temporarily bonded to the through electrode 1c of the first substrate material and the lower surface of the adhesive layer 5a.

  Since the semiconductor element 3 is manufactured with a flat shape as described above, when mounted on the first substrate material 1, it is surely picked up by a vacuum chuck, and the rewiring layer 3d and the protective conductive layer It is securely mounted (integrated) on the first substrate material 1 with high alignment accuracy between 3g and the through electrode 1c.

  In the step shown in FIG. 5B, the second substrate material (second wiring substrate) 2 is disposed with the through electrode 2c and the adhesive layer 5b facing upward, and the third substrate material (intermediate) is disposed thereon. The wiring board 4 is aligned and overlapped. At this time, a part of the wiring layer 4c on the lower surface of the third substrate material 2 overlaps the upper end surface of the through electrode 2c at the left and right positions in the drawing.

  Next, the semiconductor element 3 integrated with the first substrate material (first wiring substrate) 1 is inserted in alignment with the opening 4e of the third substrate material 4, and the first substrate material 1 is superposed on the third substrate material 4. At this time, the semiconductor element 3 is arranged so that the entire outer periphery of the semiconductor substrate 3a maintains a gap with the inner wall of the opening 4e and does not contact the wiring layers 4b and 4c of the third substrate material 4. Is done. In addition, the lower end surface of the through electrode 1c at the left and right positions of the first substrate material 1 is opposed to a part of the through electrode 2c of the second substrate material 2, and the wiring layer 4b on the upper surface of the third substrate material 4 is disposed. Overlapping part of In this manner, a stacked body of the first to third substrate materials, the substrate materials 1, 2, 4 and the semiconductor element 3 is configured.

  Then, the laminated body is thermocompression-bonded in a laminating direction in a reduced pressure atmosphere of 1 kPa or less using a vacuum cure press machine, thereby completing a package type wiring board having a multi-layered structure as shown in FIG. In this step, the adhesive layers 5a and 5b of the first and second substrate materials 1 and 2 are plastically flowed by heating and pressurizing, and the openings 4e of the third substrate material 4 and the semiconductor are formed between the substrate materials. The gap between the side periphery of the element 3 and the through hole TH are filled, and the adhesive layer material 5 is formed into a single layer as shown in FIG. As a result, a package adhesive seal in which the semiconductor element 3 is embedded in the adhesive layer material 5 can be easily obtained. At this stage, the conductive paste is hardened and the metal component is alloyed in parallel with the package sealing. As a result, even when the through electrodes are pressed between 1c and the rewiring layer 3d and the protective conductive layer 3g of the semiconductor element 3, damage to the element is avoided and a low resistance connection is obtained.

  According to the manufacturing method according to such an embodiment, the first and second substrate materials 1 and 2 use a metal foil-clad wiring substrate material such as a single-sided CCL, and the first and second substrates for interlayer connection. The second through electrodes 1c and 2c can be easily formed by printing and filling with a conductive paste. Therefore, compared with the above-described conventional built-up method (see Patent Document 1), the plating process can be eliminated through the entire package assembly process, and the production time and production cost can be greatly reduced.

  In addition, since the first to third substrate materials 1, 2, and 4 are bonded and fixed to each other through the adhesive layers 5a and 5b by the collective heat pressing process, the package substrate laminated structure can be obtained by one press. Compared with the built-up system, the heat history applied to these laminated members and the deterioration of the members can be significantly reduced.

  Furthermore, since the first to third substrate materials 1, 2, 4 and the semiconductor element 3 are manufactured in advance in separate process lines, even if a failure occurs in each assembly member for each manufacturing process, it is a defective product each time. Can be eliminated, and accumulation of yield deterioration can be avoided.

  By the way, the wiring layer 1b of the first substrate material 1 is covered with an insulating coating layer (not shown). For electrical connection with an external terminal, the insulating coating layer has a land portion or a land portion of the wiring layer 1b. An external terminal electrode made of a ball-shaped solder bump can be formed by providing a contact hole that exposes the contact portion, and using, for example, a solder resist as the insulating coating layer and pattern-printing and reflowing a solder paste. The external terminal electrode is not limited to the ball-shaped bump, and other external terminal structures such as a beam lead type can be adopted depending on the connection terminal structure of an electronic device or the like to be mounted. The form of protection by the insulating coating layer on the surface of the wiring layer 2b of the second substrate material 2 and electrical connection with external terminals is the same as that for the wiring layer 1b of the first substrate material 1.

  The second substrate material 2 is not limited to the form of the wiring substrate, and may be constituted by a flexible polyimide resin film, for example, as a support plate for the first substrate material 1, the semiconductor element 3, etc., or an insulating film such as PEN or PET Alternatively, a rigid glass epoxy resin insulating plate or a metal plate such as a copper foil may be used.

  Further, if the second substrate material 2 is made of a highly heat-conductive material, such as copper foil, it can effectively dissipate not only the role of the support plate but also the heat from the semiconductor element 3 to the outside. The electrical operation of the element 3 can be stabilized. In that case, it is possible to mount even a semiconductor element having a large calorific value, which could not be incorporated in the prior art, and the application range of the package substrate to various semiconductor elements can be expanded.

  The third substrate material 4 is not limited to the form of the wiring substrate, and may be used exclusively for a role as a spacer. The third substrate material 4 has an opening having a thickness similar to that of the semiconductor element 3 and surrounding the side periphery with a gap. For example, it can be formed of a polyimide resin film having 4e. Such a third substrate material 4 suppresses undesired flow deformation of the adhesive layer material when the first substrate material 1 and the second substrate material 2 are thermocompression bonded to each other via the adhesive layer material 5. The parallelism between the plate members 1 and 2 and the positional accuracy of the semiconductor element 3 can be improved. Thus, by providing the first to third substrate materials of various forms and appropriately combining them, it is possible to provide various types of package type multilayer wiring boards according to the multi-function / high functionality of the semiconductor element 3 Can do.

  By the way, in the multilayer wiring board of the one embodiment, the third substrate material 4 is omitted, and the first substrate material 1 and the second substrate material 2 are bonded only by the adhesive layer material 5, thereby further increasing the package. Thinning is also possible. This is because, for example, the number of functions of the semiconductor element 3 and the number of electrode pads thereof are relatively small, the chip size and the thickness are small, the number of wiring layers, the wiring layer pitch, and the wiring layer of the first substrate material 1. This can be carried out when the length and the like and the insulating substrate area (size) can be reduced, or when the layer thickness of the adhesive layer material 5 is sufficiently larger than the thickness of the semiconductor element 3. Note that the adhesive layer provided in advance on the second substrate material 2 is not necessarily provided on the entire surface of the second substrate material 2, for example, at least a portion such as being provided only in the periphery avoiding the portion corresponding to the semiconductor element. Should be provided.

  Moreover, in the said embodiment, the heat dissipation effect of the semiconductor element 3 can be improved by forming a good heat conduction layer such as a copper foil on the bottom surface of the semiconductor element 3. Furthermore, when the second substrate material 2 is a good heat conductive material, the good heat conductive layer on the bottom surface of the semiconductor element 3 is brought into direct contact with the second substrate material 2 without an adhesive layer. The heat dissipation effect is further improved.

  In the one embodiment, the package substrate type electronic component built-in type multilayer wiring substrate and the manufacturing method thereof are exemplified. However, in any embodiment, the surface of the contact portion of the rewiring layer 3d of the semiconductor element 3 is protected conductively. Covered by layer 3g. Therefore, the contact portions for the rewiring layer 3d and the through electrode 1c of the semiconductor element 3 are protected conductive layers even when subjected to various heating and chemical treatments included in the series of assembly steps of the package substrate in the embodiment as described above. Oxidation and corrosion are prevented by 3g, contact resistance can be reduced, and an abnormal increase in circuit resistance and poor conduction can be avoided. As a result, not only the semiconductor element 3 that has been flattened and thinned, but also the multilayer wiring board with a built-in electronic component including the semiconductor element 3 has remarkably improved electrical characteristics and has a flat and thin outer shape. The manufacture thereof can be easily performed at a low cost.

It is sectional drawing which shows the laminated wiring board which concerns on one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention, (a)-(e) is sectional drawing according to the process. , It is a figure for demonstrating the manufacturing method of the 1st board | substrate material which concerns on one Embodiment of this invention, (a)-(e) is sectional drawing according to the process. It is a figure for demonstrating the manufacturing method of the 3rd board | substrate material which concerns on one Embodiment of this invention, (a)-(e) is sectional drawing according to the process. It is a figure for demonstrating the assembly method of the laminated wiring board which concerns on one Embodiment of this invention, (a) And (b) is sectional drawing according to the process. It is sectional drawing which shows the principal part of the multilayer wiring board in a prior art. It is a figure for demonstrating the manufacturing method of the semiconductor element used for the multilayer wiring board in a prior art, (a)-(e) is sectional drawing according to the process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st board | substrate material 1a, 1d, 2a, 4a Insulating board | substrate 1b, 1f, 2b, 4b, 4c, Wiring layer 1c, 1g, 2c, Through electrode 2 2nd board | substrate material 3 Semiconductor element 3a Semiconductor substrate 3b Electrode part 3c Inorganic Insulating film 3d Redistribution layer 3f Organic insulating film 3g Protective conductive layer 4 Third substrate material 5 Adhesive layer material 5
5a, 5b, adhesive layer

Claims (4)

  A laminated wiring board in which a semiconductor element is embedded and bonded and sealed between a first substrate material and a second substrate material arranged facing each other, wherein the first substrate material has a wiring layer on one surface of an insulating substrate. And a through electrode made of a conductive paste that penetrates the insulating substrate and has one end surface connected to the wiring layer and the other end surface exposed on the other surface of the insulating substrate, The semiconductor element includes an electrode pad formed on a partial surface of a semiconductor substrate, an inorganic insulating film formed on the surface of the semiconductor substrate having a contact hole for the electrode pad, and the electrode pad formed on the inorganic insulating film. A redistribution layer connected to the surface, an organic insulating film having a contact hole for the redistribution layer and formed on the surface of the redistribution layer, and covering the redistribution layer surface in the contact hole of the organic insulation film Protective conductive Is configured to include a multilayer wiring board on which the other end face of the through electrode, characterized in that connected to the redistribution layer through the protective conductive layer.   The multilayer wiring board according to claim 1, wherein the protective conductive layer includes at least one selected from nickel, gold, silver, platinum, tin, palladium, and alloys thereof.   The multilayer wiring board according to claim 1, wherein the rewiring layer is formed of a copper plating layer, and the organic insulating film is formed using a photosensitive organic material as a material. A method of manufacturing a laminated wiring board in which a semiconductor element is built in and bonded and sealed between a first substrate material and a second substrate material that are arranged facing each other,
Forming the semiconductor element comprises:
(A-1) A plurality of element regions corresponding to a plurality of semiconductor elements are provided on the surface of a semiconductor wafer, electrode pads are formed for each of the element areas, and an inorganic insulating film having a first contact hole for the electrode pads is formed Forming on the wafer surface;
(A-2) forming a redistribution layer connected to the electrode pad through the first contact hole on the inorganic insulating film;
(A-3) forming a photosensitive organic material film on the wafer so as to cover the inorganic insulating film and the rewiring layer;
(A-4) Forming an organic insulating film having a second contact hole on the surface of the wafer by subjecting the photosensitive organic material film to photolithography to open a second contact hole for the rewiring layer and baking it. And a process of
(A-5) covering the surface of the rewiring layer with a protective conductive layer in the second contact hole;
(A-6) After performing wafer inspection on each element region, dicing and taking out each semiconductor element separated corresponding to each element region,
The step of bonding and sealing a semiconductor element between the first substrate material and the second substrate material includes:
(B) A wiring layer patterned on one surface of an insulating substrate, an adhesive layer formed on the other surface, and one end surface passing through the insulating substrate and the adhesive layer and connected to the wiring layer, and the other surface is the semiconductor. Preparing a first substrate material having a through electrode made of a conductive paste corresponding to a protective conductive layer on a rewiring layer of the element;
(C) a step of aligning and connecting the other end surface of the through electrode to the rewiring layer of the semiconductor element, and temporarily bonding the semiconductor element to the adhesive layer to be integrated with the first substrate material; ,
(D) providing a second substrate material facing the first substrate material;
(E) aligning and superimposing the semiconductor element integrated with the first substrate material on the second substrate material;
(F) a step of collectively heat-pressing the first substrate material and the second substrate material in an overlapping direction, surrounding the semiconductor element with the adhesive layer, and bonding the first and second substrate materials to each other. A method for manufacturing a laminated wiring board, comprising:

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