JP2010093154A - Nonvolatile semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device for being further miniaturized by realizing downsizing and high-densification of memory cells constituting the nonvolatile semiconductor memory device. <P>SOLUTION: A source line SL is formed between a memory cell MC1 and a memory cell MC2, in the manner of self-alignment. Concretely, the source line SL is formed so as to contact with both sidewalls SWs formed on a sidewall of a memory gate electrode MG1 and on a sidewall of a memory gate electrode MG2, in the manner of self-alignment. Further, not only the memory gate electrodes MG1, MG2 and MG, but also control gate electrodes CG1, CG2 and CG are formed in a sidewall shape. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing technology thereof, and more particularly to a nonvolatile semiconductor memory device that needs to be highly integrated by reducing a cell area and a technology effective when applied to the manufacturing thereof.

Japanese Patent Application Laid-Open No. 2002-289714 (Patent Document 1) describes a nonvolatile semiconductor memory device and a method for manufacturing the same, which can minimize the cell size and reduce power consumption during a program operation. Specifically, a charge storage region is formed on the semiconductor substrate. The charge storage region is formed to include a floating gate dielectric film, a floating gate, and an interpoly dielectric film. A control gate and a gate mask are stacked on the charge storage region. At this time, a source-side spacer is disposed on the side walls of the pair of control gates, and a source electrode is formed on the semiconductor substrate sandwiched between the pair of source-side spacers.
JP 2002-289714 A

  EEPROM (Electrically Erasable and Programmable Read Only Memory) and flash memory are widely used as nonvolatile semiconductor memory devices that can be electrically written and erased. These nonvolatile semiconductor memory devices (memory) represented by EEPROM and flash memory which are widely used at present are electrically conductive floating layers surrounded by a silicon oxide film under the gate electrode of a MOS (Metal Oxide Semiconductor) transistor. It has a charge storage film such as a gate electrode and a trapping insulating film, and stores information by utilizing the fact that the threshold value of the transistor varies depending on the charge storage state in the floating gate electrode and the trapping insulating film.

  This trapping insulating film refers to an insulating film having a trap level in which charges can be accumulated. An example thereof is a silicon nitride film. In a nonvolatile semiconductor memory device having a trapping insulating film, the threshold value of a MOS transistor is shifted by injection / release of electric charges into the trapping insulating film to operate as a memory element. Such a non-volatile semiconductor memory device using a trapping insulating film as a charge storage film is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor, which is compared with the case where a conductive floating gate electrode is used for the charge storage film. In addition, since charges are accumulated in discrete trap levels, the reliability of data retention is excellent. In addition, since the data retention reliability is excellent, the thickness of the silicon oxide film above and below the trapping insulating film can be reduced, and the voltage of the write / erase operation can be reduced.

  The nonvolatile semiconductor memory device configured as described above is required to reduce the size of the memory, and accordingly, the cell size is reduced and the cell density is increased.

  An object of the present invention is to provide a technology capable of achieving further miniaturization of a nonvolatile semiconductor memory device as a product by realizing reduction in size and density of memory cells constituting the nonvolatile semiconductor memory device. is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A nonvolatile semiconductor memory device in a typical embodiment includes a first memory cell and a second memory cell that are adjacent to each other. The first memory cell includes (a1) a first gate insulating film formed on the semiconductor substrate, (b1) a first control gate electrode formed on the first gate insulating film, and (c1) the first A first memory gate electrode formed on one side wall of the control gate electrode. (D1) a first stacked insulating film formed between the first control gate electrode and the first memory gate electrode and between the first memory gate electrode and the semiconductor substrate; A first sidewall insulating film formed on the sidewall of the first memory gate electrode. And (f1) a first drain region formed in the semiconductor substrate and formed in alignment with the side wall of the first control gate electrode where the first memory gate electrode is not formed, and (g1) the And a first source region formed in a semiconductor substrate and aligned with a side of the first memory gate electrode on which the first sidewall insulating film is formed. The second memory cell includes (a2) a second gate insulating film formed on the semiconductor substrate, (b2) a second control gate electrode formed on the second gate insulating film, and (c2) And a second memory gate electrode formed on one side wall of the second control gate electrode. (D2) a second stacked insulating film formed between the second control gate electrode and the second memory gate electrode and between the second memory gate electrode and the semiconductor substrate; And a second sidewall insulating film formed on the sidewall of the second memory gate electrode. And (f2) a second drain region formed in the semiconductor substrate and formed in alignment with the side wall of the second control gate electrode where the second memory gate electrode is not formed, and (g2) the And a second source region formed in the semiconductor substrate and aligned with the side wall of the second memory gate electrode on which the second sidewall insulating film is formed. At this time, the first source region and the second source region are common source regions. Here, a source wiring formed on the semiconductor substrate so as to be electrically connected to the common source region, and formed so as to be in contact with the first sidewall insulating film and the second sidewall insulating film, It is characterized by providing.

  A method for manufacturing a nonvolatile semiconductor memory device according to a representative embodiment includes (a) a step of forming an element isolation region in a semiconductor substrate, (b) a step of forming a well in the semiconductor substrate, c) forming a first dummy insulating film and a second dummy insulating film on the semiconductor substrate; and (d) forming a gate insulating film on the semiconductor substrate after the step (c). Next, (e) after the step (d), a first control gate electrode is formed on the semiconductor substrate via the first gate insulating film made of the gate insulating film on the side wall of the first dummy insulating film, Forming a second control gate electrode on the semiconductor substrate via the second gate insulating film made of the gate insulating film on the sidewall of the second dummy insulating film; and (f) after the step (e), And a step of removing the first dummy insulating film and the second dummy insulating film. Subsequently, (g) after the step (f), a step of forming a laminated insulating film on the semiconductor substrate; and (h) after the step (g), on the side wall of the first control gate electrode and on the semiconductor substrate. Forming a first memory gate electrode through a first laminated insulating film comprising the laminated insulating film, and forming a second laminated insulating film comprising the laminated insulating film on a sidewall of the second control gate electrode and on the semiconductor substrate. Forming a second memory gate electrode. And (i) after the step (h), forming a shallow first semiconductor region in the semiconductor substrate sandwiched between the first memory gate electrode and the second memory gate electrode; i) forming a first sidewall insulating film on the sidewall of the first memory gate electrode and forming a second sidewall insulating film on the sidewall of the second memory gate electrode after the step; Thereafter, (k) after the step (j), a deep first semiconductor region is formed in the semiconductor substrate sandwiched between the first sidewall insulating film and the second sidewall insulating film, and the shallow first semiconductor is formed. Forming a common source region comprising a region and the deep first semiconductor region. (L) After the step (k), on the semiconductor substrate so as to be electrically connected to the common source region, and on the first sidewall insulating film and the second sidewall insulating film Forming a source wiring so as to be in contact with each other. Finally, (m) after the step (l), a first drain region is formed in the semiconductor substrate in alignment with the sidewall of the first control gate electrode, and is aligned with the sidewall of the second control gate electrode. And a step of forming a second drain region in the semiconductor substrate.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By realizing downsizing and high density of the memory cells constituting the nonvolatile semiconductor memory device, further miniaturization of the nonvolatile semiconductor memory device as a product can be achieved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
First, before describing the nonvolatile semiconductor memory device according to the first embodiment, a nonvolatile semiconductor memory device (comparative example) according to the technique studied by the present inventors will be described. FIG. 1 is a diagram showing a layout configuration of a nonvolatile semiconductor memory device in a comparative example. FIG. 1 mainly shows a region where two adjacent memory cells are formed.

  In FIG. 1, an active region (active region) Act and element isolation regions STI1 to element isolation regions STI4 are formed on a semiconductor substrate. Each of the element isolation regions STI1 to STI4 has a rectangular shape. For example, the element isolation region STI1 and the element isolation region STI2 or the element isolation region STI3 and the element isolation region STI4 are separated from each other in the x-axis direction. Are arranged in a straight line. The element isolation region STI1 and the element isolation region STI3, or the element isolation region STI2 and the element isolation region STI4 are arranged apart from each other in the y-axis direction. In other words, when focusing on the element isolation region STI1, the element isolation region STI2 is spaced apart in the x-axis direction, and the element isolation region STI3 is spaced apart in the y-axis direction. A region between the element isolation regions STI1 to STI4 arranged so as to be separated from each other is a semiconductor region, and this semiconductor region becomes an active region Act.

  As shown in FIG. 1, the memory cell MC1 is formed in the active region Act formed between the element isolation region STI1 and the element isolation region STI3 arranged in the y-axis direction. Similarly, the memory cell MC2 is formed in the active region Act formed between the element isolation region STI2 and the element isolation region STI4 arranged in the y-axis direction.

  Hereinafter, the configuration of the memory cell MC1 will be described. A control gate electrode CG1 extends over the active region Act between the element isolation region STI1 and the element isolation region STI3 arranged side by side in the y-axis direction. A laminated insulating film MIF1 is formed on the side wall of the control gate electrode CG1, and a memory gate electrode MG1 is formed on the side wall of the control gate electrode CG1 via the laminated insulating film MIF1. In the memory cell MC1, the active region Act on the left side of the control gate electrode CG1 serves as a drain region, and a plug PLG1 is electrically connected to the drain region. On the other hand, the active region Act on the right side of the control gate electrode CG1 becomes the source region of the memory cell.

  Similarly, the configuration of the memory cell MC2 will be described. A control gate electrode CG2 extends over the active region Act between the element isolation region STI2 and the element isolation region STI4 arranged side by side in the y-axis direction. A laminated insulating film MIF2 is formed on the side wall of the control gate electrode CG2, and a memory gate electrode MG2 is formed on the side wall of the control gate electrode CG2 via the laminated insulating film MIF2. In the memory cell MC2, the active region Act on the right side of the control gate electrode CG2 serves as a drain region, and a plug PLG2 is electrically connected to this drain region. On the other hand, the active region Act on the left side of the control gate electrode CG2 becomes the source region of the memory cell.

  Therefore, the source region of the memory cell MC1 and the source region of the memory cell MC2 are formed from a common active region Act. That is, the memory cells MC1 and MC2 adjacent in the x-axis direction have a common source region. This common source region is composed of an active region Act sandwiched between the memory gate electrode MG1 and the memory gate electrode MG2 shown in FIG. The common source region extends in the y-axis direction, and the memory cell MC1, the control gate electrode CG1, and the memory gate electrode MG1 are arranged in a common memory cell (in the y-axis direction with respect to the memory cell MC1). Memory cell) and the memory cell MC2, the control gate electrode CG2, and the memory gate electrode MG2 are shared by a common memory cell (memory cells aligned in the y-axis direction with respect to the memory cell MC2). That is, in the comparative example, the source region is formed so as to be shared between adjacent memory cells. Therefore, in the semiconductor substrate, for example, the element isolation region STI1 and the element isolation region STI2 are separated from each other so that the active region Act serving as the source region can extend in the y-axis direction. Therefore, in the comparative example configured as described above, since the shared source region extends in the y-axis direction, it is necessary to separate the element isolation region STI1 and the element isolation region STI2 by the width of the source region. For this reason, for example, it is necessary to separate the memory cell MC1 and the memory cell MC2 from each other by a certain distance, which is a factor that hinders downsizing of the memory cell array.

  Furthermore, since the source region needs to extend in the y-axis direction as described above, the element isolation regions STI1 to STI4 are rectangular. This means that there are terminal portions in the element isolation regions STI1 to STI4. The presence of terminations in the element isolation regions STI1 to STI4 means that the control gate electrodes CG1 and CG2 and the memory gate electrode MG1 extending over the element isolation regions STI1 to STI4 in the y-axis direction. This means that it is necessary to prevent MG2 from protruding from the end portions of the element isolation regions STI1 to STI4. That is, in order to normally form the memory cell MC1 and the memory cell MC2, it is necessary that the control gate electrodes CG1, CG2 and the memory gate electrodes MG1, MG2 do not protrude from the end portions of the element isolation regions STI1 to STI4. It becomes.

  Therefore, in the structure of the comparative example, it is important to align the element isolation regions STI1 to STI4 with the control gate electrodes CG1 and CG2 and the memory gate electrodes MG1 and MG2. Since patterning of the element isolation regions STI1 to STI4 and patterning of the control gate electrodes CG1 and CG2 and the memory gate electrodes MG1 and MG2 are performed using photolithography technology, it is necessary to consider misalignment in these patterning. In the layout configuration of the comparative example, it is necessary to take a certain margin (alignment margin). This becomes a factor that hinders the reduction of the memory cell array of the nonvolatile semiconductor memory device.

  As described above, according to the layout configuration of the comparative example, the source region shared between the memory cells is formed by the diffusion layer formed in the semiconductor substrate. As a result, the shared source region is the diffusion layer extending in the semiconductor substrate. It is necessary to ensure (first component point). In order to realize the first component point, it is necessary to provide termination portions in the element isolation regions STI1 to STI4. As a result, the element isolation regions STI1 to STI4, the control gate electrode CG1, It is necessary to ensure an alignment margin (margin) between CG2 and the memory gate electrodes MG1 and MG2 (second constituent point). Therefore, considering these first and second configuration points, the layout configuration in the comparative example has a limit in reducing the size of the memory cell array, and it is difficult to efficiently reduce the size of the nonvolatile semiconductor memory device. There is.

  Therefore, the first embodiment provides a technology that can achieve further miniaturization of a nonvolatile semiconductor memory device that is a product by realizing reduction in size and density of memory cells that constitute the nonvolatile semiconductor memory device. The purpose is to do. In the first embodiment, the configuration of the memory cell array is devised in order to achieve this purpose. Hereinafter, the nonvolatile semiconductor memory device according to the first embodiment will be described.

  FIG. 2 is a diagram showing a layout configuration of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 2 mainly shows a region where two adjacent memory cells are formed. In FIG. 2, active regions (active regions) Act1 to Act3 and element isolation regions STI1 and STI2 are formed on a semiconductor substrate. Specifically, each of the active regions Act1 to Act3 and the element isolation regions STI1 and STI2 has a line shape extending in the x direction. The line shape active regions Act1 to Act3 and the line shape element isolation regions STI1, STI2 are alternately arranged in the y-axis direction. For example, the active region Act1 is formed so as to be sandwiched between the element isolation region STI1 and the element isolation region STI2, and the active region Act1 and the element isolation regions STI1 and STI2 are arranged in stripes.

  Next, the control gate electrode CG1 and the control gate electrode CG2 are formed so as to intersect the element isolation regions STI1 and STI2 and the active regions Act1 to Act3 extending in the x-axis direction. That is, the control gate electrodes CG1 and CG2 extend in the y-axis direction so as to straddle the element isolation regions STI1 and STI2 and the active regions Act1 to Act3. A laminated insulating film MIF1 is formed on the right side wall of the control gate electrode CG1, and a memory gate electrode MG1 is formed on the right side wall of the control gate electrode CG1 via the laminated insulating film MIF1. Similarly, a laminated insulating film MIF2 is formed on the left side wall of the control gate electrode CG2, and a memory gate electrode MG2 is formed on the left side wall of the control gate electrode CG2 via the laminated insulating film MIF2.

  A sidewall SW made of an insulating film is formed on the right side wall of the memory gate electrode MG1, and similarly, a side wall SW made of an insulating film is formed on the left side wall of the memory gate electrode MG2. A source line SL is formed so as to be sandwiched between both sidewalls SW.

  At this time, the memory cell MC1 is formed in the intersection region of the active region Act1 extending in the x-axis direction and the control gate electrode CG1, the stacked insulating film MIF1, and the memory gate electrode MG1 extending in the y-axis direction. . Similarly, a memory cell MC2 is formed in an intersecting region of the active region Act1 extending in the x-axis direction, the control gate electrode CG2, the stacked insulating film MIF2, and the memory gate electrode MG2 extending in the y-axis direction.

  In the memory cell MC1, the active region Act1 on the left side of the control gate electrode CG1 serves as a drain region, and a plug PLG1 is electrically connected to the drain region. On the other hand, the active region Act1 on the right side of the memory gate electrode MG1 becomes the source region of the memory cell, and this source region is electrically connected to the source line SL disposed on the source region. In the memory cell MC2, the active region Act1 on the right side of the control gate electrode CG2 serves as a drain region, and a plug PLG2 is electrically connected to the drain region. On the other hand, the active region Act1 on the left side of the memory gate electrode MG2 becomes the source region of the memory cell, and this source region is electrically connected to the source line SL disposed on the source region.

  That is, the memory cell MC1 and the memory cell MC2 are arranged side by side in the x-axis direction in the active region Act1 extending in the x-axis direction, and the source region of the memory cell MC1 and the source region of the memory cell MC2 are common. It is an area. A source line SL is disposed on the common source region, and the source line SL extends in the y-axis direction.

  The layout of the nonvolatile semiconductor memory device according to the first embodiment is configured as shown in FIG. 2, and the features thereof will be described below. First, the first feature point is that a source line SL is formed between the memory cell MC1 and the memory cell MC2. The source line SL is a memory cell (for example, a memory cell formed in the active region Act2 or the active region Act3) that shares the control gate electrode CG1 and the memory gate electrode MG1 with the memory cell MC1, or the memory cell MC2 and the control gate. A source region between the electrode CG2 and the memory gate electrode MG2 is electrically connected to a common memory cell (for example, a memory cell formed in the active region Act2 or the active region Act3).

  In the comparative example shown in FIG. 1, the memory cell MC1, the control gate electrode CG1, and the memory gate electrode MG1 share the memory cell (the memory cell aligned in the y-axis direction with respect to the memory cell MC1), or the memory cell MC2 and the control. In a memory cell having a common gate electrode CG2 and memory gate electrode MG2 (a memory cell arranged in the y-axis direction with respect to the memory cell MC2), a source region formed in the active region Act extends in the y-axis direction. Share the source region in each other's memory cells.

  In contrast, in the first embodiment shown in FIG. 2, the memory cell MC1, the control gate electrode CG1, and the memory gate electrode MG1 share a memory cell (for example, a memory cell formed in the active region Act2 or the active region Act3). ), And memory cells that share the memory cell MC2 with the control gate electrode CG2 and the memory gate electrode MG2 (for example, memory cells formed in the active region Act2 and the active region Act3) are formed in the active regions Act1 to Act3. The source region is not shared between memory cells (for example, memory cell MC1 and memory cell MC2). That is, as shown in FIG. 2, the active regions Act1 to Act3 extending in the x-axis direction are separated from each other by the element isolation regions STI1 and STI2. In this state, in the first embodiment, the source wiring SL is formed so as to straddle the source regions of the memory cells arranged side by side in the y-axis direction over the active regions Act1 to Act3 and the element isolation regions STI1 and STI2. -ing Since the source line SL is electrically connected to the active regions Act1 to Act3 separated from each other by the element isolation regions STI1 and STI2, the source region of the memory cells formed in the active regions Act1 to Act3 is electrically Will be connected.

  As described above, in the first embodiment, the source region of the memory cells arranged in the y-axis direction (for example, the memory cells formed in the active regions Act1 to Act3) is shared as a diffusion layer formed on the semiconductor substrate. Instead, they are electrically connected by the source line SL disposed on the active regions Act1 to Act3 and the element isolation regions STI1 and STI2 and extending in the y-axis direction. As a result, in the first embodiment, since it is not necessary to provide a shared source region extending in the y-axis direction in the semiconductor substrate, the active region Act1 is disposed adjacent to the x-axis direction as shown in FIG. Thus, the distance between the memory cell MC1 and the memory cell MC2 can be reduced. That is, in the first embodiment, since the space between the memory cell MC1 and the memory cell MC2 adjacent in the x-axis direction can be narrowed, the size of the nonvolatile semiconductor memory device can be reduced.

  In particular, in the first embodiment, as shown in FIG. 2, the source wiring is sandwiched between the memory gate electrode MG1 constituting the memory cell MC1 and the memory gate electrode MG2 constituting the memory cell MC2. SL is formed. That is, the source line SL formed so as to be sandwiched between the memory cell MC1 and the memory cell MC2 is formed in a self-aligned manner via the sidewall SW. For this reason, the distance between the memory cell MC1 and the memory cell MC2 can be minimized. That is, in the first embodiment, as a method for electrically connecting the source regions of the memory cells arranged in the y-axis direction, a diffusion layer formed in the semiconductor substrate is not used but formed on the semiconductor substrate. By using the source line SL thus formed, the memory cell array size can be reduced. Further, by forming the source wiring SL formed on the semiconductor substrate in a self-aligned manner with respect to the memory cells MC1 and MC2 adjacent in the x-axis direction, the memory cell array size can be reduced. It is. In particular, by forming the source line SL in a self-aligned manner with respect to both the memory cell MC1 and the memory cell MC2, alignment between the memory cell MC1, the memory cell MC2, and the source line SL becomes unnecessary. This means that it is not necessary to secure an alignment margin between the memory cells MC1 and MC2 and the source line SL, so that further downsizing of the nonvolatile semiconductor memory device can be achieved.

  Subsequently, as a method for electrically connecting the source regions of the memory cells arranged in the y-axis direction, the source wiring SL formed on the semiconductor substrate is used instead of using the diffusion layer formed in the semiconductor substrate. Another effect by using will be described. In the first embodiment, as shown in FIG. 2, a diffusion layer is not used to connect the source regions of memory cells arranged in the y-axis direction (for example, memory cells formed in the active regions Act1 to Act3). In addition, the source wiring SL formed on the semiconductor substrate is used. For this reason, in the semiconductor substrate, the active regions Act1 to Act3 and the element isolation regions STI1 and STI2 can each be formed in a stripe shape having a line shape.

  That is, in the comparative example, the diffusion layer in the semiconductor substrate is used to connect the source regions of the memory cells arranged in the y-axis direction (for example, memory cells formed in the active region Act). In order to secure the formation region, the element isolation regions STI <b> 1 to STI <b> 4 inevitably have a rectangular shape (see FIG. 1). This means that in the comparative example, a termination portion exists in each of the element isolation regions STI1 to STI4. As a result, in the comparative example, it is necessary to align the control gate electrodes CG1 and CG2 and the memory gate electrodes MG1 and MG2 so as not to protrude from the terminal portions of the element isolation regions STI1 to STI4. For this reason, in the comparative example, an alignment margin is ensured between the terminal portions of the element isolation regions STI1 to STI4 and the control gate electrodes CG1 and CG2 and the memory gate electrodes MG1 and MG2 to some extent in consideration of alignment accuracy. There is a need (see FIG. 1).

  On the other hand, in the first embodiment, no diffusion layer is used to connect the source regions of the memory cells arranged in the y-axis direction (for example, memory cells formed in the active regions Act1 to Act3). From this, as shown in FIG. 2, the element isolation regions STI1 to STI2 formed in the semiconductor substrate can be formed into a line shape extending in the x-axis direction. As a result, no terminal portion exists in the element isolation regions STI1 and STI2. This means that it is not necessary to align the terminal portions of the element isolation regions STI1 to STI2 with the control gate electrodes CG1 and CG2 and the memory gate electrodes MG1 and MG2. In other words, since the element isolation regions STI1 and STI2 are arranged in a line in the x-axis direction, there is a problem even if the formation positions of the control gate electrodes CG1 and CG2 and the memory gate electrodes MG1 and MG2 are slightly shifted in the x-axis direction. It does not become. Therefore, according to the first embodiment, it is not necessary to secure an alignment margin between the element isolation regions STI1 and STI2 and the control gate electrodes CG1 and CG2 and the memory gate electrodes MG1 and MG2, so that the memory cell array can be downsized. Furthermore, there is a remarkable effect that can be promoted.

  Next, a cross-sectional structure of the nonvolatile semiconductor memory device in the first embodiment will be described. FIG. 3 is a diagram showing a cross section of the nonvolatile semiconductor memory device including a cross section taken along line A-A ′ of FIG. 2. FIG. 3 illustrates a memory cell array region and a peripheral circuit region. The memory cell array region includes a cross section taken along line AA ′ in FIG. 2 (the left two of the four memory cells) and other cross sections. (The right two of the four memory cells) are shown. On the other hand, in the peripheral circuit region, one of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) constituting the peripheral circuit is shown. A dummy gate region is formed between the memory cell array region and the peripheral circuit region.

  As shown in FIG. 3, the well isolation layer NISO is formed in the semiconductor substrate 1S, and the memory cell array region and the peripheral circuit region are separated by the element isolation region STI. The element isolation region STI is formed by embedding an insulating film such as a silicon oxide film in a groove formed in the semiconductor substrate 1S.

  First, the configuration of the MISFET formed in the peripheral circuit region partitioned by the element isolation region STI will be described. The peripheral circuit region indicates a region where a peripheral circuit is formed. Specifically, a nonvolatile semiconductor memory device includes a memory cell array region in which memory cells are formed in an array (matrix), and a peripheral circuit that controls the memory cells formed in the memory cell array region. Yes. This peripheral circuit includes a word driver that controls the voltage applied to the control gate electrode of the memory cell, a sense amplifier that amplifies the output from the memory cell, and a control circuit that controls the word driver and sense amplifier. Has been. Therefore, in the peripheral circuit region shown in FIG. 3, for example, one of MISFETs constituting a word driver, a sense amplifier, a control circuit, or the like is illustrated. The n-channel MISFET constituting this peripheral circuit will be described below.

  As shown in FIG. 3, in the peripheral circuit region, a well isolation layer NISO is formed on the semiconductor substrate 1S, and a p-type well PWL2 is formed on the well isolation layer NISO. The well isolation layer NISO is formed from an n-type semiconductor region in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S, and the p-type well PWL2 is a p-type impurity such as boron (B). Is formed from a p-type semiconductor region introduced into the semiconductor substrate 1S.

  Next, a gate insulating film GOX is formed on the p-type well PWL2 (semiconductor substrate 1S), and a gate electrode G is formed on the gate insulating film GOX. The gate insulating film GOX is formed of, for example, a silicon oxide film, and the gate electrode G is formed of, for example, a polysilicon film and a cobalt silicide film formed on the surface of the polysilicon film. For example, an n-type impurity such as phosphorus is introduced into the polysilicon film constituting the gate electrode G in order to adjust the threshold voltage of the MISFET. The cobalt silicide film constituting a part of the gate electrode is formed for reducing the resistance of the gate electrode G.

  Side walls SW made of, for example, a silicon oxide film are formed on the side walls on both sides of the gate electrode G. A shallow low-concentration impurity diffusion region is formed in the semiconductor substrate 1S (p-type well PWL2) immediately below the sidewall SW. EX3 is formed. This shallow low-concentration impurity diffusion region EX3 is an n-type semiconductor region and is formed in alignment with the gate electrode G. Deep high concentration impurity diffusion regions S1 and D1 are formed outside the shallow low concentration impurity diffusion region EX3. These deep high-concentration impurity diffusion regions S1 and D1 are also n-type semiconductor regions and are formed in alignment with the sidewalls SW. A cobalt silicide film CS for reducing resistance is formed on the surface of the deep high-concentration impurity diffusion regions S1 and D1. A source region is formed by the shallow low concentration impurity diffusion region EX3 and the deep high concentration impurity diffusion region S1, and a drain region is formed by the shallow low concentration impurity diffusion region EX3 and the deep high concentration impurity diffusion region D1. In this way, the MISFET is formed in the peripheral circuit region.

  Next, the configuration of the memory cell formed in the memory cell array region will be described. In FIG. 3, since the memory cell MC1 and the memory cell MC2 have the same configuration, the configuration of the memory cell will be described here taking the memory cell MC1 as an example.

  As shown in FIG. 3, in the memory cell array region, a well isolation layer NISO made of an n-type semiconductor region is formed on a semiconductor substrate 1S, and a p-type well PWL1 is formed on the well isolation layer NISO. A memory cell MC1 is formed on the p-type well PWL1. The memory cell MC1 includes a selection unit that selects the memory cell MC1 and a storage unit that stores information. First, the configuration of the selection unit that selects the memory cell MC1 will be described. The memory cell MC1 has a gate insulating film GOX formed on the semiconductor substrate 1S (p-type well PWL1), and a control gate electrode (control electrode) CG1 is formed on the gate insulating film GOX. The gate insulating film GOX is made of, for example, a silicon oxide film, and the control gate electrode CG1 is made of, for example, a polysilicon film and a cobalt silicide film formed on the polysilicon film. The cobalt silicide film is formed to reduce the resistance of the control gate electrode CG. The control gate electrode CG1 has a function of selecting the memory cell MC1. That is, a specific memory cell is selected by the control gate electrode CG1, and a write operation, an erase operation, or a read operation is performed on the selected memory cell.

  Next, the configuration of the storage unit of the memory cell MC1 will be described. A memory gate electrode MG1 is formed on one side wall of the control gate electrode CG1 via a laminated insulating film MIF1 made of an insulating film. The memory gate electrode MG1 has a sidewall shape formed on one side wall of the control gate electrode CG1, and is formed of a polysilicon film and a cobalt silicide film formed on the polysilicon film. The cobalt silicide film is formed to reduce the resistance of the memory gate electrode MG.

  A laminated insulating film MIF1 is formed between the control gate electrode CG1 and the memory gate electrode MG1 and between the memory gate electrode MG1 and the semiconductor substrate 1S. The stacked insulating film MIF1 includes a potential barrier film EV1 formed on the semiconductor substrate 1S, a charge storage film EC formed on the potential barrier film EV1, and a potential barrier formed on the charge storage film EC. It is composed of the film EV2. The potential barrier film EV1 is made of, for example, a silicon oxide film IF1, and functions as a gate insulating film formed between the memory gate electrode MG and the semiconductor substrate 1S. The potential barrier film EV1 made of the silicon oxide film IF1 also has a function as a tunnel insulating film. For example, the storage unit of the memory cell stores and erases information by injecting electrons from the semiconductor substrate 1S into the charge storage film EC via the potential barrier film EV1 and injecting holes into the charge storage film EC. Therefore, the potential barrier film EV1 functions as a tunnel insulating film.

  The charge storage film EC formed on the potential barrier film EV1 has a function of storing charges. Specifically, in the first embodiment, the charge storage film EC is formed from the silicon nitride film IF2. The storage unit of the memory cell MC1 in the first embodiment stores information by controlling the current flowing in the semiconductor substrate 1S under the memory gate electrode MG1 depending on the presence / absence of charges stored in the charge storage film EC. It is like that. That is, information is stored using the fact that the threshold voltage of the current flowing in the semiconductor substrate 1S under the memory gate electrode MG1 changes depending on the presence or absence of charges accumulated in the charge storage film EC.

  In the first embodiment, an insulating film having a trap level is used as the charge storage film EC. An example of the insulating film having the trap level is a silicon nitride film IF2. However, the insulating film is not limited to the silicon nitride film IF2. For example, an aluminum oxide film (alumina), a hafnium oxide film, a tantalum oxide film, or the like is used. Alternatively, a high dielectric constant film having a high dielectric constant may be used. When an insulating film having a trap level is used as the charge storage film EC, charges are trapped in the trap level formed in the insulating film. Thus, charges are accumulated in the insulating film by trapping the charges at the trap level.

  Conventionally, a polysilicon film has been mainly used as the charge storage film EC. However, when a polysilicon film is used as the charge storage film EC, somewhere in the potential barrier film EV1 or the potential barrier film EV2 surrounding the charge storage film EC. If there is a defect in part, since the charge storage film EC is a conductor film, all charges stored in the charge storage film EC may be lost due to abnormal leakage.

  Therefore, a silicon nitride film IF2 that is an insulator has been used as the charge storage film EC. In this case, charges contributing to data storage are accumulated in discrete trap levels (capture levels) existing in the silicon nitride film IF2. Therefore, even if a defect occurs in a part of the potential barrier film EV1 or the potential barrier film EV2 surrounding the charge storage film EC, the charge is stored in the discrete trap levels of the charge storage film EC. Charges do not escape from the charge storage film EC. For this reason, the reliability of data retention can be improved.

  For this reason, not only the silicon nitride film IF2 but also a film including discrete trap levels can be used as the charge storage film EC, thereby improving data retention reliability. Further, in the first embodiment, the silicon nitride film IF2 having excellent data retention characteristics is used as the charge storage film EC. Therefore, the thicknesses of the potential barrier film EV1 and the potential barrier film EV2 provided for preventing the outflow of charges from the charge storage film EC can be reduced. Thus, there is an advantage that the voltage for driving the memory cell can be lowered.

  Next, the memory gate electrode MG1 is formed on one side of the side wall of the control gate electrode CG1, while the side wall SW made of a silicon oxide film is formed on the other side. Similarly, a control gate electrode CG1 is formed on one side of the sidewalls of the memory gate electrode MG1, and a sidewall SW made of a silicon oxide film is formed on the other side.

  In the semiconductor substrate 1S, a pair of shallow low-concentration impurity diffusion regions EX1, EX2 that are n-type semiconductor regions are formed in alignment with the control gate electrode CG1, and the pair of shallow low-concentration impurity diffusion regions EX1, A pair of deep high-concentration impurity diffusion regions MS and MD are formed in an outer region in contact with EX2. The deep high-concentration impurity diffusion regions MS and MD are also n-type semiconductor regions, and a cobalt silicide film CS is formed on the surface of the deep high-concentration impurity diffusion region MD. A pair of shallow low-concentration impurity diffusion regions EX1 and EX2 and a pair of deep high-concentration impurity diffusion regions MS and MD form a source region or a drain region of the memory cell. Specifically, a source region is formed by the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region MS, and a drain region is formed by the shallow low-concentration impurity diffusion region EX2 and the deep high-concentration impurity diffusion region MD.

  By forming the source region and the drain region with the shallow low-concentration impurity diffusion regions EX1, EX2 and the deep high-concentration impurity diffusion regions MS, MD, the source region and the drain region can have an LDD (Lightly Doped Drain) structure. Here, the transistor including the gate insulating film GOX, the control gate electrode CG1 formed on the gate insulating film GOX, and the above-described source region and drain region is referred to as a selection transistor. On the other hand, the insulating film MIF1 including the potential barrier film EV1, the charge storage film EC, and the potential barrier film EV2, the memory gate electrode MG1 formed on the stacked insulating film MIF1, and the above-described source region and drain region are included. The transistor will be called a memory transistor. Thereby, it can be said that the selection unit of the memory cell MC1 is configured by a selection transistor, and the storage unit of the memory cell MC1 is configured by a memory transistor. In this way, the memory cell MC1 is configured.

  Subsequently, a wiring structure connected to the memory cell MC1 will be described. Over the memory cell MC1, an interlayer insulating film IL made of a silicon oxide film is formed so as to cover the memory cell MC1. In the interlayer insulating film IL, a contact hole that penetrates the interlayer insulating film IL and reaches the cobalt silicide film CS constituting the drain region is formed. A titanium / titanium nitride film as a barrier conductor film is formed inside the contact hole, and a tungsten film is formed so as to fill the contact hole. Thus, the conductive plug PLG1 is formed by embedding the titanium / titanium nitride film and the tungsten film in the contact hole. A wiring L1 is formed on the interlayer insulating film IL, and the wiring L1 and the plug PLG1 are electrically connected. The wiring L1 is formed of, for example, a laminated film of a tantalum / tantalum nitride film and a copper film.

  Next, the source line SL that is a feature of the first embodiment will be described. As shown in FIG. 3, a source wiring SL is formed in the semiconductor substrate 1S (p-type well PWL1) so as to be in contact with the sidewall SW formed on the sidewall of the memory gate electrode MG1. The source line SL is formed on the semiconductor substrate 1S so as to be electrically connected to a source region (a shallow low-concentration impurity diffusion region EX1 and a deep high-concentration impurity diffusion region MS) formed in the semiconductor substrate 1S. . The source region functions not only as a memory cell MC1 but also as a source region for the memory cell MC2. That is, the source region constituted by the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region MS is shared by the memory cell MC1 and the memory cell MC2. Therefore, this source region is formed not only in alignment with the memory cell MC1, but also in alignment with the memory cell MC2. For example, as shown in FIG. 3, a shallow low-concentration impurity diffusion region EX1 is formed in alignment with the memory gate electrode MG2 of the memory cell MC2, and is aligned with the sidewall SW formed on the side wall of the memory gate electrode MG2. Deep deep high-concentration impurity diffusion regions MS are formed.

  Therefore, the source line SL formed on the source region contacts both the sidewall SW formed on the sidewall of the memory gate electrode MG1 and the sidewall SW formed on the sidewall of the memory gate electrode MG2. It is formed to do. That is, the source line SL is formed with the sidewall SW sandwiched between the memory gate electrode MG1 constituting the memory cell MC1 and the memory gate electrode MG2 constituting the memory cell MC2. This means that the source wiring SL formed so as to be sandwiched between the memory cell MC1 and the memory cell MC2 is formed in a self-aligned manner via the sidewall SW. For this reason, the distance between the memory cell MC1 and the memory cell MC2 can be minimized. Therefore, according to the first embodiment, it is possible to promote downsizing of the memory cell array by forming the source wiring SL as described above. The source wiring SL is formed of, for example, a polysilicon film and a cobalt silicide film formed on the surface of the polysilicon film. The cobalt silicide film is formed to reduce the resistance of the source line SL.

  Further, features of the first embodiment will be described. As shown in FIG. 3, in the first embodiment, the shape of the control gate electrode CG1 is a sidewall shape. Thereby, the width of the control gate electrode CG1 can be sufficiently narrowed, so that the cell size of the memory cell MC1 can be reduced. As a result, the memory cell array can be downsized. In a normal split gate type memory cell, the control gate electrode has a rectangular shape, and a sidewall-shaped memory gate electrode is formed on the side wall of the rectangular control gate electrode. On the other hand, in the first embodiment, as shown in FIG. 3, not only the memory gate electrode MG1 but also the control gate electrode CG1 has a sidewall shape. As a result, the size of the sidewall-shaped control gate electrode CG1 can be made smaller than the size of the rectangular control gate electrode, so that the size of the memory cell MC1 can be reduced.

  In particular, the size of the rectangular control gate electrode is determined by the minimum processing dimension of the photolithography technique, but the side wall-shaped control gate electrode CG1 is formed with a size smaller than the minimum processing dimension of the photolithography technique. There are advantages that can be made. That is, the sidewall-shaped control gate electrode CG1 can be formed as follows. For example, a rectangular dummy insulating film (for example, a silicon nitride film) is formed by photolithography, and a polysilicon film is formed so as to cover the dummy insulating film. Thereafter, anisotropic etching is performed on the polysilicon film to form a sidewall-shaped control gate electrode CG1 on the side wall of the dummy insulating film. Then, if the dummy insulating film is removed, the sidewall-shaped control gate electrode CG1 can be formed. At this time, the dummy insulating film is defined by the dimensional accuracy of the photolithography technique, but the sidewall formed on the side wall of the dummy insulating film uses an etching technique instead of the photolithography technique. It can be formed smaller than the processing dimension. Therefore, according to the first embodiment, not only the memory gate electrode MG1 but also the control gate electrode CG1 is formed in a sidewall shape, so that the size reduction of the nonvolatile semiconductor memory device can be promoted.

  The memory cell in the first embodiment is configured as described above, and the operation of the memory cell will be described below. Here, as shown in FIG. 4, the voltage applied to the control gate electrode is Vcg, and the voltage applied to the memory gate electrode is Vmg. Further, voltages applied to the source region and the drain region are Vs and Vd, respectively, and a voltage applied to the semiconductor substrate (p-type well) is Vsub. The injection of electrons into the silicon nitride film as the charge storage film is defined as “writing”, and the injection of holes into the silicon nitride film is defined as “erasing”.

  First, the write operation will be described. The writing operation is performed by hot electron writing called a so-called source side injection method (source side injection method). As the write voltage, for example, the voltage Vs applied to the source region is 6V, the voltage Vmg applied to the memory gate electrode is 12V, and the voltage Vcg applied to the control gate electrode is 1.5V. The voltage Vd applied to the drain region is controlled so that the channel current at the time of writing becomes a certain set value. The voltage Vd at this time is determined by the set value of the channel current and the threshold voltage of the selection transistor having the control gate electrode, and is, for example, about 1V. The voltage Vsub applied to the p-type well PWL (semiconductor substrate 1S) is 0V.

  The movement of charges when performing such a write operation by applying such a voltage is shown. As described above, by applying a potential difference between the voltage Vs applied to the source region and the voltage Vd applied to the drain region, electrons (electrons) flow through the channel region formed between the source region and the drain region. . Electrons flowing through the channel region are accelerated into hot electrons in the channel region (between the source region and the drain region) near the boundary between the control gate electrode CG and the memory gate electrode MG. Then, hot electrons are injected into the silicon nitride film (charge storage film EC) under the memory gate electrode MG by a vertical electric field by a positive voltage (Vmg = 12 V) applied to the memory gate electrode MG. The injected hot electrons are trapped in the trap level in the silicon nitride film, and as a result, electrons are accumulated in the silicon nitride film and the threshold voltage of the memory transistor rises. In this way, the write operation is performed.

  Next, the erase operation will be described. The erasing operation is performed by, for example, BTBT (Band to Band Tunneling) erasing using the band-to-band tunneling phenomenon. In BTBT erase, for example, the voltage Vmg applied to the memory gate electrode is −6 V, the voltage Vs applied to the source region is 6 V, the voltage Vcg applied to the control gate electrode is 0 V, and the drain region is open. As a result, the holes generated by the band-band tunneling phenomenon at the end of the source region due to the voltage applied between the source region and the memory gate electrode are accelerated by the high voltage applied to the source region to become hot holes. . A part of the hot hole is attracted to the negative voltage applied to the memory gate electrode and injected into the silicon nitride film. The injected hot holes are captured by trap levels in the silicon nitride film, and the threshold voltage of the memory transistor is lowered. In this way, the erase operation is performed.

  Next, the reading operation will be described. For reading, the voltage Vd applied to the drain region is Vdd (1.5 V), the voltage Vs applied to the source region is 0 V, the voltage Vcg applied to the control gate electrode is Vdd (1.5 V), and is applied to the memory gate electrode. The voltage Vmg is set to 0 V, and current is supplied in the direction opposite to that at the time of writing. The voltage Vd applied to the drain region and the voltage Vs applied to the source region may be switched to 0 V and 1.5 V, respectively, so that reading with the same current direction as that at the time of writing may be performed. At this time, when the memory cell is in a write state and the threshold voltage is high, no current flows through the memory cell. On the other hand, when the memory cell is in the erased state and the threshold voltage is low, a current flows through the memory cell.

  In this manner, whether the memory cell is in a written state or an erased state can be determined by detecting the presence or absence of a current flowing through the memory cell. Specifically, the presence or absence of current flowing through the memory cell is detected by a sense amplifier. For example, a reference current (reference current) is used to detect the presence or absence of a current flowing through the memory cell. That is, when the memory cell is in the erased state, a read current flows during reading, and the read current is compared with the reference current. The reference current is set lower than the read current in the erased state. If the read current is larger than the reference current as a result of comparing the read current and the reference current, it can be determined that the memory cell is in the erased state. On the other hand, when the memory cell is in a write state, no read current flows. That is, as a result of comparing the read current with the reference current, if the read current is smaller than the reference current, it can be determined that the memory cell is in the write state. In this way, a read operation can be performed.

  The nonvolatile semiconductor memory device according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings. 5 to 21 for describing a method for manufacturing a nonvolatile semiconductor memory device, a memory cell array region and a peripheral circuit region will be described while being illustrated at the same time.

  First, as shown in FIG. 5, a semiconductor substrate 1S made of a silicon single crystal into which a p-type impurity such as boron (B) is introduced is prepared. At this time, the semiconductor substrate 1S is in a state of a substantially wafer-shaped semiconductor wafer. Then, an element isolation region STI for separating the memory cell array region and the peripheral circuit region of the semiconductor substrate 1S is formed. The element isolation region STI is provided to prevent the elements from interfering with each other. The element isolation region STI can be formed using, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method. For example, in the STI method, the element isolation region STI is formed as follows. That is, the element isolation trench is formed in the semiconductor substrate 1S by using the photolithography technique and the etching technique. Then, a silicon oxide film is formed on the semiconductor substrate 1S so as to fill the element isolation trench, and then unnecessary silicon oxide formed on the semiconductor substrate 1S by chemical mechanical polishing (CMP). Remove the membrane. As a result, the element isolation region STI in which the silicon oxide film is embedded only in the element isolation trench can be formed.

  Subsequently, the well isolation layer NISO is formed by introducing impurities into the semiconductor substrate 1S in the memory cell array region. The well isolation layer NISO is formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 1S. Then, impurities are introduced into the semiconductor substrate 1S to form p-type wells PWL1 to PWL2. The p-type wells PWL1 to PWL2 are formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by an ion implantation method. Specifically, the p-type well PWL1 is formed in the memory cell array region, and the p-type well PWL2 is formed in the peripheral circuit region.

  Next, as shown in FIG. 6, a silicon nitride film is formed on the semiconductor substrate 1S. The silicon nitride film can be formed by, for example, a CVD (Chemical Vapor Deposition) method. Then, a resist film FR1 is applied on the silicon nitride film. Thereafter, the resist film FR1 is patterned by performing exposure / development processing on the applied resist film FR1. The patterning of the resist film FR1 is performed so that the resist film FR1 remains only in the region where the dummy insulating film is formed. Then, the silicon nitride film is processed by etching using the patterned resist film FR1 as a mask to form a dummy insulating film DI in the memory cell array region.

Subsequently, as shown in FIG. 7, after removing the patterned resist film FR1, a gate insulating film GOX is formed on the semiconductor substrate 1S. The gate insulating film GOX is a film that becomes a gate insulating film of a memory cell, which will be described later, and a gate insulating film of a MISFET formed in the peripheral circuit region. Therefore, the gate insulating film GOX is formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film GOX is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film GOX may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film GOX can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film as the gate insulating film GOX, it is possible to suppress a variation in threshold voltage due to diffusion of impurities in the gate electrode toward the semiconductor substrate 1S. For example, the silicon oxynitride film may be formed by heat-treating the semiconductor substrate 1S in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . Further, after forming a gate insulating film GOX made of a silicon oxide film on the surface of the semiconductor substrate 1S, the semiconductor substrate 1S is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S. The same effect can be obtained also by making it.

  Further, the gate insulating film GOX may be formed of a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film, for example. Conventionally, a silicon oxide film has been used as the gate insulating film GOX from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film GOX is required to be extremely thin. When such a thin silicon oxide film is used as the gate insulating film GOX, a so-called tunnel current is generated in which electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric constant film capable of increasing the physical film thickness even when the capacitance is the same has been used. According to the high dielectric film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced.

For example, a hafnium oxide film (HfO ₂ film), which is one of hafnium oxides, is used as the high dielectric film. Instead of the hafnium oxide film, a hafnium aluminate film, an HfON film (hafnium oxynitride film) is used. ), HfSiO films (hafnium silicate films), HfSiON films (hafnium silicon oxynitride films), HfAlO films, and other hafnium-based insulating films can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Next, a polysilicon film PF1 is formed on the semiconductor substrate 1S. The polysilicon film PF1 can be formed by, for example, a CVD method. After introducing an n-type impurity such as phosphorus into the polysilicon film PF1, a resist film FR2 is formed on the polysilicon film PF1, and the resist film FR2 is subjected to patterning by exposure and development. The patterning is performed so as to open the memory cell array region and cover the peripheral circuit region. Then, the polysilicon film PF1 is processed by etching using the patterned resist film FR2 as a mask. At this time, in the memory cell array region, the polysilicon film PF1 is anisotropically etched, and the polysilicon film PF1 remains only on the sidewall of the dummy insulating film DI. The polysilicon film PF1 formed on the side wall of the dummy insulating film DI serves as a side wall-shaped control gate electrode. As a result, the sidewall-shaped control gate electrode can be formed without being defined by the minimum processing dimension by the photolithography technique. Therefore, it is possible to promote downsizing of the memory cell. Since the peripheral circuit region is covered with the resist film FR2, the polysilicon film PF1 remains without being etched.

  Here, n-type impurities are introduced into the polysilicon film PF1 constituting the control gate electrode. For this reason, the work function value of the control gate electrode can be set to a value in the vicinity of the conduction band of silicon (4.15 eV), so that the threshold voltage of the selection transistor that is an n-channel MISFET can be reduced.

  Next, as shown in FIG. 8, after the patterned resist film FR2 and the dummy insulating film DI made of the silicon nitride film are removed, the laminated insulating film MIF is formed on the semiconductor substrate 1S covering the control gate electrodes CG1, CG2, and CG. Form. The laminated insulating film MIF is formed of, for example, a silicon oxide film, a silicon nitride film formed on the silicon oxide film, and a silicon oxide film formed on the silicon nitride film (ONO film). These laminated insulating films can be formed using, for example, a CVD method. For example, the thickness of the lower silicon oxide film is 5 nm, the thickness of the silicon nitride film is 10 nm, and the thickness of the upper silicon oxide film is 5 nm.

  Of the stacked insulating film MIF, the silicon nitride film is a film that becomes a charge storage film of the memory transistor in the memory cell array region. In the first embodiment, a silicon nitride film is used as the charge storage film, but the charge storage film may be formed of another insulating film having a trap level. For example, an aluminum oxide film (alumina film) can be used as the charge storage film.

  Subsequently, a polysilicon film PF2 is formed on the semiconductor substrate 1S. Further, an n-type impurity such as phosphorus is introduced into the polysilicon film PF2. Then, anisotropic etching is performed on the polysilicon film PF2. Thereby, in the memory cell array region, a sidewall-shaped polysilicon film PF2 is formed on the side walls of the control gate electrodes CG1, CG2, and CG. On the other hand, in the peripheral circuit region, the polysilicon film PF2 is completely removed, and the laminated insulating film MIF is exposed.

  Thereafter, as shown in FIG. 9, a resist film FR3 is formed on the semiconductor substrate 1S, and the resist film FR3 is subjected to exposure / development processing for patterning. The patterning is performed so as to cover the side wall on one side of the control gate electrodes CG1, CG2, and CG formed in the memory cell array region. Then, the sidewall-like polysilicon film PF2 not covered with the resist film FR3 of the control gate electrodes CG1, CG2, and CG is removed by etching using the patterned resist film FR3 as a mask. As a result, the sidewall-shaped memory gate electrodes MG1, MG2, and MG can be formed only on one side wall of the control gate electrodes CG1, CG2, and CG. The memory gate electrodes MG1, MG2, and MG are formed from the polysilicon film PF2.

  Next, as shown in FIG. 10, after removing the patterned resist film FR3, a resist film FR4 is formed on the semiconductor substrate 1S, and the resist film FR4 is subjected to exposure / development processing for patterning. The patterning is performed so as to expose a region sandwiched between the opposing memory gate electrodes MG1, MG2, and MG. Then, the exposed laminated insulating film MIF is removed using the patterned resist film FR4 as a mask to expose the surface of the semiconductor substrate 1S. Thereafter, by using an ion implantation method, a shallow low-concentration impurity diffusion region EX1 is formed in the semiconductor substrate 1S exposed from the mask made of the resist film FR4. The shallow low-concentration impurity diffusion region EX1 is an n-type semiconductor region, and is formed by introducing an n-type impurity such as phosphorus into the semiconductor substrate 1S.

  Subsequently, as shown in FIG. 11, after removing the patterned resist film FR4, a silicon oxide film is formed on the semiconductor substrate 1S. The silicon oxide film can be formed by using, for example, a CVD method. Then, by performing anisotropic etching on the silicon oxide film, sidewalls (sidewall insulating films) SW are formed on the side walls of the control gate electrodes CG1, CG2, CG and the memory gate electrodes MG1, MG2, MG. . Thereafter, a resist film FR5 is formed on the semiconductor substrate 1S, and the resist film FR5 is patterned by performing exposure and development processing. Patterning is performed so as to open a region sandwiched between the memory gate electrodes MG1, MG2, and MG facing each other. Then, by ion implantation using the patterned resist film FR5 as a mask, a deep high-concentration impurity diffusion region MS is formed in the semiconductor substrate 1S in alignment with the sidewall SW formed on the sidewall of the memory gate electrodes MG1, MG2, and MG. Form. The deep high-concentration impurity diffusion region MS is an n-type semiconductor region, and is a region into which n-type impurities are introduced at a higher concentration than the shallow low-concentration impurity diffusion region EX1. The source region of the memory cell is formed by the deep high concentration impurity diffusion region MS and the shallow low concentration impurity diffusion region EX1.

  Next, as shown in FIG. 12, after removing the patterned resist film FR5, a resist film FR6 is formed again on the semiconductor substrate 1S. Then, the resist film FR6 is patterned by performing an exposure / development process. The patterning is performed so as to cover the opposing memory gate electrodes MG1, MG2, and MG. The side wall SW formed on the side walls of the control gate electrodes CG1, CG2, and CG is removed by etching using the patterned resist film FR6 as a mask.

  Subsequently, as shown in FIG. 13, after removing the patterned resist film FR6, a polysilicon film PF3 is formed on the semiconductor substrate 1S. Thereafter, the polysilicon film PF3 is etched partway. Thereby, the height of the polysilicon film PF3 is made lower than the height of the sidewall SW formed on the sidewalls of the memory gate electrodes MG1, MG2, and MG.

  Next, as shown in FIG. 14, a resist film FR7 is formed on the semiconductor substrate 1S, and the resist film FR7 is subjected to exposure / development processing for patterning. The patterning is performed so as to cover the space between the opposing memory gate electrodes MG1, MG2, and MG. The polysilicon film PF3 is etched using the patterned resist film FR7 as a mask. As a result, only the polysilicon film PF3 formed between the memory gate electrodes MG1, MG2, and MG covered with the resist film FR7 remains, and the source wiring SL made of the polysilicon film PF3 is formed. That is, the source line SL can be formed in alignment with the sidewall SW formed on the sidewalls of the opposing memory gate electrodes MG1, MG2, and MG. This source line SL is electrically connected to the underlying source region (the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region MS).

  Subsequently, as shown in FIG. 15, after removing the patterned resist film FR7, the laminated insulating film MIF exposed on the semiconductor substrate 1S is removed. At this time, the stacked insulating film MIF formed between the control gate electrodes CG1, CG2, CG and the memory gate electrodes MG1, MG2, MG and between the memory gate electrodes MG1, MG2, MG and the semiconductor substrate 1S is exposed. Because it is not, it will remain.

  Next, as shown in FIG. 16, a resist film FR8 is formed on the semiconductor substrate 1S. Then, the resist film FR8 is patterned by performing an exposure / development process. The patterning is performed so as to cover the memory cell array region and leave the resist film FR8 in the gate electrode formation region in the peripheral circuit region. Thereafter, as shown in FIG. 17, a gate electrode G made of the polysilicon film PF1 is formed in the peripheral circuit region by etching using the patterned resist film FR8 as a mask. Thereafter, the patterned resist film FR8 is removed.

  Subsequently, as shown in FIG. 18, by using a photolithography technique and an ion implantation method, a shallow low-concentration impurity diffusion region EX2 is formed in the semiconductor substrate 1S in the memory cell array region, and the semiconductor substrate 1S in the peripheral circuit region is formed. A shallow low-concentration impurity diffusion region EX3 is formed therein. Specifically, in the memory cell array region, a shallow low-concentration impurity diffusion region EX2 that is an n-type semiconductor region is formed in alignment with the control gate electrodes CG1, CG2, and CG. On the other hand, in the peripheral circuit region, a shallow low-concentration impurity diffusion region EX3 that is an n-type semiconductor region is formed in alignment with the gate electrode G.

  Next, as shown in FIG. 19, a silicon oxide film is formed on the semiconductor substrate 1S by using, for example, a CVD method, and then anisotropic etching is performed on the silicon oxide film to thereby form a sidewall. SW is formed. Specifically, a side wall SW is formed on one side wall of the control gate electrodes CG1, CG2, and CG in the memory cell array region. On the other hand, in the peripheral circuit region, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G.

  Thereafter, the deep high concentration impurity diffusion region MD and the deep high concentration impurity diffusion regions S1 and D1 are formed in the semiconductor substrate 1S by using an ion implantation method. Specifically, in the memory cell array region, a deep high-concentration impurity diffusion region MD is formed in alignment with the sidewall SW formed on the sidewalls of the control gate electrodes CG1, CG2, and CG. On the other hand, in the peripheral circuit region, deep high-concentration impurity diffusion regions S1 and D1 are formed in alignment with the sidewall SW formed on the sidewall of the gate electrode G. In the memory cell array region, the drain region of the memory cell is formed by the deep high concentration impurity diffusion region MD and the shallow low concentration impurity diffusion region EX2. Similarly, in the peripheral circuit region, the source region or the drain region of the MISFET is formed by the deep high concentration impurity diffusion regions S1 and D1 and the shallow low concentration impurity diffusion region EX3. Thus, after forming the deep high-concentration impurity diffusion regions MD, S1, and D1, heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Next, the silicide process will be described with reference to FIG. A cobalt film is formed on the semiconductor substrate 1S. At this time, in the memory cell array region, a cobalt film is formed so as to be in direct contact with the exposed control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG, and the source line SL. Similarly, the cobalt film is also in direct contact with the deep high-concentration impurity diffusion region MD. On the other hand, also in the peripheral circuit region, the cobalt film contacts the gate electrode G and the deep high-concentration impurity diffusion regions S1 and D1.

  Thereafter, heat treatment is performed on the semiconductor substrate 1S. As a result, in the memory cell array region, the control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG, the polysilicon films PF1, PF2, and PF3 constituting the source line SL and the cobalt film are reacted. Then, a cobalt silicide film CS is formed. As a result, the control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG, and the source line SL have a stacked structure of the polysilicon films PF1, PF2, and PF3 and the cobalt silicide film CS, respectively. The cobalt silicide film CS is formed to reduce the resistance of the control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG and the source line SL. Similarly, by the heat treatment described above, the cobalt silicide film CS is formed by the reaction between silicon and the cobalt film on the surface of the deep high-concentration impurity diffusion region MD. Therefore, it is possible to reduce the resistance even in the deep high-concentration impurity diffusion region MD.

  Similarly, also in the peripheral circuit region, the polysilicon film PF1 constituting the gate electrode G and the cobalt film are reacted to form the cobalt silicide film CS. As a result, each gate electrode G has a laminated structure of the polysilicon film PF1 and the cobalt silicide film CS. The cobalt silicide film CS is formed to reduce the resistance of the gate electrode G. By the heat treatment described above, the cobalt silicide film CS is formed by the reaction between the silicon and the cobalt film on the surfaces of the deep high-concentration impurity diffusion regions S1 and D1. For this reason, it is possible to reduce the resistance even in the deep high-concentration impurity diffusion regions S1 and D1.

  Then, the unreacted cobalt film is removed from the semiconductor substrate 1S. In the first embodiment, the cobalt silicide film CS is formed. However, for example, a nickel silicide film or a titanium silicide film may be formed instead of the cobalt silicide film CS. As described above, a plurality of memory cells can be formed in the memory cell array region of the semiconductor substrate 1S, and a MISFET can be formed in the peripheral circuit region.

  Next, the wiring process will be described with reference to FIG. As shown in FIG. 20, an interlayer insulating film IL is formed on the main surface of the semiconductor substrate 1S. The interlayer insulating film IL is formed of, for example, a silicon oxide film, and can be formed using, for example, a CVD method using TEOS (tetraethyl orthosilicate) as a raw material. Thereafter, the surface of the interlayer insulating film IL is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, contact holes CNT are formed in the interlayer insulating film IL by using a photolithography technique and an etching technique. A plurality of contact holes CNT are formed in the memory cell array region and the peripheral circuit region. Then, a titanium / titanium nitride film is formed on interlayer insulating film IL including the bottom surface and inner wall of contact hole CNT. The titanium / titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. This titanium / titanium nitride film has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later process, from diffusing into silicon.

  Subsequently, a tungsten film is formed on the entire main surface of the semiconductor substrate 1S so as to fill the contact holes CNT. This tungsten film can be formed using, for example, a CVD method. Then, unnecessary plugs PLG1, PLG2, and PLG can be formed by removing unnecessary titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL by using, for example, a CMP method.

  Next, as shown in FIG. 21, an interlayer insulating film IL2 is formed on the interlayer insulating film IL on which the plugs PLG1, PLG2, and PLG are formed. Then, a trench is formed in the interlayer insulating film IL2 by using a photolithography technique and an etching technique. Thereafter, a tantalum / tantalum nitride film is formed on the interlayer insulating film IL2 including the inside of the trench. This tantalum / tantalum nitride film can be formed by sputtering, for example. Subsequently, after a seed film made of a thin copper film is formed on the tantalum / tantalum nitride film by, for example, a sputtering method, an electrolytic plating method using this seed film as an electrode is formed on the interlayer insulating film IL2 in which the groove is formed. A copper film is formed. Thereafter, the copper film exposed on the interlayer insulating film IL2 other than the inside of the trench is removed by polishing, for example, by CMP, thereby leaving the copper film only in the trench formed in the interlayer insulating film IL2. . Thereby, the wiring L1 can be formed. Furthermore, a multilayer wiring is formed in the upper layer of the wiring L1, but the description here is omitted. In this manner, the nonvolatile semiconductor memory device in the first embodiment can be finally formed.

(Embodiment 2)
FIG. 22 is a sectional view showing a sectional structure of the nonvolatile semiconductor memory device according to the second embodiment. The nonvolatile semiconductor memory device in the second embodiment and the nonvolatile semiconductor memory device in the first embodiment have substantially the same configuration, and the difference is in the shape of the control gate electrodes CG1, CG2, and CG. Specifically, in the first embodiment, the control gate electrodes CG1, CG2, and CG have a sidewall shape. In the second embodiment, the control gate electrodes CG1, CG2, and CG have a rectangular shape. Is different. However, also in the second embodiment, as shown in FIG. 22, the source wiring is sandwiched between the memory gate electrode MG1 constituting the memory cell MC1 and the memory gate electrode MG2 constituting the memory cell MC2. SL is formed. That is, the source line SL formed so as to be sandwiched between the memory cell MC1 and the memory cell MC2 is formed in a self-aligned manner via the sidewall SW. For this reason, the distance between the memory cell MC1 and the memory cell MC2 can be minimized. Therefore, also in the second embodiment, as in the first embodiment, the memory cells constituting the nonvolatile semiconductor memory device can be reduced and the density thereof can be increased, and the nonvolatile semiconductor memory device as a product can be realized. The remarkable effect which can achieve further size reduction can be acquired.

  The nonvolatile semiconductor memory device according to the second embodiment is configured as described above. Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. To do.

  First, in the same manner as in the first embodiment, the element isolation region STI is formed in the semiconductor substrate 1S, and then the impurity is introduced into the semiconductor substrate 1S in the memory cell array region to form the well isolation layer NISO. The well isolation layer NISO is formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 1S. Then, impurities are introduced into the semiconductor substrate 1S to form p-type wells PWL1 to PWL2. The p-type wells PWL1 to PWL2 are formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by an ion implantation method. Specifically, the p-type well PWL1 is formed in the memory cell array region, and the p-type well PWL2 is formed in the peripheral circuit region.

  Next, as shown in FIG. 23, a gate insulating film GOX is formed on the semiconductor substrate 1S, and then a polysilicon film PF1 is formed on the gate insulating film GOX. The polysilicon film PF1 can be formed by, for example, a CVD method. The gate insulating film GOX is formed of, for example, a silicon oxide film. However, as in the first embodiment, a silicon oxynitride film or a high dielectric constant film having a higher dielectric constant than the silicon oxide film may be used. Good. After introducing an n-type impurity such as phosphorus into the polysilicon film PF1, a resist film FR10 is formed on the polysilicon film PF1. Then, the resist film FR10 is patterned by performing exposure / development processing. The patterning is performed so as to cover the peripheral circuit region and to leave the resist film FR10 in the region where the control gate electrodes CG1, CG2, and CG are formed in the memory cell array region.

  Subsequently, the polysilicon film PF1 and the gate insulating film GOX are processed by etching using the patterned resist film FR10 as a mask. Thereby, the control gate electrodes CG1, CG2, and CG made of the polysilicon film PF1 can be formed in the memory cell array region. Since the control gate electrodes CG1, CG2, and CG formed at this time are formed using a normal photolithography technique, they are processed into a rectangular shape.

  Here, n-type impurities are introduced into the polysilicon film PF1 constituting the control gate electrode. For this reason, the work function value of the control gate electrode can be set to a value in the vicinity of the conduction band of silicon (4.15 eV), so that the threshold voltage of the selection transistor that is an n-channel MISFET can be reduced.

  Subsequently, as shown in FIG. 24, after removing the patterned resist film FR10, a laminated insulating film MIF is formed on the semiconductor substrate 1S covering the control gate electrodes CG1, CG2, and CG. The laminated insulating film MIF is formed of, for example, a silicon oxide film, a silicon nitride film formed on the silicon oxide film, and a silicon oxide film formed on the silicon nitride film (ONO film). These laminated insulating films can be formed using, for example, a CVD method. For example, the thickness of the lower silicon oxide film is 5 nm, the thickness of the silicon nitride film is 10 nm, and the thickness of the upper silicon oxide film is 5 nm.

  Of the stacked insulating film MIF, the silicon nitride film is a film that becomes a charge storage film of the memory transistor in the memory cell array region. In the second embodiment, a silicon nitride film is used as the charge storage film, but the charge storage film may be formed of another insulating film having a trap level. For example, an aluminum oxide film (alumina film) can be used as the charge storage film.

  Next, a polysilicon film PF2 is formed on the semiconductor substrate 1S. Further, an n-type impurity such as phosphorus is introduced into the polysilicon film PF2. Then, anisotropic etching is performed on the polysilicon film PF2. Thereby, in the memory cell array region, a sidewall-shaped polysilicon film PF2 is formed on the side walls of the control gate electrodes CG1, CG2, and CG. On the other hand, in the peripheral circuit region, the polysilicon film PF2 is completely removed, and the laminated insulating film MIF is exposed.

  Thereafter, as shown in FIG. 25, a resist film FR11 is formed on the semiconductor substrate 1S, and the resist film FR11 is subjected to patterning by exposure and development. The patterning is performed so as to cover the side wall on one side of the control gate electrodes CG1, CG2, and CG formed in the memory cell array region. Then, the sidewall-like polysilicon film PF2 not covered with the resist film FR11 of the control gate electrodes CG1, CG2, and CG is removed by etching using the patterned resist film FR11 as a mask. As a result, the sidewall-shaped memory gate electrodes MG1, MG2, and MG can be formed only on one side wall of the control gate electrodes CG1, CG2, and CG. The memory gate electrodes MG1, MG2, and MG are formed from the polysilicon film PF2.

  Next, as shown in FIG. 26, after the patterned resist film FR11 is removed, a resist film FR12 is formed on the semiconductor substrate 1S, and the resist film FR12 is subjected to exposure and development processing for patterning. The patterning is performed so as to expose a region sandwiched between the opposing memory gate electrodes MG1, MG2, and MG. Then, the exposed laminated insulating film MIF is removed using the patterned resist film FR12 as a mask to expose the surface of the semiconductor substrate 1S. Thereafter, by using an ion implantation method, a shallow low-concentration impurity diffusion region EX1 is formed in the semiconductor substrate 1S exposed from the mask made of the resist film FR12. The shallow low-concentration impurity diffusion region EX1 is an n-type semiconductor region, and is formed by introducing an n-type impurity such as phosphorus into the semiconductor substrate 1S.

  Subsequently, as shown in FIG. 27, after removing the patterned resist film FR12, a silicon oxide film is formed on the semiconductor substrate 1S. The silicon oxide film can be formed by using, for example, a CVD method. Then, by performing anisotropic etching on the silicon oxide film, sidewalls (sidewall insulating films) SW are formed on the side walls of the control gate electrodes CG1, CG2, CG and the memory gate electrodes MG1, MG2, MG. . Thereafter, a resist film FR13 is formed on the semiconductor substrate 1S, and the resist film FR13 is patterned by performing exposure and development processing. Patterning is performed so as to open a region sandwiched between the memory gate electrodes MG1, MG2, and MG facing each other. Then, by ion implantation using the patterned resist film FR13 as a mask, a deep high-concentration impurity diffusion region MS is formed in the semiconductor substrate 1S in alignment with the sidewall SW formed on the sidewall of the memory gate electrodes MG1, MG2, and MG. Form. The deep high-concentration impurity diffusion region MS is an n-type semiconductor region, and is a region into which n-type impurities are introduced at a higher concentration than the shallow low-concentration impurity diffusion region EX1. The source region of the memory cell is formed by the deep high concentration impurity diffusion region MS and the shallow low concentration impurity diffusion region EX1.

  Next, as shown in FIG. 28, after removing the patterned resist film FR13, a resist film FR14 is formed again on the semiconductor substrate 1S. Then, the resist film FR14 is patterned by performing exposure / development processing. The patterning is performed so as to cover the opposing memory gate electrodes MG1, MG2, and MG. The side wall SW formed on the side walls of the control gate electrodes CG1, CG2, and CG is removed by etching using the patterned resist film FR14 as a mask.

  Subsequently, as shown in FIG. 29, after removing the patterned resist film FR14, a polysilicon film PF3 is formed on the semiconductor substrate 1S. Thereafter, the polysilicon film PF3 is etched partway. Thereby, the height of the polysilicon film PF3 is made lower than the height of the sidewall SW formed on the sidewalls of the memory gate electrodes MG1, MG2, and MG.

  Next, as shown in FIG. 30, a resist film FR15 is formed on the semiconductor substrate 1S, and the resist film FR15 is subjected to patterning by exposure and development processing. The patterning is performed so as to cover the space between the opposing memory gate electrodes MG1, MG2, and MG. The polysilicon film PF3 is etched using the patterned resist film FR15 as a mask. As a result, only the polysilicon film PF3 formed between the memory gate electrodes MG1, MG2, and MG covered with the resist film FR15 remains, and the source wiring SL made of the polysilicon film PF3 is formed. That is, the source line SL can be formed in alignment with the sidewall SW formed on the sidewalls of the opposing memory gate electrodes MG1, MG2, and MG. This source line SL is electrically connected to the underlying source region (the shallow low-concentration impurity diffusion region EX1 and the deep high-concentration impurity diffusion region MS).

  Subsequently, as shown in FIG. 31, after removing the patterned resist film FR15, the laminated insulating film MIF exposed on the semiconductor substrate 1S is removed. At this time, the stacked insulating film MIF formed between the control gate electrodes CG1, CG2, CG and the memory gate electrodes MG1, MG2, MG and between the memory gate electrodes MG1, MG2, MG and the semiconductor substrate 1S is exposed. Because it is not, it will remain.

  Next, as shown in FIG. 32, a resist film FR16 is formed on the semiconductor substrate 1S. Then, the resist film FR16 is patterned by performing exposure / development processing. The patterning is performed so as to cover the memory cell array region and leave the resist film FR16 in the gate electrode formation region in the peripheral circuit region. Thereafter, as shown in FIG. 33, the gate electrode G made of the polysilicon film PF1 is formed in the peripheral circuit region by etching using the patterned resist film FR16 as a mask. Thereafter, the patterned resist film FR16 is removed.

  Subsequently, as shown in FIG. 34, by using an ion implantation method, a shallow low-concentration impurity diffusion region EX2 is formed in the semiconductor substrate 1S in the memory cell array region, and a shallow low concentration in the semiconductor substrate 1S in the peripheral circuit region. A concentration impurity diffusion region EX3 is formed. Specifically, in the memory cell array region, a shallow low-concentration impurity diffusion region EX2 that is an n-type semiconductor region is formed in alignment with the control gate electrodes CG1, CG2, and CG. On the other hand, in the peripheral circuit region, a shallow low-concentration impurity diffusion region EX3 that is an n-type semiconductor region is formed in alignment with the gate electrode G.

  Next, as shown in FIG. 35, a silicon oxide film is formed on the semiconductor substrate 1S by using, for example, a CVD method, and then the silicon oxide film is subjected to anisotropic etching to form a sidewall. SW is formed. Specifically, a side wall SW is formed on one side wall of the control gate electrodes CG1, CG2, and CG in the memory cell array region. On the other hand, in the peripheral circuit region, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G.

  Thereafter, a deep high-concentration impurity diffusion region MD and deep high-concentration impurity diffusion regions S1 and D1 are formed in the semiconductor substrate 1S by using a photolithography technique and an ion implantation method. Specifically, in the memory cell array region, a deep high-concentration impurity diffusion region MD is formed in alignment with the sidewall SW formed on the sidewalls of the control gate electrodes CG1, CG2, and CG. On the other hand, in the peripheral circuit region, deep high-concentration impurity diffusion regions S1 and D1 are formed in alignment with the sidewall SW formed on the sidewall of the gate electrode G. In the memory cell array region, the drain region of the memory cell is formed by the deep high concentration impurity diffusion region MD and the shallow low concentration impurity diffusion region EX2. Similarly, in the peripheral circuit region, the source region or the drain region of the MISFET is formed by the deep high concentration impurity diffusion regions S1 and D1 and the shallow low concentration impurity diffusion region EX3. Thus, after forming the deep high-concentration impurity diffusion regions MD, S1, and D1, heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Next, the silicide process will be described with reference to FIG. A cobalt film is formed on the semiconductor substrate 1S. At this time, in the memory cell array region, a cobalt film is formed so as to be in direct contact with the exposed control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG, and the source line SL. Similarly, the cobalt film is also in direct contact with the deep high-concentration impurity diffusion region MD. On the other hand, also in the peripheral circuit region, the cobalt film contacts the gate electrode G and the deep high-concentration impurity diffusion regions S1 and D1.

  Thereafter, heat treatment is performed on the semiconductor substrate 1S. Thus, as shown in FIG. 36, in the memory cell array region, the control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG, and the polysilicon films PF1, PF2, and PF3 constituting the source line SL. And a cobalt film are reacted to form a cobalt silicide film CS. As a result, the control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG, and the source line SL have a stacked structure of the polysilicon films PF1, PF2, and PF3 and the cobalt silicide film CS, respectively. The cobalt silicide film CS is formed to reduce the resistance of the control gate electrodes CG1, CG2, and CG, the memory gate electrodes MG1, MG2, and MG and the source line SL. Similarly, by the heat treatment described above, the cobalt silicide film CS is formed by the reaction between silicon and the cobalt film on the surface of the deep high-concentration impurity diffusion region MD. Therefore, it is possible to reduce the resistance even in the deep high-concentration impurity diffusion region MD.

  Similarly, also in the peripheral circuit region, the polysilicon film PF1 constituting the gate electrode G and the cobalt film are reacted to form the cobalt silicide film CS. As a result, each gate electrode G has a laminated structure of the polysilicon film PF1 and the cobalt silicide film CS. The cobalt silicide film CS is formed to reduce the resistance of the gate electrode G. By the heat treatment described above, the cobalt silicide film CS is formed by the reaction between the silicon and the cobalt film on the surfaces of the deep high-concentration impurity diffusion regions S1 and D1. For this reason, it is possible to reduce the resistance even in the deep high-concentration impurity diffusion regions S1 and D1.

  Then, the unreacted cobalt film is removed from the semiconductor substrate 1S. In the second embodiment, the cobalt silicide film CS is formed. However, for example, a nickel silicide film or a titanium silicide film may be formed instead of the cobalt silicide film CS. As described above, a plurality of memory cells can be formed in the memory cell array region of the semiconductor substrate 1S, and a MISFET can be formed in the peripheral circuit region.

  Next, the wiring process will be described with reference to FIG. As shown in FIG. 36, an interlayer insulating film IL is formed on the main surface of the semiconductor substrate 1S. The interlayer insulating film IL is formed of, for example, a silicon oxide film, and can be formed using, for example, a CVD method using TEOS (tetraethyl orthosilicate) as a raw material. Thereafter, the surface of the interlayer insulating film IL is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, contact holes CNT are formed in the interlayer insulating film IL by using a photolithography technique and an etching technique. A plurality of contact holes CNT are formed in the memory cell array region and the peripheral circuit region. Then, a titanium / titanium nitride film is formed on interlayer insulating film IL including the bottom surface and inner wall of contact hole CNT. The titanium / titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. This titanium / titanium nitride film has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later process, from diffusing into silicon.

  Subsequently, a tungsten film is formed on the entire main surface of the semiconductor substrate 1S so as to fill the contact holes CNT. This tungsten film can be formed using, for example, a CVD method. Then, unnecessary plugs PLG1, PLG2, and PLG can be formed by removing unnecessary titanium / titanium nitride films and tungsten films formed on the interlayer insulating film IL by using, for example, a CMP method.

  Next, as shown in FIG. 37, an interlayer insulating film IL2 is formed on the interlayer insulating film IL on which the plugs PLG1, PLG2, and PLG are formed. Then, a trench is formed in the interlayer insulating film IL2 by using a photolithography technique and an etching technique. Thereafter, a tantalum / tantalum nitride film is formed on the interlayer insulating film IL2 including the inside of the trench. This tantalum / tantalum nitride film can be formed by sputtering, for example. Subsequently, after a seed film made of a thin copper film is formed on the tantalum / tantalum nitride film by, for example, a sputtering method, an electrolytic plating method using this seed film as an electrode is formed on the interlayer insulating film IL2 in which the groove is formed. A copper film is formed. Thereafter, the copper film exposed on the interlayer insulating film IL2 other than the inside of the trench is removed by polishing, for example, by CMP, thereby leaving the copper film only in the trench formed in the interlayer insulating film IL2. . Thereby, the wiring L1 can be formed. Furthermore, a multilayer wiring is formed in the upper layer of the wiring L1, but the description here is omitted. In this manner, the nonvolatile semiconductor memory device according to the second embodiment can be finally formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is a figure which shows the layout structure of the non-volatile semiconductor memory device in the comparative example which this inventor examined. It is a figure which shows the layout structure of the non-volatile semiconductor memory device in Embodiment 1 of this invention. 1 is a cross-sectional view showing a cross-sectional structure of a nonvolatile semiconductor memory device in Embodiment 1. FIG. 6 is a diagram showing operating conditions of the nonvolatile semiconductor memory device in the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 5. FIG. 7 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 6. FIG. 8 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 7. FIG. 9 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 8. FIG. 10 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 9. FIG. 11 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 10. FIG. 12 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 11. FIG. 13 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 12. FIG. 14 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 13. FIG. 15 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 14. FIG. 16 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 16. FIG. 18 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 17. FIG. 19 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device subsequent to FIG. 18. FIG. 20 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 19. FIG. 21 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 20. FIG. 6 is a cross-sectional view showing a cross-sectional structure of a nonvolatile semiconductor memory device in a second embodiment. 11 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in the second embodiment. FIG. FIG. 24 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 23. FIG. 25 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 24. FIG. 26 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 25; FIG. 27 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 26; FIG. 28 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device subsequent to FIG. 28. FIG. 30 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 29. FIG. 31 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 30; FIG. 32 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 31. FIG. 33 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device following FIG. 32. FIG. 34 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 33. FIG. 35 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 34. FIG. 36 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 35. FIG. 37 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 36.

Explanation of symbols

1S semiconductor substrate Act active region Act1 active region Act2 active region Act3 active region CG control gate electrode CG1 control gate electrode CG2 control gate electrode CNT contact hole CS cobalt silicide film D1 deep high-concentration impurity diffusion region DI dummy insulating film EC charge storage film EV1 Potential barrier film EV2 Potential barrier film EX1 Shallow low-concentration impurity diffusion region EX2 Shallow low-concentration impurity diffusion region EX3 Shallow low-concentration impurity diffusion region FR1 to FR16 Resist film G Gate electrode GOX Gate insulating film IF1 Silicon oxide film IF2 Silicon nitride film IF3 Oxide Silicon film IL Interlayer insulating film IL2 Interlayer insulating film L1 wiring MC1 memory cell MC2 memory cell MD Deep high-concentration impurity diffusion region MI Multilayer insulation film MIF1 Multilayer insulation film MIF2 Multilayer insulation film MG Memory gate electrode MG1 Memory gate electrode MG2 Memory gate electrode MS Deep high-concentration impurity diffusion region NISO well isolation layer PF1 Polysilicon film PF2 Polysilicon film PF3 Polysilicon film PLG plug PLG1 plug PLG2 plug PWL1 p-type well PWL2 p-type well S1 deep high-concentration impurity diffusion region SL source wiring STI element isolation region STI1 element isolation region STI2 element isolation region STI3 element isolation region STI4 element isolation region SW sidewall

Claims (22)

A first memory cell and a second memory cell adjacent to each other;
The first memory cell includes
(A1) a first gate insulating film formed on the semiconductor substrate;
(B1) a first control gate electrode formed on the first gate insulating film;
(C1) a first memory gate electrode formed on one side wall of the first control gate electrode;
(D1) a first stacked insulating film formed between the first control gate electrode and the first memory gate electrode and between the first memory gate electrode and the semiconductor substrate;
(E1) a first sidewall insulating film formed on a sidewall of the first memory gate electrode;
(F1) a first drain region formed in the semiconductor substrate and formed in alignment with a side wall of the first control gate electrode where the first memory gate electrode is not formed;
(G1) a first source region formed in the semiconductor substrate and formed in alignment with a side wall of the first memory gate electrode on which the first sidewall insulating film is formed;
The second memory cell includes
(A2) a second gate insulating film formed on the semiconductor substrate;
(B2) a second control gate electrode formed on the second gate insulating film;
(C2) a second memory gate electrode formed on one side wall of the second control gate electrode;
(D2) a second stacked insulating film formed between the second control gate electrode and the second memory gate electrode and between the second memory gate electrode and the semiconductor substrate;
(E2) a second sidewall insulating film formed on a sidewall of the second memory gate electrode;
(F2) a second drain region formed in the semiconductor substrate and formed in alignment with the side wall of the second control gate electrode where the second memory gate electrode is not formed;
(G2) a second source region formed in the semiconductor substrate and formed in alignment with a side wall of the second memory gate electrode on which the second sidewall insulating film is formed,
The first source region and the second source region are non-volatile semiconductor memory devices that are common source regions,
A source wiring formed on the semiconductor substrate so as to be electrically connected to the common source region, and formed so as to be in contact with the first sidewall insulating film and the second sidewall insulating film; A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein the source wiring is formed to match the first sidewall insulating film and the second sidewall insulating film. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein the first memory gate electrode and the second memory gate electrode have a sidewall shape. The nonvolatile semiconductor memory device according to claim 1,
A nonvolatile film characterized in that a silicide film is formed on surfaces of the first control gate electrode, the first memory gate electrode, the second control gate electrode, the second memory gate electrode, and the source wiring. Semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein the first control gate electrode and the second control gate electrode have a sidewall shape. The nonvolatile semiconductor memory device according to claim 1,
The first stacked insulating film and the second stacked insulating film include a first potential barrier film, a charge storage film formed on the first potential barrier film, and a second potential formed on the charge storage film. A non-volatile semiconductor memory device, comprising a barrier film. The nonvolatile semiconductor memory device according to claim 6,
The non-volatile semiconductor memory device, wherein the first memory cell or the second memory cell performs a write operation by injecting hot electrons generated by a source side injection method into the charge storage film. The nonvolatile semiconductor memory device according to claim 6,
The nonvolatile memory device according to claim 1, wherein the first memory cell or the second memory cell performs an erasing operation by injecting hot holes generated by a band-to-band tunneling phenomenon into the charge storage film. The nonvolatile semiconductor memory device according to claim 6,
The nonvolatile semiconductor memory device, wherein the first potential barrier film and the second potential barrier film are formed of a silicon oxide film, and the charge storage film is formed of a silicon nitride film. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein the source wiring includes a polysilicon film. The nonvolatile semiconductor memory device according to claim 10,
The nonvolatile semiconductor memory device, wherein the first control gate electrode, the first memory gate electrode, the second control gate electrode, and the second memory gate electrode include a polysilicon film. The nonvolatile semiconductor memory device according to claim 1,
An active region in which the first drain region, the second drain region, and the common source region are formed in the semiconductor substrate;
An element isolation region formed in the semiconductor substrate is formed,
The non-volatile semiconductor memory device, wherein the active region and the element isolation region extend in the first direction in parallel while being adjacent to each other. The nonvolatile semiconductor memory device according to claim 12,
The first control gate electrode, the first memory gate electrode, the second control gate electrode, the second memory gate electrode, and the source line extend in a second direction that intersects the first direction. A non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 13,
There are a plurality of the active region and the element isolation region,
The non-volatile semiconductor memory device, wherein the plurality of active regions and the plurality of element isolation regions are formed in stripes in the semiconductor substrate. The nonvolatile semiconductor memory device according to claim 14,
The non-volatile semiconductor memory device, wherein the element isolation region is formed by embedding an insulating film in a groove formed in the semiconductor substrate. (A) forming an element isolation region in a semiconductor substrate;
(B) forming a well in the semiconductor substrate;
(C) forming a first dummy insulating film and a second dummy insulating film on the semiconductor substrate;
(D) after the step (c), forming a gate insulating film on the semiconductor substrate;
(E) After the step (d), a first control gate electrode is formed on the semiconductor substrate via the first gate insulating film made of the gate insulating film on the side wall of the first dummy insulating film, and the second Forming a second control gate electrode on the semiconductor substrate via a second gate insulating film made of the gate insulating film on the side wall of the dummy insulating film;
(F) After the step (e), a step of removing the first dummy insulating film and the second dummy insulating film;
(G) After the step (f), a step of forming a laminated insulating film on the semiconductor substrate;
(H) After the step (g), a first memory gate electrode is formed on a sidewall of the first control gate electrode and on the semiconductor substrate via a first stacked insulating film made of the stacked insulating film, and the second memory gate electrode is formed. Forming a second memory gate electrode on the side wall of the control gate electrode and the semiconductor substrate via the second laminated insulating film made of the laminated insulating film;
(I) after the step (h), forming a shallow first semiconductor region in the semiconductor substrate sandwiched between the first memory gate electrode and the second memory gate electrode;
(J) after the step (i), forming a first sidewall insulating film on the sidewall of the first memory gate electrode, and forming a second sidewall insulating film on the sidewall of the second memory gate electrode;
(K) After the step (j), a deep first semiconductor region is formed in the semiconductor substrate sandwiched between the first sidewall insulating film and the second sidewall insulating film, and the shallow first semiconductor region Forming a common source region comprising the deep first semiconductor region;
(L) After the step (k), on the semiconductor substrate so as to be electrically connected to the common source region and to be in contact with the first sidewall insulating film and the second sidewall insulating film. Forming a source wiring in
(M) After the step (l), a first drain region is formed in the semiconductor substrate in alignment with the side wall of the first control gate electrode, and in alignment with the side wall of the second control gate electrode. Forming a second drain region in the semiconductor substrate. A method for manufacturing a nonvolatile semiconductor memory device, comprising: A method of manufacturing a nonvolatile semiconductor memory device according to claim 16,
A method of manufacturing a nonvolatile semiconductor memory device, wherein the first control gate electrode and the second control gate electrode have sidewall shapes. A method of manufacturing a nonvolatile semiconductor memory device according to claim 17,
The method of manufacturing a nonvolatile semiconductor memory device, wherein the first memory gate electrode and the second memory gate electrode have a sidewall shape. A method of manufacturing a nonvolatile semiconductor memory device according to claim 16,
The laminated insulating film includes a first silicon oxide film, a silicon nitride film formed on the first silicon oxide film, and a second silicon oxide film formed on the silicon nitride film. A method for manufacturing a nonvolatile semiconductor memory device. (A) forming an element isolation region in a semiconductor substrate;
(B) forming a well in the semiconductor substrate;
(C) forming a gate insulating film on the semiconductor substrate;
(D) After the step (c), a first control gate electrode is formed on the semiconductor substrate via a first gate insulating film made of the gate insulating film, and the first insulating film made of the gate insulating film is formed on the semiconductor substrate. Forming a second control gate electrode through a two-gate insulating film;
(E) after the step (d), a step of forming a laminated insulating film on the semiconductor substrate;
(F) After the step (e), a first memory gate electrode is formed on a sidewall of the first control gate electrode and on the semiconductor substrate via a first stacked insulating film made of the stacked insulating film, and the second memory gate electrode is formed. Forming a second memory gate electrode on the side wall of the control gate electrode and the semiconductor substrate via the second laminated insulating film made of the laminated insulating film;
(G) after the step (f), forming a shallow first semiconductor region in the semiconductor substrate sandwiched between the first memory gate electrode and the second memory gate electrode;
(H) After the step (g), forming a first sidewall insulating film on the sidewall of the first memory gate electrode and forming a second sidewall insulating film on the sidewall of the second memory gate electrode;
(I) After the step (h), a deep first semiconductor region is formed in the semiconductor substrate sandwiched between the first sidewall insulating film and the second sidewall insulating film, and the shallow first semiconductor region Forming a common source region comprising the deep first semiconductor region;
(J) After the step (i), on the semiconductor substrate so as to be electrically connected to the common source region, and in contact with the first sidewall insulating film and the second sidewall insulating film. Forming a source wiring in
(K) After the step (j), a first drain region is formed in the semiconductor substrate in alignment with the side wall of the first control gate electrode, and in alignment with the side wall of the second control gate electrode Forming a second drain region in the semiconductor substrate. A method for manufacturing a nonvolatile semiconductor memory device, comprising: A method of manufacturing a nonvolatile semiconductor memory device according to claim 20,
The method of manufacturing a nonvolatile semiconductor memory device, wherein the first memory gate electrode and the second memory gate electrode have a sidewall shape. A method of manufacturing a nonvolatile semiconductor memory device according to claim 20,
The laminated insulating film includes a first silicon oxide film, a silicon nitride film formed on the first silicon oxide film, and a second silicon oxide film formed on the silicon nitride film. A method for manufacturing a nonvolatile semiconductor memory device.

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