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JP2010093037A - Multilayer ceramic capacitor and method of manufacturing the same - Google Patents

Multilayer ceramic capacitor and method of manufacturing the same Download PDF

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JP2010093037A
JP2010093037A JP2008261220A JP2008261220A JP2010093037A JP 2010093037 A JP2010093037 A JP 2010093037A JP 2008261220 A JP2008261220 A JP 2008261220A JP 2008261220 A JP2008261220 A JP 2008261220A JP 2010093037 A JP2010093037 A JP 2010093037A
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internal
laminate
ceramic capacitor
multilayer ceramic
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JP5332480B2 (en
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Hiroyoshi Takashima
浩嘉 高島
Shingo Okuyama
晋吾 奥山
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Murata Manufacturing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor that has reduced alignment precision required in a lamination process and dispenses with any special processes, such as etching processing, and to provide a method of manufacturing the multilayer ceramic capacitor. <P>SOLUTION: Internal electrodes 4a, 4b are alternately stacked inside a chip-like laminate 20, while sandwiching a ceramic layer. External electrodes 16a, 16b are formed at both the ends of the chip-line laminate 20 each. The internal and external electrodes 4a, 16a include Ag particles, and the internal and external electrodes 4b, 16b include Cu particles. The internal and external electrodes 4a, 16a including Ag particles are electrically connected each other, and the internal and external electrodes 4b, 16b including Cu particles are electrically connected each other. Different kinds of metals Ag-Cu of the internal and external electrodes 4b, 16a and 4a, 16b are separated and are not connected electrically. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は、積層セラミックコンデンサおよびその製造方法に関する。   The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

従来より、通常の積層セラミックコンデンサは以下の方法によって製作されている。先ず、セラミックグリーンシートの表面に所定サイズの長方形の内部電極パターンを縦横に配列して印刷した後、該セラミックグリーンシートを複数枚積み重ねて積層体とする。次に、積層体を所定サイズにカットしてチップ状積層体を形成する。このチップ状積層体は、一方の端部に内部電極が導出された層と他方の端部に内部電極が導出された層とが交互に積層されている。次に、チップ状積層体の両端部にそれぞれ外部電極を形成し、内部電極と外部電極を電気的に接続して完成品としている。   Conventionally, ordinary multilayer ceramic capacitors have been manufactured by the following method. First, rectangular internal electrode patterns of a predetermined size are arranged on the surface of the ceramic green sheet in a vertical and horizontal manner, and then a plurality of ceramic green sheets are stacked to form a laminate. Next, the laminate is cut into a predetermined size to form a chip-like laminate. In this chip-like laminate, layers in which internal electrodes are led out at one end and layers in which internal electrodes are led out at the other end are alternately laminated. Next, external electrodes are formed on both ends of the chip-like laminate, and the internal electrodes and external electrodes are electrically connected to complete the product.

また、特許文献1に記載されている積層セラミックコンデンサの製造方法は、第1の金属材料からなる第1の内部電極と第2の金属材料からなる第2の内部電極とを、絶縁層を間にして交互に積層して積層体を形成する。ここに、第1の金属材料と第2の金属材料とは、異なるエッチング耐性を有している。次に、第1の内部電極を、第1の金属材料をエッチング処理可能な液を用いてエッチング処理し、前記積層体の第1の端面から後退させる。同様にして、第2の内部電極を、第2の金属材料をエッチング処理可能な液を用いてエッチング処理し、前記積層体の第1の端面に対向する第2の端面から後退させる。次に、積層体の第1および第2の端面にそれぞれ第1および第2の外部電極を形成し、第1の内部電極を第2の外部電極に電気的に接続するとともに、第2の内部電極を第1の外部電極に電気的に接続して完成品としている。   In addition, the method for manufacturing a multilayer ceramic capacitor described in Patent Document 1 includes a first internal electrode made of a first metal material and a second internal electrode made of a second metal material, with an insulating layer interposed therebetween. In this manner, a laminated body is formed by alternately laminating. Here, the first metal material and the second metal material have different etching resistances. Next, the first internal electrode is etched using a liquid capable of etching the first metal material, and is retracted from the first end face of the stacked body. Similarly, the second internal electrode is etched using a liquid capable of etching the second metal material, and is retracted from the second end face facing the first end face of the laminate. Next, first and second external electrodes are respectively formed on the first and second end faces of the multilayer body, the first internal electrode is electrically connected to the second external electrode, and the second internal electrode The electrode is electrically connected to the first external electrode to obtain a finished product.

特開平6−5459号公報Japanese Patent Laid-Open No. 6-5459

しかしながら、従来の通常の積層セラミックコンデンサの製造方法では、縦横に配列された長方形の各内部電極パターンが所定の層間ずれ量に収まるようにするため、セラミックグリーンシートを積み重ねる際の位置合わせに時間がかかるとともに、セラミックグリーンシートの積重ね装置も複雑なものであった。特に、近年の薄層大容量の積層セラミックコンデンサでは、積層枚数が多くて積層時間を短縮できず、さらに、積重ね装置が高価格となるため、製造コストを低減することができなかった。   However, in the conventional method of manufacturing a multilayer ceramic capacitor, time is required for alignment when stacking the ceramic green sheets so that the rectangular internal electrode patterns arranged vertically and horizontally can be accommodated within a predetermined amount of interlayer displacement. In addition, the ceramic green sheet stacking apparatus is complicated. In particular, in a thin ceramic capacitor having a large capacity in recent years, the number of laminated layers cannot be shortened and the stacking time cannot be shortened. Further, since the stacking apparatus becomes expensive, the manufacturing cost cannot be reduced.

また、特許文献1に記載されている製造方法では、内部電極層に全面形成された内部電極を絶縁層を間にして交互に積層するため、積層の際の位置合わせに時間がかからないという利点はあるが、エッチング処理を必要とするため、エッチング装置、エッチング液の管理および廃液処理のために製造コストがアップするという不具合があった。   Further, in the manufacturing method described in Patent Document 1, since the internal electrodes formed on the entire surface of the internal electrode layer are alternately stacked with the insulating layer in between, the advantage that it does not take time for alignment at the time of stacking is advantageous. However, since an etching process is required, there is a problem in that the manufacturing cost increases due to the etching apparatus, the management of the etching liquid, and the waste liquid treatment.

それゆえに、この発明の主たる目的は、積層工程で要求される位置合わせ精度が緩く、かつ、エッチング処理などの特殊な工程を必要としない積層セラミックコンデンサおよびその製造方法を提供することである。   SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor having a low alignment accuracy required in the lamination process and not requiring a special process such as an etching process, and a method for manufacturing the same.

この発明は、第1の金属粒子を含む第1の内部電極が形成された第1の絶縁層と、第2の金属粒子を含む第2の内部電極が形成された第2の絶縁層とを交互に積層して構成した積層体と、積層体の両端部にそれぞれ設けた第1の金属粒子を含む第1の外部電極および第2の金属粒子を含む第2の外部電極と、を備え、第1の内部電極と第1の外部電極が電気的に接続し、第2の内部電極と第2の外部電極が電気的に接続していること、を特徴とする、積層セラミックコンデンサである。   The present invention includes a first insulating layer in which a first internal electrode containing first metal particles is formed, and a second insulating layer in which a second internal electrode containing second metal particles is formed. A laminated body configured by alternately laminating, and a first external electrode including first metal particles and a second external electrode including second metal particles respectively provided at both ends of the laminated body, The multilayer ceramic capacitor is characterized in that the first internal electrode and the first external electrode are electrically connected, and the second internal electrode and the second external electrode are electrically connected.

この発明では、異種金属同士が親和性が低く、両者の電気的導通が困難であるという性質を利用している。すなわち、互いに異なる金属粒子を含む第1および第2の内部電極をそれぞれ形成した第1の絶縁層と第2の絶縁層とを交互に積層して積層体とし、積層体の両端部にそれぞれ第1の金属粒子を含む第1の外部電極および第2の金属粒子を含む第2の外部電極を形成している。従って、積層体を焼成することにより、内部電極と外部電極が同種金属同士である接合界面では、合金化して電気的接続が得られる。一方、内部電極と外部電極が異種金属同士である接合界面では合金化できず、両者は離隔して電気的接続が得られない。この結果、第1の内部電極と第1の外部電極が電気的に接続し、第2の内部電極と第2の外部電極が電気的に接続する。   The present invention utilizes the property that different metals have low affinity and electrical continuity between them is difficult. That is, a first insulating layer and a second insulating layer each formed with first and second internal electrodes containing different metal particles are alternately stacked to form a stacked body, and the first and second insulating layers are respectively stacked at both ends of the stacked body. A first external electrode including one metal particle and a second external electrode including second metal particles are formed. Therefore, by firing the laminate, an electrical connection is obtained by alloying at the joint interface where the internal electrode and the external electrode are of the same metal type. On the other hand, it cannot be alloyed at the joint interface where the internal electrode and the external electrode are made of different metals, and the two electrodes are separated from each other and cannot be electrically connected. As a result, the first internal electrode and the first external electrode are electrically connected, and the second internal electrode and the second external electrode are electrically connected.

また、この発明は、第1の金属粒子を含む第1の内部電極を第1の絶縁層の表面に形成する工程と、第2の金属粒子を含む第2の内部電極を第2の絶縁層の表面に形成する工程と、第1の絶縁層と第2の絶縁層とを交互に積層して積層体を形成する工程と、積層体を所定の寸法にカットしてチップ状積層体を形成する工程と、第1の金属粒子を含む第1の外部電極ペーストをチップ状積層体の一方の端部に付与する工程と、第2の金属粒子を含む第2の外部電極ペーストをチップ状積層体の他方の端部に付与する工程と、第1の外部電極ペーストおよび第2の外部電極ペーストを焼き付ける工程と、を備えたことを特徴とする、積層セラミックコンデンサの製造方法である。   The present invention also includes a step of forming a first internal electrode including first metal particles on the surface of the first insulating layer, and a second internal electrode including second metal particles as the second insulating layer. Forming a laminated body by alternately laminating a first insulating layer and a second insulating layer, and cutting the laminated body into a predetermined size to form a chip-like laminated body A step of applying a first external electrode paste including the first metal particles to one end of the chip-shaped laminate, and a second external electrode paste including the second metal particles being stacked in the chip shape. A method of manufacturing a multilayer ceramic capacitor, comprising: a step of applying to the other end of the body; and a step of baking the first external electrode paste and the second external electrode paste.

この発明では、積層工程で要求される位置合わせ精度が緩く、かつ、エッチング処理などの特殊な工程を必要としない、量産に適した積層セラミックコンデンサの製造方法が得られる。   According to the present invention, it is possible to obtain a method for manufacturing a multilayer ceramic capacitor suitable for mass production, in which the alignment accuracy required in the multilayer process is low and a special process such as an etching process is not required.

そして、第1の金属粒子をAgとし、第2の金属粒子をCuとすることにより、AgやCuは導電性等が良好であるため、電気特性に優れた積層セラミックコンデンサとなる。   Then, by setting the first metal particles to Ag and the second metal particles to Cu, Ag and Cu have good conductivity and the like, so that a multilayer ceramic capacitor having excellent electrical characteristics is obtained.

この発明によれば、積層工程で要求される位置合わせ精度が緩く、かつ、エッチング処理などの特殊な工程を必要としないので、積層時間を短縮でき、さらに、設備装置の低価格化を達成できる。この結果、積層セラミックコンデンサの製造コストを低減できる。   According to the present invention, the alignment accuracy required in the laminating process is loose, and a special process such as an etching process is not required, so that the laminating time can be shortened and the cost of the equipment can be reduced. . As a result, the manufacturing cost of the multilayer ceramic capacitor can be reduced.

この発明の上述の目的,その他の目的,特徴および利点は、図面を参照して行う以下の発明を実施するための最良の形態の説明から一層明らかとなろう。   The above object, other objects, features, and advantages of the present invention will become more apparent from the following description of the best mode for carrying out the invention with reference to the drawings.

(第1の実施形態)
図1は積層セラミックコンデンサの製造方法を示すフローチャートであり、図2〜図7は積層セラミックコンデンサを製造するための各工程を順次示した図である。以下、この発明に係る積層セラミックコンデンサをその製造方法とともに説明する。
(First embodiment)
FIG. 1 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor, and FIGS. 2 to 7 are diagrams sequentially showing respective steps for manufacturing the multilayer ceramic capacitor. Hereinafter, a multilayer ceramic capacitor according to the present invention will be described together with a manufacturing method thereof.

先ず、工程S1で、キャリアフィルム上に図2に示すようなセラミックグリーンシート2a,2bを形成する。ただし、図2にはセラミックグリーンシート2aのみを記載している。キャリアフィルムにはPET(ポリエチレンテレフタレート)樹脂などが用いられる。セラミックグリーンシート2a,2bの厚みは、例えば0.3μm以上に設定される。   First, in step S1, ceramic green sheets 2a and 2b as shown in FIG. 2 are formed on a carrier film. However, FIG. 2 shows only the ceramic green sheet 2a. A PET (polyethylene terephthalate) resin or the like is used for the carrier film. The thickness of the ceramic green sheets 2a and 2b is set to 0.3 μm or more, for example.

次に、工程S2で、セラミックグリーンシート2aの表面全面に、印刷法によりAg粒子を含む内部電極4aを形成する。内部電極4aの形成には、Ag粉を主成分とし、樹脂材料や溶剤などと混合して周知の方法でペースト状にしたものを用いる。内部電極4aはセラミックグリーンシート2aの全面に形成されるため、印刷時のにじみを心配する必要がなく、内部電極4aのサイズのばらつきもなくなる。   Next, in step S2, an internal electrode 4a containing Ag particles is formed on the entire surface of the ceramic green sheet 2a by a printing method. For the formation of the internal electrode 4a, a paste containing Ag powder as a main component, mixed with a resin material, a solvent or the like and made into a paste by a well-known method is used. Since the internal electrode 4a is formed on the entire surface of the ceramic green sheet 2a, there is no need to worry about bleeding during printing, and there is no variation in the size of the internal electrode 4a.

同様にして、セラミックグリーンシート2bの表面全面に、Cu粒子を含む内部電極4bを形成する。なお、CuペーストとAgペーストは、共材添加量や金属粒子径・形状・表面のコーティングなどを最適化し、後工程の焼成時の熱収縮率がほぼ等しくなるようにしている。さらに、層間デラミネーションを抑えるため、CuペーストとAgペーストに使用する樹脂材料や溶剤などは同種類のものが好ましい。   Similarly, the internal electrode 4b containing Cu particles is formed on the entire surface of the ceramic green sheet 2b. It should be noted that the Cu paste and the Ag paste are optimized in terms of the amount of co-material added, the metal particle diameter, shape, surface coating, and the like, so that the thermal shrinkage rate during firing in the subsequent process is substantially equal. Furthermore, in order to suppress interlayer delamination, the same kind of resin materials and solvents used for the Cu paste and the Ag paste are preferable.

次に、工程S3で、セラミックグリーンシート2a,2bをそれぞれキャリアフィルムから剥離した後、図3に示すようにセラミックグリーンシート2a,2bを交互に積層する。内部電極4a,4bがセラミックグリーンシート2a,2bの全面に形成されているため、セラミックグリーンシート2a,2bをキャリアフィルムから容易に剥離できる。積層時に求められるシート2a,2bの位置決め精度は緩くてもよく、±500μmの誤差範囲内であれば十分である。また、セラミックグリーンシート2a,2bを積み重ねる際に、積層ずれを問題としなくてもよいため、積層時の仮圧着を必ずしも行う必要がなく、積層時の仮圧着を行わないときには簡素な積重ね装置ですむ。   Next, in step S3, the ceramic green sheets 2a and 2b are respectively peeled from the carrier film, and then the ceramic green sheets 2a and 2b are alternately laminated as shown in FIG. Since the internal electrodes 4a and 4b are formed on the entire surface of the ceramic green sheets 2a and 2b, the ceramic green sheets 2a and 2b can be easily peeled from the carrier film. The positioning accuracy of the sheets 2a and 2b required at the time of lamination may be loose, and is sufficient if it is within an error range of ± 500 μm. Also, when stacking the ceramic green sheets 2a and 2b, there is no need to cause stacking misalignment, so it is not always necessary to perform temporary crimping at the time of stacking. Mu

さらに、内部電極4a,4bを形成したセラミックグリーンシート2a,2bの上下に、複数枚の保護用セラミックグリーンシート8を積層して圧着(本圧着)して積層体10とする。このとき、内部電極4a,4bがセラミックグリーンシート2a,2bの全面に形成されているため、圧着時の圧力が内部電極4a,4b全面に均等に加わり、内部電極4a,4bの歪みが発生しにくい。そして、長方形の内部電極パターンを縦横に配列して作成する従来の積層セラミックコンデンサの製造方法において、積層セラミックコンデンサの薄層化に伴って発生していた段差問題(積層セラミックコンデンサ表面において内部電極4a,4bが重なった部分と重なっていない部分との間で段差が生じる問題)も解消される。さらに、内部電極4a,4bの流動も生じ難いため、後述のチップ状積層体20の高さ寸法を均一化できる。   Further, a plurality of protective ceramic green sheets 8 are laminated on the upper and lower sides of the ceramic green sheets 2a and 2b on which the internal electrodes 4a and 4b are formed, and are pressure-bonded (mainly pressure-bonded) to obtain a laminated body 10. At this time, since the internal electrodes 4a and 4b are formed on the entire surface of the ceramic green sheets 2a and 2b, the pressure at the time of crimping is uniformly applied to the entire surfaces of the internal electrodes 4a and 4b, and distortion of the internal electrodes 4a and 4b occurs. Hateful. Then, in the conventional method for manufacturing a multilayer ceramic capacitor in which rectangular internal electrode patterns are arranged vertically and horizontally, the step problem that has occurred with the thinning of the multilayer ceramic capacitor (the internal electrode 4a on the surface of the multilayer ceramic capacitor). , 4b) is also eliminated. Furthermore, since the internal electrodes 4a and 4b are less likely to flow, the height dimension of the chip-shaped laminate 20 described later can be made uniform.

次に、工程S4で、積層体10を図2に一点鎖線で表示したカット線Pに沿って所定サイズ毎に切り出す。これにより、図4に示すチップ状積層体20を作成する。このとき、チップ状積層体20の長さ方向の寸法は、焼成時の収縮量を考慮して製品寸法より若干大きく設定されている。また、チップ状積層体20の幅方向の寸法は、焼成時の収縮量と次工程S5での保護材12(図5参照)の厚みを考慮して設定されている。内部電極4a,4bがセラミックグリーンシート2a,2bの全面に形成されているため、カット位置検出と位置決めが不要となり、定ピッチでのカットができる。従って、カット機の低価格化とカットスピードの向上が可能となる。チップ状積層体20の四つの側面をなすカット面には、内部電極4a,4bが露出している。   Next, in step S4, the laminated body 10 is cut out for each predetermined size along the cut line P indicated by a one-dot chain line in FIG. Thereby, the chip-shaped laminated body 20 shown in FIG. 4 is created. At this time, the dimension in the length direction of the chip-shaped laminate 20 is set slightly larger than the product dimension in consideration of the amount of shrinkage during firing. Moreover, the dimension of the width direction of the chip-shaped laminated body 20 is set in consideration of the shrinkage amount during firing and the thickness of the protective material 12 (see FIG. 5) in the next step S5. Since the internal electrodes 4a and 4b are formed on the entire surface of the ceramic green sheets 2a and 2b, it is not necessary to detect and position the cutting position, and the cutting can be performed at a constant pitch. Therefore, it is possible to reduce the price of the cutting machine and improve the cutting speed. The internal electrodes 4a and 4b are exposed on the cut surfaces forming the four side surfaces of the chip-shaped laminate 20.

次に、工程S5で、図5に示すようにチップ状積層体20の幅方向の対向する側面にそれぞれ保護材12を形成する。保護材12はセラミックスラリをチップ状積層体20の側面に塗布することによって形成される。セラミックスラリはセラミックグリーンシート2a,2bと同様のセラミック材料からなることが好ましい。焼成時に同一条件で両者を焼成することができるとともに、セラミックグリーンシート2a,2bとセラミックスラリとの界面で異常反応を起こさせないためである。保護材12の厚みは50〜100μm程度とする。   Next, in step S5, as shown in FIG. 5, the protective material 12 is formed on each side surface facing the width direction of the chip-shaped stacked body 20 respectively. The protective material 12 is formed by applying a ceramic slurry to the side surface of the chip-like laminate 20. The ceramic slurry is preferably made of the same ceramic material as the ceramic green sheets 2a and 2b. This is because both can be fired under the same conditions during firing, and an abnormal reaction is not caused at the interface between the ceramic green sheets 2a, 2b and the ceramic slurry. The thickness of the protective material 12 shall be about 50-100 micrometers.

次に、工程S6で、チップ状積層体20を焼成する。異種金属からなる内部電極4a,4bが等しく焼成できるように、雰囲気や昇温条件を設定する。   Next, the chip-shaped laminate 20 is fired in step S6. The atmosphere and temperature rise conditions are set so that the internal electrodes 4a and 4b made of different metals can be fired equally.

次に、工程S7で、図6に示すようにチップ状積層体20の長さ方向の対向する側面にそれぞれ、Ag粒子を含む外部電極16aおよびCu粒子を含む外部電極16bを形成する。外部電極16a、16bは、内部電極4a,4bの形成に用いたAg粉やCu粉を主成分とし、樹脂材料や溶剤などと混合して周知の方法でペースト状にしたものを塗布することによって形成する。   Next, in step S7, as shown in FIG. 6, the external electrode 16a containing Ag particles and the external electrode 16b containing Cu particles are formed on the opposite side surfaces of the chip-like laminate 20 in the length direction. The external electrodes 16a and 16b are formed by applying a paste formed by a well-known method, which is mainly composed of Ag powder or Cu powder used to form the internal electrodes 4a and 4b, mixed with a resin material or a solvent. Form.

次に、工程S8で、外部電極16a,16bの焼付けを行う。このとき、図7に示すように内部電極4aと外部電極16aの接合界面は同種金属(Ag)同士であり、内部電極4bと外部電極16bの接合界面も同種金属(Cu)同士である。従って、この同種金属同士である接合界面では合金化が起こり、電気的接続が得られる。   Next, in step S8, the external electrodes 16a and 16b are baked. At this time, as shown in FIG. 7, the joint interface between the internal electrode 4a and the external electrode 16a is the same kind of metal (Ag), and the joint interface between the internal electrode 4b and the external electrode 16b is also the same kind of metal (Cu). Therefore, alloying occurs at the bonding interface of the same kind of metals, and electrical connection is obtained.

一方、内部電極4bと外部電極16aの接合界面および内部電極4aと外部電極16bの接合界面は異種金属(Ag−Cu)同士である。異種金属であるAgとCuはほとんど固溶しない金属であるため、この異種金属同士である接合界面では合金化が起きず、接合界面の外部電極16a,16bに含まれているAg,Cu金属粒子がそれぞれの外部電極16a,16b側に移動しながら焼結する。これにより、異種金属同士である接合界面では、Ag,Cu金属粒子の移動による隙間が生じる。この隙間は外部電極16a,16b中のガラスフリットが流入して埋められる。従って、異種金属同士である接合界面では両者は離隔して電気的接続が得られない。   On the other hand, the bonding interface between the internal electrode 4b and the external electrode 16a and the bonding interface between the internal electrode 4a and the external electrode 16b are made of different metals (Ag—Cu). Since the dissimilar metals Ag and Cu are metals that hardly dissolve, the alloying does not occur at the joint interface between the dissimilar metals, and the Ag and Cu metal particles contained in the external electrodes 16a and 16b at the joint interface Are sintered while moving to the external electrodes 16a and 16b. As a result, a gap due to the movement of the Ag and Cu metal particles is generated at the bonding interface, which is a dissimilar metal. The gap is filled with the glass frit in the external electrodes 16a and 16b. Therefore, the two are separated from each other at the bonding interface, which is a dissimilar metal, and electrical connection cannot be obtained.

次に、工程S9で、外部電極16a,16bの表面に、電解めっきや無電解めっきによりめっきを行う。   Next, in step S9, the surfaces of the external electrodes 16a and 16b are plated by electrolytic plating or electroless plating.

こうして、得られた積層セラミックコンデンサは、Ag粒子を含む内部電極4aと外部電極16a同士が電気的に接続し、Cu粒子を含む内部電極4bと外部電極16b同士が電気的に接続している。一方、内部電極4bと外部電極16aおよび内部電極4aと外部電極16bの異種金属(Ag−Cu)同士は離隔して電気的に接続していない。そして、外部電極16a,16bの焼付け工程S8で、外部電極16a,16bと内部電極4a,4bとの間の電気的な接続および非接続を制御できるので、エッチング処理などの煩雑な作業が不要となる。さらに、外部電極16a,16bと内部電極4a,4bとの間隔を最小化できるため、同一体積の積層セラミックコンデンサであっても、静電容量の大きいものが得られる。また、内部電極4a,4bをセラミックグリーンシート2a、2bの表面全面に形成しているので、積層時に求められるシート2a,2bの位置決め精度は緩くてもよい。   Thus, in the obtained multilayer ceramic capacitor, the internal electrode 4a containing Ag particles and the external electrode 16a are electrically connected, and the internal electrode 4b containing Cu particles and the external electrode 16b are electrically connected. On the other hand, the dissimilar metals (Ag—Cu) of the internal electrode 4b and the external electrode 16a, and the internal electrode 4a and the external electrode 16b are not separated and electrically connected. In the baking step S8 of the external electrodes 16a and 16b, the electrical connection and disconnection between the external electrodes 16a and 16b and the internal electrodes 4a and 4b can be controlled, so that complicated work such as an etching process is unnecessary. Become. Further, since the distance between the external electrodes 16a and 16b and the internal electrodes 4a and 4b can be minimized, even a multilayer ceramic capacitor having the same volume can be obtained with a large capacitance. Further, since the internal electrodes 4a and 4b are formed on the entire surface of the ceramic green sheets 2a and 2b, the positioning accuracy of the sheets 2a and 2b required at the time of lamination may be loose.

以上のように、積層工程S3で要求される位置合わせ精度が緩く、かつ、エッチング処理などの特殊な工程を必要としないので、積層時間を短縮でき、さらに、設備装置の簡易化、小型化、低価格化を達成できる。この結果、積層セラミックコンデンサの製造コストを低減できる。   As described above, the alignment accuracy required in the laminating step S3 is loose, and no special process such as an etching process is required, so that the laminating time can be shortened, and the equipment is simplified and miniaturized. Lower prices can be achieved. As a result, the manufacturing cost of the multilayer ceramic capacitor can be reduced.

(第2の実施形態)
第2の実施形態は、図1で示したフローチャートにおいて、工程S5の保護材12の形成後、工程S10で、チップ状積層体20の長さ方向の対向する側面にそれぞれ、Ag粒子を含む外部電極16aおよびCu粒子を含む外部電極16bを形成する(図6参照)。外部電極16a、16bは、内部電極4a,4bの形成に用いたAg粉やCu粉を主成分とし、樹脂材料や溶剤などと混合して周知の方法でペースト状にしたものを塗布することによって形成する。
(Second Embodiment)
According to the second embodiment, in the flowchart shown in FIG. 1, after the formation of the protective material 12 in step S <b> 5, in the step S <b> 10, external surfaces containing Ag particles are respectively provided on the side surfaces facing in the length direction of the chip-shaped stacked body 20. The electrode 16a and the external electrode 16b containing Cu particles are formed (see FIG. 6). The external electrodes 16a and 16b are formed by applying a paste formed by a well-known method by mixing Ag powder or Cu powder used for forming the internal electrodes 4a and 4b as a main component and mixing with a resin material or a solvent. Form.

次に、工程S11で、チップ状積層体20を焼成する。焼成条件は、異種金属からなる内部電極4a,4bおよび外部電極16a,16bが等しく焼成できるように、雰囲気や昇温条件を設定する。このとき、図7に示すように内部電極4aと外部電極16aの接合界面は同種金属(Ag)同士であり、内部電極4bと外部電極16bの接合界面も同種金属(Cu)同士である。従って、この同種金属同士である接合界面では互いに固溶して合金化が起こり、電気的接続が得られる。   Next, in step S11, the chip-shaped stacked body 20 is fired. The firing conditions are set such as the atmosphere and the temperature raising conditions so that the internal electrodes 4a and 4b and the external electrodes 16a and 16b made of different metals can be fired equally. At this time, as shown in FIG. 7, the joint interface between the internal electrode 4a and the external electrode 16a is the same kind of metal (Ag), and the joint interface between the internal electrode 4b and the external electrode 16b is also the same kind of metal (Cu). Therefore, at the joint interface, which is the same kind of metal, solid solutions are formed and alloying occurs, and electrical connection is obtained.

一方、内部電極4bと外部電極16aの接合界面および内部電極4aと外部電極16bの接合界面は異種金属(Ag−Cu)同士である。異種金属であるAgとCuはほとんど固溶しない金属であるため、この異種金属同士である接合界面では合金化が起きず、接合界面の内部電極4a,4bおよび外部電極16a,16bに含まれているAg,Cu金属粒子がそれぞれの母材側(内部電極4a,4bおよび外部電極16a,16b側)に移動しながら焼結する。これにより、異種金属同士である接合界面では、Ag,Cu金属粒子の移動による隙間が生じる。この隙間はセラミックグリーンシート2a,2b中のセラミックが流入して埋められる。従って、異種金属同士である接合界面では両者は離隔して電気的接続が得られない。   On the other hand, the bonding interface between the internal electrode 4b and the external electrode 16a and the bonding interface between the internal electrode 4a and the external electrode 16b are made of different metals (Ag—Cu). Since the dissimilar metals Ag and Cu are metals that hardly dissolve, alloying does not occur at the joining interface between these dissimilar metals, and they are included in the internal electrodes 4a and 4b and the external electrodes 16a and 16b at the joining interface. The sintered Ag and Cu metal particles are sintered while moving to the respective base materials (internal electrodes 4a and 4b and external electrodes 16a and 16b). As a result, a gap due to the movement of the Ag and Cu metal particles is generated at the bonding interface, which is a dissimilar metal. This gap is filled with the ceramic in the ceramic green sheets 2a and 2b. Therefore, the two are separated from each other at the bonding interface, which is a dissimilar metal, and electrical connection cannot be obtained.

次に、工程S9で、外部電極16a,16bの表面に、電解めっきや無電解めっきによりめっきを行って、積層セラミックコンデンサを得る。   Next, in step S9, the surfaces of the external electrodes 16a and 16b are plated by electrolytic plating or electroless plating to obtain a multilayer ceramic capacitor.

こうして、得られた積層セラミックコンデンサは、焼成工程S11で、外部電極16a,16bと内部電極4a,4bとの間の電気的な接続および非接続を制御できるので、エッチング処理などの煩雑な作業が不要となる。さらに、外部電極16a,16bの形成工程S10の後に、内部電極4a,4bと外部電極16a,16bを同時に焼成するので、異種金属同士である接合界面に発生する隙間をセラミックで埋めることができ、前記第1の実施形態のようにガラスフリットで埋める場合と比較して、デラミネーションなどが発生し難い。   Thus, since the obtained multilayer ceramic capacitor can control electrical connection and disconnection between the external electrodes 16a and 16b and the internal electrodes 4a and 4b in the firing step S11, complicated operations such as an etching process can be performed. It becomes unnecessary. Furthermore, since the internal electrodes 4a and 4b and the external electrodes 16a and 16b are simultaneously fired after the formation step S10 of the external electrodes 16a and 16b, the gap generated at the bonding interface between different metals can be filled with ceramic, As compared with the case of filling with glass frit as in the first embodiment, delamination is less likely to occur.

(他の実施形態)
なお、この発明は、前記実施形態に限定されるものではなく、その要旨の範囲内で種々に変形される。例えば、金属粒子の組み合わせとして、前記実施形態ではAg粒子とCu粒子の組み合わせを例にして説明したが、必ずしもこの組み合わせに限るものではなく、電気的な接続および非接続が得られる他の異種金属の組み合わせであってもよい。
(Other embodiments)
In addition, this invention is not limited to the said embodiment, In the range of the summary, it changes variously. For example, as the combination of metal particles, in the above-described embodiment, the combination of Ag particles and Cu particles has been described as an example. However, the combination is not necessarily limited to this combination, and other dissimilar metals that can be electrically connected and disconnected are obtained. A combination of these may be used.

また、積層体10からチップ状積層体20を切り出したときに、チップ状積層体20の内部電極4a,4bの幅がチップ状積層体20の幅より小さくなるように、複数本のストライプ状の内部電極4a,4bパターンをセラミックグリーンシート2a、2bの表面に形成することにより、チップ状積層体20の側面に保護材12を形成する工程を省略してもよい。また、複数のコンデンサ素子を内蔵したアレイタイプの積層セラミックコンデンサであってもよい。   Further, when the chip-like laminate 20 is cut out from the laminate 10, a plurality of stripe-like structures are formed so that the width of the internal electrodes 4a, 4b of the chip-like laminate 20 is smaller than the width of the chip-like laminate 20. By forming the internal electrodes 4a and 4b patterns on the surfaces of the ceramic green sheets 2a and 2b, the step of forming the protective material 12 on the side surface of the chip-like laminate 20 may be omitted. Further, it may be an array type multilayer ceramic capacitor incorporating a plurality of capacitor elements.

この発明の積層セラミックコンデンサの製造方法の一例を示すフローチャートである。It is a flowchart which shows an example of the manufacturing method of the multilayer ceramic capacitor of this invention. 積層セラミックコンデンサに用いられるセラミックグリーンシートと内部電極とを示す平面図である。It is a top view which shows the ceramic green sheet and internal electrode which are used for a multilayer ceramic capacitor. セラミックグリーンシートの積層を説明するための斜視図である。It is a perspective view for demonstrating lamination | stacking of a ceramic green sheet. チップ状積層体を示す斜視図である。It is a perspective view which shows a chip-shaped laminated body. 保護材を形成されたチップ状積層体を示す斜視図である。It is a perspective view which shows the chip-shaped laminated body in which the protective material was formed. 図5の線VI−VIにおける断面を示す模式図である。It is a schematic diagram which shows the cross section in line VI-VI of FIG. 図6に続く製造工程を示す断面模式図である。FIG. 7 is a schematic cross-sectional view showing the manufacturing process following FIG. 6.

符号の説明Explanation of symbols

2a,2b セラミックグリーンシート
4a,4b 内部電極
16a,16b 外部電極
20 チップ状積層体
2a, 2b Ceramic green sheet 4a, 4b Internal electrode 16a, 16b External electrode 20 Chip-shaped laminate

Claims (3)

第1の金属粒子を含む第1の内部電極が形成された第1の絶縁層と、第2の金属粒子を含む第2の内部電極が形成された第2の絶縁層とを交互に積層して構成した積層体と、
前記積層体の両端部にそれぞれ設けた前記第1の金属粒子を含む第1の外部電極および前記第2の金属粒子を含む第2の外部電極と、を備え、
前記第1の内部電極と前記第1の外部電極が電気的に接続し、前記第2の内部電極と前記第2の外部電極が電気的に接続していること、
を特徴とする、積層セラミックコンデンサ。
The first insulating layer in which the first internal electrode including the first metal particles is formed and the second insulating layer in which the second internal electrode including the second metal particle is formed are alternately stacked. A laminate composed of
A first external electrode including the first metal particles and a second external electrode including the second metal particles provided at both ends of the laminate, respectively.
The first internal electrode and the first external electrode are electrically connected, and the second internal electrode and the second external electrode are electrically connected;
A multilayer ceramic capacitor characterized by
第1の金属粒子を含む第1の内部電極を第1の絶縁層の表面に形成する工程と、
第2の金属粒子を含む第2の内部電極を第2の絶縁層の表面に形成する工程と、
前記第1の絶縁層と前記第2の絶縁層とを交互に積層して積層体を形成する工程と、
前記積層体を所定の寸法にカットしてチップ状積層体を形成する工程と、
前記第1の金属粒子を含む第1の外部電極ペーストを前記チップ状積層体の一方の端部に付与する工程と、
前記第2の金属粒子を含む第2の外部電極ペーストを前記チップ状積層体の他方の端部に付与する工程と、
前記第1の外部電極ペーストおよび前記第2の外部電極ペーストを焼き付ける工程と、
を備えたことを特徴とする、積層セラミックコンデンサの製造方法。
Forming a first internal electrode containing first metal particles on the surface of the first insulating layer;
Forming a second internal electrode containing second metal particles on the surface of the second insulating layer;
Forming the laminate by alternately laminating the first insulating layer and the second insulating layer;
Cutting the laminate into predetermined dimensions to form a chip-like laminate;
Applying a first external electrode paste containing the first metal particles to one end of the chip-shaped laminate;
Applying a second external electrode paste containing the second metal particles to the other end of the chip-shaped laminate;
Baking the first external electrode paste and the second external electrode paste;
A method for producing a multilayer ceramic capacitor, comprising:
前記第1の金属粒子がAgであり、前記第2の金属粒子がCuであることを特徴とする、請求項2に記載の積層セラミックコンデンサの製造方法。   The method for manufacturing a multilayer ceramic capacitor according to claim 2, wherein the first metal particles are Ag, and the second metal particles are Cu.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8773839B2 (en) 2009-12-11 2014-07-08 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component
US8773840B2 (en) 2009-12-11 2014-07-08 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
US9082556B2 (en) 2009-12-11 2015-07-14 Murata Manufacturing Co., Ltd. Monolithic ceramic capacitor
US9245688B2 (en) 2009-12-11 2016-01-26 Murata Manufacturing Co., Ltd. Monolithic ceramic capacitor
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CN102683016B (en) * 2011-03-09 2016-06-08 三星电机株式会社 Multilayer ceramic capacitor and method of manufacturing same
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