JP2010093012A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device having an FinFET structure which suppresses a short channel effect effectively even if a bulk substrate is used, and a method for manufacturing the same. <P>SOLUTION: An SiC epitaxial layer 2 is formed on an Si substrate 1, and an Si epitaxial layer 3 is formed on a protrusion part 2t of the SiC epitaxial layer 2. Both the protrusion part 2t and the Si epitaxial layer 3 extend to a first direction, and show a unidirectionally extending shape. An oxide film 8, a nitride film 9, and a gate oxide film 20 are formed on a top surface and both sides of the Si epitaxial layer 3. A gate electrode G2 is formed on the top surface and the sides of the Si epitaxial layer 3 through the oxide film 8, the nitride film 9, and the gate oxide film 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a Fin-type MOS transistor and a method for manufacturing the same.

  The term “MOS” has been used in the past for metal / oxide / semiconductor laminated structures, and is taken from the acronym Metal-Oxide-Semiconductor. However, in particular, in a field effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), materials for a gate insulating film and a gate electrode have been improved from the viewpoint of recent integration and improvement of a manufacturing process.

  For example, in a MOS transistor, polycrystalline silicon has been adopted instead of metal as a material of a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor stacked structure, and is not presumed in this specification. That is, in view of technical common sense, here, “MOS” has not only an abbreviation derived from the word source but also a broad meaning including a laminated structure of a conductor / insulator / semiconductor.

  With the miniaturization, the conventional planar type MOS transistor has severe suppression of the short channel effect, and therefore, the structure of a Fin type MOS transistor (hereinafter sometimes abbreviated as “FinFET”) is drawing attention.

  On the other hand, as a strained Si technology for the channel, there is a stress application method using a liner nitride film formed above the MOS transistor. It is a problem that it cannot be stressed. Hereinafter, this point will be described in detail.

  Along with miniaturization, the gate length is also reduced, but the space between the gates is also reduced (narrowed). Then, the gap between the gate and the gate is filled with the liner nitride film so that a desired stress is not applied, or when the liner nitride film is thick, a contact opening failure occurs.

  Therefore, it is conceivable to use a liner nitride film having a higher stress in order to reduce the thickness of the liner nitride film. However, in this case, there is a problem that the liner nitride film is cracked, stress is not applied, and the application of the liner nitride film becomes more severe with miniaturization.

  Recently, in order to improve the driving capability of a MOS transistor, strained Si technology for the channel has also become important. In particular, the improvement of the driving capability of a P-type (PMOS) transistor is important because it directly affects the device performance. .

  Next, a description will be given of recent technology related to improvement of the driving capability of the PMOS transistor in the FinFET.

  First, Non-Patent Document 1 discloses a technique using a uniaxial compression strain SGOI or GOI for a PMOS transistor. SGOI is a structure in which a region corresponding to an SOI layer having an SOI structure is formed by a SiGe layer. By such SGOI, all of uniaxial compressive strain, SiGe channel material, and (110) plane orientation are converted into hole mobility. Can contribute.

  Non-Patent Document 2 discloses a technique for improving the driving capability of a PMOS transistor by recessing a source / drain region, embedding a SiGe layer, and applying a compressive stress to a channel, as in a planar transistor. .

  However, the stress application method of digging down the source / drain region and filling the SiGe layer makes it difficult to form a SiGe layer by sufficiently digging and epi-growing as the source / drain regions are reduced in size. I can't apply.

  On the other hand, in Non-Patent Document 3, a SiGe layer is epitaxially grown in the Fin portion of the source / drain region, and a compressive stress is applied to the channel due to the difference in lattice constant between Si and SiGe, thereby improving the driving capability of the PMOS transistor. Disclosed techniques.

  Further, Non-Patent Document 4 discloses a PMOS transistor in which a biaxial strain is introduced by epitaxially growing a Si layer on a SiC layer. That is, a structure is disclosed in which a SiC layer is provided under a channel in a digging SiGe structure in a source / drain region of a planar type MOS transistor. However, the structure disclosed here is based on the biaxial strain of SiC.

  A FinFET formed on a bulk substrate is disclosed in Non-Patent Document 5, for example. In this case, the FinFET is formed using a Si substrate, and the channel material of the FinFET is Si.

Toshifumi Irisawa et al. "High Performance Multi-Gate pMOSFET using Uniaxially-Strained SGOI channels", 2005 IEDM Technical Digest P. Verheyen et al. "25% Drive Current improvement for p-type Multiple Gate FET (MuFET) Devices by the Introduction of Recessed Si0.8Ge0.2 in the Source and Drain Regions.", 2005 Symposium on VLSI Techinology Digest of Technical papers Jack Kabalieros et al. "Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering", 2006 Symposium on VLSI Techinology Digest of Technical papers Kah-Wee et al. "Beneath-The-Channel Strain-Structure (STS) and Embedded Source / Drain Stressors for Strain and Performance Enhancement of Nanoscale MOSFETs", 2007 Symposium on VLSI Techinology Digest of Technical papers H. Kawasaki al. "Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond", 2006 Symposium on VLSI Techinology Digest of Technical papers

  As disclosed in Non-Patent Document 1 to Non-Patent Document 3, a transistor structure using an SOI wafer type FinFET is mainly used to suppress the short channel effect, and a strain technique mainly using SiGe is adopted. A PMOS transistor was manufactured.

  However, the SOI wafer is not only expensive, but if the SOI wafer is used, the FD type SOI transistor (including the case of FinFET) has a low drain withstand voltage, so that an I / O unit (high voltage operation) used in a normal device is used. Part)), and the I / O part requires a bulk transistor, so that there is a problem of poor matching in manufacturing a device.

  There are two types of FinFETs: a type using an SOI wafer and a type using a conventional bulk substrate. The former is advantageous for suppressing the short channel effect, but the latter is advantageous in consideration of cost and consistency with peripheral circuits. is there.

  The present invention has been made to solve the above-mentioned problems, and it is intended to obtain a semiconductor device having a FinFET structure and a method for manufacturing the same that can effectively suppress the short channel effect even when a bulk substrate is used. Objective.

  According to one embodiment of the present invention, a SiC epitaxial layer is formed on a Si substrate. At least the upper layer portion of the SiC epitaxial layer has a unidirectionally extending shape extending in a predetermined direction. A Si epitaxial layer is formed on the upper layer portion, and the Si epitaxial layer has a unidirectionally extending shape extending in the predetermined direction. A gate oxide film is formed on the side surface of the Si epitaxial layer, and a gate electrode formed via the gate oxide film is formed.

  According to this embodiment, when the upper layer portion of the SiC epitaxial layer and the Si epitaxial layer are processed in a unidirectionally extending shape, the channel length in one direction from the upper layer portion of the lower SiC epitaxial layer to the Si epitaxial layer Compressive stress in the direction is generated more strongly than other direction axes. For this reason, the FinFET of the first embodiment can improve the hole mobility and improve the driving capability of the transistor.

  In addition, the occurrence of leakage current due to short channel characteristics, which has been a problem with FinFETs formed on bulk substrates, is also caused by the potential barrier due to the difference in band gap between Si (Si epitaxial layer 3) and SiC (SiC epitaxial layer 2). Therefore, the junction leakage current can be reduced with the difference in the band gap.

<Embodiment 1>
(First aspect)
FIG. 1 is an explanatory view showing a perspective sectional structure of a first mode of a P-type FinFET according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional structure at a cross-section C1 in FIG.

  As shown in these drawings, a SiC epitaxial layer 2 (first semiconductor layer) is formed on a Si substrate 1 which is a semiconductor substrate. The SiC epitaxial layer 2 has a protruding portion 2t which is an upper layer portion thereof. The projecting portion 2t is formed in a substantially rectangular parallelepiped shape (hereinafter sometimes abbreviated as “one-way extending shape”) extending in a slanting vertical direction (first direction) in FIG.

  A Si epitaxial layer 3 (second semiconductor layer) is formed on the protrusion 2t of the SiC epitaxial layer 2. The Si epitaxial layer 3 is also formed in a substantially rectangular parallelepiped shape (hereinafter sometimes abbreviated as “one-way extending shape”) extending in the first direction, and has an upper surface and side surfaces. In addition, the isolation insulating film 11 is formed on the upper surface of the SiC epitaxial layer 2 excluding the protruding portion 2t with the same height as the upper surface of the protruding portion 2t.

  As shown in FIG. 1, gate oxide films 20 are formed on both side surfaces of the Si epitaxial layer 3, and as shown in FIGS. 1 and 2, an oxide film is formed on the upper surface of the Si epitaxial layer 3. 8 and nitride film 9 are laminated. Further, the gate electrode G 2 is formed on the upper surface and the side surface of the Si epitaxial layer 3 through the oxide film 8, the nitride film 9 and the gate oxide film 20. The gate electrode G2 is formed so as to extend in the lateral direction (second direction) in FIG. 1 and has a T-shape in plan view. A nitride film 19 is formed on the gate electrode G2.

  As shown in FIG. 2, in the Si epitaxial layer 3, a region under the gate electrode G2 becomes an N-type body region 3b, and a P-type source region 3s and a drain region 3d are formed with the body region 3b interposed therebetween. The

  The channel region is a region in both side surfaces of the Si epitaxial layer 3 under the gate oxide film 20. That is, the gate electrode G2 functions as a double gate.

  The body region 3b, the drain region 3d, the source region 3s, the gate oxide film 20, and the gate electrode G2 constitute a PMOS FinFET.

  In FIG. 2, a leak current L1 indicates a leak current due to a short channel effect, and a leak current L2 indicates a leak current due to junction leak.

  As described above, in the first mode of the first embodiment, the regions in the both side surfaces of the Si epitaxial layer 3 are channel regions. Therefore, the Si epitaxial layer 3 is subjected to compressive stress by the SiC epitaxial layer 2 having a lower lattice constant.

  FIGS. 3 and 4 are explanatory views showing how compressive stress is applied to the Si epitaxial layer 3 by the SiC epitaxial layer 2.

  As shown in FIG. 3, when the Si epitaxial layer 3 is formed on the entire surface of the SiC epitaxial layer 2, compressive stresses F1 and F2 in two directions (first and second directions) act on the Si epitaxial layer 3. .

  On the other hand, as shown in FIG. 4, the Si epitaxial layer 3 extends in the first direction (predetermined direction) when the protruding portion 2t of the SiC epitaxial layer 2 and the Si epitaxial layer 3 are processed into a unidirectionally extending shape. Because of the existing shape, the compressive stress F1 in one axial direction from the SiC epitaxial layer 2 acts on the Si epitaxial layer 3 more strongly than the other directional axes. The compressive stress F1 is in the channel length direction of the completed PMOS transistor.

  Thus, in the first mode of the first embodiment, when the projecting portion 2t and the Si epitaxial layer 3 are processed as a unidirectionally extending shape, the Si epitaxial layer 3 is projected from the projecting portion 2t of the lower SiC epitaxial layer 2. On the other hand, the compressive stress F1 in the channel length direction in one direction is generated more strongly than the other direction axes. For this reason, the FinFET of the first embodiment can improve the hole mobility and improve the driving capability of the transistor.

  In addition, leakage current L1 due to short channel characteristics, which has been a problem with FinFETs formed on bulk substrates, is also caused by the potential barrier due to the difference in band gap between Si (Si epitaxial layer 3) and SiC (SiC epitaxial layer 2). Therefore, the junction leakage current L2 can be reduced due to the difference in the band gap.

  Further, since the gate electrode G2 has a double gate structure, the transistor characteristics are stabilized. Hereinafter, this point will be described in detail.

  In the case of the tri-gate (three-plane) structure, electric field concentration from the gate electrode occurs at the upper corner of the Si epitaxial layer 3 and the breakdown voltage tends to be weakened. Further, in the case of the tri-gate structure, unless the Si crystal plane is carefully examined, the film thickness of the gate oxide film on the upper surface and the side surface of the Si epitaxial layer 3 is different and affects the transistor characteristics. On the other hand, in the case of the double gate structure, the transistor characteristics are stabilized due to the absence of the above-mentioned material of concern.

  Therefore, by forming a P-type FinFET using a bulk substrate, cost and peripheral circuit consistency can be improved.

  5 to 22 are cross-sectional views showing a method of manufacturing a P-type FinFET which is the first mode of the first embodiment. In these drawings, a description will be given as a process of manufacturing a PMOS transistor and an NMOS transistor in each of the Planar transistor portion R1 and the Fin transistor portion R2. Further, these drawings show a cross-sectional structure in the direction of formation of the gate electrode G2 in FIG. 1 and the direction of the T-shaped I portion (second direction).

  First, as shown in FIG. 5, a Si substrate 1 which is a bulk substrate (wafer) is prepared. The Si substrate 1 has a Planar transistor formation region R1 and a Fin transistor formation region R2.

  Then, as shown in FIG. 6, the SiC epitaxial layer 2 is formed on the Si substrate 1 by the epitaxial growth method, and the Si epitaxial layer 3 is formed on the SiC epitaxial layer 2 by the epitaxial growth method. Further, an oxide film 4 is deposited on the Si epitaxial layer 3. In the SiC epitaxial layer 2, in order to suppress crystal defects, generally, C contained in a crystal lattice position in SiC is within 5%.

  Next, as shown in FIG. 7, a patterned resist 5 is provided only on the PMOS transistor formation portion R2p in the Fin transistor formation region R2 using photolithography. Then, the SiC epitaxial layer 2, the Si epitaxial layer 3 and the oxide film 4 in the region exposed from the resist 5 are selectively removed by dry etching, and the SiC epitaxial layer 2 and the Si epitaxial layer are formed only in the PMOS transistor formation portion R1p. The layer 3 and the oxide film 4 are left.

  After that, as shown in FIG. 8, after removing the resist 5, oxide film sidewalls 6 are formed on the side surfaces of the SiC epitaxial layer 2 and the Si epitaxial layer 3 remaining in the PMOS transistor formation portion R1p. The oxide film sidewall 6 is provided to prevent epitaxial growth from the side surfaces of the SiC epitaxial layer 2 and the Si epitaxial layer 3. A part of the oxide film sidewall 6 may be provided on the side surface of the oxide film 4.

  Subsequently, as shown in FIG. 9, the Si epitaxial layer 7 is formed by selective epitaxial growth from the Si substrate 1. At this time, the formation is performed such that the formation height of the Si epitaxial layer 7 substantially matches the formation height of the Si epitaxial layer 3.

  Then, as shown in FIG. 10, a portion of oxide film 4 and oxide film sidewall 6 exposed from Si epitaxial layer 7 is removed.

  Next, as shown in FIG. 11, an oxide film 8 and a nitride film 9 are sequentially deposited on the entire surface, and a resist 10 is formed on the nitride film 9 using photolithography.

  Thereafter, as shown in FIG. 12, the nitride film 9, the oxide film 8, the Si epitaxial layer 7, the Si epitaxial layer 3, the SiC epitaxial layer 2 and the oxide film sidewall 6 are selectively etched by using the resist 10 as a mask. Etch in a quantity to form a trench (not shown). The first etching amount is set to an amount in which at least a portion of the SiC epitaxial layer 2 remains without being removed in the PMOS transistor formation portion R2p.

  As a result, the protruding portion 2t of the unidirectionally extending Si epitaxial layer 3 and the SiC epitaxial layer 2 can be obtained.

  After the resist is removed, as shown in FIG. 12, an isolation insulating film 11 such as an oxide film is formed on the entire surface by being buried in the trench, and then the isolation insulating film is made up to the height of the nitride film 9 using CMP processing. 11 is removed. That is, the nitride film 9 functions as a stopper film.

  As a result, the Planar transistor formation region R1 and the Fin transistor formation region R2 are insulated and separated by the isolation insulating film 11. Further, in the Planar transistor formation region R1, the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n are insulated and separated by the isolation insulating film 11, and in the Fin transistor formation region R2, between the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n. Is isolated by the isolation insulating film 11.

  Then, as shown in FIG. 13, a patterned resist 12 is formed on the Planar transistor formation region R1 using a photoengraving technique, and a dry etching process is performed on the isolation insulating film 11 in the Fin transistor formation region R2 to etch back. Then remove some. It is desirable that the upper surface of the etched isolation insulating film 11 at this time is approximately equal to the SiC / Si interface between the SiC epitaxial layer 2 and the Si epitaxial layer 3.

  When the upper surface of the isolation insulating film 11 in the Fin transistor formation region R2 is located below the SiC / Si interface, the short channel suppression effect is enhanced, and the upper surface of the isolation insulating film 11 is located above the SiC / Si interface. In this case, since the region under the gate oxide film 20 serving as a channel is surely only the Si epitaxial layer 3, variation in transistor characteristics is reduced.

  Next, as shown in FIG. 14, gate oxide films 20 are formed on the side surfaces of the Si epitaxial layers 3 and 7 exposed from the isolation insulating film 11 in the Fin transistor formation region R <b> 2. At this time, when the upper surface of the isolation insulating film 11 is located below the SiC / Si interface in the PMOS transistor formation portion R2p, the gate oxide film 20 is also formed on a part of the side surface of the SiC epitaxial layer 2.

  Thereafter, as shown in FIG. 14, a polysilicon layer 13 is deposited on the entire surface. In this example, polysilicon is shown as the gate material. As the gate material, a material such as polysilicon or TiN that can obtain a desired transistor threshold value depending on the device may be selected.

  Then, as shown in FIG. 15, a CMP process is performed on the polysilicon layer 13, and the polysilicon layer 13 is etched away to the formation height of the nitride film 9 in the Planar transistor formation region R1 and the Fin transistor formation region R2. That is, the nitride film 9 functions as a stopper film. Therefore, all the polysilicon layer 13 on the Planar transistor formation region R1 is removed.

  Then, as shown in FIG. 16, a patterned resist 14 is formed on the Fin transistor formation region R2, and the nitride film 9 in the Planar transistor formation region R1 exposed from the resist 14 is removed.

  Further, as shown in FIG. 17, after removing the resist 14, the oxide film 8 in the Planar transistor formation region R1 is removed.

  Then, as shown in FIG. 18, an underlying oxide film 28 is formed on the surface of the Si epitaxial layer 7 in the Planar transistor formation region R1 and on the surface of the polysilicon layer 13 in the Fin transistor formation region R2.

  Subsequently, the various processes necessary for transistor formation (impurity implantation for well formation and impurity implantation to the channel for adjusting the threshold voltage Vth) are distinguished by NMOS / PMOS in the Planar transistor formation region R1, and the photoengraving process and ion implantation are performed. Performed using a process (not shown). Thereafter, the underlying oxide film 28 is removed.

  Thereafter, as shown in FIG. 19, a gate oxide film 23 is formed on the entire surface, and then a polysilicon layer 15 is deposited on the entire surface.

  Then, as shown in FIG. 20, a CMP process is performed on the polysilicon layer 15 to remove the polysilicon layer 15 up to the height of the nitride film 9 in the Fin transistor formation region R2. That is, the nitride film 9 functions as a stopper film. Therefore, a part of the polysilicon layer 15 in the Planar transistor formation region R1 remains.

  Next, as shown in FIG. 21, a polysilicon layer 16 is deposited on the entire surface, a nitride film 19 is further deposited, and then a patterned resist 18 is formed using photolithography.

  Then, as shown in FIG. 22, the nitride film 19 and the polysilicon layers 16, 15 and 13 are dry-etched using the resist 18 as a mask. As a result, a gate electrode G1 is formed in each of the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n in the Planar transistor formation region R1, and a gate electrode is formed in each of the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n in the Fin transistor formation region R2. G2 is formed.

  Thereafter, an impurity introduction process for forming a source / drain region is performed, and a p-type transistor is sandwiched between the channel region which is the surface of the Si epitaxial layer 3 (SiC epitaxial layer 2) under the gate oxide film 20 in the PMOS transistor formation portion R2p. Source / drain regions are formed. Similarly, a P-type source / drain region is formed in the PMOS transistor formation portion R1p, and an N-type source / drain region is formed in each of the NMOS transistor formation portions R1n and R2n.

  As a result, the PMOS transistor Q11 and the NMOS transistor Q12 are completed in the Planar transistor formation region R1, and the PMOS transistor Q21 and the NMOS transistor Q22 are completed in the Fin transistor formation region R2.

  In this way, a P-type FinFET formed in the PMOS transistor formation portion R2p in the Fin transistor formation region R2 (as shown in the first mode of the first embodiment shown in FIGS. 1 and 2 can be obtained. That is, the PMOS transistor Q21 shown by the gate peripheral region A1 in Fig. 22 is the P-type FinFET of the first mode of the first embodiment shown in Fig. 1 and Fig. 2. In Fig. 22, the gate electrode G2 The shape is shown in a simplified manner.

  As described above, in the manufacturing method according to the first aspect of the first embodiment, the SiC epitaxial layer 2 and the Si epitaxial layer 3 are selectively formed only in the PMOS transistor formation portion R2p in the Fin transistor formation region R2. Further, efficiency is improved such as simultaneously forming the gate electrodes G1 and G2 of the NMOS transistors Q12 and Q22 in the PMOS transistor Q11 and Q21 in the Planar transistor formation region R1 and the NMOS transistor Q12 and Q22 in the Fin transistor formation region R2.

  As a result, the PMOS transistor and the NMOS transistor having the respective structures of the Planar transistor and the Fin transistor can be manufactured using the same manufacturing process.

(Second aspect)
FIG. 23 is an explanatory diagram showing a perspective cross-sectional structure of the second mode of the P-type FinFET according to the first embodiment of the present invention.

  As shown in the figure, the Si substrate 1 has a protruding portion 1t in part. The projecting portion 1t is formed to extend in an oblique vertical direction (first direction) in FIG. A SiC epitaxial layer 2 is formed on the protrusion 1t of the Si substrate 1. The SiC epitaxial layer 2 as a whole has a substantially rectangular parallelepiped unidirectionally extending shape extending in the first direction.

  A Si epitaxial layer 3 is selectively formed on the SiC epitaxial layer 2. The Si epitaxial layer 3 also has a substantially rectangular parallelepiped unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces. Further, the isolation insulating film 21 is formed on the Si substrate 1 excluding the projecting portion 1t at a height approximately equal to the upper surface of the SiC epitaxial layer 2.

  Thus, the entire SiC epitaxial layer 2 is formed in the same shape as the Si epitaxial layer 3 in plan view, and both the SiC epitaxial layer 2 and the Si epitaxial layer 3 have a unidirectionally extending shape.

  As shown in FIG. 23, as in the first mode, gate oxide films 20 are formed on both side surfaces of the Si epitaxial layer 3, and oxide films 8 and 8 are formed on the upper surface of the Si epitaxial layer 3. And the nitride film 9 is laminated | stacked. Further, the gate electrode G2 is formed on the upper surface and the side surface of the Si epitaxial layer 3 through the oxide film 8, the nitride film 9, and the gate oxide film 20 as in the first embodiment. The gate electrode G2 is formed so as to extend in the horizontal direction (second direction) in FIG. 23, and the planar shape is T-shaped. A nitride film 19 is formed on the gate electrode G2.

  In the second mode of the first embodiment, similarly to the first mode shown in FIG. 2, in the Si epitaxial layer 3, the region under the gate electrode G2 is an N-type body region. A P-type source region and a drain region are formed on both sides.

  The channel region is a region in both side surfaces of the Si epitaxial layer 3 under the gate oxide film 20. That is, the gate electrode G2 functions as a double gate.

  The body region, the drain region, the source region, the gate oxide film 20 and the gate electrode G2 constitute a PMOS FinFET.

  The second mode of the first embodiment is similar to the first mode in that when the SiC epitaxial layer 2 and the Si epitaxial layer 3 are processed into a unidirectionally extending shape, the Si epitaxial layer 3 is lower than the lower SiC epitaxial layer 2. On the other hand, the compressive stress F1 in the channel length direction in one axis direction is generated more strongly than the other direction axes. For this reason, the FinFET of the second aspect has improved hole mobility, and can improve the driving capability of the transistor.

  Further, in the second mode, the entire SiC epitaxial layer 2 is formed in a unidirectionally extended shape, so that uniaxial stress (compressive stress F1) is applied more strongly in the channel length direction (perpendicular to the gate width direction of the gate electrode G2). Since it can be applied, the transistor driving capability can be improved more than in the first embodiment.

  Further, since the gate electrode G2 has a double gate structure, the transistor characteristics are stabilized.

  In addition, the short channel characteristics that have been a problem with FinFETs formed on bulk substrates are also suppressed due to the potential barrier due to the difference in band gap between Si and SiC, and junction leakage is reduced due to the difference in band gap. Can be achieved.

  24 to 35 are cross-sectional views showing a method of manufacturing a P-type FinFET which is the second mode of the first embodiment. In these drawings, a description will be given as a process of manufacturing a PMOS transistor and an NMOS transistor in each of the Planar transistor portion R1 and the Fin transistor portion R2. Further, these drawings show a cross-sectional structure in the formation direction of the gate electrode G2 in FIG. 23 and the direction of the T-shaped I portion (second direction).

  First, the structure shown in FIG. 24 is obtained through the same process as the manufacturing method of the first aspect shown in FIGS.

  Thereafter, using the wrench 10 as a mask, the nitride film 9, oxide film 8, Si epitaxial layer 7, Si epitaxial layer 3, SiC epitaxial layer 2 and oxide sidewall 6 are selectively etched with a second etching amount to form a trench ( (Not shown). The second etching amount is set to an amount that is removed from the SiC epitaxial layer 2 to a part of the surface of the Si substrate 1 in the PMOS transistor formation portion R2p.

  As a result, as shown in FIG. 25, both the SiC epitaxial layer 2 and the Si epitaxial layer 3 are processed into a unidirectionally extending shape in the PMOS transistor formation portion R2p.

  Further, as shown in FIG. 25, an isolation insulating film 21 such as an oxide film is formed on the entire surface by being buried in the trench, and then the isolation insulating film 21 is removed up to the height of the nitride film 9 using a CMP process.

  As a result, the Planar transistor formation region R1 and the Fin transistor formation region R2 are insulated and separated by the isolation insulating film 21. Further, in the Planar transistor formation region R1, the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n are insulated and separated by the isolation insulating film 21, and in the Fin transistor formation region R2, between the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n. Is isolated by the isolation insulating film 21.

  Then, as shown in FIG. 26, a patterned resist 12 is formed on the Planar transistor formation region R1 using photolithography, and a dry etching process is performed on the isolation insulating film 21 in the Fin transistor formation region R2 to etch back. Then remove some. It is desirable that the upper surface of the etched isolation insulating film 21 at this time is approximately the same as the SiC / Si interface between the SiC epitaxial layer 2 and the Si epitaxial layer 3 as in the first embodiment.

  Next, as shown in FIG. 27, a gate oxide film 20 is formed on each side surface of the Si epitaxial layers 3 and 7 exposed from the isolation insulating film 21 in the Fin transistor formation region R2. At this time, when the upper surface of the isolation insulating film 21 is located below the SiC / Si interface in the PMOS transistor formation portion R2p, the gate oxide film 20 is further formed on a part of the side surface of the SiC epitaxial layer 2. Thereafter, a polysilicon layer 13 is deposited on the entire surface as in the first embodiment.

  Then, as shown in FIG. 28, the polysilicon layer 13 is subjected to a CMP process, and the polysilicon layer 13 is etched away to the formation height of the nitride film 9 in the planar transistor forming region R1 and the fin transistor forming region R2. Therefore, all the polysilicon layer 13 on the Planar transistor formation region R1 is removed.

  Then, as shown in FIG. 29, a patterned resist 14 is formed on the Fin transistor formation region R2, and the nitride film 9 in the Planar transistor formation region R1 exposed from the resist 14 is removed.

  Further, as shown in FIG. 30, after removing the resist 14, the oxide film 8 in the Planar transistor formation region R1 is removed.

  Then, as shown in FIG. 31, an underlying oxide film 28 is formed on the surface of the Si epitaxial layer 7 in the Planar transistor formation region R1 and on the surface of the polysilicon layer 13 in the Fin transistor formation region R2.

  Subsequently, as in the first embodiment, various processes necessary for transistor formation are differentiated by NMOS / PMOS in the Planar transistor formation region R1, and are performed using a photolithography process and an ion implantation process (not shown). Thereafter, the underlying oxide film 28 is removed.

  Thereafter, as shown in FIG. 32, a gate oxide film 23 is formed on the entire surface, and then a polysilicon layer 15 is deposited.

  Then, as shown in FIG. 33, a CMP process is performed on the polysilicon layer 15 to remove the polysilicon layer 15 up to the height of the nitride film 9 in the Fin transistor formation region R2. Therefore, the polysilicon layer 15 and the gate oxide film 23 in the Fin transistor formation region R2 are all removed.

  Next, as shown in FIG. 34, a polysilicon layer 16 is deposited on the entire surface, a nitride film 19 is further deposited, and then a patterned resist 18 is formed using a photoengraving technique.

  Then, as shown in FIG. 35, dry etching is performed on the nitride film 19 and the polysilicon layers 16, 15, and 13 using the resist 18 as a mask. As a result, the gate electrode G1 is formed in each of the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n in the Planar transistor formation region R1, and the gate electrode G2 is formed in each of the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n in the Fin transistor formation region R2. It is formed.

  Thereafter, as in the first embodiment, impurity introduction processing for forming the source / drain regions is performed, the PMOS transistor Q11 and NMOS transistor Q12 are placed in the Planar transistor forming region R1, and the PMOS transistor Q21 and NMOS transistor are placed in the Fin transistor forming region R2. Each Q22 is completed.

  As a result, the structure shown in the second mode of the first embodiment shown in FIG. 23 can be obtained as a P-type FinFET formed in the PMOS transistor forming portion R2p in the Fin transistor forming region R2. That is, the PMOS transistor Q21 indicated by the gate peripheral region A2 in FIG. 35 is the second aspect of the first embodiment shown in FIG. In FIG. 35, the shape of the gate electrode G2 is simplified.

<Embodiment 2>
(First aspect)
FIG. 36 is an explanatory diagram showing a perspective sectional structure of the first mode of the P-type FinFET according to the second embodiment of the present invention. FIG. 37 is a cross-sectional view showing a cross-sectional structure at a cross section C2 in FIG.

  As shown in these drawings, SiC epitaxial layer 2 is formed on Si substrate 1. The SiC epitaxial layer 2 has a protrusion 2t on the upper layer. This protrusion 2t is formed in a substantially rectangular parallelepiped shape extending in the diagonally vertical direction (first direction) in FIG. 36, and has a unidirectionally extending shape.

  A Si epitaxial layer 3 (second lower semiconductor layer in the second semiconductor layer) is formed on the protruding portion 2t of the SiC epitaxial layer 2. The Si epitaxial layer 3 is also formed as a unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces. In addition, the isolation insulating film 11 is formed on the SiC epitaxial layer 2 excluding the protruding portion 2t at the same height as the upper surface of the protruding portion 2t. Further, an SiC layer 22 (second upper semiconductor layer in the second semiconductor layer) is formed on the Si epitaxial layer 3 so as to extend in the first direction. That is, the SiC layer 22 also has a unidirectionally extending shape.

  36, gate oxide films 20 are formed on both side surfaces of the Si epitaxial layer 3 and the SiC layer 22, and as shown in FIGS. 36 and 37, on the upper surface of the SiC layer 22. The oxide film 8 and the nitride film 9 are laminated. Further, the gate electrode G 2 is formed on the upper surface of the SiC layer 22 and on the side surfaces of the SiC epitaxial layer 2 and the SiC layer 22 through the oxide film 8, the nitride film 9 and the gate oxide film 20. The gate electrode G2 is formed extending in the horizontal direction (second direction) in FIG. 36, and the planar shape is T-shaped. A nitride film 19 is formed on the gate electrode G2.

  As shown in FIG. 37, in the Si epitaxial layer 3 and the SiC layer 22, the regions under the gate electrode G2 become N-type body regions 3b and 22b, and the P-type source region 3s and the body regions 3b and 22b are sandwiched therebetween. 22s and drain regions 3d and 22d are formed, respectively.

  The channel region is a region in both side surfaces of the Si epitaxial layer 3 and the SiC layer 22 under the gate oxide film 20. That is, the gate electrode G2 functions as a double gate.

  The body regions 3b and 22b, the drain regions 3d and 22d, the source regions 3s and 22d, the gate oxide film 20, and the gate electrode G2 constitute a PMOS FinFET.

  As described above, in the first mode of the second embodiment, the regions in the both side surfaces of the Si epitaxial layer 3 are channel regions. Therefore, compressive stress is applied to the Si epitaxial layer 3 by the SiC epitaxial layer 2 and the SiC layer 22 having a small lattice constant of the lower layer and the upper layer, respectively.

  38 and 39 are explanatory views showing how compressive stress is applied to the Si epitaxial layer 3 by the SiC epitaxial layer 2 and the SiC layer 22.

  As shown in FIG. 38, in the stage where the Si epitaxial layer 3 is formed on the entire surface of the SiC epitaxial layer 2 and the SiC layer 22 is formed on the Si epitaxial layer 3, two directions (first and second directions) are formed. , Compressive stresses F1 and F2 act on the Si epitaxial layer 3.

  On the other hand, as shown in FIG. 39, at the stage where the Si epitaxial layer 3, the SiC layer 22, and the protrusion 2t are processed as a one-way extending shape, the Si epitaxial layer 3 has a shape extending in the first direction. Therefore, the compressive stress F1 in the uniaxial direction acts on the Si epitaxial layer 3 more strongly than the other axial directions from the Si epitaxial layer 3 and the SiC layer 22, respectively.

  As described above, the first aspect of the second embodiment is that when the Si epitaxial layer 3, the SiC layer 22, and the protruding portion 2t are processed in a unidirectionally extending shape, the protruding portion 2t of the lower SiC epitaxial layer 2 and A compressive stress F1 in the channel length direction in one direction is generated from the upper SiC layer 22 to the Si epitaxial layer 3 more strongly than the other direction axis. For this reason, the FinFET of the second embodiment can improve the hole mobility and improve the driving capability of the transistor.

  Further, in addition to the SiC epitaxial layer 2 below the Si epitaxial layer 3, the compressive stress F1 from the SiC layer 22 above the Si epitaxial layer 3 is added, so that further improvement in hole mobility improves the current drive of the transistor over that of the first embodiment. Ability can be improved.

  Further, since the gate electrode G2 has a double gate structure, the transistor characteristics are stabilized.

  In addition, the short channel characteristics that have been a problem with FinFETs formed on bulk substrates are also suppressed due to the potential barrier due to the difference in band gap between Si and SiC, and junction leakage is reduced due to the difference in band gap. Can be achieved.

  The manufacturing method of the P-type FinFET which is the first mode of the second embodiment performs the same process as the first mode of the first embodiment shown in FIGS. 5 to 22 except for the following points. After that. Only different points will be described below.

  In the manufacturing method according to the first aspect of the first embodiment, in the step shown in FIG. 6, after formation of Si epitaxial layer 3, SiC layer 22 is further formed on Si epitaxial layer 3 by an epitaxial growth method. Then, an oxide film 4 is deposited on the SiC layer 22.

(Second aspect)
FIG. 40 is an explanatory view showing a perspective sectional structure of the second mode of the P-type FinFET according to the second embodiment of the present invention.

  As shown in the figure, the Si substrate 1 has a protruding portion 1t in part. The projecting portion 1t is formed to extend in an oblique vertical direction (first direction) in FIG. A SiC epitaxial layer 2 is formed on the protrusion 1t of the Si substrate 1. The entire SiC epitaxial layer 2 is formed in a substantially rectangular parallelepiped shape extending in the first direction. That is, the entire SiC epitaxial layer 2 has a shape extending in one direction.

  A Si epitaxial layer 3 is selectively formed on the SiC epitaxial layer 2. The Si epitaxial layer 3 is also formed as a unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces. Further, the isolation insulating film 21 is formed on the Si substrate 1 excluding the projecting portion 1t at a height approximately equal to the upper surface of the SiC epitaxial layer 2. Further, an SiC layer 22 is formed on the Si epitaxial layer 3 so as to extend in the first direction. That is, the entire SiC layer 22 has a unidirectionally extending shape.

  As shown in FIG. 40, the gate oxide film 20 is formed on both side surfaces of the Si epitaxial layer 3 and the SiC layer 22 and the oxidized surface is oxidized on the upper surface of the SiC layer 22 as in the first embodiment. A film 8 and a nitride film 9 are laminated. Further, as in the first embodiment, the gate electrode G2 is formed on the upper surface of the SiC layer 22 and on the side surfaces of the Si epitaxial layer 3 and the SiC layer 22 via the oxide film 8, the nitride film 9, and the gate oxide film 20. Is done. The gate electrode G2 is formed extending in the lateral direction (second direction) in FIG. 40, and the planar shape is T-shaped. A nitride film 19 is formed on the gate electrode G2.

  In the second mode of the second embodiment, similarly to the first mode shown in FIG. 37, in the Si epitaxial layer 3 and the SiC layer 22, the region under the gate electrode G2 becomes an N-type body region. A P-type source region and drain region are formed with the body region interposed therebetween.

  The channel region is a region in both side surfaces of the Si epitaxial layer 3 and the SiC layer 22 under the gate oxide film 20. That is, the gate electrode G2 functions as a double gate.

  The body region, the drain region, the source region, the gate oxide film 20 and the gate electrode G2 constitute a PMOS FinFET.

  In the second mode of the second embodiment, when the SiC epitaxial layer 2, the Si epitaxial layer 3, and the SiC layer 22 are processed in a unidirectionally extended shape, the lower SiC epitaxial layer 2 and A compressive stress F1 in the channel length direction in one axial direction is generated more strongly in the Si epitaxial layer 3 from each of the upper SiC layers 22 than in the other axial directions. For this reason, the FinFET of the second aspect has improved hole mobility, and can improve the driving capability of the transistor.

  In addition to the SiC epitaxial layer 2, the current driving capability of the transistor can be improved over that of the first embodiment by further improving the hole mobility by the amount of compressive stress F1 from the SiC layer 22.

  In addition, in the second mode, since the entire SiC epitaxial layer 2 has a unidirectionally extended shape, uniaxial stress (compressive stress F1) can be applied more strongly in the channel length direction. There is an effect that the driving capability of the transistor can be improved.

  In addition, the short channel characteristic that has been a problem with FinFETs formed on bulk substrates is also suppressed due to the potential barrier due to the difference in band gap between Si and SiC, and the junction leakage is reduced due to the difference in the band gap. Can be planned.

  In addition, the manufacturing method of P type FinFET which is the 2nd aspect of Embodiment 2 is 2nd of Embodiment 1 shown in FIGS. 5-11 and FIGS. 24-35 except the following points. It is performed through the same processing as that of the embodiment. Only different points will be described below.

  In the manufacturing method according to the second aspect of the first embodiment (the same process part as in the first aspect), in the step shown in FIG. 6, after the formation of the Si epitaxial layer 3, SiC is further formed on the Si epitaxial layer 3 by epitaxial growth. Layer 22 is formed. Then, an oxide film 4 is deposited on the SiC layer 22.

<Modification>
As a modification of the first embodiment (first and second modes) and the second embodiment (first and second modes), a source / drain region of a P-type FinFET formed in a PMOS transistor formation portion R2p A structure in which a SiGe layer is further formed thereon can be considered.

  FIGS. 41 to 48 are explanatory views schematically showing a manufacturing method of a modification of the first embodiment and the second embodiment in a perspective sectional structure. Hereinafter, a manufacturing method of a modification will be described with reference to these drawings. Note that the manufacturing method shown in FIGS. 41 to 48 is applied to the second mode of the first embodiment, and shows a structure in which two PMOS transistors are connected in parallel.

  FIG. 41 shows the structure of the second mode of the first embodiment immediately after forming the one-way extending shape. That is, the structure at the stage where the resist 12 is removed after the process shown in FIG.

  FIG. 42 shows the structure of the second mode of the first embodiment immediately after formation of the gate electrode G2. That is, the structure immediately after the gate electrode G2 is formed in the step shown in FIG. 26 and 35 have a cross-sectional structure along the oblique vertical direction of FIGS. 41 and 42. Hereinafter, the process after the formation of the gate electrode G2 will be described with reference to FIGS.

  First, as shown in FIG. 43, after the offset spacers 31 are formed on the side surfaces of the gate electrode G2 and the nitride film 19, LDD implantation (oblique implantation) is performed.

  Thereafter, as shown in FIG. 44, the offset spacers 31 mainly formed on the nitride film 9 are removed by an oxide film dry etching process, and a silicon nitride film 32 for forming a sidewall is deposited on the entire surface.

  Note that the LDD implantation is performed before the oxide film dry etching process. When the implantation is performed after the oxide film dry etching process, the oxide film dry etching process is inserted with respect to the width of the offset spacer 31 on the side surface of the gate electrode G2. This is in order to avoid the variation in processing and the influence on the LDD implantation profile.

  On the other hand, the oxide film dry etching process is performed after the LDD implantation and before the silicon nitride film 32 is formed because the insulating film laminated structure formed on the Si epitaxial layer 3 is formed of the oxide film 8, the nitride film 9, and the offset spacer 31. This is because the oxide film and the nitride film composed of the (oxide film) and the silicon nitride film 32 are stacked twice. In such a laminated structure, the oxide film of the offset spacer 31 becomes an obstacle in the selective epi-growth or silicide process in the subsequent process, so that the oxide film dry etching process is performed to avoid the process from becoming difficult.

  Then, as shown in FIG. 45, the silicon nitride film 32 is etched back by a dry etching process, whereby the sidewalls made of the offset spacers 31 and the silicon nitride film 32 remaining on the top and side surfaces of the gate electrode G2 and the nitride film 19 are obtained. 33 is formed. Thereafter, ion implantation for forming source / drain regions is performed as necessary. At this time, the nitride film 9 is also removed.

  Next, as shown in FIG. 46, after the oxide film 8 is removed, it is selected on the upper and side surfaces of the Si epitaxial layer 3 so as to be adjacent to the source / drain regions by epitaxial growth from the surface of the Si epitaxial layer 3. A SiGe epitaxial layer 25 (third semiconductor layer) is formed. The removal of the oxide film 8 is usually performed by a wet (etching) process such as hydrofluoric acid. In addition, after the wet treatment, a bake treatment is usually performed in a hydrogen atmosphere at about 600 ° C. to 1000 ° C. before the formation of the selective SiGe epitaxial layer 25 in order to remove the natural oxide film.

  Then, selective Si epitaxial growth is continuously performed to form an Si epitaxial layer (not shown) as a cap film on the selective SiGe epitaxial layer 25. The cap film is provided for preventing Ge contamination and stabilizing the silicide later. For convenience of explanation, a stacked structure of Si / SiGe is shown as the selective SiGe epitaxial layer 25.

  Thereafter, as shown in FIG. 47, a silicide region 26 made of, for example, NiPtSi is formed on the selective SiGe epitaxial layer 25 (cap film thereof).

  Thereafter, as shown in FIG. 48, a contact hole 27 and the like are formed by a normal back-end process (interlayer insulating film deposition, contact opening, wiring process).

  As described above, the modification is formed by forming the selective SiGe epitaxial layer 25 on at least the side surface of the Si epitaxial layer 3 adjacent to the source / drain regions, thereby applying stress from the selective SiGe epitaxial layer 25 to the channel region. A synergistic effect works, and further, the hole mobility can be improved and the driving capability of the transistor can be improved.

<Embodiment 3>
(First aspect)
FIG. 49 is an explanatory view showing a perspective sectional structure of the first mode of the P-type FinFET according to the third embodiment of the present invention. 50 is a cross-sectional view showing a cross-sectional structure at a cross-section C3 in FIG.

  As shown in these drawings, SiC epitaxial layer 2 is formed on Si substrate 1. The SiC epitaxial layer 2 has a protrusion 2t at a part thereof. The projecting portion 2t has a unidirectionally extending shape extending obliquely in the longitudinal direction (first direction) in FIG.

  Si epitaxial layer 3 is formed on protrusion 2t of SiC epitaxial layer 2. The Si epitaxial layer 3 is also formed as a unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces. In addition, the isolation insulating film 11 is formed on the SiC epitaxial layer 2 excluding the protruding portion 2t at the same height as the upper surface of the protruding portion 2t.

  As shown in FIGS. 49 and 50, a gate oxide film 24 is formed on the upper surface and both side surfaces of the Si epitaxial layer 3. Further, a gate electrode G 3 is formed on the upper surface and the side surface of the Si epitaxial layer 3 through the gate oxide film 24. The gate electrode G3 is formed so as to extend in the lateral direction (second direction) in FIG. 49, and the planar shape is T-shaped. A nitride film 39 is formed on the gate electrode G3.

  As shown in FIG. 50, in the Si epitaxial layer 3, the region under the gate electrode G3 becomes an N-type body region 3b, and a P-type source region 3s and a drain region 3d are formed across the body region 3b. The

  The channel region is a region in the upper surface and both side surfaces of the Si epitaxial layer 3 under the gate oxide film 24. That is, the gate electrode G3 functions as a trigate.

  The body region 3b, the drain region 3d, the source region 3s, the gate oxide film 24 and the gate electrode G3 constitute a PMOS FinFET.

  As described above, in the first mode of the third embodiment, regions in the upper surface and both side surfaces of the Si epitaxial layer 3 are used as channel regions. Therefore, the Si epitaxial layer 3 is subjected to compressive stress by the SiC epitaxial layer 2 having a lower lattice constant.

  As described above, the first mode of the third embodiment is similar to the first and second embodiments, when the projecting portion 2t and the Si epitaxial layer 3 are processed into a unidirectionally extended shape. A compressive stress is generated in the channel length direction in one axial direction from the protrusion 2t of the epitaxial layer 2 more strongly than in the other axial directions. For this reason, the FinFET of Embodiment 3 can improve the hole mobility and improve the driving capability of the transistor.

  Moreover, since the gate electrode G3 has a tri-gate structure in the first mode of the third embodiment, compared with the first mode of the first embodiment that employs the gate electrode G2 having a double gate structure, the Si epitaxial layer is formed. Since the upper surface of the layer 3 can also be used as a channel region, there is an effect that the current driving capability is further improved.

  In addition, the short channel characteristics that have been a problem with FinFETs formed on bulk substrates are also suppressed due to the potential barrier due to the difference in band gap between Si and SiC, and junction leakage is reduced due to the difference in band gap. Can be achieved.

  51 to 62 are cross-sectional views showing a method of manufacturing a P-type FinFET which is the first mode of the third embodiment. In these drawings, a description will be given as a process of manufacturing a PMOS transistor and an NMOS transistor in each of the Planar transistor portion R1 and the Fin transistor portion R2. Further, these drawings show a cross-sectional structure in the formation direction of the gate electrode G3 in FIG. 49 and the direction of the T-shaped I portion (second direction).

  First, the structure shown in FIG. 51 is obtained through the same process as the manufacturing method of the first aspect of the first embodiment shown in FIGS.

  That is, as shown in FIG. 51, the Planar transistor formation region R1 and the Fin transistor formation region R2 are insulated and separated by the isolation insulating film 11. Further, in the Planar transistor formation region R1, the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n are insulated and separated by the isolation insulating film 11, and in the Fin transistor formation region R2, between the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n. Thus, a structure is obtained in which isolation is performed by the isolation insulating film 11.

  Then, as shown in FIG. 52, a patterned resist 12 is formed on the Planar transistor formation region R1 using photolithography, and a dry etching process is performed on the isolation insulating film 11 in the Fin transistor formation region R2 to etch back. Then remove some. It is desirable that the upper surface of the etched isolation insulating film 11 at this time be approximately the same as the SiC / Si interface between the SiC epitaxial layer 2 and the Si epitaxial layer 3 as in the first and second embodiments.

  Further, as shown in FIG. 52, the nitride film 9 in the Fin transistor formation region R2 is removed by dry etching. Thereafter, the oxide film 8 in the Fin transistor formation region R2 is also removed by wet etching. The reason why the oxide film 8 is removed by the wet etching process is that the upper surface of the Si epitaxial layer 3 in the Fin transistor formation region R2 is not damaged by dry etching.

  Next, as shown in FIG. 53, a gate oxide film 24 is formed on the upper and side surfaces of the Si epitaxial layers 3 and 7 exposed from the isolation insulating film 11 in the Fin transistor formation region R2. At this time, when the upper surface of the isolation insulating film 11 is located below the SiC / Si interface in the PMOS transistor formation portion R2p, the gate oxide film 24 is also formed on a part of the side surface of the SiC epitaxial layer 2. Thereafter, as shown in FIG. 53, a polysilicon layer 13 is deposited on the entire surface.

  Next, as shown in FIG. 54, a CMP process is performed on the polysilicon layer 13, and the polysilicon layer 13 is etched away to the formation height of the nitride film 9 in the planar transistor formation region R1 and the fin transistor formation region R2. Therefore, all the polysilicon layer 13 on the Planar transistor formation region R1 is removed.

  Then, as shown in FIG. 55, after depositing a nitride film 36 on the entire surface, a patterned resist 14 is formed on the Fin transistor formation region R2.

  Subsequently, as shown in FIG. 56, the nitride film 36 and the nitride film 9 in the Planar transistor formation region R1 exposed from the resist 14 are removed.

  Further, as shown in FIG. 57, after removing the resist 14, the oxide film 8 in the Planar transistor formation region R1 is removed.

  Then, as shown in FIG. 58, an underlying oxide film 28 is selectively formed on the surface of the Si epitaxial layer 7 in the Planar transistor formation region R1.

  Subsequently, the various processes necessary for transistor formation (impurity implantation for well formation and impurity implantation to the channel for adjusting the threshold voltage Vth) are distinguished by NMOS / PMOS in the Planar transistor formation region R1, and the photoengraving process and ion implantation are performed. Performed using a process (not shown). Thereafter, the underlying oxide film 28 is removed.

  Thereafter, as shown in FIG. 59, a gate oxide film 23 is formed in the planar transistor formation region R1, and then a polysilicon layer 15 is deposited on the entire surface.

  Then, as shown in FIG. 60, a CMP process is performed on the polysilicon layer 15 to remove the polysilicon layer 15 up to the height of the nitride film 36 in the Fin transistor formation region R2. Therefore, a part of the polysilicon layer 15 in the Planar transistor formation region R1 remains.

  Next, as shown in FIG. 61, a nitride film 37 is deposited on the entire surface, and then a patterned resist 18 is formed using a photoengraving technique.

  Then, as shown in FIG. 62, dry etching is performed on the nitride films 37 and 36 and the polysilicon layers 15 and 13 using the resist 18 as a mask. As a result, the gate electrode G1 is formed in each of the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n in the Planar transistor formation region R1, and the gate electrode G3 is formed in each of the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n in the Fin transistor formation region R2. It is formed. Note that the laminated structure of the nitride films 36 and 37 corresponds to the nitride film 39 shown in FIGS.

  Thereafter, impurity introduction processing for forming the source / drain regions is performed, and the PMOS transistor Q11 and the NMOS transistor Q12 are completed in the Planar transistor formation region R1, and the PMOS transistor Q31 and the NMOS transistor Q32 are completed in the Fin transistor formation region R2. To do.

  As a result, the structure shown in the first mode of the third embodiment shown in FIGS. 49 and 50 can be obtained as a P-type FinFET formed in the PMOS transistor formation portion R2p in the Fin transistor formation region R2. That is, the PMOS transistor Q21 indicated by the gate peripheral region A3 in FIG. 62 is the first mode of the third embodiment shown in FIGS. In FIG. 62, the shape of the gate electrode G3 is simplified.

(Second aspect)
FIG. 63 is an explanatory view showing a perspective sectional structure of a second mode of the P-type FinFET according to the third embodiment of the present invention.

  As shown in the figure, the Si substrate 1 has a protruding portion 1t in part. The projecting portion 1t is formed to extend in an oblique vertical direction (first direction) in FIG. A SiC epitaxial layer 2 is formed on the protrusion 1t of the Si substrate 1. The SiC epitaxial layer 2 is formed as a unidirectionally extending shape extending in the first direction.

  A Si epitaxial layer 3 is selectively formed on the SiC epitaxial layer 2. The Si epitaxial layer 3 is also formed as a unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces. Further, the isolation insulating film 21 is formed on the Si substrate 1 excluding the projecting portion 1t at a height approximately equal to the upper surface of the SiC epitaxial layer 2.

  As shown in FIG. 63, the gate oxide film 24 is formed on the upper surface and both side surfaces of the Si epitaxial layer 3 as in the first embodiment. Further, similarly to the first embodiment, the gate electrode G3 is formed on the upper surface and the side surface of the Si epitaxial layer 3 via the gate oxide film 24. The gate electrode G3 is formed to extend in the horizontal direction (second direction) in FIG. 63, and the planar shape is T-shaped. A nitride film 39 is formed on the gate electrode G3.

  Also in the second mode of the third embodiment, similarly to the first mode shown in FIG. 50, in the Si epitaxial layer 3, the region under the gate electrode G3 becomes an N-type body region. A P-type source region and a drain region are formed on both sides.

  The channel region is a region in the upper surface and both side surfaces of the Si epitaxial layer 3 under the gate oxide film 24. That is, the gate electrode G3 functions as a trigate.

  The body region, the drain region, the source region, the gate oxide film 24, and the gate electrode G3 described above form a PMOS FinFET.

  The second mode of the third embodiment is similar to the first mode in that when the SiC epitaxial layer 2 and the Si epitaxial layer 3 are processed into a unidirectionally extending shape, the Si epitaxial layer 3 is lower than the lower SiC epitaxial layer 2. On the other hand, a stronger compressive stress F1 is generated in the channel length direction in one axial direction than in the other axial directions. For this reason, the FinFET of the second aspect has improved hole mobility, and can improve the driving capability of the transistor.

  Furthermore, in the second aspect, the entire SiC epitaxial layer 2 is formed in a unidirectionally extended shape, and the uniaxial stress can be applied more strongly in the channel length direction, so that the transistor driving capability is improved over that of the first aspect. The effect which can be made is produced.

  Further, in the second mode of the third embodiment, since the gate electrode G3 has a tri-gate structure, the current is further increased as compared with the second mode of the first embodiment in which the gate electrode G2 having a double gate structure is adopted. Drive ability is improved.

  In addition, the short channel characteristics that have been a problem with FinFETs formed on bulk substrates are also suppressed due to the potential barrier due to the difference in band gap between Si and SiC, and junction leakage is reduced due to the difference in band gap. Can be achieved.

  64 to 75 are cross-sectional views showing a method of manufacturing a P-type FinFET which is the second mode of the third embodiment. In these drawings, a description will be given as a process of manufacturing a PMOS transistor and an NMOS transistor in each of the Planar transistor portion R1 and the Fin transistor portion R2. Further, these drawings show a cross-sectional structure in the formation direction of the gate electrode G3 in FIG. 63 and the direction of the T-shaped I portion (second direction).

  First, similar to the manufacturing method of the second mode of the first embodiment shown in FIGS. 5 to 11 and FIGS. 24 and 25 (FIGS. 5 to 11 are the same processes as the first mode of the first embodiment). The structure shown in FIG. 64 is obtained through various processes.

  That is, as shown in FIG. 64, the Planar transistor formation region R1 and the Fin transistor formation region R2 are insulated and separated by the isolation insulating film 21. Further, in the Planar transistor formation region R1, the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n are insulated and separated by the isolation insulating film 21, and in the Fin transistor formation region R2, between the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n. Thus, a structure is obtained in which insulation is separated by the isolation insulating film 21.

  Then, as shown in FIG. 65, a patterned resist 12 is formed on the Planar transistor formation region R1 using photolithography, and a dry etching process is performed on the isolation insulating film 21 in the Fin transistor formation region R2 to etch back. Then remove some. At this time, the upper surface of the etched isolation insulating film 21 is desirably set to the same level as the SiC / Si interface between the SiC epitaxial layer 2 and the Si epitaxial layer 3, as in the first and second embodiments.

  Further, as shown in FIG. 65, the nitride film 9 in the Fin transistor formation region R2 is removed by dry etching. Thereafter, the oxide film 8 in the Fin transistor formation region R2 is also removed by wet etching. The reason why the oxide film 8 is removed by the wet etching process is that the upper surface of the Si epitaxial layer 3 is not damaged by the dry etching.

  Next, as shown in FIG. 66, a gate oxide film 24 is formed on the upper and side surfaces of the Si epitaxial layers 3 and 7 exposed from the isolation insulating film 21 in the Fin transistor formation region R2. At this time, when the upper surface of the isolation insulating film 21 is located below the SiC / Si interface in the PMOS transistor formation portion R2p, the gate oxide film 24 is also formed on a part of the side surface of the SiC epitaxial layer 2. Thereafter, as shown in FIG. 66, a polysilicon layer 13 is deposited on the entire surface.

  Next, as shown in FIG. 67, the polysilicon layer 13 is subjected to a CMP process, and the polysilicon layer 13 is etched away to the formation height of the nitride film 9 in the planar transistor formation region R1 and the fin transistor formation region R2. Therefore, all the polysilicon layer 13 on the Planar transistor formation region R1 is removed.

  As shown in FIG. 68, after depositing a nitride film 36 on the entire surface, a patterned resist 14 is formed on the Fin transistor formation region R2.

  Subsequently, as shown in FIG. 69, the nitride film 36 and the nitride film 9 in the Planar transistor formation region R1 exposed from the resist 14 are removed.

  Further, as shown in FIG. 70, after removing the resist 14, the oxide film 8 in the Planar transistor formation region R1 is removed.

  Then, as shown in FIG. 71, an underlying oxide film 28 is selectively formed on the surface of the Si epitaxial layer 7 in the Planar transistor formation region R1.

  Subsequently, as in the first embodiment, various processes necessary for transistor formation are differentiated by NMOS / PMOS in the Planar transistor formation region R1, and are performed using a photolithography process and an ion implantation process (not shown). Thereafter, the underlying oxide film 28 is removed.

  Thereafter, as shown in FIG. 72, a gate oxide film 23 is formed in the Planar transistor formation region R1, and then a polysilicon layer 15 is deposited on the entire surface.

  Then, as shown in FIG. 73, a CMP process is performed on the polysilicon layer 15 to remove the polysilicon layer 15 up to the height of the nitride film 36 in the Fin transistor formation region R2. Therefore, a part of the polysilicon layer 15 in the Planar transistor formation region R1 remains.

  Next, as shown in FIG. 74, a nitride film 37 is deposited on the entire surface, and then a patterned resist 18 is formed using a photoengraving technique.

  75, dry etching is performed on the nitride films 37 and 36 and the polysilicon layers 15 and 13 using the resist 18 as a mask. As a result, the gate electrode G1 is formed in each of the PMOS transistor formation portion R1p and the NMOS transistor formation portion R1n in the Planar transistor formation region R1, and the gate electrode G3 is formed in each of the PMOS transistor formation portion R2p and the NMOS transistor formation portion R2n in the Fin transistor formation region R2. Formed. The laminated structure of the nitride films 36 and 37 corresponds to the nitride film 39 shown in FIG.

  Thereafter, impurity introduction processing for forming source / drain regions is performed, and the PMOS transistor Q11 and NMOS transistor Q12 are completed in the Planar transistor formation region R1, and the PMOS transistor Q31 and NMOS transistor Q32 are completed in the Fin transistor formation region R2, respectively.

  As a result, the structure shown in the second mode of the third embodiment shown in FIG. 63 can be obtained as a P-type FinFET formed in the PMOS transistor formation portion R2p of the Fin transistor formation region R2. That is, the PMOS transistor Q21 indicated by the gate peripheral region A4 in FIG. 75 is the second aspect of the third embodiment shown in FIG. In FIG. 75, the shape of the gate electrode G3 is simplified.

<Embodiment 4>
(First aspect)
FIG. 76 is an explanatory diagram showing a perspective sectional structure of the first mode of the P-type FinFET according to the fourth embodiment of the present invention. 77 is a cross-sectional view showing a cross-sectional structure taken along a cross-section C4 in FIG.

  As shown in these drawings, SiC epitaxial layer 2 is formed on Si substrate 1. The SiC epitaxial layer 2 has a protrusion 2t at a part thereof. The projecting portion 2t is formed as a one-way extending shape extending in the longitudinal direction (first direction) in FIG.

  Si epitaxial layer 3 is formed on protrusion 2t of SiC epitaxial layer 2. The Si epitaxial layer 3 is also formed as a unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces. In addition, the isolation insulating film 11 is formed on the SiC epitaxial layer 2 excluding the protruding portion 2t at the same height as the upper surface of the protruding portion 2t. Further, an SiC layer 22 is formed on the Si epitaxial layer 3 so as to extend in the first direction. That is, the SiC layer 22 also has a unidirectionally extending shape.

  As shown in FIGS. 76 and 77, a gate oxide film 24 is formed on the upper surface of the SiC layer 22 and on both side surfaces of the SiC layer 22 and the Si epitaxial layer 3. Further, a gate electrode G 3 is formed on the upper surface of SiC layer 22 and on the side surfaces of SiC epitaxial layer 2 and SiC layer 22 through gate oxide film 24. The gate electrode G3 is formed so as to extend in the horizontal direction (second direction) in FIG. 76, and the planar shape is T-shaped. A nitride film 39 is formed on the gate electrode G3.

  As shown in FIG. 77, in the Si epitaxial layer 3 and the SiC layer 22, regions under the gate electrode G2 become N-type body regions 3b and 22b, and P-type source regions 3s and 22s and the body region 3b are sandwiched therebetween. Drain regions 3d and 22d are formed, respectively.

  Under the gate oxide film 24, a region in the upper surface of the SiC layer 22 and a region in both side surfaces of the Si epitaxial layer 3 and the SiC layer 22 become channel regions. That is, the gate electrode G3 functions as a trigate.

  The body regions 3b and 22b, the drain regions 3d and 22d, the source regions 3s and 22d, the gate oxide film 24, and the gate electrode G3 constitute a PMOS FinFET.

  As described above, in the first mode of the fourth embodiment, regions in the upper surface of SiC layer 22 and in both side surfaces of SiC layer 22 and Si epitaxial layer 3 are used as channel regions. Therefore, compressive stress is applied to the Si epitaxial layer 3 by the SiC epitaxial layer 2 and the SiC layer 22 having a small lattice constant of the lower layer and the upper layer, respectively.

  Therefore, the first mode of the fourth embodiment is similar to the second embodiment in that when the protruding portion 2t, the Si epitaxial layer 3 and the SiC layer 22 are processed in a unidirectionally extending shape, the lower SiC epitaxial layer 2 is processed. From the protruding portion 2t and the upper SiC layer 22, a compressive stress F1 in the channel length direction in one direction is generated more strongly than the other direction axis with respect to the Si epitaxial layer 3. For this reason, the FinFET of the fourth embodiment can improve the hole mobility and improve the driving capability of the transistor.

  In addition to the SiC epitaxial layer 2, the current driving capability of the transistor can be improved over that of the third embodiment by further improving the hole mobility as much as the compressive stress F1 from the SiC layer 22 is applied.

  Further, in the first mode of the fourth embodiment, since the gate electrode G3 has a tri-gate structure, the current is further increased as compared with the first mode of the second embodiment in which the gate electrode G2 having a double gate structure is adopted. Drive ability is improved.

  In addition, the short channel characteristics that have been a problem with FinFETs formed on bulk substrates are also suppressed due to the potential barrier due to the difference in band gap between Si and SiC, and junction leakage is reduced due to the difference in band gap. Can be achieved.

  In addition, the manufacturing method of P type FinFET which is the 1st aspect of Embodiment 4 is 1st of Embodiment 3 shown in FIGS. 5-12 and FIGS. 51-62 except the following points. It is performed through the same processing as that of the embodiment. Only different points will be described below.

  In the manufacturing method according to the first aspect of the third embodiment, in the step shown in FIG. 6, after formation of Si epitaxial layer 3, SiC layer 22 is further formed on Si epitaxial layer 3 by an epitaxial growth method. Then, an oxide film 4 is deposited on the SiC layer 22.

(Second aspect)
FIG. 78 is an explanatory view showing a perspective sectional structure of the second mode of the P-type FinFET according to the fourth embodiment of the present invention.

  As shown in the figure, the Si substrate 1 has a protruding portion 1t in part. This protrusion 1t is formed to extend in the vertical direction (first direction) in FIG. A SiC epitaxial layer 2 is formed on the protrusion 1t of the Si substrate 1. The SiC epitaxial layer 2 is formed as a unidirectionally extending shape extending in the first direction.

  A Si epitaxial layer 3 is selectively formed on the SiC epitaxial layer 2. The entire Si epitaxial layer 3 is also formed as a unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces. Further, the isolation insulating film 21 is formed on the Si substrate 1 excluding the projecting portion 1t at a height approximately equal to the upper surface of the SiC epitaxial layer 2. Further, a SiC layer 22 extending in the first direction and extending in one direction is formed on the Si epitaxial layer 3.

  As shown in FIG. 78, the gate oxide film 24 is formed on the upper surface of the SiC epitaxial layer 3 and on both sides of the SiC layer 22 as in the first embodiment. Further, similarly to the first embodiment, the gate electrode G3 is formed on the upper surface of the SiC layer 22 and on the side surfaces of the Si epitaxial layer 3 and the SiC layer 22 via the gate oxide film 24. The gate electrode G3 is formed to extend in the horizontal direction (second direction) in FIG. 78, and the planar shape is T-shaped. A nitride film 39 is formed on the gate electrode G3.

  In the second mode of the fourth embodiment, similarly to the first mode shown in FIG. 77, in the Si epitaxial layer 3 and the SiC layer 22, the region under the gate electrode G3 becomes an N-type body region. A P-type source region and drain region are formed with the body region interposed therebetween.

  The channel region is a region in the upper surface of SiC layer 22 below gate oxide film 24 and in both side surfaces of Si epitaxial layer 3 and SiC layer 22. That is, the gate electrode G3 functions as a trigate.

  The body region, the drain region, the source region, the gate oxide film 24, and the gate electrode G3 described above form a PMOS FinFET.

  In the second mode of the fourth embodiment, when the SiC epitaxial layer 2, the Si epitaxial layer 3, and the SiC layer 22 are processed in a unidirectionally extended shape, the lower SiC epitaxial layer 2 and A compressive stress F1 in the channel length direction in one direction is generated from the upper SiC layer 22 to the Si epitaxial layer 3 more strongly than the other direction axis. For this reason, the FinFET of the second aspect has improved hole mobility, and can improve the driving capability of the transistor.

  In addition, in the second aspect, the entire SiC epitaxial layer 2 is formed in a unidirectionally extended shape, and the uniaxial stress can be applied more strongly in the channel length direction, so that the driving capability of the transistor is higher than that in the first aspect. There is an effect that can be improved.

  In addition to the SiC epitaxial layer 2, the current driving capability of the transistor can be improved over that of the third embodiment by further improving the hole mobility as much as the compressive stress F1 from the SiC layer 22 is applied.

  Further, in the second mode of the fourth embodiment, since the gate electrode G3 has a tri-gate structure, the current is further increased as compared with the second mode of the second embodiment in which the gate electrode G2 having a double gate structure is adopted. Drive ability is improved.

  In addition, the short channel characteristics that have been a problem with FinFETs formed on bulk substrates are also suppressed due to the potential barrier due to the difference in band gap between Si and SiC, and junction leakage is reduced due to the difference in band gap. Can be achieved.

  In addition, the manufacturing method of P type FinFET which is the 2nd aspect of Embodiment 4 is the 2nd of Embodiment 3 shown in FIGS. 5-12 and FIGS. 54-75 except the following points. It is performed through the same processing as that of the embodiment. Only different points will be described below.

  In the manufacturing method according to the second aspect of the third embodiment (the same process portion as in the first aspect), in the step shown in FIG. 6, after the formation of the Si epitaxial layer 3, SiC is further formed on the Si epitaxial layer 3 by the epitaxial growth method. Layer 22 is formed. Then, an oxide film 4 is deposited on the SiC layer 22.

<Modification>
As a modification of the third embodiment (first and second modes) and the fourth embodiment (first and second modes), a source / drain region of a P-type FinFET formed in a PMOS transistor formation portion R2p A structure in which a SiGe layer is formed at least on the side surface of the Si epitaxial layer 3 is conceivable. In addition, in a manufacturing method, it carries out similarly to the manufacturing process shown in FIGS.

<Embodiment 5>
FIG. 79 is an explanatory view showing a perspective sectional structure of a P-type FinFET according to the fifth embodiment of the present invention. 80 is a cross-sectional view showing a cross-sectional structure taken along a cross-section C5 in FIG.

  As shown in these drawings, a buried oxide film 42 is formed on a support substrate 41, and an SOI layer 43 (silicon layer) made of Si is formed on the buried oxide film 42. That is, in the fifth embodiment, a P-type FinFET is formed on an SOI substrate including the support substrate 41, the buried oxide film 42, and the SOI layer 43. That is, an SOI substrate having an SOI layer 43 on the top as the semiconductor substrate is employed.

  The SOI layer 43 is formed as a unidirectionally extending shape extending in the vertical direction (first direction) in FIG. An epitaxial SiC layer 44 is formed as a unidirectionally extending shape on the SOI layer 43 along the first direction.

  An epitaxial Si layer 45 is selectively formed on the epitaxial SiC layer 44. The epitaxial Si layer 45 is also formed as a unidirectionally extending shape extending in the first direction, and has an upper surface and side surfaces.

  79 and 80, the gate oxide film 24 is formed on the upper surface of the epitaxial Si layer 45 and on both sides of the SOI layer 43, the epitaxial SiC layer 44, and the epitaxial Si layer 45. Further, the gate electrode G 3 is formed on the upper surface and the side surface of the epitaxial Si layer 45 via the gate oxide film 24. The gate electrode G3 is formed so as to extend in the lateral direction (second direction) in FIG. 79, and has a T-shaped planar shape.

  As shown in FIG. 80, in the stacked structure composed of the SOI layer 43, the epitaxial SiC layer 44, and the epitaxial Si layer 45, a region under the gate electrode G3 becomes an N-type body region 46b, and a P-type is sandwiched between the body region 46b. The source region 46s and the drain region 46d are respectively formed.

  The channel region is a region in the upper surface of the epitaxial Si layer 45 under the gate oxide film 24 and in both side surfaces of the stacked structure. That is, the gate electrode G3 functions as a trigate.

  The body region 46b, the drain region 46d, the source region 46s, the gate oxide film 24, and the gate electrode G3 constitute a PMOS FinFET.

  As described above, in the fifth embodiment, regions in the upper surface of the epitaxial Si layer 45 and in both side surfaces of the stacked structure are used as channel regions. Therefore, compressive stress is applied to the epitaxial Si layer 45 (SOI layer 43) by the epitaxial SiC layer 44 having a lower lattice constant.

  81 and 82 are explanatory views showing how compressive stress is applied to the epitaxial Si layer 45 by the epitaxial SiC layer 44. FIG.

  As shown in FIG. 81, when the epitaxial SiC layer 44 and the epitaxial Si layer 45 have a relatively wide planar area in two directions, the compressive stresses F1 and F2 in the two directions (first and second directions) are applied to the epitaxial Si layer. Work to 45.

  On the other hand, as shown in FIG. 82, when the epitaxial SiC layer 44 and the epitaxial Si layer 45 are processed into a unidirectionally extending shape, the epitaxial Si layer 45 has a shape extending in the first direction. The compressive stress F1 in the uniaxial direction from the SiC layer 44 acts on the epitaxial Si layer 45 stronger than the other axes.

  As described above, in the fifth embodiment, when the epitaxial SiC layer 44 and the epitaxial Si layer 45 are processed in a unidirectionally extending shape, the uniaxial channel from the lower epitaxial SiC layer 44 to the Si epitaxial layer 3 is obtained. Longitudinal compressive stress F1 is generated more strongly than the other axes. For this reason, the FinFET of the fifth embodiment can improve the hole mobility and improve the driving capability of the transistor.

  In addition, in the fifth embodiment, by forming the FinFET on the SOI substrate, the buried oxide film 42 is formed under the unidirectionally extended shape as compared with the first to fourth embodiments using the bulk substrate. Therefore, the short channel characteristics and junction leakage can be drastically reduced.

(Other aspects)
The structure shown in FIGS. 79 and 80 is basically a structure in which the structure of the third embodiment is formed on an SOI substrate, and has the same effects as those of the third embodiment. Similarly, the structure of the first embodiment is formed on an SOI substrate as shown in FIG. 83, the structure of the second embodiment is formed on an SOI substrate as shown in FIG. As shown, the structure of Embodiment 4 can be formed on an SOI substrate. Even if these structures are adopted, in addition to the effects of the fifth embodiment described above, the effects described in the first, second, and fourth embodiments are similarly performed.

  In addition, the description about FIGS. 83-85 attaches | subjects the same code | symbol, and abbreviate | omits description. 84 and 85 correspond to SiC layer 22 in the second and fourth embodiments.

  In addition, the above-described drawings are shown as the structure of the second mode of each of the first to fourth embodiments. However, if the SOI layer 43 is sufficiently thick, the first to fourth embodiments are described. Of course, it is also possible to form with the structure of each 1st aspect.

  Of course, a structure in which a SiGe layer is formed on the source / drain regions is also conceivable as a modification.

  The manufacturing method of the fifth embodiment is the same as the manufacturing method of the first to fourth embodiments except that the Si substrate 1 is replaced with an SOI substrate (support substrate 41, buried oxide film 42, and SOI layer 43). It is the same.

  The present invention is applicable to all devices using FinFETs.

It is explanatory drawing which shows the perspective cross-section of the 1st aspect of P type FinFET which is Embodiment 1 of this invention. It is sectional drawing which shows the cross-section in the predetermined cross section of FIG. 6 is an explanatory diagram showing how compressive stress is applied to the Si epitaxial layer by the SiC epitaxial layer in the first embodiment. FIG. 6 is an explanatory diagram showing how compressive stress is applied to the Si epitaxial layer by the SiC epitaxial layer in the first embodiment. FIG. 9 is a cross-sectional view showing a method of manufacturing the P-type FinFET which is the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the first aspect of the first embodiment. FIG. It is explanatory drawing which shows the perspective cross-section of the 2nd aspect of P type FinFET which is Embodiment 1 of this invention. 9 is a cross-sectional view showing a method of manufacturing the P-type FinFET that is the second mode of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of the second aspect of the first embodiment. FIG. It is explanatory drawing which shows the perspective cross-section of the 1st aspect of P type FinFET which is Embodiment 2 of this invention. FIG. 37 is a cross-sectional view showing a cross-sectional structure in a predetermined cross section of FIG. 36. FIG. 10 is an explanatory diagram showing how compressive stress is applied to the Si epitaxial layer by the SiC epitaxial layer in the second embodiment. FIG. 10 is an explanatory diagram showing how compressive stress is applied to the Si epitaxial layer by the SiC epitaxial layer in the second embodiment. It is explanatory drawing which shows the perspective cross-section of the 2nd aspect of P type FinFET which is Embodiment 2 of this invention. It is explanatory drawing which shows typically the manufacturing method of the modification of Embodiment 1 and Embodiment 2 by a perspective cross-section structure. It is explanatory drawing which shows typically the manufacturing method of a modification with a perspective cross-section. It is explanatory drawing which shows typically the manufacturing method of a modification with a perspective cross-section. It is explanatory drawing which shows typically the manufacturing method of a modification with a perspective cross-section. It is explanatory drawing which shows typically the manufacturing method of a modification with a perspective cross-section. It is explanatory drawing which shows typically the manufacturing method of a modification with a perspective cross-section. It is explanatory drawing which shows typically the manufacturing method of a modification with a perspective cross-section. It is explanatory drawing which shows typically the manufacturing method of a modification with a perspective cross-section. It is explanatory drawing which shows the perspective cross-section of the 1st aspect of P type FinFET which is Embodiment 3 of this invention. It is sectional drawing which shows the cross-section in the predetermined cross section of FIG. 11 is a cross-sectional view showing a method of manufacturing a P-type FinFET that is the first aspect of the third embodiment. FIG. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. FIG. 11 is a cross-sectional view showing the method for manufacturing the first aspect of the third embodiment. It is explanatory drawing which shows the perspective cross-section of the 2nd aspect of P type FinFET which is Embodiment 3 of this invention. 11 is a cross-sectional view showing a method of manufacturing a P-type FinFET that is the second mode of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. 12 is a cross-sectional view showing the manufacturing method of the second aspect of the third embodiment. FIG. It is explanatory drawing which shows the perspective cross-section of the 1st aspect of P type FinFET which is Embodiment 4 of this invention. FIG. 77 is a cross-sectional view showing a cross-sectional structure in a predetermined cross section of FIG. 76. It is explanatory drawing which shows the perspective cross-section of the 2nd aspect of P type FinFET which is Embodiment 4 of this invention. It is explanatory drawing which shows the perspective cross-section of P type FinFET which is Embodiment 5 of this invention. FIG. 80 is a cross-sectional view showing a cross-sectional structure in a predetermined cross section of FIG. 79. FIG. 10 is an explanatory diagram showing how compressive stress is applied to an epitaxial Si layer by an epitaxial SiC layer in the fifth embodiment. FIG. 10 is an explanatory diagram showing how compressive stress is applied to an epitaxial Si layer by an epitaxial SiC layer in the fifth embodiment. FIG. 25 is an explanatory diagram showing another aspect of the fifth embodiment. FIG. 25 is an explanatory diagram showing another aspect of the fifth embodiment. FIG. 25 is an explanatory diagram showing another aspect of the fifth embodiment.

Explanation of symbols

  1 Si substrate, 2 SiC epitaxial layer, 3 Si epitaxial layer, 3b, 22b body region, 3d, 22d, 46d drain region, 3s, 22s, 46s source region, 8 oxide film, 9, 19, 39 nitride film, 11 isolation Insulating film, 20 gate oxide film, 21 isolation insulating film, 22, 47 SiC layer, 24 gate insulating film, 25 selective SiGe epitaxial layer, 41 support substrate, 42 buried oxide film, 43 SOI layer, 44 epitaxial SiC layer, 45 epitaxial Si layer, G1-G3 gate electrode.

Claims (17)

A semiconductor device including a PMOS transistor,
A semiconductor substrate;
A first semiconductor layer formed on the semiconductor substrate and containing SiC as a constituent material, wherein at least an upper layer portion of the first semiconductor layer exhibits a unidirectionally extending shape extending in a predetermined direction;
A second semiconductor layer formed on the upper layer of the first semiconductor layer and containing Si as a constituent material. The second semiconductor layer has an upper surface and side surfaces, and extends in the predetermined direction. Exhibiting a unidirectionally extended shape,
A gate insulating film formed on at least a side surface of the second semiconductor layer;
A gate electrode formed on the side surface of the second semiconductor layer via the gate insulating film,
The second semiconductor layer includes P-type source / drain regions formed across a channel region that is a surface of the second semiconductor layer under the gate insulating film,
The PMOS transistor includes the gate insulating film, the gate electrode, the channel region, and the source / drain region.
Semiconductor device. The semiconductor device according to claim 1,
The first semiconductor layer is entirely formed in a unidirectionally extending shape along the predetermined direction.
Semiconductor device. A semiconductor device according to claim 1 or claim 2, wherein
The second semiconductor layer includes
A second lower semiconductor layer whose constituent material is Si;
A second upper semiconductor layer formed on the second lower semiconductor layer and made of SiC as a constituent material;
Semiconductor device. A semiconductor device according to any one of claims 1 to 3,
The gate insulating film is
Including a gate insulating film formed only on a side surface of the second semiconductor layer;
Semiconductor device. A semiconductor device according to any one of claims 1 to 3,
The gate insulating film is
A gate insulating film formed on an upper surface and a side surface of the second semiconductor layer;
The gate electrode is further formed on the upper surface of the second semiconductor layer via the gate insulating film.
Semiconductor device. A semiconductor device according to any one of claims 1 to 5,
A third semiconductor layer that is formed on at least a side surface of the second semiconductor layer so as to be adjacent to the source / drain regions, and includes SiGe as a constituent material;
Semiconductor device. A semiconductor device according to any one of claims 1 to 6,
The semiconductor substrate comprises a bulk substrate;
Semiconductor device. A semiconductor device according to any one of claims 1 to 6,
The semiconductor substrate includes an SOI substrate which is a silicon layer which is an uppermost layer portion.
Semiconductor device. A method of manufacturing a semiconductor device including a PMOS transistor having a fin-type structure,
(a) preparing a semiconductor substrate containing Si as a constituent material;
(b) forming a first semiconductor layer containing SiC as a constituent material on the semiconductor substrate portion using an epitaxial growth method;
(c) forming a second semiconductor layer containing Si as a constituent material on the first semiconductor layer using an epitaxial growth method;
(d) A pattern in which the first and second semiconductor layers are patterned so that at least the upper layer portion of the first semiconductor layer and the entire second semiconductor layer have an upper surface and side surfaces and extend in a predetermined direction. A direction extending shape;
(e) forming a gate insulating film on at least a side surface of the second semiconductor layer;
(f) forming a gate electrode on a side surface of the second semiconductor layer through the gate insulating film;
(g) further forming a P-type source / drain region sandwiching a channel region which is a surface of the second semiconductor layer under the gate insulating film,
The gate electrode, the gate insulating film, the channel region, and the source / drain region constitute the fin-type PMOS transistor.
A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 9, comprising:
The step (d) includes forming the entire first semiconductor layer into the unidirectionally extending shape,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 9 or 10,
Step (c)
(c-1) forming a second lower semiconductor layer containing Si as a constituent material on the first semiconductor layer using an epitaxial growth method;
(c-2) forming a second upper semiconductor layer containing SiC as a constituent material on the second lower semiconductor layer using an epitaxial growth method;
The second semiconductor layer includes a stacked structure of the second lower semiconductor layer and the second upper semiconductor layer.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 9 to 11,
The step (e) includes forming the gate insulating film only on the side surface of the second semiconductor layer.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 9 to 11,
The step (e) includes forming the gate insulating film on an upper surface and a side surface of the second semiconductor layer,
The step (f) includes forming the gate electrode on the upper surface and the side surface of the second semiconductor layer through the gate insulating film.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 9 to 13,
Step (g)
Forming a third semiconductor layer containing SiGe as a constituent material on at least a side surface of the second semiconductor layer so as to be adjacent to the source / drain region;
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 9 to 14,
The semiconductor substrate comprises a bulk substrate;
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 9 to 14,
The semiconductor substrate includes an SOI substrate whose uppermost layer is a silicon layer,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 9 to 16,
The semiconductor substrate includes a planar transistor formation region and a fin transistor formation region, and the planar transistor formation region includes a first PMOS transistor formation portion and a first NMOS transistor formation portion, and the fin transistor formation The region includes a second PMOS transistor formation portion and a second NMOS transistor formation portion,
In the step (d), in the second PMOS transistor formation portion, at least the upper layer portion of the first semiconductor layer and the second semiconductor layer are formed to extend in the one direction, and the planar transistor is formed. Removing the first and second semiconductor layers of the second NMOS transistor formation portion in the entire formation region and the fin type transistor formation region,
In the step (e), a gate electrode is formed on a side surface of the second semiconductor layer through the gate insulating film in the second PMOS transistor formation portion, and the first transistor in the planar transistor formation region is formed. Forming a gate electrode for a MOS transistor in each of the first NMOS transistor, the first NMOS transistor formation, and the second NMOS transistor formation in the fin-type transistor formation region,
A method for manufacturing a semiconductor device.

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