JP2010093076A - Semiconductor package and semiconductor device - Google Patents

Abstract

A semiconductor package that can freely design the shape and arrangement of a WLP inductor without being limited by the arrangement of a pad portion, and contributes to further miniaturization and higher performance.
In a semiconductor package of the present invention, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer are sequentially stacked on a semiconductor substrate. The first electrode 12a, the second electrode 12b, and the conductive portion 12c made of the first conductive layer constitute an IC circuit provided on the semiconductor substrate, a connection terminal of the inductor portion 15a, an input / output terminal of the IC circuit, and wiring. It has a spiral inductor portion 15a composed of the second conductive layer and a pad portion 15b located in the outer peripheral region from the inductor portion. One end of the inductor portion is electrically connected to the first electrode, and the other end of the inductor portion is electrically connected to the wiring. The wiring forms an underpass structure portion of the inductor portion. The second insulating layer has a fourth opening 16a that exposes the pad portion.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor package that incorporates an on-chip inductor (also abbreviated as “WLP inductor”) as an inductive element by applying a wafer level package (WLP) technology, and a semiconductor device including the semiconductor package. .

  In recent years, due to the rapid development of the information communication market, there has been a strong demand for downsizing and cost reduction of high-frequency circuits mounted on wireless communication devices and the like. On the other hand, by improving the high-frequency characteristics of transistors by miniaturization of Si-CMOS technology, active elements such as transistors and passive elements such as inductors are fabricated on a Si substrate and integrated on a single chip in the field of high-frequency circuits. The development of such semiconductor packages is progressing. However, an inductor formed on a Si substrate by a semiconductor process has a large resistance due to the use of a thin Al wiring, and because the distance between the inductor and the Si substrate is short, it is caused by eddy currents induced in the Si substrate. Since the substrate loss is large, a high Q value (quality factor) cannot be obtained.

  Therefore, as a high-performance inductor that can be integrated into an IC on a Si substrate, a technique for forming an inductor using a WLP rewiring process has been proposed (for example, see Patent Document 1). By utilizing the thick film copper plating rewiring process of WLP and the insulating layer of thick film resin, the wiring resistance can be reduced and the substrate loss can be reduced by increasing the distance between the inductor and the Si substrate. Compared with the case of forming with a high-performance inductor has been developed that achieves a high Q value.

  As an example of a mounting method of WLP, a method of connecting an input / output terminal of an IC manufactured on a semiconductor substrate to bumps arranged in a grid array by a rewiring process and performing flip-chip bonding with a bump surface facing down Is used. With recent miniaturization and higher functionality of high-frequency circuits, there is an increasing demand for further miniaturization of bump pitch.

However, in a conventional WLP having a built-in inductor, the inductor wiring and the pads for mounting the bumps (hereinafter also referred to as “bump pads”) are formed in the same plane. Arrangement must be avoided, and the arrangement of the bump pads or the free design of the inductor shape is limited. In addition, in a semiconductor package that requires bumps arranged at a narrow pitch, it may be difficult to form an inductor by rewiring.
JP 2003-347410 A

The present invention has been made in view of the above circumstances, and the shape and arrangement of the WLP inductor can be freely designed without being limited by the arrangement of the pad portion (bump pad functioning as an external input / output terminal). The first object is to provide a semiconductor package that contributes to further miniaturization and higher performance.
It is a second object of the present invention to provide a semiconductor device in which a semiconductor package mounting method using a conventional technique can be adopted without being limited by the arrangement of the pad portion.

In order to solve the above-described problem, a semiconductor package according to claim 1 of the present invention includes a chip-like semiconductor substrate having a first electrode, a second electrode, and a conductive portion each including a first conductive layer on one surface. A spiral-shaped inductor portion which is arranged to cover the first conductive layer and one surface of the semiconductor substrate and the second conductive layer is disposed on the first insulating layer And a semiconductor package comprising at least a pad portion located in an outer peripheral region from the inductor portion, and a second insulating layer disposed so as to cover the first insulating layer and the second conductive layer, The one electrode, the second electrode, and the conductive portion respectively constitute a connection terminal of the IC circuit and the inductor portion provided on the semiconductor substrate, an input / output terminal of the IC circuit, and a wiring. ) Is the first The first electrode and the other end (inner peripheral end) of the inductor part are electrically connected to the wiring through a third opening provided in the first insulating layer through a first opening provided in the edge layer, respectively. And the wiring functions as an underpass structure portion of the inductor portion, and the pad portion penetrates the first insulating layer through a second opening provided in the first insulating layer. The semiconductor package according to claim 2, wherein the semiconductor package is electrically connected to two electrodes, and the second insulating layer has a fourth opening that exposes at least a part of the pad portion. In Claim 1, The said pad part is provided in the position which overlaps with said 2nd electrode.
A semiconductor device according to a third aspect of the present invention uses the semiconductor package according to the first or second aspect, and includes a pad portion constituting the semiconductor package and a wiring board that is separate from the semiconductor package, It is electrically connected by wire bonding.

In the semiconductor package according to the present invention, a pad portion that functions as an input / output terminal for an external signal when the substrate is mounted is arranged in an outer peripheral region from the inductor portion within the same surface of the chip-like semiconductor substrate. As a result, the presence of the pad portion (bump pad functioning as an external input / output terminal) does not limit the shape and arrangement of the inductor portion, and the WLP inductor can be freely designed in the chip plane. . Therefore, the present invention provides a semiconductor package that can be further reduced in size and performance.
The semiconductor device according to the present invention uses the above-described semiconductor package, and includes a pad portion (bump pad functioning as an external input / output terminal) constituting the semiconductor package and a wiring board that is separate from the semiconductor package. It is electrically connected by bonding. Therefore, since the semiconductor device having this configuration can employ a semiconductor package mounting method using a conventional technique, the specifications of the inductor can be freely designed and formed.

Hereinafter, an embodiment of a semiconductor package according to the present invention will be described with reference to the drawings.
1A and 1B are diagrams for explaining a semiconductor package according to an embodiment of the present invention. FIG. 1A is a cross-sectional view taken along line AA in FIG. 1B, and FIG. It is a top view of the semiconductor package (for example, high frequency IC chip) which comprises an inductor part in a semiconductor substrate. FIG. 1 shows an active element such as a transistor (not shown: corresponding to “IC circuit”) and a passive element such as an inductor (corresponding to “inductor part”) on a Si substrate (corresponding to “semiconductor substrate”). An example of a semiconductor package built in and integrated on one chip is shown.

  A semiconductor package 1 according to an embodiment of the present invention includes a chip-like semiconductor substrate 11 provided with a first electrode 12a, a second electrode 12b, and a conductive portion 12c formed of a first conductive layer 12 on one surface, A first insulating layer 14 disposed so as to cover one surface of the first conductive layer 12 and the semiconductor substrate 11, and a spiral shape disposed on the first insulating layer 14 and configured by the second conductive layer 15. Inductor portion 15a, a pad portion 15b located in an outer peripheral region from the inductor portion 15a, and a second insulating layer 16 disposed so as to cover the first insulating layer 14 and the second conductive layer 15. ing.

  The first electrode 12a, the second electrode 12b, and the conductive portion 12c are respectively connected to an IC circuit (not shown) provided on the semiconductor substrate 11, a connection terminal of the inductor portion 15a, and an IC circuit (not shown). I / O terminals and wiring. Further, one end (outer peripheral end) of the inductor portion 15a passes through the first opening 14a provided in the first insulating layer 14, and the other end (inner peripheral end) of the first electrode 12a and the inductor portion 15a is the first opening. The wiring 12c is electrically connected to each other through a third opening 14c provided in one insulating layer 14, and the wiring 12c functions as an underpass structure portion of the inductor portion 15a. Further, the second insulating layer 16 has a fourth opening 16a that exposes at least a part of the pad portion 15b.

As shown in FIG. 1, a semiconductor wafer such as a Si wafer is used as the semiconductor substrate 11 in the semiconductor package of this embodiment.
The first electrode 12a, the second electrode 12b, and the wiring (underpass structure portion) 12c are all composed of the first conductive layer 12, and are made of, for example, Al. The first electrode 12a electrically connects the outer peripheral end of the inductor portion (also referred to as “WLP inductor”) 15a, and the underpass structure portion 12c individually connects the inner peripheral end of the WLP inductor 15a to an IC circuit (not shown). Function as a connection terminal. At this time, the underpass structure portion 12c is arranged so as to cross the lower portion of the spiral structure portion of the inductor portion 15a.

The first electrode 12a functions as a connection terminal between the IC circuit (not shown) and the inductor portion 15a. On the other hand, the second electrode 12b functions as an input / output terminal of an IC circuit (not shown), and is disposed on the semiconductor substrate 11 in the outer peripheral region from the inductor portion 15a.
The semiconductor substrate 11 includes a passivation film 13 formed of an insulating film such as SiN or SiO _{2 in a} region where the first conductive layer 12 is not provided on one surface thereof. The passivation film 13 is formed by, for example, the LP-CVD method, and the film thickness is, for example, 0.1 to 0.5 μm.

The first insulating layer 14 is arranged so as to cover one surface of the semiconductor substrate 11, and is formed at a position aligned with the first opening 14a and the second electrode 12b formed at a position aligned with the first electrode 12a. The second opening 14b is formed, and the third opening 14c is formed at a position aligned with one end of the wiring (underpass structure) 12c. The 1st insulating layer 14 consists of insulating resins, such as a polyimide resin, an epoxy resin, a silicone resin, for example, The thickness is 1-30 micrometers.
Examples of the method for forming the first insulating layer 14 include a spin coating method, a printing method, and a laminating method. The three openings 14a, 14b, and 14c described above can be formed by, for example, patterning using a photolithography technique.

The second conductive layer 15 is disposed on the first insulating layer 14, and an inductor portion 15 a serving as an inductive element is provided in part of the second conductive layer 15, and a pad portion that functions as an input / output terminal for external signals when mounted on the other part of the substrate. 15b. The outer peripheral end of the inductor portion 15a penetrates the first insulating layer 14 through the first opening 14a, and the inner peripheral end of the first electrode 12a and the inductor portion 15a is first insulated through the third opening 14c. One end of the wiring (underpass structure portion) 12c penetrating the layer 14 and the pad portion 15b penetrate the first insulating layer 14 through the second opening 14b and are electrically connected to the second electrode 12b. .
For example, Cu or the like is used as the material of the second conductive layer 15, and the thickness thereof is, for example, 1 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The second conductive layer 15 can be formed by, for example, a plating method such as electrolytic copper plating, a sputtering method, a vapor deposition method, or a combination of two or more methods.

The second insulating layer 16 is a sealing resin layer that is disposed on the second conductive layer 15 and protects the second conductive layer 15, and is a fourth opening formed at a position aligned with the pad portion 15 b. 16a. The 2nd insulating layer 16 consists of insulating resins, such as a polyimide resin, an epoxy resin, a silicone resin, for example, The thickness is 5-10 micrometers, for example.
Examples of the method for forming the second insulating layer 16 include a spin coating method, a printing method, and a laminating method. The opening 16a can be formed by patterning using a photolithography technique, for example.

  As described above, the pad portion 15b, which is formed of the second conductive layer 15 and functions as an input / output terminal for an external signal when the substrate is mounted, is arranged on the outer peripheral area of the semiconductor substrate 11 constituting the IC chip. Thus, there is no restriction on the shape and arrangement of the inductor portion 15a formed in the central portion of the IC chip. As a result, the inductor portion 15a using the WLP rewiring process can be freely designed and formed in the chip surface, so that a higher-performance IC package of a high-frequency IC can be obtained.

  Furthermore, in the semiconductor package 1 of the present invention, it is preferable that the second electrode 12b and the pad portion 15b are arranged at positions where they overlap each other when viewed from above. As a result, the region on the semiconductor substrate 11 can be utilized to the maximum, and a semiconductor package that contributes to further miniaturization can be obtained.

  At this time, an underpass wiring crossing the spiral structure portion of the inductor is formed by the second conductive layer 15, and the second insulating layer 16 is disposed, and the spiral portion of the inductor and the input of an external signal are provided as the third conductive layer. A structure for forming an output terminal may be used. Thereby, the distance between the spiral portion of the inductor and the semiconductor substrate 11 is increased, and the Q value of the inductor can be further improved.

Furthermore, the semiconductor package 1 of the present invention has a pad portion 15b that functions as an input / output terminal for an external signal arranged in the outer peripheral area of the semiconductor substrate 11 constituting the IC chip. It can be mounted face-up on a separate wiring board, and the pad portion 15b and the input / output terminals of the wiring board can be electrically connected by wire bonding. Thereby, the mounting method of the semiconductor package 1 using the conventional technique can be used, and the specification of the inductor portion 15a can be freely designed and formed. Further, mounting with face-up brings about a reduction in the influence of the inductor on the wiring board.
At this time, a bump made of, for example, Au or solder may be formed on the pad 15b that functions as an input / output terminal for an external signal, and the IC chip may be flip-chip mounted on the wiring board.

  The present invention can be used for, for example, a semiconductor package incorporating an on-chip inductor as an inductive element, or a semiconductor device including the semiconductor package.

The schematic diagram which shows an example of the semiconductor package which concerns on this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor package, 11 Semiconductor substrate, 12 1st conductive layer, 12a 1st electrode, 12b 2nd electrode, 12c wiring (underpass structure part), 13 passivation film, 14 1st insulating layer, 14a 1st opening part, 14b 2nd opening part, 14c 3rd opening part, 15 2nd conductive layer, 15a Inductor part, 15b Pad part (external input / output terminal), 16 2nd insulating layer, 16a 4th opening part.

Claims (3)

A chip-like semiconductor substrate having a first electrode, a second electrode, and a conductive portion formed on the first conductive layer on one side, and a first conductive layer and one side of the semiconductor substrate arranged to cover one side. A first insulating layer formed on the first insulating layer, a spiral-shaped inductor portion arranged on the first insulating layer and configured by a second conductive layer, a pad portion located in an outer peripheral region from the inductor portion, and the first insulating layer And a second insulating layer arranged to cover the second conductive layer, and a semiconductor package comprising at least
The first electrode, the second electrode, and the conductive portion respectively constitute a connection terminal of an IC circuit and an inductor portion provided on the semiconductor substrate, an input / output terminal of the IC circuit, and a wiring,
One end of the inductor portion through the first opening provided in the first insulating layer, the first electrode, and the other end of the inductor portion through the third opening provided in the first insulating layer, the wiring, The wiring is electrically connected, the wiring functions as an underpass structure portion of the inductor portion, and the pad portion is connected to the first insulating layer through a second opening provided in the first insulating layer. Penetrates and is electrically connected to the second electrode,
The semiconductor package, wherein the second insulating layer has a fourth opening that exposes at least a part of the pad.   The semiconductor package according to claim 1, wherein the pad portion is provided at a position overlapping the second electrode.   A semiconductor package according to claim 1 or 2, wherein a pad portion constituting the semiconductor package and a wiring board separate from the semiconductor package are electrically connected by wire bonding. A featured semiconductor device.

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