JP2010092934A - Method of manufacturing semiconductor light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor light-emitting element that includes a substrate and a group III compound semiconductor layer formed thereupon, the substrate being made of a material different from a compound semiconductor constituting the semiconductor layer and that includes a narrow wavelength distribution. <P>SOLUTION: The method of manufacturing the semiconductor light-emitting element having the group III compound semiconductor layer includes a semiconductor layer film forming step of forming the group III compound semiconductor layer of ≥8 μm in total thickness on the substrate 11 having an amount of warping H of ±30 μm, and having a diameter D and a thickness d, wherein the diameter D and thickness d of the substrate 11 satisfy the expression (1) 0.7×10<SP>2</SP>≤(D/d)≤1.5×10<SP>2</SP>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly to a method for manufacturing a semiconductor light emitting device having a group III compound semiconductor layer.

  In general, in a semiconductor light emitting device having a compound semiconductor layer such as a III-V group compound semiconductor layer, a compound semiconductor layer is formed on a substrate made of a sapphire single crystal, and a positive electrode, a negative electrode, and the like are further provided. A surface to be ground is ground and polished, and then cut into an appropriate shape to prepare a light emitting element chip (see Patent Document 1).

JP 2008-177525 A

By the way, when a substrate made of a material different from the compound semiconductor composing the semiconductor layer is used, and the semiconductor layer is formed on this substrate, the substrate is warped due to a difference in thermal expansion coefficient between the substrate and the compound semiconductor. There is.
When the amount of warpage of the substrate increases in this way, there is a problem that the wavelength distribution σ of the obtained semiconductor light-emitting element increases and the defect rate of the product increases remarkably. Such a phenomenon tends to become more prominent as the substrate diameter increases.
It is also known that internal stress is generated due to processing conditions when forming a semiconductor layer on a substrate, and the substrate is likely to warp.

  An object of the present invention is to have a step of forming a group III compound semiconductor layer on a substrate made of a material different from the material constituting the semiconductor layer, and a wavelength distribution σ of the emission wavelength of the obtained semiconductor light emitting device An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device capable of reducing the size of the semiconductor light emitting device.

Thus, according to the present invention, there is provided a method for manufacturing a semiconductor light emitting device having a group III compound semiconductor layer, wherein the total thickness is formed on a substrate having a warp amount H in the range of ± 30 μm and having a diameter D and a thickness d. Having a semiconductor layer forming step of forming a group III compound semiconductor layer having a thickness of 8 μm or more, wherein the diameter D and the thickness d of the substrate satisfy the relationship of the following formula (1): A manufacturing method is provided.
0.7 × 10 ² ≦ (D / d) ≦ 1.5 × 10 ² (1)

Here, in the method for manufacturing a semiconductor light emitting device to which the present invention is applied, the group III compound semiconductor layer preferably contains a group III nitride.
Moreover, it is preferable that the diameter D of the board | substrate to be used is the range of 50 mm-155 mm, and it is preferable that the thickness d of a board | substrate is the range of 0.4 mm-1.5 mm.

Next, in the method for manufacturing a semiconductor light emitting device to which the present invention is applied, it is preferable that the warpage amount H of the substrate is selected from the ranges of 0 <H ≦ 30 μm and −30 μm ≦ H <0.
Furthermore, it is preferable that the warpage amount H of the substrate is selected from a range of −10 μm <H <0.
Furthermore, when the substrate diameter D is 50 mm to 51 mm, the warpage amount H of the substrate is selected from the range of 0 <H ≦ 30 μm and −30 μm ≦ H <0, and when the substrate diameter D is 100 mm to 102 mm, The warp amount H of the substrate is preferably selected from the range of −10 μm <H <0.
The substrate is preferably made of a material different from that of the group III compound semiconductor.
Furthermore, the substrate is preferably made of sapphire.

Next, the method for manufacturing a semiconductor light emitting device to which the present invention is applied preferably includes an intermediate layer forming step of forming an intermediate layer between the substrate and the group III compound semiconductor layer by a sputtering method.
The group III compound semiconductor layer is preferably formed by sequentially stacking a base layer, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate.
Further, the group III compound semiconductor layer is preferably formed on the substrate by metal organic chemical vapor deposition.

  According to the present invention, in the method for manufacturing a semiconductor light emitting device, when the group III compound semiconductor layer is formed on the substrate made of a material different from the material constituting the semiconductor layer, the warp amount H is in the range of ± 30 μm. Further, by using a substrate in which the relationship between the diameter D and the thickness d of the substrate satisfies the above-described formula (1), the wavelength distribution of the emission wavelength is not affected by a plurality of processes in the manufacturing process. A semiconductor wafer (semiconductor light emitting device) having a small σ can be manufactured. In particular, according to the method for manufacturing a semiconductor light emitting device of the present invention, the wavelength distribution σ can be 6 nm or less, preferably 5 nm or less.

  Hereinafter, embodiments of the present invention will be described in detail. In addition, this invention is not limited to the following embodiment, It can implement by changing variously within the range of the summary. Further, the drawings to be used are for explaining the present embodiment and do not represent the actual size.

(Semiconductor light emitting device)
The semiconductor light emitting device manufactured in the present embodiment usually has a predetermined substrate and a compound semiconductor layer formed on the substrate. Examples of the compound semiconductor constituting the compound semiconductor layer include a III-V group compound semiconductor, a II-VI group compound semiconductor, a IV-IV group compound semiconductor, and the like. In the present embodiment, a III-V group compound semiconductor is preferable, and among these, a group III nitride compound semiconductor is preferable. Hereinafter, a semiconductor light emitting device having a group III nitride compound semiconductor will be described as an example.

FIG. 1 is a diagram illustrating an example of a semiconductor light emitting device manufactured in the present embodiment. As shown in FIG. 1, in the semiconductor light emitting device 1, a base layer 13, an n-type semiconductor layer 14, a light emitting layer 15, and a p-type semiconductor layer 16 are sequentially stacked on an intermediate layer 12 formed on a substrate 11. These constitute the compound semiconductor layer (group III compound semiconductor layer) 20.
Further, a translucent positive electrode 17 is laminated on the p-type semiconductor layer 16, a positive electrode bonding pad 18 is formed thereon, and an exposed region 14d formed in the n-type contact layer 14a of the n-type semiconductor layer 14 is formed. A negative electrode 19 is laminated.

Here, the n-type semiconductor layer 14 formed on the base layer 13 made of a group III compound semiconductor has an n-type contact layer 14a and an n-type cladding layer 14b. The light emitting layer 15 has a structure in which barrier layers 15a and well layers 15b are alternately stacked. In the p-type semiconductor layer 16, a p-type cladding layer 16a and a p-type contact layer 16b are stacked.
In the present embodiment, the total thickness of the compound semiconductor layers (group III compound semiconductor layers) 20 formed on the substrate 11 is at least 8 μm or more, preferably 8.5 μm or more, more preferably 9 μm or more. is there. Moreover, the total thickness of these is 15 micrometers or less, Preferably it is 14 micrometers or less, More preferably, it is 13 micrometers or less.
When the total thickness of the compound semiconductor layer (group III compound semiconductor layer) 20 is excessively thin, in particular, when the film thickness of the base layer 13 and the n-type semiconductor layer 14 is thin, the light emitting layer 15 and the P-type to be stacked thereafter. Since the crystallinity of the semiconductor layer 16 is deteriorated, the emission intensity tends to be weak when the semiconductor light emitting element 1 is formed.

(Substrate 11)
The substrate 11 is made of a material different from the group III nitride compound semiconductor, and a group III nitride semiconductor crystal is epitaxially grown on the substrate 11. Examples of the material constituting the substrate 11 include sapphire, silicon carbide (silicon carbide: SiC), silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, zirconium boride, and oxidation. Examples include gallium, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten, and molybdenum. Among these, sapphire and silicon carbide (silicon carbide: SiC) are preferable.
Further, the surface of the substrate 11 is preferably different in surface roughness Ra (arithmetic mean roughness) between the surface (front surface) on which the semiconductor layer is laminated and the opposite surface (back surface). In particular, it is preferable to use a substrate in which the surface roughness Ra is such that the front surface ≦ the back surface.

(Intermediate layer 12)
As described above, in the present embodiment, the substrate 11 is made of a material different from that of the group III nitride compound semiconductor. For this reason, it is preferable to provide the intermediate layer 12 that exhibits a buffer function on the substrate 11 when the compound semiconductor layer 20 is formed by metal organic chemical vapor deposition (MOCVD) as described later. In particular, the intermediate layer 12 preferably has a single crystal structure from the viewpoint of the buffer function. When the intermediate layer 12 having a single crystal structure is formed on the substrate 11, the buffer function of the intermediate layer 12 works effectively, and the base layer 13 and the compound semiconductor layer 20 formed on the intermediate layer 12 are good. It becomes a crystal film having a good orientation and crystallinity.
The intermediate layer 12 preferably contains A1, and particularly preferably contains A1N which is a group III nitride. The material constituting the intermediate layer 12 is not particularly limited as long as it is a group III nitride compound semiconductor represented by the general formula A1GaInN. Furthermore, As and P may be contained as a group V. In the case where the intermediate layer 12 has a composition containing A1, GaA1N is preferable, and the composition of A1 is preferably 50% or more.

  As a material used for the underlayer 13, a group III nitride (GaN-based compound semiconductor) containing Ga is used, and in particular, A1GaN or GaN can be suitably used. The film thickness of the underlayer 13 is 0.1 μm or more, preferably 0.5 μm or more, more preferably 1 μm or more.

(N-type semiconductor layer 14)
The n-type semiconductor layer 14 includes an n-type contact layer 14a and an n-type cladding layer 14b. As the n-type contact layer 14a, a GaN-based compound semiconductor is used in the same manner as the base layer 13. Moreover, it is preferable that the gallium nitride compound semiconductor which comprises the base layer 13 and the n-type contact layer 14a is the same composition, The total film thickness of these is 0.1 micrometer-20 micrometers, Preferably it is 0.5 micrometer-15 micrometers, Preferably, it is set in the range of 1 μm to 12 μm.

  The n-type cladding layer 14b can be formed of A1GN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. In the case of using GaInN, it is desirable to make it larger than the GaInN band gap of the well layer 15b constituting the light emitting layer 15 described later. The film thickness of the n-type cladding layer 14b is preferably in the range of 5 nm to 500 nm, more preferably 5 nm to 100 nm.

(Light emitting layer 15)
The light emitting layer 15 includes a barrier layer 15a made of a gallium nitride-based compound semiconductor and a well layer 15b made of a gallium nitride-based compound semiconductor containing indium, which are alternately stacked. The barrier layers 15a are stacked in the order in which the barrier layers 15a are arranged on the type semiconductor layer 16 side. In the present embodiment, the light emitting layer 15 includes six barrier layers 15a and five well layers 15b that are alternately and repeatedly stacked, and the barrier layer 15a is disposed on the uppermost layer and the lowermost layer of the light emitting layer 15, A well layer 15b is arranged between the barrier layers 15a.

The barrier layer 15a, for example, the well layer 15b larger bandgap energy _{A1 c Ga 1-c N (} 0 ≦ c ≦ 0.3) than that of a gallium nitride-based compound semiconductor containing indium gallium nitride, such as A compound semiconductor can be suitably used.
Furthermore, the well layer 15b can be formed using indium as the semiconductor gallium nitride-based compound containing, for _example, can be used _{Ga 1-s In s N (} 0 <s <0.4) GaN such as indium.
The film thickness of the well layer 15b is not particularly limited, but is preferably a film thickness at which a quantum effect can be obtained, that is, a critical film thickness region. For example, the thickness of the well layer 15b is preferably in the range of 1 nm to 10 nm, and more preferably 2 nm to 6 nm.

(P-type semiconductor layer 16)
The p-type semiconductor layer 16 includes a p-type cladding layer 16a and a p-type contact layer 16b. As the p-type cladding layer 16a, preferably, one having A1 _d Ga _1-d N (0 <d ≦ 0.4) is mentioned. The film thickness of the p-type cladding layer 16a is preferably 1 nm to 400 nm, more preferably 5 nm to 100 nm.
The a p-type contact layer 16b, at least _{A1 e Ga 1-e N (} 0 ≦ e <0.5) comprising gallium nitride-based compound semiconductor layer. The film thickness of the p-type contact layer 16b is not particularly limited, but is preferably 10 nm to 500 nm, and more preferably 50 nm to 200 nm.

(Translucent positive electrode 17)
Examples of the material constituting the translucent positive electrode 17 include ITO (In ₂ O ₃ —SnO ₂ ), AZO (ZnO—Al ₂ O ₃ ), IZO (In ₂ O ₃ —ZnO), and GZO (ZnO—Ga). Conventionally known materials such as ₂ O ₃ ) can be mentioned. Moreover, the structure of the translucent positive electrode 17 is not specifically limited, A conventionally well-known structure is employable. The translucent positive electrode 17 may be formed so as to cover almost the entire surface on the p-type semiconductor layer 16, or may be formed in a lattice shape or a tree shape.

(Positive electrode bonding pad 18)
The positive electrode bonding pad 18 as an electrode formed on the translucent positive electrode 17 is made of, for example, a conventionally known material such as Au, Al, Ni, or Cu. The structure of the positive electrode bonding pad 18 is not particularly limited, and a conventionally known structure can be adopted.
The thickness of the positive electrode bonding pad 18 is in the range of 100 nm to 1000 nm, preferably in the range of 300 nm to 500 nm.

(Negative electrode 19)
As shown in FIG. 1, the negative electrode 19 includes a compound semiconductor layer 20 (n-type semiconductor layer 14, light emitting layer 15, and p) further formed on the intermediate layer 12 and the base layer 13 formed on the substrate 11. The n-type semiconductor layer 16) is formed so as to be in contact with the n-type contact layer 14a of the n-type semiconductor layer 14. Therefore, when forming the negative electrode 19, the p-type semiconductor layer 16, the light emitting layer 15, and the n-type semiconductor layer 14 are partially removed to form an exposed region 14 d of the n-type contact layer 14 a, and the negative electrode is formed thereon. 19 is formed.
As the material of the negative electrode 19, negative electrodes having various compositions and structures are well known, and these known negative electrodes can be used without any limitation, and can be provided by conventional means well known in this technical field.

(Manufacturing method of semiconductor light emitting device)
In the present embodiment, the semiconductor light emitting device 1 usually forms the compound semiconductor layer 20 on the substrate 11 (semiconductor layer forming step), and then grinds the substrate 11 to a predetermined thickness, It is formed by cutting into an appropriate size.
First, on a sapphire substrate 11 having a predetermined diameter D and thickness d, a gas containing a group V element and a metal material are activated and reacted with plasma to cause an intermediate layer 12 made of a group III nitride. Is deposited. Subsequently, the base layer 13, the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are sequentially stacked on the formed intermediate layer 12.

In this Embodiment, the diameter D of the board | substrate 11 used when forming the compound semiconductor layer 20 into a film is normally selected from the range of 50 mm-155 mm. The thickness d of the substrate 11 is usually selected from the range of 0.4 mm to 1.5 mm, preferably 0.4 mm to 1.2 mm.
At this time, it is preferable that the substrate 11 to be used has a warpage amount H selected from the ranges of 0 <H ≦ 30 μm and −30 μm ≦ H <0. Further, it is preferable that the warpage amount H of the substrate 11 is selected from the range of −10 μm <H <0.
In the present embodiment, particularly when the diameter D of the substrate 11 is about 50 mm to 51 mm (about 2 inches), the warpage amount H of the substrate 11 is selected from the ranges of 0 <H ≦ 30 μm and −30 μm ≦ H <0. It is preferable that Further, when the diameter D of the substrate 11 is about 100 mm to 102 mm (about 4 inches), the warp amount H of the substrate 11 is preferably selected from the range of −10 μm <H <0.

  Here, the warpage of the substrate is defined as the difference between the maximum value and the minimum value of the distance between the reference surface and the wafer surface when the substrate is placed on a horizontal reference surface. In the present application, the amount of warpage H of the substrate 11 was measured by measuring the SORI value with a laser beam oblique incidence interferometer (flatness tester FT-17) manufactured by NIDEK. A positive value is used when the warping direction is convex, and a negative value is used when the direction of warping is concave.

Next, in the present embodiment, the diameter D and the thickness d of the substrate 11 used when forming the compound semiconductor layer 20 satisfy the relationship of the following formula (1).
0.7 × 10 ² ≦ (D / d) ≦ 1.5 × 10 ² (1)
In the present embodiment, when the compound semiconductor layer 20 is formed over the substrate 11 made of a material different from the material constituting the compound semiconductor layer 20, the relationship between the diameter D and the thickness d satisfies the above formula (1). By selecting such a substrate 11, a compound semiconductor wafer having a small wavelength distribution σ of emission wavelength can be manufactured without being affected by a plurality of processes in the manufacturing process. Here, the compound semiconductor wafer is obtained by forming the compound semiconductor layer 20 on the substrate 11.
Here, when the ratio (D / d) of the diameter D of the substrate 11 to the thickness d of the substrate 11 used when forming the compound semiconductor layer 20 is excessively small, the wavelength distribution σ of the emission wavelength varies. However, since the amount of raw material used for the substrate 11 itself increases, the cost of the substrate 11 increases. Furthermore, the amount of grinding increases due to the grinding process of the substrate 11 to be described later, so that the throughput tends to deteriorate.
On the other hand, if (D / d) is excessively large, the amount of warpage of the compound semiconductor wafer increases, so that the wavelength distribution σ of the emission wavelength increases, and the yield of the semiconductor light emitting device 1 tends to decrease. Furthermore, even if the variation in the thickness d of the substrate 11 is within the thickness tolerance, the wavelength distribution σ of the emission wavelength varies, making it difficult to manufacture a stable compound semiconductor wafer. In addition, when the amount of warpage of the compound semiconductor wafer increases, in the process of manufacturing the semiconductor light emitting device 1, exposure failure of the photoresist, robot transport error, unstable measurement of electrical characteristics by the probe, and unstable focusing during laser processing. It becomes a factor of yield reduction. In this case, there is a method of managing the thickness tolerance of the substrate 11 narrowly, but it becomes very difficult to manufacture the substrate 11, which causes an increase in cost.

  In the present embodiment, when the group III nitride semiconductor crystal is epitaxially grown on the substrate 11 described above, the intermediate layer 12 is formed on the substrate 11 by a sputtering method to react and react with the raw material. It is preferable (intermediate layer forming step). Here, the group V element is nitrogen, the nitrogen gas fraction in the gas when forming the intermediate layer 12 is in the range of 50% to 99% or less, and the intermediate layer 12 is formed as a single crystal structure. . Thereby, the intermediate layer 12 having good crystallinity can be formed on the substrate 11 as an alignment film having specific anisotropy in a short time. As a result, a group III nitride semiconductor with good crystallinity can be efficiently grown on the intermediate layer 12.

In the present embodiment, after the intermediate layer 12 is formed by sputtering, an underlayer 13, an n-type semiconductor layer 14, a light-emitting layer 15, and a p-type semiconductor are formed thereon by metal organic chemical vapor deposition (MOCVD). Layer 16 is preferably deposited sequentially.
In the MOCVD method, hydrogen (H ₂ ) or nitrogen (N ₂ ) is used as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) is used as a Ga source as a group III source, trimethyl aluminum (TMA) or triethyl aluminum is used as an Al source. (TEA), trimethylindium (TMI) or triethylindium (TEI) as an In source, ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like as an N source that is a group V material.
As the dopant, for n-type, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) as a Si raw material, germanium gas (GeH ₄ ), tetramethyl germanium ((CH ₃ ) ₄ Ge), tetraethyl germanium (Ge) as a Ge raw material An organic germanium compound such as (C ₂ H ₅ ) ₄ Ge) can be used.

  The gallium nitride-based compound semiconductor can be configured to contain other group III elements in addition to Al, Ga, and In, and Ge, Si, Mg, Ca, Zn, Be, and the like as necessary. The dopant element can be contained. Furthermore, it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.

  In addition, after forming the base layer 13 in the compound semiconductor layer 20 by the MOCVD method, each layer of the n-type contact layer 14a and the n-type cladding layer 14b is formed by the sputtering method, and the light emitting layer 15 thereon is formed by the MOCVD method. The p-type cladding layer 16a and the p-type contact layer 16b constituting the p-type semiconductor layer 16 may be formed by reactive sputtering.

After the intermediate layer 12, the base layer 13, and the compound semiconductor layer 20 are formed on the substrate 11 having the diameter D and the thickness d described above, the translucent positive electrode 17 is formed on the p-type semiconductor layer 16 of the compound semiconductor layer 20. The positive electrode bonding pad 18 is formed thereon. Further, a wafer in which the negative electrode 19 is provided in the exposed region 14d formed in the n-type contact layer 14a of the n-type semiconductor layer 14 is formed.
Thereafter, the surface to be ground of the substrate 11 is ground and polished until it reaches a predetermined thickness. In the present embodiment, the wafer substrate 11 is ground by a grinding process of about 20 minutes, and the thickness of the substrate 11 is reduced from about 900 μm to about 120 μm, for example. Furthermore, in this embodiment, the thickness of the substrate 11 is polished from about 120 μm to about 80 μm by a polishing process for about 15 minutes following the grinding process.
Next, the wafer in which the thickness of the substrate 11 is adjusted is cut into a square of 350 μm square, for example, so that the intermediate layer 12, the base layer 13, and the compound semiconductor layer 20 are formed on the substrate 11. 1 is formed.

Hereinafter, the present invention will be described in more detail based on examples. However, the present invention is not limited to the following examples unless it exceeds the gist.
Evaluation methods of the warpage amount H of the sapphire substrate used in the examples and the emission wavelength distribution (wavelength distribution σ) obtained from the compound semiconductor wafer are as follows.

(1) Warpage amount H of sapphire substrate
The amount of warpage H of the sapphire substrate was evaluated based on the SORI value measured with a laser beam oblique incidence interferometer (manufactured by Nidec Co., Ltd .: Flatness Tester FT-17). The SORI value was measured in a state where the sapphire substrate was attracted to a bow tester of a flatness tester and tilted 8 degrees from the vertical to the near side. The measurement was performed in a range excluding the outer periphery of 1 mm of the sapphire substrate (inside value of 1 mm).

(2) Distribution of emission wavelength obtained from compound semiconductor wafer (wavelength distribution σ)
The measurement of the wavelength distribution σ of the emission wavelength is not limited in the present invention, but it can be preferably performed using a PL mapper (manufactured by ACCENT: RPM-Σ).

(Examples 1-9 and comparative examples)
A sapphire substrate 11 having a diameter D and a thickness d shown in Table 1 is used, and as shown in FIG. 1, an intermediate layer 12 made of AlN is formed on the substrate 11 by a sputtering method to a thickness of 0.05 μm. A wafer on which an underlayer 13 made of undoped GaN having a thickness of 8 μm and an n-type contact layer 14a made of Si-doped GaN having a thickness of 2 μm were formed by metal organic chemical vapor deposition (MOCVD). Created. Further, an n-type cladding layer 14b made of In _0.1 Ga _0.9 N having a thickness of 250 nm is formed thereon by MOCVD, and then a barrier layer 15a made of Si-doped GaN having a thickness of 16 nm and a thickness of 2. A well layer 15b made of 5 nm of In _0.2 Ga _0.8 N was stacked five times, and finally a light emitting layer 15 having a multiple quantum well structure in which a barrier layer 15a was provided was formed.
Further, a p-type cladding layer 16a made of Mg-doped Al _0.07 Ga _0.93 N having a thickness of 10 nm and a p-type contact layer 16b made of Mg-doped GaN having a thickness of 150 nm were sequentially formed.
The gallium nitride-based compound semiconductor layer was laminated by MOCVD under normal conditions well known in the technical field.
Thereafter, the wavelength distribution σ was measured by the above-mentioned PL mapper (manufactured by ACCENT: RPM-Σ), and the results shown in Table 1 were obtained.
Next, a light-transmitting positive electrode 17 made of IZO having a thickness of 250 nm is formed on the p-type contact layer 16b made of GaN, and then a protective film made of SiO ₂ is well-known in the art. A chip for a light emitting device was manufactured under normal conditions.

From the results shown in Table 1, the substrate 11 in which the diameter D and the thickness d satisfy the relationship of the formula (1) described above and the warpage amount H is in the range of ± 30 μm is used, and the total amount on the substrate 11 is It can be seen that the compound semiconductor wafers (Examples 1 to 9) prepared by forming the compound semiconductor layer 20 having a thickness of 8 μm or more (10 μm) show favorable numerical values of the wavelength distribution σ of the emission wavelength of 5 nm or less. .
In this case, for example, the wavelength distribution of the emission wavelength is greater in the case of the concave shape (Examples 4 and 5) than in the case of the convex shape (Examples 6 and 7) of the substrate 11 having a substrate diameter D of 100 mm. σ tends to be better.
Further, the smaller the D / d value, the better the wavelength distribution σ of the emission wavelength tends to be better. In particular, it is remarkable when compared at the same diameter (comparison between Examples 1 and 2, comparison between Examples 3 and 4, and comparison between Examples 8 and 9).
As a comparative example, even when the amount of warpage H is in the range of ± 30 μm, the wavelength distribution was greatly disturbed so that it could not be measured when the relationship of the above-described formula (1) was not satisfied.

It is a figure explaining an example of the semiconductor light emitting element manufactured in this Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light emitting element, 11 ... Substrate, 12 ... Intermediate layer, 13 ... Underlayer, 14 ... N-type semiconductor layer, 15 ... Light emitting layer, 16 ... P-type semiconductor layer, 17 ... Translucent positive electrode, 18 ... Positive electrode bonding Pad, 19 ... negative electrode, 20 ... compound semiconductor layer (group III compound semiconductor layer)

Claims (12)

A method of manufacturing a semiconductor light emitting device having a group III compound semiconductor layer,
A semiconductor layer forming step of forming a group III compound semiconductor layer having a total thickness of 8 μm or more on a substrate having a warpage amount H of ± 30 μm and a diameter D and a thickness d;
The method for manufacturing a semiconductor light emitting element, wherein the diameter D and the thickness d of the substrate satisfy a relationship of the following formula (1).
0.7 × 10 ² ≦ (D / d) ≦ 1.5 × 10 ² (1)   The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the group III compound semiconductor layer contains a group III nitride.   The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the diameter D of the substrate is selected from a range of 50 mm to 155 mm.   4. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the thickness d of the substrate is selected from a range of 0.4 mm to 1.5 mm. 5.   5. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the warpage amount H of the substrate is selected from the ranges of 0 <H ≦ 30 μm and −30 μm ≦ H <0.   6. The method for manufacturing a semiconductor light emitting element according to claim 1, wherein a warpage amount H of the substrate is selected from a range of −10 μm <H <0.   When the diameter D of the substrate is 50 mm to 51 mm, the warpage amount H of the substrate is selected from the range of 0 <H ≦ 30 μm and −30 μm ≦ H <0, and the diameter D of the substrate is 100 mm to 102 mm. 7. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the warpage amount H of the substrate is selected from a range of −10 μm <H <0.   The method for manufacturing a semiconductor light-emitting element according to claim 1, wherein the substrate is made of a material different from that of the group III compound semiconductor.   The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the substrate is made of sapphire.   10. The semiconductor light emitting device according to claim 1, further comprising an intermediate layer forming step of forming an intermediate layer between the substrate and the group III compound semiconductor layer by a sputtering method. Manufacturing method.   11. The group III compound semiconductor layer is formed by stacking a base layer, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer in order on the substrate. The manufacturing method of the semiconductor light-emitting device of description.   The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the group III compound semiconductor layer is formed on the substrate by metal organic chemical vapor deposition.

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