JP2010087601A - Sound signal processing circuit - Google Patents

Abstract

An audio signal processing circuit capable of setting audio signal processing without necessarily using a microcomputer is provided.
An audio signal processing circuit receives a clock signal and setting data corresponding to the clock signal, holds a setting data, and at least one of a first audio signal and a second audio signal input in parallel. When one of the signals is input to the processing circuit that performs processing based on the setting data of the holding circuit and the first output instruction signal, the clock signal from the control circuit is output to the holding circuit, and the second output instruction When a signal is input, a clock signal output circuit that outputs a clock signal to the holding circuit based on the first audio signal, and when a first output instruction signal is input, setting data from the control circuit is output to the holding circuit And a setting data output circuit for outputting setting data to the holding circuit based on the second audio signal when the second output instruction signal is input.
[Selection] Figure 1

Description

  The present invention relates to an audio signal processing circuit.

  In recent years, an FM (Frequency Modulation) transmission circuit has been used to play music data stored in a portable music playback device or the like, for example, with a car stereo (see, for example, Patent Document 1 or Patent Document 2).

FIG. 8 shows an example of a configuration of a transmission apparatus 200 using the FM transmission circuit 300 for transmitting an audio signal. The frequency of the carrier wave in the FM transmitter circuit 300 needs to be determined in consideration of the frequency of FM radio or the like used in the vicinity in order to avoid interference. Therefore, first, the user needs to set the frequency of the carrier wave in the FM transmitter circuit 300. Specifically, the user operates a key (not shown) of the setting device 310 so that the frequency of the carrier wave displayed on the display screen (not shown) of the setting device 310 becomes a desired frequency. Further, when the carrier frequency is determined, the user operates a key (not shown) of setting device 310 so that the carrier frequency data is output to microcomputer 320. The microcomputer 320 outputs the frequency data from the setting device 310 to the FM transmission circuit 300 as serial data SDA synchronized with the clock signal SCL. The FM transmitter circuit 300 generates a stereo composite signal based on the audio signals RIN and LIN input from the music playback device 330 and a carrier wave having a frequency based on the serial data SDA input from the microcomputer 320, and the carrier wave is stereo. By modulating with the composite signal, an output signal OUT is output to an antenna (not shown). The resistors 400 and 410 are pull-up resistors for the clock signal SCL and serial data SDA, respectively.
JP 2006-262521 A JP 2007-88657 A

  In the transmission device 200 described above, in addition to the FM transmission circuit 300, a setting device 310 and a microcomputer 320 for setting the frequency of the carrier wave in the FM transmission circuit 300 are necessary. In general, the setting device 310 includes a display screen (not shown) for displaying the frequency of a carrier wave, a drive circuit for driving the display screen, and the like, and the microcomputer 320 is configured on a separate chip from the FM transmitter circuit 300. Further, in the general transmission apparatus 200, for example, when the user sets the transmission power of the FM transmission circuit 300, the microcomputer 320 is necessarily required as in the case where the frequency of the carrier wave is set.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an audio signal processing circuit capable of setting audio signal processing without necessarily using a microcomputer.

  In order to achieve the above object, an audio signal processing circuit according to one aspect of the present invention receives a clock signal and setting data corresponding to the clock signal, and is input in parallel with a holding circuit that holds the setting data. A processing circuit that performs processing based on the setting data of the holding circuit with respect to at least one of the first audio signal and the second audio signal, and a control circuit that outputs the clock signal and the setting data. The clock signal and the first audio signal corresponding to the clock signal can be input, and when the first output instruction signal is input, the clock signal from the control circuit is output to the holding circuit. A clock signal output circuit for outputting the clock signal to the holding circuit based on the first audio signal when the second output instruction signal is input; and the control circuit. And the second audio signal corresponding to the setting data can be input. When the first output instruction signal is input, the setting data from the control circuit is input to the holding circuit. And a setting data output circuit that outputs the setting data to the holding circuit based on the second audio signal when the second output instruction signal is input.

  An audio signal processing circuit capable of setting audio signal processing without necessarily using a microcomputer can be provided.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

  FIG. 1 is a diagram showing a configuration of an FM transmitter circuit 10 according to an embodiment of the present invention. The FM transmission circuit 10 is a circuit for transmitting audio signals RIN (first audio signal) and LIN (second audio signal) input from the music playback device 20 to, for example, a car stereo (not shown). In the present embodiment, the audio signals RIN and LIN correspond to the right audio signal and the left audio signal of the stereo audio signals, respectively, and the FM transmitter circuit 10 is an integrated circuit. Although details will be described later, the FM transmitter circuit 10 of this embodiment performs FM transmission based on either the audio signals RIN and LIN from the music playback device 20 or the clock signal SCLK2 and the data SDA2 from the microcomputer 23. It is assumed that settings are made for processing of audio signals RIN and LIN input to the circuit 10.

  First, the outline of each circuit constituting the FM transmitter circuit 10 will be described. The FM transmitter circuit 10 (audio signal processing circuit) includes audio signal amplifier circuits 30 and 31, selection circuits (SEL) 32 and 33, a first setting circuit 40, an output circuit 41, and terminals 80 to 85.

  The audio signal amplifier circuit 30 (first amplifier circuit) amplifies the audio signal RIN input via the capacitor 21 and the terminal 80 to a logic level at which data held in a shift register 50 (to be described later) can be updated, and a clock signal It is a circuit that outputs as SCLK1.

  The audio signal amplifier circuit 31 (second amplifier circuit) amplifies the audio signal LIN input via the capacitor 22 and the terminal 81 to a logic level at which data held in the shift register 50 can be updated, and outputs the amplified data as data SDA1. Circuit. Although details will be described later, in the present embodiment, the audio signal amplifier circuit 31 has the same configuration as the audio signal amplifier circuit 30 except that the audio signal LIN is input via the capacitor 22 and the terminal 81. And

  The selection circuit (first selection circuit) 32, based on the logic level of the control signal CONT input via the terminal 84, the clock signal SCLK2 from the microcomputer 23 (control circuit) input via the terminal 82, This is a circuit that outputs one of the clock signal SCLK1 from the audio signal amplifier circuit 30 as the clock signal SCLK. Specifically, when the control signal CONT is at a high level (hereinafter, H level), the selection circuit 32 outputs the clock signal SCLK2 from the microcomputer 23 as the clock signal SCLK. On the other hand, when the control signal CONT is at a low level (hereinafter referred to as L level), the selection circuit 32 outputs the clock signal SCLK1 from the audio signal amplifier circuit 30 as the clock signal SCLK.

  The selection circuit (second selection circuit) 33 is based on the logic level of the control signal CONT input via the terminal 84, and the data SDA2 from the microcomputer 23 input via the terminal 83 and the audio signal amplification circuit 31. Is one of the data SDA1 and the data SDA. Specifically, when the control signal CONT is at the H level, the selection circuit 33 outputs the data SDA2 from the microcomputer 23 as the data SDA. On the other hand, when the control signal CONT is at the L level, the selection circuit 33 outputs the data SDA1 from the audio signal amplification circuit 31 as the data SDA. Note that the selection circuit 33 of this embodiment has the same configuration as the selection circuit 32. In addition, a switch 24 that can output either the power supply voltage VCC or the ground GND to the terminal 84 is connected to the terminal 84 in accordance with a user setting. Therefore, for example, when the switch 24 is set so that the output from the switch 24 becomes the power supply voltage VCC, the control signal CONT becomes H level. On the other hand, when the switch 24 is set so that the output from the switch 24 becomes the ground GND, the control signal CONT becomes L level. In this embodiment, the H level control signal CONT corresponds to the first output instruction signal of the present invention, and the L level control signal CONT corresponds to the second output instruction signal of the present invention. The audio signal amplifier circuit 30 and the selection circuit 32 correspond to the clock signal output circuit of the present invention, and the audio signal amplifier circuit 31 and the selection circuit 33 correspond to the setting data output circuit of the present invention.

  The first setting circuit 40 (holding circuit) supplies latch data LD for setting the frequency, level, and the like of the output signal OUT output from the FM transmitter circuit 10 to the output circuit 41 based on the clock signal SCLK and the data SDA. It is a circuit to output. The first setting circuit 40 includes a shift register 50, an address decoder 51, and a latch circuit 52.

  The output circuit 41 (processing circuit) is based on the audio signals RIN and LIN input from the music playback device 20 via the capacitors 21 and 22 and the terminals 80 and 81, and the latch data LD input from the first setting circuit 40. This is a circuit that performs the above processing. The audio signals RIN and LIN are subjected to processing such as modulation and amplification so that they can be received by a car stereo (not shown), for example, and output as an output signal OUT from an antenna (not shown) connected to the terminal 85. Is done. The output circuit 41 includes a second setting circuit 60, a stereo modulation circuit 61, a frequency modulation circuit 62, and a power amplifier 63.

Next, details of each circuit constituting the FM transmitter circuit 10 will be described.
As shown in FIG. 2, the audio signal amplifying circuit 30 includes resistors 100 and 101, voltage sources 110 and 111, a bias current source 112, NPN transistors 120 to 123, and PNP transistors 130 to 133.

  The other end of the capacitor 21 to which the audio signal RIN is input at one end is connected to one end of the resistor 100 and the base of the NPN transistor 120 via a terminal 80. The other end of the resistor 100 is connected to a voltage source 110 that generates a predetermined level of voltage V1. In this embodiment, since the base current of the NPN transistor 120 is designed to be sufficiently small, the current flowing from the capacitor 21 via the terminal 80 flows to the resistor 100 and the voltage source 110. Therefore, the audio signal RIN input to the capacitor 21 is generated at a node where the DC level is shifted to the voltage V1 and the terminal 80 and one end of the resistor 100 are connected. That is, the resistor 100 and the voltage source 110 are a level shift circuit that shifts the DC level of the audio signal RIN to the voltage V1. In the present embodiment, the audio signal RIN whose DC level is level-shifted to the voltage V1 is referred to as an audio signal RIN1.

  One end of the resistor 101 is connected to the base of the NPN transistor 121, and the other end of the resistor 101 is connected to the voltage source 111 that generates the voltage V2. In the present embodiment, since the base current of the NPN transistor 121 is designed to be sufficiently small, the voltage V <b> 2 is a voltage applied to the base of the NPN transistor 121. Note that the voltage V2 in this embodiment is lower than the voltage V1.

  The bias current source 112, the NPN transistors 120 to 123, and the PNP transistors 130 to 133 constitute a comparator. More specifically, when the base voltage of the NPN transistor 120 is higher than the base voltage of the NPN transistor 121, the NPN transistor 120 is turned on and the NPN transistor 121 is turned off. Therefore, the current I1 of the bias current source 112 flows through the diode-connected PNP transistor 130. On the other hand, the diode-connected PNP transistor 131 is turned off. The PNP transistor 130 and the PNP transistor 132 of this embodiment constitute a current mirror circuit having an equal size ratio. Therefore, the PNP transistor 132 supplies the current I1 to the diode-connected NPN transistor 122. Since the base voltage of the diode-connected NPN transistor 122 and the base voltage of the NPN transistor 123 are common, the NPN transistor 123 is turned on. Also, the PNP transistors 131 and 133 constitute a current mirror circuit having the same size ratio as the PNP transistors 130 and 132. For this reason, the PNP transistor 133 is turned off in the same manner as the PNP transistor 131. Therefore, the clock signal SCLK1 output from the node to which the collector of the NPN transistor 123 and the collector of the PNP transistor 133 are connected is at a low level (hereinafter, L level).

  On the other hand, when the base voltage of the NPN transistor 120 is lower than the base voltage of the NPN transistor 121, the NPN transistor 120 is turned off and the NPN transistor 121 is turned on. Therefore, the PNP transistor 130 is turned off and the PNP transistor 131 is turned on, so that the current I1 flows through the PNP transistor 131. When the PNP transistor 130 is turned off, the PNP transistor 132 is also turned off. As a result, the NPN transistors 122 and 123 are also turned off. Further, when the PNP transistor 131 is turned on, the PNP transistor 133 is turned on. As a result, contrary to the above, the clock signal SCLK1 becomes high level (hereinafter, H level).

  Here, an example of the operation of the audio signal amplifier circuit 30 when the audio signal RIN is output from the music playback device 20 will be described with reference to FIG. Here, it is assumed that the audio signal RIN is output from the music playback device 20 from time T0 to time T1. Furthermore, in this embodiment, the audio signal RIN is output from the music playback device 20 with a predetermined amplitude, and the voltage V2 is set so that the voltage V2 falls within the amplitude range of the level-shifted audio signal RIN1. I will do it. As described above, since the voltage V2 is set lower than the voltage V1, the clock signal SCLK1 becomes L level before the time T0 when the audio signal RIN is output. When the audio signal RIN is input between time T0 and time T1, the audio signal RIN1 whose DC level is level-shifted to the voltage V1 is generated. Therefore, when the level of the audio signal RIN1 is higher than the voltage V2, the clock signal SCLK1 becomes L level, and when the level of the audio signal RIN1 is lower than the voltage V2, the clock signal SCLK1 becomes H level. That is, when the audio signal RIN is output, the audio signal amplifier circuit 30 amplifies and inverts the audio signal RIN having a predetermined amplitude, and outputs a clock signal SCLK1 having a logic level at which the amplitude becomes the power supply voltage VCC. .

  The audio signal amplifier circuit 31 has the same configuration as the audio signal amplifier circuit 30 except that the audio signal LIN is input via the capacitor 22 and the terminal 81, and the resistors 100, 101, The voltage sources 110 and 111, the bias current source 112, NPN transistors 120 to 123, and PNP transistors 130 to 133 are included. Therefore, the audio signal amplifying circuit 31 amplifies and inverts the audio signal LIN output from the music playback device 20, and outputs logic level data SDA1.

  A selection circuit 32A, which is a first embodiment of the selection circuit 32, is shown in FIG.

  The selection circuit 32A includes NMOS transistors 140 and 141, PMOS transistors 150 and 151, and an inverter 160. The NMOS transistor 140 and the PMOS transistor 150, and the NMOS transistor 141 and the PMOS transistor 151 respectively constitute a transmission gate circuit. Further, the control signal CONT is applied to the gates of the NMOS transistor 140 and the PMOS transistor 151, and the output of the inverter 160, which has inverted the logic level of the control signal CONT, is applied to the gates of the NMOS transistor 141 and the PMOS transistor 150. Therefore, when the control signal CONT is at the H level, the transmission gate circuit composed of the NMOS transistor 140 and the PMOS transistor 150 is turned on, and the transmission gate circuit composed of the NMOS transistor 141 and the PMOS transistor 151 is turned off. As a result, the clock signal SCLK2 is output as the clock signal SCLK from the selection circuit 32A. On the other hand, when the control signal CONT is at the L level, the transmission gate circuit composed of the NMOS transistor 140 and the PMOS transistor 150 is turned off and the transmission gate circuit composed of the NMOS transistor 141 and the PMOS transistor 151 is turned on contrary to the case described above. . Therefore, the clock signal SCLK1 is output as the clock signal SCLK from the selection circuit 32A.

  A selection circuit 32B, which is a second embodiment of the selection circuit 32, is shown in FIG.

  The selection circuit 32B includes NMOS transistors 170 to 173, PMOS transistors 180 to 183, and inverters 190 and 191. In the selection circuit 32B, the control signal CONT is applied to the gates of the NMOS transistor 173 and the PMOS transistor 180. The output of the inverter 190, which is the inverted logic level of the control signal CONT, is applied to the gates of the NMOS transistor 171 and the PMOS transistor 182. The NMOS transistor 170 and the PMOS transistor 181 and the NMOS transistor 172 and the PMOS transistor 183 constitute an inverter. Therefore, when the control signal CONT is at the H level, the NMOS transistor 173 and the PMOS transistor 182 are turned on, and the NMOS transistor 171 and the PMOS transistor 180 are turned off. Therefore, the clock signal SCLK2 is output as the clock signal SCLK from the selection circuit 32B. On the other hand, when the control signal CONT is at the L level, the NMOS transistor 173 and the PMOS transistor 182 are turned off, and the NMOS transistor 171 and the PMOS transistor 180 are turned on. Therefore, the clock signal SCLK1 is output as the clock signal SCLK from the selection circuit 32B.

  As described above, the selection circuit 33 has the same configuration as the selection circuit 32. Therefore, the selection circuit 33A, which is the first embodiment of the selection circuit 33, includes the NMOS transistors 140 and 141, the PMOS transistors 150 and 151, and the inverter 160, similarly to the selection circuit 32A. Therefore, when the control signal CONT is at the H level, the selection circuit 33A outputs the data SDA2 as the data SDA, and when the control signal CONT is at the L level, the data SDA1 is output as the data SDA.

  The selection circuit 33B according to the second embodiment of the selection circuit 33 includes NMOS transistors 170 to 173, PMOS transistors 180 to 183, and inverters 190 and 191 as in the selection circuit 32B. Therefore, when the control signal CONT is at the H level, the selection circuit 33B outputs the data SDA2 as the data SDA, and when the control signal CONT is at the L level, the selection data SDA1 is output as the data SDA.

  The shift register 50 in the first setting circuit 40 is an n-bit register, and is a circuit that sequentially shifts and holds the data SDA when the clock signal SCLK rises. The shift register 50 outputs n1 bit data input earlier in time among the held n bit data to the address decoder 51 as the address selection signal AO, and n2 bits input later in time. Is output to the latch circuit 52 as setting data DO.

  It is assumed that a predetermined address of n1 bits is allocated to the address decoder 51, and when the address selection signal AO matches the predetermined address, a decode signal DEC for updating the data held by the latch circuit 52 is Output to the latch circuit 52.

  When the decode signal DEC is output, the latch circuit 52 latches the n2-bit setting data DO output from the shift register 50 and outputs the setting data DO to the output circuit 41 as the latch data LD.

  The second setting circuit 60 in the output circuit 41 outputs predetermined n3 bit data out of the n2 bit latch data LD input from the latch circuit 52 to the stereo modulation circuit 61 as the first setting signal SET1. The n4 bit data is output to the frequency modulation circuit 62 as the second setting signal SET2, and the predetermined n5 bit data is output to the power amplifier 63 as the third setting signal SET3.

  The stereo modulation circuit 61 is a circuit that generates the stereo composite signal SO after setting the audio signals RIN and LIN input from the music playback device 20 to a level based on the n3 bit first setting signal SET1. Note that the stereo modulation circuit 61 of the present embodiment includes an attenuator (not shown) that can attenuate the levels of the audio signals RIN and LIN based on the first setting signal SET1 of n3 bits.

  The frequency modulation circuit 62 is a circuit that generates a carrier wave having a frequency based on the n4-bit second setting signal SET 2 and modulates the carrier wave with the stereo composite signal SO from the stereo modulation circuit 61. In the present embodiment, the carrier wave modulated by the stereo composite signal SO is the modulation signal MOD.

  The power amplifier 63 is a circuit that amplifies the power of the modulation signal MOD with an amplification factor based on the third setting signal SET3 of n5 bits, and outputs it as an output signal OUT from an antenna (not shown) connected to the terminal 85.

  In the present embodiment, as described above, the configuration of each of the stereo modulation circuit 61, the frequency modulation circuit 62, and the power amplifier 63 can be set, but every time the latch data LD is updated. It is not necessary to change the state of all circuits. That is, it is possible to change the state of one or two of the stereo modulation circuit 61, the frequency modulation circuit 62, and the power amplifier 63. Specifically, for example, when only the amplification factor in the power amplifier 63 is changed, n3 bits of data for the first setting signal SET and n4 for the second setting signal SET2 among the already held latch data LD. Data in which only the n5 bit data for the third setting signal SET3 is changed without being changed to the bit data may be updated to the latch circuit 52 as new latch data LD.

<< Operation of FM transmitter circuit 10 when control signal CONT is at L level >>
First, when the control signal CONT is at L level, that is, the user performs setting for processing of the audio signals RIN and LIN input to the FM transmitter circuit 10 based on the audio signals RIN and LIN from the music playback device 20. The operation of the FM transmitter circuit 10 when it is selected to do will be described.

  Here, it is assumed that the selection circuits 32A and 33A of the first embodiment are used in the FM transmitter circuit 10, and the switch 24 is set so that the terminal 84 is connected to the ground GND. The shift register 50 has 10 bits, and among the data input to the shift register 50, 4 bits input earlier in time are the address selection signal AO, and 6 bits input later in time are the setting data DO. It will be explained as being. Of the 6-bit setting data DO, 2 bits input to the shift register 50 following the address selection signal AO are data for setting the attenuation amount of an attenuator (not shown), and the next 2 bits are the frequency of the carrier wave. And the last two bits are data for setting the amplification factor of the power amplifier 63.

  Further, the address assigned to the address decoder 51 is, for example, (1, 0, 1, 0), and is hereinafter referred to as first address data AD1 in the present embodiment. Further, data for a desired attenuation of an attenuator (not shown), for example, (1, 1), data for a desired frequency of a carrier wave, for example (0, 1), data for a desired amplification factor of the power amplifier 63, For example, it is assumed that (1,0). Therefore, in the present embodiment, in order for the desired data to be set in the stereo modulation circuit 61, the frequency modulation circuit 62, and the power amplifier 63, the first setting circuit 40 has the first setting circuit 40 when the clock signal SCLK rises. , Data (1, 0, 1, 0) and data (1, 1), (0, 1), (1, 0) need to be sequentially input to the shift register 50 as data SDA. In the present embodiment, data (1, 1), (0, 1), (1) sequentially input for making desired settings in each circuit of the stereo modulation circuit 61, the frequency modulation circuit 62, and the power amplifier 63. , 0) are collectively referred to as first data D1 (1, 1, 0, 1, 1, 0).

  Further, as described above, each of the audio signal amplifier circuits 30 and 31 amplifies and inverts the level-shifted audio signals RIN1 and LIN1, and outputs them as the clock signal SCLK1 and the data SDA1. Therefore, in order for the first address data AD1 and the first data D1 to be output as the data SDA1 from the audio signal amplifier circuits 30 and 31 at the rising edge of the clock signal SCLK, the first address data at the falling edge of the inverted clock signal SCLK1 Data obtained by inverting each bit of the data AD1 and the first data D1 needs to be input to the audio signal amplifier circuit 31 as the audio signal LIN. In this embodiment, data (0, 1, 0, 1) obtained by inverting each bit of the first address data AD1 is set as second address data AD2, and data (0, 0) obtained by inverting each bit of the first data D1. , 1, 0, 0, 1) is the second data D2. Further, in the music playback device 20 of the present embodiment, the second address data AD2 and the second data D2 are output as the audio signal LIN in synchronization with the falling of the predetermined clock signal output as the audio signal RIN. Suppose that a music file for setting is stored in advance.

  First, as shown in FIG. 6, the user operates the music playback device 20 to read and play the setting music file stored in the music playback device 20. As a result, the music playback device 20 outputs a predetermined clock signal as the audio signal RIN and the second address data AD2 and the second data D2 as the audio signal LIN, respectively. The audio signals RIN and LIN become the audio signals RIN1 and LIN1 whose DC levels are shifted to the voltage V1 as described above. The audio signal amplifier circuits 30 and 31 amplify, invert, and output the audio signals RIN1 and LIN1, respectively. Therefore, the audio signal amplifier circuit 30 outputs the clock signal SCLK1, and the audio signal amplifier circuit 31 outputs the first address data AD1 and the first data D1 as data SDA1 in synchronization with the rising edge of the clock signal SCLK1. The Rukoto. Since the control signal CONT is at the L level, the clock signals SCLK1 and data SDA1 are output as the clock signal SCLK and data SDA from the selection circuits 32A and 33A, respectively. Therefore, the first data D1 is sequentially input to the shift register 50 in the first setting circuit 40 following the first address data AD1. Since the first address data AD1 is set to match the address assigned to the address decoder 51, when all the first address data AD1 and the first data D1 are held in the shift register 50, the address decoder 51 The decode signal DEC is output. The shift register 50 outputs the first data D1 as setting data DO to the latch circuit 52. When the decode signal DEC is input, the latch circuit 52 outputs the first data D1 as the latch data LD of the output circuit 41. This is output to the second setting circuit 60. Therefore, the second setting circuit 60 sends the first setting signal SET1, the second setting signal SET2, and the third setting signal SET3 to the stereo modulation circuit 61, the frequency modulation circuit 62, and the power amplifier 63, respectively, based on the first data D1. Therefore, a desired state is set in each circuit described above. Then, the user selects a desired music file stored in the music playback device 20 and operates the music playback device 20 so that audio signals RIN and LIN based on the desired music file are output from the music playback device 20. To do. As a result, the output circuit 41 modulates a carrier wave having a desired frequency with the stereo composite signal SO corresponding to the audio signals RIN and LIN, and outputs an output signal OUT having a desired level to an antenna (not shown). . That is, the selected music file is reproduced by a car stereo (not shown). In general, the data SDA based on the audio signal LIN when the music file is reproduced matches the second address data AD2, and is input to the shift register 50 in synchronization with the clock signal SCLK output when the music file is reproduced. Is unlikely. Therefore, it is unlikely that the latch data LD is erroneously updated while the music file is being played. That is, the FM transmission circuit 10 of the present embodiment changes the setting only when the setting music file is reproduced.

  Although the case where the selection circuits 32A and 33A of the first embodiment are used has been described here, the first data D1 is similarly transferred to the shift register even if the selection circuits 32B and 33B of the second embodiment are used. 50 can be set.

<< Operation of FM transmitter circuit 10 when control signal CONT is at H level >>
Next, when the control signal CONT is at the H level, that is, the user performs setting for processing of the audio signals RIN and LIN input to the FM transmitter circuit 10 based on the clock signal SCLK2 and the data SDA2 from the microcomputer 23. The operation of the FM transmitter circuit 10 when it is selected to do will be described. Here again, it is assumed that the address assigned to the address decoder 51 is the first address data AD 1 described above, and desired for each of the stereo modulation circuit 61, frequency modulation circuit 62, and power amplifier 63 in the FM transmission circuit 10. This data is the first data D1 described above. In the FM transmitter circuit 10, the selection circuits 32A and 33A of the first embodiment are used.

  First, the user operates a setting device (not shown) in order to set the carrier frequency in the FM transmitter circuit 10 to a desired setting. Then, the user operates a setting device (not shown) so that the carrier frequency data and the like are transferred to the microcomputer 23. After the user operates a setting device (not shown) to transfer frequency data and the like, the microcomputer 23 synchronizes with the rising edge of the clock signal SCLK2 at a predetermined timing, and the first address data AD1 and the first data D1. Are sequentially output as data SDA2. Since the control signal CONT is at the H level, the clock signals SCLK2 and data SDA2 are output from the selection circuits 32A and 33A as the clock signal SCLK and data SDA, respectively. Therefore, the first data D1 is output to the second setting circuit 60 of the output circuit 41 as in the case where the control signal CONT is at the L level. As a result, a desired state is set in each of the stereo modulation circuit 61, the frequency modulation circuit 62, and the power amplifier 63, and the music file stored in the music playback device 20 can be played back by a car stereo (not shown). It becomes.

  Although the case where the selection circuits 32A and 33A of the first embodiment are used has been described here, the first data D1 is similarly applied when the selection circuits 32B and 33B of the second embodiment are used. Can be set in the shift register 50.

  When the control signal CONT is at the L level, the FM transmitter circuit 10 of the present embodiment having the configuration described above receives a predetermined clock signal as the audio signal RIN and the second address data AD2 as the audio signal LIN from the music playback device 20. Further, by inputting the second data D2, it is possible to set the attenuation amount of the audio signals RIN and LIN input to the FM transmitter circuit 10, the frequency of the carrier wave, and the amplification factor of the modulation signal MOD. Further, when the control signal CONT is at the H level, the FM transmission circuit 10 receives the clock signal SCLK2 and the data SDA2 including the first address data AD1 and the first data D1 from the microcomputer 23, thereby causing the FM transmission circuit 10 to 10, the attenuation amount of the audio signals RIN and LIN, the frequency of the carrier wave, and the amplification factor of the modulation signal MOD can be set. Generally, in order to set the above-described frequency and the like in the FM transmission circuit, a microcomputer is always required. In order to set the carrier frequency, for example, as described in Japanese Patent Application Laid-Open No. 2007-88657, a setting device for setting the carrier frequency, a display screen for displaying the carrier frequency (not shown) And a drive circuit for driving the display screen. In the FM transmitter circuit 10 of this embodiment, when the switch 24 is set so that the control signal CONT becomes L level, the setting for processing of the audio signals RIN and LIN based on the music file for setting from the music playback device 20 is performed. It is possible to Therefore, in this embodiment, it is not always necessary to use the microcomputer 23 in order to set the state of each circuit in the FM transmitter circuit 10. However, if the setting of the switch 24 is changed so that the control signal CONT becomes H level, the FM transmitter circuit 10 sets the processing for the audio signals RIN and LIN based on the clock signal SCLK2 and the data SDA2 from the microcomputer 23. Is possible. Therefore, for example, when the switch 24 is mounted on the board, the user connects the terminal 84 to either the power supply voltage VCC or the ground GND to set the processing of the audio signals RIN and LIN. Whether or not to use can be freely selected.

  The amplitude levels of the audio signals RIN and LIN output from the music playback device 20 differ depending on the music playback device 20 used by the user. The FM transmitter circuit 10 of the present embodiment is configured to include audio signal amplifier circuits 30 and 31 that amplify the levels of the audio signals RIN and LIN and output them as a clock signal SCLK1 and data SDA1, respectively. Therefore, for example, even when the amplitude levels of the audio signals RIN and LIN output from the music playback device 20 are small, the clock signals SCLK1 and data SDA1 that can reliably update the data held in the shift register 50 are output. Is possible. Further, when the control signal CONT is at the L level, the selection circuits 32 and 33 select the clock signal SCLK1 and the data SDA1 and output them to the shift register 50. On the other hand, when the control signal CONT is at the H level, the selection circuits 32 and 33 select the clock signal SCLK2 and the data SDA2 from the microcomputer 23 and output them to the shift register 50. By including such a circuit, the FM transmitter circuit 10 of the present embodiment can make settings for processing of the audio signals RIN and LIN without necessarily using the microcomputer 23.

  In addition, the said Example is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  The audio signal amplifier circuit 30 of the present embodiment is realized with the configuration shown in FIG. 2, but may be configured with an inverting amplifier circuit using a general operational amplifier, for example. When the audio signal amplifier circuit 30 is configured by an inverting amplifier circuit, the audio signal RIN is amplified even when a low level audio signal RIN is input by increasing the gain of the inverting amplifier circuit. A logic level clock signal SCLK is output.

  The output circuit 41 of the present embodiment is configured such that the attenuation amount of an attenuator (not shown) in the stereo modulation circuit 61, the frequency of the carrier wave in the frequency modulation circuit 62, and the amplification factor of the power amplifier 63 are set based on the latch data LD. However, it is not limited to this. For example, the output circuit 41 includes a bias current circuit (not shown) that supplies a bias current corresponding to the reference current to each circuit that configures the output circuit 41. Based on the latch data LD, the bias current circuit ( A reference current value (not shown) may be set. In this case, for example, when the second setting circuit 60 sets the reference current value to be zero based on the latch data LD, the current consumption of the output circuit 41 is suppressed. The second setting circuit 60 may be configured to change the stereo composite signal SO output from the stereo modulation circuit 61 from a stereo signal to a monaural signal based on the latch data LD.

  Further, the attenuator (not shown) of the stereo modulation circuit 61 according to the present embodiment attenuates both the levels of the input audio signals RIN and LIN based on the latch data LD. For example, the attenuator (not shown) The first attenuator (not shown) and the second attenuator (not shown) are provided so that the levels of the audio signals RIN and LIN can be attenuated, and two are provided based on the latch data LD. Only the attenuation amount of one of the attenuators may be changed.

It is a figure which shows the structure of FM transmission circuit 10 which is one Embodiment of this invention. 1 is a diagram illustrating an embodiment of audio signal amplifier circuits 30 and 31. FIG. 6 is a diagram for explaining the operation of the audio signal amplifier circuit 30. FIG. 3 is a diagram illustrating a first embodiment of selection circuits 32 and 33. FIG. FIG. 6 is a diagram illustrating a second embodiment of selection circuits 32 and 33. 6 is a diagram for explaining an example of the operation of the FM transmitter circuit 10. FIG. 6 is a diagram for explaining an example of the operation of the FM transmitter circuit 10. FIG. It is a figure which shows the structure of a transmitter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 FM transmission circuit 20 Music reproduction apparatus 21,22 Capacitor 30,31 Audio | voice signal amplification circuit 32,33 Selection circuit (SEL)
40 first setting circuit 41 output circuit 50 shift register 51 address decoder 52 latch circuit 60 second setting circuit 61 stereo modulation circuit 62 frequency modulation circuit 63 power amplifier 80 to 85 terminals 100, 101 resistors 110, 111 voltage source 112 bias current source 120 to 123 NPN transistor 130 to 133 PNP transistor 140, 141, 170 to 173 NMOS transistor 150, 151, 180 to 183 PMOS transistor 160, 190, 191 Inverter

Claims (2)

A holding circuit for receiving a clock signal and setting data corresponding to the clock signal and holding the setting data;
A processing circuit that performs processing based on the setting data of the holding circuit for at least one of the first audio signal and the second audio signal input in parallel;
The clock signal from the control circuit that outputs the clock signal and the setting data and the first audio signal corresponding to the clock signal can be input, and when the first output instruction signal is input, the control A clock signal output circuit that outputs the clock signal from the circuit to the holding circuit and outputs the clock signal to the holding circuit based on the first audio signal when a second output instruction signal is input;
The setting data from the control circuit and the second audio signal corresponding to the setting data can be input. When the first output instruction signal is input, the setting data from the control circuit is input to the setting data. A setting data output circuit that outputs the setting data to the holding circuit based on the second audio signal when the second output instruction signal is input to the holding circuit;
An audio signal processing circuit comprising: The audio signal processing circuit according to claim 1,
The clock signal output circuit includes:
A first amplifying circuit for amplifying the first audio signal according to the clock signal and outputting the amplified signal as the clock signal;
When the first output instruction signal is input, the clock signal from the control circuit is selected and output to the holding circuit, and when the second output instruction signal is input, the clock signal from the first amplifier circuit is selected. A first selection circuit that selects and outputs the clock signal to the holding circuit;
Including
The setting data output circuit includes:
A second amplifying circuit for amplifying the second audio signal according to the setting data and outputting as the setting data;
When the first output instruction signal is input, the setting data from the control circuit is selected and output to the holding circuit, and when the second output instruction signal is input, the setting signal from the second amplifier circuit is output. A second selection circuit that selects and outputs the setting data to the holding circuit;
An audio signal processing circuit comprising:

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