JP2010087379A - Color imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a color imaging device, reduced in crosstalk and not requiring an infrared-cutting filter. <P>SOLUTION: The color imaging device is provided with a first conduction type substrate 11, a second conduction type electric charge producing layer 12, laminated on the substrate and provided with the density of impurities of 1×10<SP>14</SP>cm<SP>-3</SP>to 1×10<SP>11</SP>cm<SP>-3</SP>, first conduction type surface embedded regions 13R, 13G, 13B buried into the upper part of the electric charge producing layer, second conduction type transmission channel forming wells 19R, 19G, 19B and amplifying circuit forming wells 18R, 18G, 18B, which are buried into the other one part of upper part of the electric charge producing layer to positions deeper than the lower surface of the surface embedded region so as to enclose the surface embedded region, and first conduction type electric charge detecting regions 16R, 16G, 16B which are buried into one part above the transmission channel forming well. In this case, the position of potential barrier generated in the electric charge producing layer is moved from the side of substrate to the side of surface embedded region in respective picture elements by impressing first and second electric potentials on the substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a color imaging apparatus, and more particularly to an amplification type solid-state imaging apparatus capable of color imaging having an amplifier circuit in a pixel portion.

  In general, as an amplification type solid-state imaging device, a device having a pixel portion having an amplification function and a scanning circuit arranged around the pixel portion, and reading out pixel data from the pixel portion by the scanning circuit is widely used. ing.

As a method of ensuring sensitivity in near infrared light and reducing crosstalk between pixels, proposals for forming an image sensor on a high resistance substrate have been proposed (see Patent Document 1 and Non-Patent Document 1). ). In Patent Document 1, a CCD image sensor is formed on a high-resistivity epilayer. In Non-Patent Document 2, a CMOS image sensor is formed on a p ^-- epi layer 312 having a high resistivity as shown in FIG. Formed.

In FIG. 22, a p ⁻ -epi layer having an extremely low impurity density of about 1 × 10 ¹² cm ⁻³ on a p ⁺ substrate 111 having a high impurity density of 1 × 10 ¹⁸ cm ⁻³ or more ( In the following, the p ⁻ -epi layer having an extremely low impurity density is referred to as a “π epi layer”.) 312 is formed so as to have a thickness g of about 20 μm, and the π epi layer 312 and the n-type surface buried region 113 are formed. And an embedded photodiode. One transfer transistor and a three-transistor amplifier circuit 117 are arranged in one pixel area to constitute a four-transistor pixel. As shown in FIG. 22, a p ⁺ pinning layer 114 is formed on the n-type surface buried region 113, and charges are transferred from the buried photodiode to the charge detection floating diffusion region 116 via the transfer gate electrode 115. Amplified by the amplifier circuit 117. Each of the three transistors constituting the amplifier circuit 117 includes a source region 152 and a drain region 153 provided on the p ⁺ well 118, and a gate electrode provided on the channel between the source region 152 and the drain region 153. 151. With this structure, if a reverse bias potential of about 1 V is applied to the n-type surface buried region 113 constituting the buried photodiode with respect to the π epi layer 312, in principle, the lower side of the buried photodiode is p ⁺ Even for infrared light that is depleted to near the substrate 111 and the light penetration depth exceeds 10 μm, the generated charge is led to the photodiode by the vertical electric field in the depletion layer and becomes effective sensitivity. It is predicted that the lateral spread will be suppressed and the crosstalk between pixels will be small.
US Pat. No. 6,608,337 J. et al. Janesick et al., “CMOS Minimal Array”, Proc. SPIE 6295, August 2006

  However, image sensors with increased infrared sensitivity have problems that are incompatible with color imaging. In a single-plate color imaging apparatus that performs color imaging using one image sensor, color filters 401R, 401G, and 401B are usually formed on each pixel to obtain color information as shown in FIG. In particular, there are many examples using three primary color filters 401R, 401G, 401B of red (R), green (G), and blue (B), and their spectral characteristics are generally as shown in FIG. As is clear from this, all the color filters 401R, 401G, and 401B transmit infrared light having a wavelength of 800 nm or more. For this reason, the infrared light component of the light source becomes an extra signal in each color information and is mixed, resulting in a decrease in saturation. In order for each of the color filters 401R, 401G, and 401B to transmit only the respective color components, it is essential to combine with an infrared cut filter (IRC) that cuts infrared light. Generally, as shown in FIG. An IRC that does not pass a wavelength of 650 nm or more is used. However, in such a color imaging system using IRC, even if the image sensor itself has high infrared sensitivity, infrared imaging cannot be performed.

  For this reason, as shown in FIG. 25, a method of inserting an IRC 63 provided with an attaching / detaching device 64 between the image sensor 61 and the imaging lens 62 is conceivable. That is, by inserting the IRC 63 in front of the image sensor 61 during color imaging and removing the IRC 63 from the front surface of the image sensor 61 during infrared imaging, good spectral characteristics can be obtained for both color imaging and infrared imaging. Here, the position of the IRC 63 may be the front surface of the imaging lens 62. However, this method requires a mechanism system including a driving device in the imaging system, and places a burden on the cost, size, reliability, and the like of the imaging system.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a color imaging apparatus that can reduce color crosstalk and can perform color imaging without using IRC.

In order to achieve the above object, according to an aspect of the present invention, there is provided a color imaging device in which color filters having different wavelength characteristics are arranged on a plurality of adjacent pixels, and each of the plurality of pixels includes: A substrate made of a semiconductor of the first conductivity type and having an impurity density of 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less; and (b) an impurity density of the second conductivity type provided on the substrate. A charge generation layer made of a semiconductor layer having a thickness of 1 × 10 ¹⁴ cm ⁻³ or less and 1 × 10 ¹¹ cm ⁻³ or more and a thickness of 10 μm or more and 50 μm or less, and (c) a charge generation layer over a part of the charge generation layer So as to function as a surface buried region composed of a first conductivity type semiconductor region buried so as to constitute a photoelectric conversion element, and (d) an inter-pixel separation region for electrically separating a plurality of pixels. Other part of the top of the charge generation layer below the surface buried region Transfer channel formation well and amplification with a second conductivity type and an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, embedded to a position deeper than the surface and surrounding the surface buried region on the planar pattern A circuit formation well, (e) a charge detection region made up of a first conductivity type semiconductor region embedded in a part of the transfer channel formation well, and (f) amplification. The gist of the invention is to include an amplifier circuit that is configured by using a part of the upper part of the circuit formation well and amplifies and reads out the potential of the charge detection region. The charge generation layer is a common layer of a plurality of pixels. By applying a first potential and a second potential higher than the first potential to the substrate, the charge generation layer of each pixel The position of the potential barrier generated inside is moved from the substrate side to the surface buried region side.

  According to the aspect of the present invention, the position of the potential peak formed in the charge generation layer corresponding to the optically effective depth is formed deep during infrared imaging to ensure high infrared sensitivity and low crosstalk. At the same time, the color peaks are formed with a shallow potential peak, resulting in low infrared sensitivity, and color mixing between color filters due to infrared sensitivity is prevented without using an optical filter that controls infrared light, and color reproduction is achieved. Sexuality is enhanced.

  According to the present invention, it is possible to provide a color imaging apparatus capable of performing color imaging without reducing crosstalk and using IRC.

  Next, first to third embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The first to third embodiments shown below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the technical scope described in the claims.

(First embodiment)
As shown in FIG. 1, the color imaging device (two-dimensional color image sensor) according to the first embodiment of the present invention has the same pixel array unit 1 and peripheral circuit units (2, 3, 4, 5). This is an amplification type solid-state imaging device integrated on a semiconductor chip. The pixel array unit 1 includes a red (R) pixel X _ij−1 , a green (G) pixel X _ij , and a blue (B) pixel X _{ij + 1} (i = 1 to m; j = 1 to 2) in a two-dimensional matrix. n: m is an arbitrary positive integer, and n is a positive integer that is a multiple of 3.) are periodically arranged. As shown in FIG. 3, the R pixel X _ij-1 red (R) color filter 31R, the on G pixel X _ij is green (G) color filter 31R, the B pixel X _{ij + 1} blue ( B) A color filter 31R is provided. In consideration of the convenience of displaying the cross-sectional view of FIG. 3, in FIG. 1, a three-color stripe system in which R, G, B color filters are periodically arranged in the row direction in the order of R, G, B. However, the present invention is not limited to this, and various color filter arrays as shown in FIGS. 19 to 21 can be adopted in addition to the Bayer method as shown in FIG.

A vertical shift register (vertical scanning circuit) 3 is provided on the left side of the pixel array unit 1 via a timing generation circuit 4, and a horizontal shift register (horizontal scanning circuit) 2 is provided on the lower side. A bias generation circuit 7 is provided on the lower side of the right side of 1. In FIG. 1, the internal structure is illustrated only for the pixel X _ij in the i row and the j column, but each pixel X _{11 to} X _1m ; X _{21 to} X _2m ;..; X _{i1 to} X _im ; ...; X _n1 ~X _nm, similar to the pixel X _ij of row i and column j, the detection circuit _{D 11 ~D 1m; D 21 ~D} 2m; ......; D i1 ~D im; ......; D n1 ~ D _nm and the amplifier (voltage read-out buffer _{amplifier) a 11 ~A 1m; a 21} ~A 2m; of a _n1 amplification type solid-state imaging device includes a _{~A nm; ......; a i1 ~A} im; ...... Constitutes a pixel. As shown in FIG. 3, the detection circuit D _ij (i = 1 to m; j = 1 to n: m and n are integers) is provided on the upper part of the substrate 11 made of semiconductor (silicon). A photoelectric conversion element (embedded photodiode) PD _ij and a charge transfer unit (transfer gate electrode) 15 are provided.

The pixel X _ij in the pixel array section 1 is sequentially scanned by the timing generation circuit 4, the vertical shift register (vertical scanning circuit) 3 driven by the timing generation circuit 4, and the horizontal shift register (horizontal scanning circuit) 2, and the pixel signal Reading and electronic shutter operation are executed. That is, in the color imaging apparatus according to the first embodiment of the present invention, the pixel array unit 1 is arranged in the pixel rows X _{11 to} X _1m ; X _{21 to} X _2m ;..; X _{i1 to} X _im ; by scanning in the vertical direction in X _n1 to X _nm units, each pixel row _{X 11 ~X 1m; X 21 ~X} 2m; ......; X i1 ~X im; ......; X n1 ~X nm pixel signal each pixel column _{X 11 ~X n1; X 12 ~X} n2; ......; X 1j ~X nj; ......; X 1m ~X amplification type solid-state image pickup for reading out the pixel signal by the vertical signal lines provided for each _nm It is the configuration of the device.

Signal readout from each pixel X _{11 to} X _1m ; X _{21 to} X _2m ; ......; X _{i1 to} X _im ; ......; X _{n1 to} X _nm is generally the same as that of a normal CMOS image sensor. in the lower part of the array 1 (output side), a plurality of column processing circuit _{Q 1, Q 2, ......,} Q j, ......, a _{Q m,} respectively pixel column _{X 11 ~X n1; X 12 ~X} n2 ; X _{1j to} X _nj ; ......; arranged corresponding to X _{1m to} X _nm to constitute the signal processing unit 5. The pixel signals of the pixel columns X _{11 to} X _n1 read out from the pixel array unit 1 by the vertical signal lines are sequentially input to the column processing circuit Q ₁ of the signal processing unit 5 and subjected to the pixel specific noise removal processing. The Similarly, the pixel signals of the pixel columns X _{12 to} X _n2 are sequentially input to the column processing circuit Q ₂ of the signal processing unit 5 and subjected to a process for removing pixel specific noise,..., And the pixel columns X _{1j to} X pixel signals _nj, the signal processing unit is sequentially input to the column processing circuit Q _j of 5, removal processing of the pixel-specific noise is performed. Further, the pixel signals of the pixel column X _{1 m} to X _nm, the signal processing unit is sequentially input to the column processing circuit Q _m of 5, removal processing of the pixel-specific noise is performed. That is, since each unit pixel X _ij of the pixel array unit 1 includes a characteristic error inherent to the MOS transistor or the like constituting the unit pixel X _ij , a video signal is formed as it is from the pixel signal read from each unit pixel X _ij. Then, the characteristic variation between the pixels X _ij affects the video signal and appears as noise in the image.

As shown in FIG. 1, a constant current transistor T _{LNj serving as} a common load is connected to the j-th column vertical signal line B _j of the pixel array unit 1, for example, an amplifying circuit A _{ij in the} i-th row and j-th column. And the constant current transistor T _LNj form a source follower circuit, and the output V _outj of the source follower circuit is read out to the column processing circuit Q _j . Although not shown, the vertical signal line of another row _{B 1, B 2, ......,} B j-1, B j + 1, ......, similarly to B _m, the common load constant Current transistors T _LN1 , T _LN2 ,..., T _LNj−1 , T _{LNj + 1} ,..., T _LNm are connected to form a source follower circuit, and outputs V _out1 , V _{out2 ,. ..., V outj-1, V} outj + 1, ......, V outm are each column processing circuit _{Q 1, Q 2, ......,} Q j-1, Q j + 1, ......, read the _{Q m} . Via a vertical signal line B _j, the vertical selection signal S _i to the high level of the i-th row to the gate electrode of the switching transistor TS _ij for pixel selection of the amplifier circuit A _ij (see FIG. _{5.) (S i = "} 1 )) _Is applied to make the switching transistor TS _ij conductive, and a constant voltage Vb is applied from the bias generation circuit 7 to the gate electrode of the constant current transistor T _LNj , whereby a signal read transistor (amplification transistor) The charges accumulated in the charge detection region 16 amplified by TA _ij (see FIG. 5) are read out of the pixel array unit 1 as the output V _outj of the source follower circuit. Although not shown, the output of the signal processing unit 5 is displayed in color through a white balance circuit, a saturation adjustment circuit, a gain control circuit, a γ-correction circuit, and the like.

2 shows the R pixel X _ij−1 , G pixel X _ij , B pixel X _{ij + 1} ,..., R pixel X _{i + 1j−1} , G pixel X _{i + 1j} , B pixel X shown in FIG. A part of the periodic arrangement of _{i + 1j + 1,.} That is, the units of the periodic arrangement of the R pixel X _ij−1 , the G pixel X _ij , and the B pixel X _{ij + 1} are respectively a red (R) photodiode PD _ij−1 and a green (G) photodiode PD _ij , The blue (B) photodiode PD _{ij + 1} and the second conductivity type (p-type) amplification circuit forming well 18R disposed adjacent to each of the photodiodes PD _ij−1 , PD _ij , PD _{ij + 1} . 18G, 18B and second conductivity type (p-type) transfer channel formation wells 19R, 19G, 19B are provided in a planar positional relationship. The amplification circuit formation wells 18R, 18G, 18B,... Are respectively regions between photodiodes PD _ij-2 (not shown) and photodiodes PD _ij-1 adjacent to each other in the row direction, and photodiodes PD _ij−1 . Element isolation is performed in a region between the photodiodes PD _ij , a region between the photodiodes PD _ij and the photodiodes PD _{ij + 1} , and a region between the photodiodes PD _{ij + 1} and the photodiodes PD _{ij + 2} (not shown). Similarly, a region between photodiodes PD _ij-1 and photodiodes PD _{i + 1j-1} adjacent in the column direction, a region between photodiodes PD _ij and photodiodes PD _{i + 1j} , photodiode PD _An element isolation region is formed in a region between _{ij + 1} and the photodiode PD _{i + 1j + 1} . The transfer channel formation wells 19R, 19G, and 19B have an impurity density of about 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less, and the amplification circuit formation wells 18R, 18G, and 18B have an impurity density of 3 × 10 ¹⁵ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less. The impurity density of the transfer channel formation wells 19R, 19G, and 19B can be set lower than the impurity density of the amplification circuit formation wells 18R, 18G, and 18B. In some cases, the transfer channel formation wells 19R, 19G, and 19B The impurity density may be equal to the impurity density of the amplifier circuit formation wells 18R, 18G, and 18B.

FIG. 3 corresponds to a cross-sectional view seen from the III-III direction of FIG. 2, and R pixel X _ij-1 and G pixel X constituting the pixel array unit 1 of the amplification type solid-state imaging device of the first embodiment. A cross-sectional structure of one unit of a periodic arrangement of _ij and B pixel X _{ij + 1} is shown. As shown in FIG. 3, a silicon substrate of the first conductivity type (n-type) having an impurity density of 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less (hereinafter simply referred to as “substrate”). on 11, the impurity density of 1 × 10 ¹⁴ cm ^-3 or less, 1 × 10 ¹¹ cm ^-3 or more very low impurity concentration second conductivity type having a thickness of the charge generation layer 12 made of the epitaxial layer ([pi type) R pixel X _ij-1 , G pixel X _ij , B pixel which is formed so that a is 10 μm or more and 50 μm or less and forms one unit of the RGB periodic array of the color imaging apparatus according to the first embodiment Each of X _{ij + 1} is configured.

In the R pixel X _ij-1 , the second conductivity type (p-type) ultra-low impurity density charge generation layer 12 is used as an anode region, and the first conductivity type (n-type) surface buried region 13R is used as a cathode region. Embedded photodiode (hereinafter abbreviated as “photodiode”) PD _ij-1, which is a four-transistor type in which one transfer transistor and three-transistor amplification circuit A _ij-1 are arranged in one pixel region, respectively. R pixel X _ij-1 is configured (see FIG. 5). In the G pixel X _ij , a photodiode PD _ij is configured with the second conductivity type ultra-low impurity density charge generation layer 12 as an anode region and the first conductivity type surface buried region 13G as a cathode region. A four-transistor type G pixel X _ij in which one transfer transistor and a three-transistor amplifier circuit A _ij are arranged in the region is configured. In the B pixel X _{ij + 1} , the photodiode PD _{ij + 1} is configured using the second conductivity type ultra-low impurity density charge generation layer 12 as an anode region and the first conductivity type surface buried region 13B as a cathode region. In addition, a 4-transistor type B pixel X _{ij + 1} in which one transfer transistor and a three-transistor amplification circuit A _{ij + 1} are arranged in one pixel region is configured. Then, R photodiode PD _ij-1, on top of the red (R) color filter 31R is, green (G) color filter 31R is formed on the G photodiode PD _ij is on the B photodiode PD _{ij + 1} Is provided with a blue (B) color filter 31R.

As shown in FIG. 3, the second conductivity type is formed on the first conductivity type (n-type) surface buried regions 13R, 13G, and 13B of the photodiodes PD _ij−1 , PD _ij , and PD _{ij + 1.} (P ⁺ -type) pinning layers 14R, 14G, and 14B are formed. The pinning layers 14R, 14G, and 14B are layers that suppress the generation of carriers on the surface in the dark, and are layers that fix (pinning) the surface potential to the ground potential. Ensure stable surface potential.

In the R pixel X _ij−1 , charges are transferred from the R photodiode PD _ij−1 to the charge detection region 16R via the transfer gate electrode 15R, and are amplified by the amplifier circuit A _ij−1 . In the G pixel X _ij , charges are transferred from the G photodiode PD _ij to the charge detection region 16G via the transfer gate electrode 15G, amplified by the amplifier circuit A _ij , and in the B pixel X _{ij + 1} , the transfer gate electrode Charge is transferred from the B photodiode PD _{ij + 1} to the charge detection region 16B via 15B, and is amplified by the amplifier circuit A _{ij + 1} .

Each of the three transistors constituting the amplifier circuit A _ij-1 of the R pixel X _ij-1 is disposed on a second conductivity type (p ⁺ type) well (amplifier circuit formation well) 18R having a high impurity density. For example, the source region 52R of the first conductivity type (n ⁺ type), the drain region 53R of the first conductivity type, and the gate electrode 51R provided on the channel between the source region 52R and the drain region 53R are reset. The transistor TR _ij-1 can be configured (see FIG. 5). Similarly, each of the three transistors constituting the amplification circuit A _ij-1 of the G pixel X _ij is disposed on the second conductivity type amplification circuit formation well 18G having a high impurity density. For example, the first conductivity type The reset transistor TR _ij can be configured by the source region 52G and the drain region 53G of the first conductivity type, and the gate electrode 51G provided on the channel between the source region 52G and the drain region 53G. Each of the three transistors constituting the amplifier circuit A _ij-1 of the B pixel X _{ij + 1} is disposed on the second impurity type well-conducting circuit forming well 18B having a high impurity density. The region 52B and the drain region 53B of the first conductivity type and the gate electrode 51B provided above the channel between the source region 52B and the drain region 53B It is possible to configure the phototransistor TR ij _{+ 1.} The amplification circuit formation wells 18R, 18G, and 18B are deeper than the n-type surface buried regions 13R, 13G, and 13B, respectively.

The R pixel X _ij-1 of the color imaging device according to the first embodiment is further below the charge detection region 16R and the transfer gate electrode 15R and between the surface buried region 13R and the amplifier circuit formation well 18R. A second conductivity type (p-type) transfer channel forming well 19R having an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less and a depth equal to that of the amplifier circuit forming well 18R is provided in the region. ing. The G pixel X _ij has an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more in a region between the surface buried region 13G and the amplifier circuit formation well 18G below the charge detection region 16G and the transfer gate electrode 15G. A second conductivity type (p-type) transfer channel formation well 19G having a depth equal to or less than 1 × 10 ¹⁸ cm ⁻³ and a depth equal to that of the amplification circuit formation well 18G is formed, and the B pixel X _{ij + 1} has a charge detection region In the region between the surface buried region 13B and the amplifier circuit formation well 18B below 16B and the transfer gate electrode 15B, the impurity density is 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. The second conductivity type (p-type) transfer channel formation well 19B is formed, the length of which is the same as the amplification circuit formation well 18B. That is, the transfer channel formation wells 19R, 19G, and 19B are deeper than the first conductivity type surface buried regions 13R, 13G, and 13B, respectively. The amplification circuit formation wells 18R, 18G, and 18B and the transfer channel formation wells 19R, 19G, and 19B are each given a ground potential through the p ⁺ type top contact regions 20R, 20G, and 20B. As described above, the impurity density of the transfer channel formation wells 19R, 19G, and 19B can be set lower than the impurity density of the amplification circuit formation wells 18R, 18G, and 18B, but the transfer channel formation wells 19R, 19G, and 19B. When the impurity density of each of the amplification circuit formation wells 18R, 18G, and 18B is made equal, the junction depth of the transfer channel formation wells 19R, 19G, and 19B and the junction depth of the amplification circuit formation wells 18R, 18G, and 18B are the same. If they are equal, the transfer channel formation wells 19R, 19G, and 19B and the amplifier circuit formation wells 18R, 18G, and 18B become an integral region.

An insulating film is formed on each of the pinning layers 14R, 14G, 14B, and further on each of transfer channel forming wells 19R, 19G, 19B between the pinning layers 14R, 14G, 14B and the charge detection regions 16R, 16G, 16B. (Not shown) is formed, and similarly, insulating films (not shown) are also formed on the respective amplification circuit forming wells 18R, 18G, 18B. The transfer gate electrode 15R is provided on the insulating film between the pinning layer 14R and the charge detection region 16R, and the gate electrode 51R is provided on the insulating film between the source region 52R and the drain region 53R. The transfer gate electrode 15G is provided on the insulating film between the pinning layer 14G and the charge detection region 16G, the gate electrode 51G is provided on the insulating film between the source region 52G and the drain region 53G, and the transfer gate electrode 15B. Is provided on the insulating film between the pinning layer 14B and the charge detection region 16B, and the gate electrode 51B is provided on the insulating film between the source region 52B and the drain region 53B. The insulating film is preferably a silicon oxide film (SiO ₂ film), but has an insulated gate structure of an insulated gate transistor (MIS transistor) using various insulating films other than the silicon oxide film (SiO ₂ film). May be. For example, an ONO film composed of a three-layered film of silicon oxide film (SiO ₂ film) / silicon nitride film (Si ₃ N ₄ film) / silicon oxide film (SiO ₂ film) may be used. Furthermore, at least one element of strontium (Sr), aluminum (Al), magnesium (Mg), yttrium (Y), hafnium (Hf), zirconium (Zr), tantalum (Ta), and bismuth (Bi) is contained. Oxides containing or silicon nitride containing these elements can be used as the insulating film. In FIG. 3, the substrate 11 is provided with substrate potential switching means for switching the substrate potential between the low potential VL and the high potential VH, and its purpose and effect will be described with reference to FIG.

4 corresponds to a cross-sectional view seen from the IV-IV direction of FIG. 2 and shows the structure of the G pixel X _ij1 constituting the pixel array unit 1 of the amplification type solid-state imaging device of the first embodiment. As shown in FIG. 4, the impurity density is 1 × 10 ¹⁴ cm on the first conductivity type (n-type) substrate 11 having an impurity density of 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less. ⁻³ or less, and the charge generation layer 12 made of the second conductivity type (π-type) epi layer having an extremely low impurity density of 1 × 10 ¹¹ cm ⁻³ or more is formed to have a thickness of 10 μm or more and 50 μm or less. , G pixel X _ij is configured. That is, the photodiode PD _ij is configured with the charge generation layer 12 having an extremely low impurity density as the anode region and the first conductivity type (n-type) surface buried region 13 as the cathode region. A G color filter 31R is provided on the G photodiode PD _ij , but is not shown. As shown in FIG. 4, a second conductivity type ( ^{p.sup. +} Type) pinning layer 14G is formed on the first conductivity type surface buried region 13G of the G photodiode PD _ij . Then, a second conductivity type (p ⁺ type) having an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less deeper than the surface buried region 13G so as to surround the G photodiode PD _ij . An amplification circuit forming well 18G is arranged. Although illustration is omitted, since the structures of the R pixel X _ij-1 and B pixel X _{ij + 1} viewed from the direction parallel to the IV-IV direction are substantially the same, the redundant description is omitted.

FIG. 5 shows an example of the amplifier circuit A _ij arranged in the amplifier circuit formation well 18G. As shown in FIG. 5, the charge detection region 16G has a gate electrode of a signal readout transistor (amplification transistor) TA _ij constituting the amplification circuit A _ij and a reset transistor by a surface wiring via a contact plug (not shown). The TR _ij source electrode is connected. The drain electrode of the reset transistor TR _{ij and} the drain electrode of the signal readout transistor (amplification transistor) TA _ij are connected to the power supply V _DD respectively, and the source electrode of the signal readout transistor (amplification transistor) TA _ij is the switching transistor TS for pixel selection. It is connected to the drain electrode of _ij . The reset signal R _{i is set} to the high (H) level (R _i = “1”) to the reset gate electrode of the reset transistor TR _ij , and the charges accumulated in the charge detection region 16G are discharged, respectively. Reset. The source electrode of the pixel selection switching transistor TS _ij is connected to the vertical signal line B _j of j columns, and the vertical selection signal S _{i of the i-th} horizontal line is driven to the gate electrode by the timing generation circuit 4 to be vertical. It is given from the shift register (vertical scanning circuit) 3. For example, as the amplifier circuit A _ij of the G pixel X _ij , the first conductivity type source region 52G and the first conductivity type drain region 53G provided on the amplifier circuit formation well 18G shown in FIG. if a gate electrode 51G provided on the upper portion of the channel between the drain region 53G constitute a reset transistor TR _ij, drain region 54G and the first conductive of a first conductivity type provided on the amplifier circuit forming well 18G The signal read transistor (amplification transistor) TA _ij is of the first conductivity type by the gate electrode 55G provided on the channel between the source / drain shared region 56G and the channel between the drain region 54G and the source / drain shared region 56G. The source / drain shared region 56G, the first conductivity type source region 58G, and the source / drain shared region Switching transistor TS _ij is composed of a gate electrode 57G provided on the upper portion of the channel between the regions 56G beauty source region 58G. However, the layout of the amplifier circuit A _ij can have various topologies, and is not limited to the above. Depending on the circuit topology, for example, if the circuit configuration is such that the n ⁺ region 54G adjacent to the n ⁺ type drain region 53G is connected to the common power supply wiring V _DD , the n ⁺ region adjacent to the drain region 53G. 54G may be configured as a continuous integrated region.

Although the circuit display is omitted, the circuit configurations of the amplifier circuits A _ij-1 and A _{ij + 1} are substantially the same, and the amplifier circuit A _ij-1 of the R pixel X _ij-1 is shown in FIG. A first conductivity type source region 52R and a first conductivity type drain region 53R provided on the amplifier circuit formation well 18R, and a gate electrode 51R provided on the channel between the source region 52R and the drain region 53R; Is configured as the reset transistor TR _ij-1 , the first conductivity type drain region 54R and the first conductivity type source / drain shared region 56R, the drain region 54R and the source provided on the amplification circuit formation well 18R. drain shared area upper portion provided gate electrode 55R in signal readout transistor channel between the 56R (amplification transistor) TA _ij-1 is of a first conductivity type source Scan-drain shared region 56R and the source region of the first conductivity type 58R, source and drain shared area 56R beauty switching transistor TS _ij-1 in the gate electrode 57R provided in the upper portion of the channel between the source region 58R is configured Is done. Similarly, as the amplifier circuit A _{ij + 1} of the B pixel X _{ij + 1} , a first conductivity type source region 52B and a first conductivity type drain region 53B provided on the amplifier circuit formation well 18B shown in FIG. If the gate electrode 51B provided above the channel between the source region 52B and the drain region 53B constitutes the reset transistor TR _{ij + 1} , the first conductivity type provided on the amplifier circuit formation well 18B is assumed. The signal readout transistor (amplification transistor) TA _ij is formed by the drain region 54B and the source / drain shared region 56B of the first conductivity type, and the gate electrode 55B provided on the channel between the drain region 54B and the source / drain shared region 56B. ₊₁ is the source / drain shared region 56B of the first conductivity type and the source region 58B of the first conductivity type, and the source / drain The switching transistor TS _{ij + 1} is configured by the gate electrode 57B provided on the upper part of the channel between the common region 56B and the source region 58B.

In the R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} of the color imaging device according to the first embodiment shown in FIG. Since the state is close to that of a semiconductor, the depletion layer extends from the interface between the first conductivity type surface buried regions 13R, 13G, and 13B and the second conductivity type charge generation layer 12 toward the substrate 11 very deeply. That is, the impurity density of the charge generation layer 12 forming the photodiodes PD _ij−1 , PD _ij , PD _{ij + 1} of the R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} is 1 ×. In a state close to an intrinsic semiconductor of 10 ¹³ cm ⁻³ or less, the depth of the depletion layer end is 15 μm or more, so that most of the charge generation layer 12 is depleted. Therefore, as shown in FIG. 7, sufficient sensitivity can be maintained even with near-infrared light having a wavelength of 800 nm or more that penetrates 10 μm or more into silicon.

As described above, in the color imaging device according to the first embodiment, the charge generation layer 12 close to an intrinsic semiconductor is adopted, and depletion layers in the photodiodes PD _ij−1 , PD _ij , and PD _{ij + 1} regions are formed. The substrate 11 is formed deeply, ensuring high infrared sensitivity and low crosstalk, and the potential of the substrate 11 is set to the first potential (low potential) VL and the second potential (high potential) higher than the first potential. Substrate potential switching means for switching to VH is provided. Various semiconductor switches such as transistors can be used for switching the substrate potential, but mechanical switches may be used.

  By providing the substrate potential switching means, as shown in FIG. 6, the potential of the substrate 11 is set to the first potential (low potential) VL at the time of infrared imaging, thereby forming a deep potential peak position in the depletion layer. In color imaging, the potential of the substrate 11 is set to a second potential (high potential) VH that is higher than the first potential, so that the position of the potential peak in the depletion layer is shallow. .

In FIG. 6, d1 is the thickness of the pinning layers 14R, 14G, 14B of the photodiodes PD _ij-1 , PD _ij , PD _{ij + 1} , d2 is the thickness of the surface buried regions 13R, 13G, 13B, and d3 is an extremely low impurity. The thickness d4 of the charge generation layer 12 having a density represents the thickness of the substrate 11 (see FIG. 3). At the time of infrared imaging, by setting the potential of the substrate 11 to the first potential VL which is a low potential, the position 22 of the potential peak formed in the charge generation layer 12 having an extremely low impurity density is d6 from the surface. (See FIG. 3). For example, if d6 = 10 μm or more, as is apparent from FIG. 7, sufficiently large sensitivity can be secured for near infrared rays having a wavelength of 800 nm to 900 nm.

  On the other hand, at the time of color imaging, by setting the potential of the substrate 11 to the second potential VH, which is a high potential, the position 23 of the potential peak formed in the charge generation layer 12 with an extremely low impurity density is from the surface. d5 (see FIG. 3. For example, if d5 = 2 μm or less, as is clear from FIG. 7, the sensitivity can be suppressed to a sufficiently small sensitivity with respect to near-infrared wavelengths of 800 nm to 900 nm.

  When the potential of the substrate 11 is the first potential VL, in order to prevent electron injection from the substrate 11 side to the surface buried regions 13R, 13G, 13B, electrons are injected from the substrate 11 to the surface side. The height of the potential barrier VB2 for preventing it is desirable to ensure 0.5V or more. The height of the potential peak formed in the charge generation layer 12 to prevent the injection of electrons is the value of the first potential VL, the impurity density of the substrate 11, the impurity density of the charge generation layer 12 and its thickness. d3, the impurity density of the pinning layers 14R, 14G, and 14B, the thickness d1, the impurity density of the surface buried regions 13R, 13G, and 13B, the thickness d2, the impurity density of the amplification circuit formation wells 18R, 18G, and 18B, and the thickness thereof It depends on the thickness d7, the impurity density of the transfer channel formation wells 19R, 19G, and 19B, the thickness d7, and the planar layout. Therefore, when the first potential VL applied to the potential of the substrate 11 is the ground potential, the first potential VL is sufficient if the height of the potential barrier for preventing electron injection from the substrate 11 side to the surface side is insufficient. What is necessary is just to raise the VL value a little (0.5V or less) and to secure the height of the potential barrier.

  When the potential of the substrate 11 is the second potential VH, as shown in FIG. 6, the potential of the substrate 11 is higher than the potentials VA1 and VA3 of the surface buried regions 13R, 13G, and 13B. Here, VA1 represents a potential when charge is not accumulated in the surface buried region, and VA3 represents a potential when the charge is sufficiently accumulated. Therefore, in order to prevent electrons from flowing out from the surface buried regions 13R, 13G, and 13B forming the photodiode to the substrate 11, it is desirable to secure the potential barrier heights VB1 and VB3 to 0.5 V or more. The potential barrier heights VB1 and VB3 when the potential of the substrate 11 is the second potential VH are the values of the second potential VH, the impurity density of the substrate 11, the impurity density of the charge generation layer 12, and its thickness d3. The impurity density and thickness d1 of the pinning layers 14R, 14G and 14B, the impurity density and thickness d2 of the surface buried regions 13R, 13G and 13B, and the impurity density and thickness of the amplification circuit forming wells 18R, 18G and 18B It depends on the impurity density and thickness d7 of the transfer channel formation wells 19R, 19G and 19B, and the planar layout.

The planar layout, spacing w ₁ of the amplifier circuit forming well 18B shown in FIG. 3 and the transfer channel formation well 19R, interval w ₁ between the amplifier circuit forming well 18R and the transfer channel formation well 19G, the amplifier circuit forming well 18G And the distance w ₁ between the transfer channel formation well 19B and the distance l ₁ between the amplification circuit formation well 18G and the amplification circuit formation well 18G shown in FIG. 4 are important (not shown, but similar to FIG. 3) Of course, the interval l ₁ between the amplification circuit formation well 18R and the amplification circuit formation well 18R and the interval l ₁ between the amplification circuit formation well 18B and the amplification circuit formation well 18B are also important.

  For example, as shown in FIG. 14 of the second embodiment to be described later, in the one-dimensional model of the n-π-n hook structure without the amplifier circuit formation well 18G and the transfer channel formation well 19G, the potential of the substrate 11 is Even when the potential of 2 (high potential) VH = 5.1V, the barrier height of the potential barrier formed in the charge generation layer 12 is about 0.025V, and it is understood that the potential barrier is hardly formed. .

The potential barrier formed in the charge generation layer 12 in the color imaging device according to the first embodiment is similar to the potential barrier formed in the channel of the bipolar mode electrostatic induction transistor (BSI). In other words, when focusing on the G pixel X _ij , the n-type surface buried region 13G is the BSIT source region, the π-type charge generation layer 12 is the BSIT channel region, and the n-type substrate 11 is the BSIT drain. The region, the amplification circuit formation well 18G, and the transfer channel formation well 19G correspond to the gate region of the BSIT that sandwiches both sides of the channel. In BSIT, the potential distribution of the n-π-n hook structure from the source region to the drain region is caused by the electrostatic induction effect by the p ⁺ gate region sandwiching both sides of the channel. The potential barrier is formed. To this end, the potential of the saddle point, the distance between the p ⁺ gate region and the p ⁺ gate regions, such as the establishment of cross models lifted by electrostatic induction effect of the p ⁺ gate region upward in FIG. 6 (Refer to IEICE Transactions '80 / 8, Vol. J63-C, No. 8, p529-536 etc.). The electrostatic induction effect of raising the potential of the buttocks point is that if the amplification circuit formation well 18G and the transfer channel formation well 19G are at ground potential, the π-type charge generation layer 12, the p-type amplification circuit formation well 18G and the transfer channel formation are formed. It depends on the diffusion potential (built-in potential) of the π-p junction formed by the well 19G. p ⁺ as the potential of the gate region and the p ⁺ spacing The smaller channel with the gate region is increased approaching the potential of the p ⁺ gate regions, the amplifier circuit forming well 18R and the transfer channel formed well along the row direction The smaller the distance w _{1 from} 19G and the distance l ₁ between the amplifier circuit forming well 18G and the amplifier circuit forming well 18G along the column direction, the higher the potential barrier formed in the charge generation layer 12. When the well interval w _{1 in the} row direction and the well interval l _{1 in the} column direction become more than twice the Debye length of electrons in the charge generation layer 12, electrostatic capacitance is generated by the amplification circuit formation well 18 R and the transfer channel formation well 19 G. The inductive effect is undesirable because it is screened by electrons.

In order for the potential of the buttock point to be effectively raised by the electrostatic induction effect in the cross-shaped model, the junction depth of the amplification circuit forming well 18R and the transfer channel forming well 19G surrounding the surface buried region 13G is determined by the surface buried region 13G. It can be easily understood that the depth deeper than the junction depth is effective considering the potential effect generated by the amplification circuit formation well 18R and the transfer channel formation well 19G. For example, if the junction depth of the surface buried region 13G is about 0.2 to 0.3 μm, the junction depth between the amplifier circuit formation well 18R and the transfer channel formation well 19G is the junction depth of the surface buried region 13G. About 2 to 5 times as effective. When the junction depth between the amplification circuit formation well 18R and the transfer channel formation well 19G becomes less than twice the junction depth of the surface buried region 13G, the electrostatic effect exerted by the amplification circuit formation well 18R and the transfer channel formation well 19G Since the induction effect is difficult to reach the buttocks, it is not preferable. Considering the cruciform model, the distance w ₁ between the amplification circuit formation well 18R and the transfer channel formation well 19G along the row direction, and the distance l between the amplification circuit formation well 18G and the amplification circuit formation well 18G along the column direction. ₁ is preferably about the junction depth between the amplification circuit formation well 18R and the transfer channel formation well 19G. However, the amplifier circuit formation well 18R and the transfer channel formation well 19G spacing w _1, and may be determined the optimum value of the distance l ₁ between the amplifier circuit forming well 18G along the column direction and the amplification circuit forming well 18G. In general, if the junction depth of the surface buried region 13G is about 0.2 to 0.3 μm, the distance w ₁ between the amplifier circuit formation well 18R and the transfer channel formation well 19G along the row direction and the column direction. The interval l ₁ between the amplification circuit formation well 18G and the amplification circuit formation well 18G along the line is preferably 4 μm or less.

In consideration of the balance of the lines of electric force in the cross model, the distance w ₁ between the amplification circuit formation well 18R and the transfer channel formation well 19G along the row direction and the amplification circuit formation well 18G along the column direction The distance l ₁ between the amplification circuit formation well 18G is preferably selected to be 3 to 6 times the junction depth of the amplification circuit formation well 18R and the transfer channel formation well 19G. The interval w ₁ between the amplification circuit formation well 18R and the transfer channel formation well 19G along the row direction and the interval l ₁ between the amplification circuit formation well 18G and the amplification circuit formation well 18G along the column direction are the amplification circuit formation well. If it becomes too large compared to the junction depth of 18R and transfer channel formation well 19G, it will be difficult to effectively raise the potential at the heel point.

In consideration of the diffusion potential (built-in potential) of the π-p junction formed by the π-type charge generation layer 12, the p-type amplifier circuit formation well 18G, and the transfer channel formation well 19G, the amplifier circuit formation well 18R and the transfer channel formation well The area on the plane pattern occupied by 19G is
Although it is desirable that the area is relatively larger than the area on the planar pattern occupied by the surface buried region 13G, the area occupied by the surface buried region 13G with respect to the pixel area is actually a trade-off condition with the sensitivity characteristics of the pixel. The ratio, that is, the fill factor is determined, but for example, it may be selected at about 30%.

As described above, the impurity density of the transfer channel formation wells 19R, 19G, and 19B can be set lower than the impurity density of the amplification circuit formation wells 18R, 18G, and 18B, but is formed in the charge generation layer 12. In order to increase the height of the potential barrier, the impurity density of the transfer channel formation wells 19R, 19G, and 19B is equal to the impurity density of the amplification circuit formation wells 18R, 18G, and 18B, and both are 2 × 10 ¹⁷ cm. ^It is preferable to set a higher value of about ^{−3 to} 4 × 10 ¹⁸ cm ⁻³ .

  As shown in FIG. 6, by forming in the charge generation layer 12 potential peaks of barrier heights VB1 and VB3 that prevent electrons from flowing out from the surface buried regions 13R, 13G, and 13B to the substrate 11, It is possible to change the effective depth during infrared imaging and color imaging while maintaining the accumulation operation by changing the potential of the substrate 11.

The blooming suppression in the present invention uses a transfer transistor as shown in FIG. 8 (a) it is focused on G pixel X _ij, along the charge transfer direction to the charge detection region 16G via the transfer gate electrode 15G of the transfer transistor from the G photodiode PD _ij of G pixel X _ij sectional FIG. 8B shows a potential distribution at the same place. Here, by making both the off potential Φ _TX (off) of the transfer transistor and the off potential Φ _RT (off) of the reset transistor positive, the charge accumulation of the G photodiode PD _ij is performed while the transfer transistor is in the off state. On the other hand, when the G photodiode PD _ij reaches saturation, excess charge is discharged to the drain region 53G of the potential Vdd through the channel of the transfer transistor and the reset transistor, so that blooming is prevented. Note that if the gate electrode 51G of the reset transistor is turned on while the charge accumulation of the G photodiode PD _ij is performed, the off-potential Φ _RT (off) of the reset transistor does not necessarily have to be positive. Since the R pixel X _ij-1 and the B pixel X _{ij + 1} are substantially the same as the G pixel X _ij , the redundant description is omitted.

  FIG. 9 is a diagram showing the difference in spectral characteristics when the potential of the substrate 11 is changed in the present invention. First, the potential of the substrate 11 is set to a low potential (first potential) VL, typically a ground voltage, and the position of the potential peak formed in the charge generation layer 12 having an extremely low impurity density is deep from the surface, for example, 16 μm. Then, the spectral characteristic at that time is a curve indicated by “IR mode”. On the other hand, the potential of the substrate 11 is set to a high potential (second potential) VH, typically a power supply voltage, and the position of the potential peak formed in the charge generation layer 12 having an extremely low impurity density is shallow from the surface. If the thickness is 1 μm, the spectral characteristic at that time becomes a curve indicated by “color mode”. The vertical axis in FIG. 9 is normalized (normalized) so that the peak value is 1 for both “IR mode” and “color mode”. In the response before normalization, the peak value of “IR mode” is about twice the peak value of “color mode”.

  When the R, G, B color filters 31R, 31G, 31B have spectral characteristics as shown in FIG. 24, the characteristics represented by R, G, B as products with the “color mode” curve during color imaging are as follows. Thus, a good color signal with little color mixture can be obtained. On the other hand, at the time of infrared imaging, the average output of each of the R, G, B color filters 31R, 31G, 31B has a characteristic represented by IR as a product with the “IR mode” curve, and has high infrared sensitivity. Can be secured. In FIG. 9, the color filters 31R, 31G, and 31B assume a Bayer array as shown in FIG. 18, and the average output is (2G + R + B) / 4. In the Bayer array shown in FIG. 18, the resolution of green is N / 2 and the resolution of red and blue is N / 4 with respect to the total number N of pixels.

  In the case of FIG. 9, some infrared components still remain in each color signal, R, G, and B at the time of color imaging. In order to suppress this more completely, as shown in FIG. 10, a value obtained by multiplying the same color signal during infrared imaging by a specific ratio k may be subtracted from each color signal during color imaging. In the example of FIG. 10, k = 0.15 with respect to the response after normalization. Thereby, the infrared component of 800 nm or more can be made almost zero, and the infrared component at the time of color imaging can be more completely removed. Thereby, the color reproducibility can be further enhanced.

  The description of the color imaging device according to the first embodiment is aimed at achieving both color imaging and infrared imaging, but the color imaging device according to the first embodiment is limited to this. However, the present invention can be applied to a case where only color imaging is intended. That is, in the conventional color imaging, as described with reference to FIG. 24, IRC is indispensable. However, according to the color imaging device according to the first embodiment, the method described in FIGS. Among these, by using the color imaging portion, it is possible to perform good color imaging without IRC.

  As a conventional technique using an n substrate, a low impurity density p layer is formed on a low impurity density n substrate as disclosed in, for example, Japanese Patent Application Laid-Open No. 09-331058, and a CCD ( There is an example in which a charge-coupled device is formed, but a vertical overflow that applies a reverse bias potential of about 15 V to the n substrate and discharges excessive charges generated in the photoelectric conversion element in the p layer to the n substrate side. The drain structure is a technique different from the structure for making the infrared sensitivity variable in the color imaging device according to the first embodiment.

(Second Embodiment)
The outline of the layout on the semiconductor chip of the color imaging device (two-dimensional color image sensor) according to the second embodiment of the present invention is the same as that of the color imaging device according to the first embodiment shown in FIG. Therefore, a duplicate description is omitted. However, although a three-color stripe type color filter array is illustrated in FIG. 1, the present invention is not limited to this, and various color filter arrays as shown in FIGS. 18 to 21 can be employed.

11 shows the R pixel X _ij−1 , G pixel X _ij , B pixel X _{ij + 1} ,..., R pixel X _{i + 1j−1} , G pixel X _{i + 1j} , B pixel X shown in FIG. A part of the periodic arrangement of _{i + 1j + 1,.} That is, R pixels X _ij−1 , G pixels X _ij , and B pixels X _{ij + 1} are periodically arranged in units of R photodiode PD _ij−1 , G photodiode PD _ij , and B photodiode PD _{ij +, respectively. 1} , and second conductivity type wells 18R, 18G, 18B and second conductivity type (p type) amplifier circuit forming wells 18R, 18G, 18B arranged adjacent to the photodiodes PD _ij-1 , PD _ij , PD _{ij + 1} , respectively. p-type) transfer channel formation wells 19R, 19G, and 19B are provided as a planar positional relationship. The amplification circuit formation wells 18R, 18G, 18B,... Are respectively regions between photodiodes PD _ij-2 (not shown) and photodiodes PD _ij-1 adjacent to each other in the row direction, and photodiodes PD _ij−1 . Element isolation is performed in a region between the photodiodes PD _ij , a region between the photodiodes PD _ij and the photodiodes PD _{ij + 1} , and a region between the photodiodes PD _{ij + 1} and the photodiodes PD _{ij + 2} (not shown). Similarly, a region between photodiodes PD _ij-1 and photodiodes PD _{i + 1j-1} adjacent in the column direction, a region between photodiodes PD _ij and photodiodes PD _{i + 1j} , photodiode PD _An element isolation region is formed in a region between _{ij + 1} and the photodiode PD _{i + 1j + 1} . The amplifier circuit formation wells 18R, 18G, and 18B and the transfer channel formation wells 19R, 19G, and 19B are semiconductor regions having an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less.

FIG. 12 corresponds to a cross-sectional view as viewed from the XII-XII direction of FIG. 11, and the R pixel X _ij-1 and G pixel X constituting the pixel array unit 1 of the amplification type solid-state imaging device of the second embodiment. A cross-sectional structure of one unit of a periodic arrangement of _ij and B pixel X _{ij + 1} is shown. As shown in FIG. 12, an impurity density of 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less of a first conductivity type (n-type) silicon substrate 11 is used. The charge generation layer 12 made of a second conductivity type (π-type) epitaxial layer close to an intrinsic semiconductor of 10 ¹⁴ cm ⁻³ or less and 1 × 10 ¹¹ cm ⁻³ or more is formed so that the thickness a becomes 10 μm or more and 50 μm or less. The R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} are configured to form one unit of the RGB periodic array of the color imaging apparatus according to the second embodiment. Yes.

In the R pixel X _ij−1 , the charge generation layer 12 close to the second conductivity type (p-type) intrinsic semiconductor is used as an anode region, and the first conductivity type (n-type) surface buried region 13R is used as a cathode region. A 4-transistor type R pixel X _ij-1 is configured, which includes a diode PD _ij-1 and in which one transfer transistor and a three-transistor amplifier circuit A _ij-1 are arranged in one pixel region (FIG. 5). reference.). In the G pixel X _ij , a photodiode PD _ij is configured with the charge generation layer 12 as an anode region and the first conductivity type surface buried region 13G as a cathode region, and one transfer transistor and 3 A 4-transistor type G pixel X _{ij in} which the transistor amplification circuits A _ij are respectively arranged is configured. In the B pixel X _{ij + 1} , a photodiode PD _{ij + 1} is configured with the charge generation layer 12 as an anode region and the first conductivity type surface buried region 13B as a cathode region, and one pixel region includes one photodiode PD _{ij + 1} . A four-transistor type B pixel X _{ij + 1} in which a transfer transistor and a three-transistor amplification circuit A _{ij + 1} are respectively arranged is configured. Then, R photodiode PD _ij-1, the R color filter 31R is formed on the, G color filters 31R on top of G photodiode PD _ij is, B photodiode PD _{ij + 1} of B color filter 31R is formed on Is provided.

As shown in FIG. 12, on the surface buried regions 13R, 13G, and 13B of the photodiodes PD _ij−1 , PD _ij , and PD _{ij + 1} , the second conductivity type (p ⁺ type) pinning layer 14R is formed. , 14G, 14B are formed. The pinning layers 14R, 14G, and 14B are layers that suppress the generation of carriers on the surface in the dark, and are layers that fix (pinning) the surface potential to the ground potential. Ensure stable surface potential.

In the R pixel X _ij−1 , charges are transferred from the R photodiode PD _ij−1 to the charge detection region 16R via the transfer gate electrode 15R, and are amplified by the amplifier circuit A _ij−1 . In the G pixel X _ij , charges are transferred from the G photodiode PD _ij to the charge detection region 16G via the transfer gate electrode 15G, amplified by the amplifier circuit A _ij , and in the B pixel X _{ij + 1} , the transfer gate electrode Charge is transferred from the B photodiode PD _{ij + 1} to the charge detection region 16B via 15B, and is amplified by the amplifier circuit A _{ij + 1} .

Unlike the color imaging device according to the first embodiment, in the color imaging device according to the second embodiment shown in FIGS. 11 and 12, the charge detection region 16R and the source region shown in FIGS. 52R forms an integrated charge detection region 16R, the charge detection region 16R constitutes the source region of the reset transistor TR _ij-1 of the R pixel X _ij-1 , the transfer channel formation well 19R, the amplification circuit formation well 18R, Is located inside the charge detection region 16R on the planar pattern. Similarly, the charge detection region 16G and the source region 52G shown in FIGS. 2 and 3 form an integrated charge detection region 16G, and the charge detection region 16G constitutes the source region of the reset transistor TR _ij of the G pixel X _ij. 2 and 3, the charge detection region 16B and the source region 52B are integrated to form a charge detection region 16B, and the charge detection region 16B is the source of the reset transistor TR _{ij + 1} of the B pixel X _{ij + 1.} It constitutes an area. The boundary between the transfer channel formation well 19G and the amplification circuit formation well 18G is located inside the charge detection region 16G on the plane pattern, and the boundary between the transfer channel formation well 19B and the amplification circuit formation well 18B is on the plane pattern. It is located inside the charge detection region 16B.

Therefore, in the amplifier circuit A _{ij-1 of} the R pixel X _ij-1 , the first conductivity type (n ⁺ type) charge detection region 16R, the first conductivity type drain region 53R, the charge detection region 16R, and the drain region A reset transistor TR _ij-1 is configured by the gate electrode 51R provided on the upper part of the channel between 53R (see FIG. 5). Similarly, in the amplifier circuit A _ij-1 of the G pixel X _ij , the first conductivity type charge detection region 16G and the first conductivity type drain region 53G, and the upper part of the channel between the charge detection region 16G and the drain region 53G And the gate electrode 51G provided in the _first pixel constitute a reset transistor TR _ij, and in the amplifier circuit A _{ij-1 of} the B pixel X _{ij + 1} , the first conductivity type charge detection region 16B and the first conductivity type drain region 53B and the gate electrode 51B provided above the channel between the charge detection region 16B and the drain region 53B constitute a reset transistor TR _{ij + 1} .

  The amplification circuit formation wells 18R, 18G, and 18B and the transfer channel formation wells 19R, 19G, and 19B are deeper than the surface buried regions 13R, 13G, and 13B, respectively, as in the color imaging device according to the first embodiment. However, in the color imaging device according to the second embodiment, the first conductivity type (n-type) block layer 21R is provided at the bottom of each of the amplification circuit formation well 18R and the transfer channel formation well 19R to amplify. The diffusion and inflow of holes (carriers) from the circuit formation well 18R and the transfer channel formation well 19R to the charge generation layer 12 is blocked, and the first conductivity type is formed in the bottom portions of the amplification circuit formation well 18G and the transfer channel formation well 19G. An (n-type) block layer 21G is provided, and an amplification circuit formation well 18G and a transfer channel formation well 19G In addition, the diffusion flow of holes (carriers) into the charge generation layer 12 is blocked, and a first conductivity type (n-type) block layer 21B is provided at the bottom of each of the amplification circuit formation well 18B and the transfer channel formation well 19B. The diffusion flow of holes (carriers) from the amplification circuit formation well 18B and the transfer channel formation well 19B to the charge generation layer 12 is blocked.

FIG. 13 corresponds to a cross-sectional view seen from the XIII-XIII direction of FIG. 11 and shows the structure of the G pixel X _ij1 constituting the pixel array unit 1 of the amplification type solid-state imaging device of the second embodiment. As shown in FIG. 13, the impurity density is 1 × 10 ¹⁴ cm on the first conductivity type (n-type) substrate 11 having an impurity density of 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less. ^-3 or less, a charge generation layer 12 made of an epi layer of the second conductivity type (π type) close to an intrinsic semiconductor of 1 × 10 ¹¹ cm ⁻³ or more is formed to have a thickness of 10 μm or more and 50 μm or less, A G pixel X _ij is configured. That is, the photodiode PD _ij is configured with the charge generation layer 12 close to an intrinsic semiconductor as the anode region and the surface buried region 13 as the cathode region. As can be seen from FIG. 12, the G color filter 31R is provided on the G photodiode PD _ij , but the illustration thereof is omitted in FIG. As shown in FIG. 13, a second conductivity type ( ^{p.sup. +} Type) pinning layer 14G is formed on the first conductivity type surface buried region 13G of the G photodiode PD _ij . Then, a second conductivity type (p ⁺ type) having an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less deeper than the surface buried region 13G so as to surround the G photodiode PD _ij . An amplification circuit forming well 18G is arranged. Although not shown, the structures of the R pixel X _ij-1 and the B pixel X _{ij + 1} viewed from the direction parallel to the XIII-XIII direction are substantially the same, and thus a duplicate description is omitted.

In the R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} of the color imaging device according to the second embodiment shown in FIGS. 11 to 13, the charge generation layer 12 as a whole has a very low impurity density. Therefore, the depletion layer extends from the interface between the first conductivity type surface buried regions 13R, 13G, and 13B and the second conductivity type charge generation layer 12 toward the substrate 11 very much. deep. That is, the impurity density of the charge generation layer 12 forming the photodiodes PD _ij−1 , PD _ij , PD _{ij + 1} of the R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} is 1 ×. In a state close to an intrinsic semiconductor of 10 ¹³ cm ⁻³ or less, the depth of the depletion layer end is 15 μm or more, so that most of the charge generation layer 12 is depleted. Therefore, as shown in FIG. 7, sufficient sensitivity can be maintained even with near-infrared light having a wavelength of 800 nm or more that penetrates 10 μm or more into silicon.

As described above, the color imaging device according to the second embodiment employs the charge generation layer 12 close to an intrinsic semiconductor, as in the color imaging device according to the first embodiment, so that the photodiode PD _{ij− 1} , PD _ij , and PD _{ij + 1} regions are formed deeply to ensure high infrared sensitivity and low crosstalk, and the potential of the substrate 11 is set to the first potential (low potential) VL and the first Substrate potential switching means for switching to a second potential (high potential) VH that is higher than the first potential. Various semiconductor switches such as transistors can be used for switching the substrate potential, but mechanical switches may be used.

  In the color imaging device according to the second embodiment, the block layer 21R is provided at the bottom of each of the amplification circuit formation well 18R and the transfer channel formation well 19R, and the bottom of each of the amplification circuit formation well 18G and the transfer channel formation well 19G. Since the block layer 21G is provided in the part and the block layer 21B is provided in the bottom part of each of the amplifier circuit formation well 18B and the transfer channel formation well 19B, the potential barrier heights VB1 and VB3 shown in FIG. However, by providing the substrate potential switching means, the potential in the depletion layer can be reduced by setting the potential of the substrate 11 to the first potential (low potential) VL during infrared imaging, as shown in FIG. The position of the mountain is controlled to be deeply formed, and the potential of the substrate 11 is set to the first potential during color imaging. As a second potential (high electric potential) VH of high potential, it can be controlled to shallow the position of the potential hill in the depletion layer.

  When the potential of the substrate 11 is the first potential (low potential) VL, the height of the potential peak formed in the charge generation layer 12 to prevent the injection of electrons is equal to the first potential VL. Values, the impurity density of the substrate 11, the impurity density of the charge generation layer 12, its thickness d3, the impurity density of the pinning layers 14R, 14G, 14B, its thickness d1, and the impurity density of the surface buried regions 13R, 13G, 13B The thickness d2, the impurity density of the amplification circuit formation wells 18R, 18G, and 18B and the thickness d7, the impurity density of the transfer channel formation wells 19R, 19G, and 19B and the thickness d7, and the impurities of the block layers 21R, 21G, and 21B It depends on the density and its thickness d8 and the planar layout.

Further, when the potential of the substrate 11 is the second potential (high potential) VH, the potential barrier heights VB1 and VB3 are the values of the second potential (high potential) VH, the impurity density of the substrate 11, and Impurity density of charge generation layer 12 and its thickness d3, impurity density of pinning layers 14R, 14G and 14B, its thickness d1, impurity density of surface buried regions 13R, 13G and 13B and its thickness d2, formation of amplifier circuit Impurity density and thickness d7 of wells 18R, 18G and 18B, impurity density and thickness d7 of transfer channel forming wells 19R, 19G and 19B, impurity density and thickness d8 of block layers 21R, 21G and 21B, and Depends on the planar layout. The planar layout, spacing w ₁ of the amplifier circuit forming well 18B shown in FIG. 12 and the transfer channel formation well 19R, interval w ₁ between the amplifier circuit forming well 18R and the transfer channel formation well 19G, the amplifier circuit forming well 18G And the interval w ₁ between the transfer channel formation well 19B and the interval l ₁ between the amplification circuit formation well 18G and the amplification circuit formation well 18G shown in FIG. 12 are important (not shown, but similar to FIG. 12) Of course, the interval l ₁ between the amplification circuit formation well 18R and the amplification circuit formation well 18R and the interval l ₁ between the amplification circuit formation well 18B and the amplification circuit formation well 18B are also important. The well interval w ₁ and the well interval l ₁ are set to a distance within twice the Debye length of electrons in the charge generation layer 12, and the static electricity generated by the amplification circuit formation wells 18 R, 18 G, 18 B and the transfer channel formation wells 19 R, 19 G, 19 B The effect of electrical potential may be prevented from being screened by electrons.

For example, the impurity density of the substrate 11 is 2 × 10 ¹⁴ cm ⁻³ , the impurity density of the pinning layer 14G is 1 × 10 ¹⁹ cm ⁻³ , the thickness d1 = 0.2 μm; the impurity density of the surface buried region 13G is 5 × 10 ¹⁶ cm ⁻³ , its thickness d2 = 0.3 μm; the charge generation layer 12 has an impurity density of 1 × 10 ¹³ cm ⁻³ and its thickness d3 = 22 μm, and the amplification circuit formation well 18G and the transfer channel formation well 19G In a one-dimensional model having no p ⁺ -n-π-n structure, when the potential of the substrate 11 is set to the second potential (high potential) VH = 5.1 V, as shown in FIG. The barrier heights of the potential barriers VB1 and VB3 formed in (1) are about 0.025 V, and it can be seen that the potential barriers VB1 and VB3 are hardly formed.

On the other hand, as shown in FIG. 15, the impurity density of the substrate 11 is 2 × 10 ¹⁴ cm ⁻³ , the impurity density of the pinning layer 14G is 1 × 10 ¹⁹ cm ⁻³ , its thickness d1 = 0.2 μm; The impurity density of the charge generation layer 12 is set to 1 × 10 ¹³ cm ⁻³ and the thickness d3 = 20 μm, and the surface buried region 13G is formed to have an impurity density of 5 × 10 ¹⁶ cm ⁻³ and a thickness d2 = 0.3 μm. In a one-dimensional model of a p ⁺ -np-π-n structure in which a p layer 10G having an impurity density of 4 × 10 ¹⁵ cm ⁻³ and a thickness d9 = 0.5 μm is inserted between the charge generation layers 12 and A potential barrier having a barrier height of about 0.83 V is formed in the p layer 10G.

On the other hand, for example, the impurity density of the substrate 11 is 2 × 10 ¹⁴ cm ⁻³ , the impurity density of the pinning layer 14G is 1 × 10 ¹⁸ cm ⁻³ , the thickness d1 = 0.1 μm; the impurity density of the surface buried region 13G 3 × 10 ¹⁷ cm ⁻³ , its thickness d2 = 0.2 μm; Impurity density of the amplification circuit forming well 18G 3 × 10 ¹⁷ cm ⁻³ , its thickness d7 = 0.9 μm; Impurity density of the transfer channel forming well 19G 3 × 10 ¹⁷ cm ⁻³ , its thickness d7 = 0.9 μm; impurity density 1 × 10 ¹⁶ cm ^{−3 of} the block layer 21G, its thickness d8 = 0.4 μm; well spacing w _{1 in the} row direction = 2. 8 μm; Under the condition of well spacing l ₁ = 3.8 μm in the column direction, the thickness d3 of the charge generation layer 12 is set to 25 μm, and the impurity density is 1 × 10 ¹³ cm ⁻³ , 5 × 10 ¹² cm ^{−. 3,} 1 in the case of changing a × 10 ¹² cm ^-3 is that shown in FIG. 6 Similarly, any more than 0.5V in the charge generating layer 12 of the barrier height of the potential barrier that is formed, has been confirmed by simulation.

  As described above, in the color imaging device according to the second embodiment, the barrier height VB1, which prevents electrons from flowing out from the surface buried regions 13R, 13G, 13B to the substrate 11 in the charge generation layer 12, is provided. By forming the peak of the potential of VB3, it becomes possible to change the effective depth during infrared imaging and color imaging while maintaining the accumulation operation by changing the potential of the substrate 11.

  The description of the color imaging device according to the second embodiment is intended to achieve both color imaging and infrared imaging, but the color imaging device according to the second embodiment is limited to this. However, the present invention can be applied to a case where only color imaging is intended. That is, in the conventional color imaging, as described with reference to FIG. 24, IRC is indispensable. However, according to the color imaging apparatus according to the second embodiment, the method described in FIGS. Among these, by using the color imaging portion, it is possible to perform good color imaging without IRC. Others are substantially the same as those of the color imaging apparatus according to the first embodiment, and a duplicate description is omitted.

(Third embodiment)
The outline of the layout on the semiconductor chip of the color imaging device (two-dimensional color image sensor) according to the third embodiment of the present invention is the same as that of the color imaging device according to the first embodiment shown in FIG. Therefore, a duplicate description is omitted. However, although a three-color stripe type color filter array is illustrated in FIG. 1, the present invention is not limited to this, and various color filter arrays as shown in FIGS. 18 to 21 can be employed.

16 shows the R pixel X _ij−1 , G pixel X _ij , B pixel X _{ij + 1} ,..., R pixel X _{i + 1j−1} , G pixel X _{i + 1j} , B pixel X shown in FIG. A part of the periodic arrangement of _{i + 1j + 1,.} That is, R pixels X _ij−1 , G pixels X _ij , and B pixels X _{ij + 1} are periodically arranged in units of R photodiode PD _ij−1 , G photodiode PD _ij , and B photodiode PD _{ij +, respectively. 1} , and second conductivity type wells 18R, 18G, 18B and second conductivity type (p type) amplifier circuit forming wells 18R, 18G, 18B arranged adjacent to the photodiodes PD _ij-1 , PD _ij , PD _{ij + 1} , respectively. p-type) transfer channel formation wells 19R, 19G, and 19B are provided as a planar positional relationship. The amplification circuit formation wells 18R, 18G, 18B,... Are respectively regions between photodiodes PD _ij-2 (not shown) and photodiodes PD _ij-1 adjacent to each other in the row direction, and photodiodes PD _ij−1 . Element isolation is performed in a region between the photodiodes PD _ij , a region between the photodiodes PD _ij and the photodiodes PD _{ij + 1} , and a region between the photodiodes PD _{ij + 1} and the photodiodes PD _{ij + 2} (not shown). Similarly, a region between photodiodes PD _ij-1 and photodiodes PD _{i + 1j-1} adjacent in the column direction, a region between photodiodes PD _ij and photodiodes PD _{i + 1j} , photodiode PD _An element isolation region is formed in a region between _{ij + 1} and the photodiode PD _{i + 1j + 1} . The amplifier circuit formation wells 18R, 18G, and 18B and the transfer channel formation wells 19R, 19G, and 19B are semiconductor regions having an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less.

In the color imaging device according to the second embodiment shown in FIG. 11, each photodiode PD _{i, j−1} , PD _{i, j} , PD _{i, j + 1} ,..., PD _{i + 1, j −1} , PD _{i + 1, j} , PD _{i + 1, j + 1} ,..., First conductivity type surface buried regions 13R, 13G, 13B and their surrounding amplification circuit forming wells 18R, 18G, 18B and the transfer channel forming wells 19R, 19G, and 19B are in contact with each other, but slightly around the surface buried regions 13R, 13G, and 13B as shown in FIG. A gap exists, and only the p ⁺ type pinning layers 14R, 14G, and 14B exist on the silicon surface corresponding to this portion. If the gap is small, hole diffusion into the charge generation layer 12 can be suppressed to a small extent.

FIG. 17 corresponds to a cross-sectional view seen from the XVII-XVII direction of FIG. 16, and R pixel X _ij-1 and G pixel X constituting the pixel array unit 1 of the amplification type solid-state imaging device of the third embodiment. A cross-sectional structure of one unit of a periodic arrangement of _ij and B pixel X _{ij + 1} is shown. As shown in FIG. 17, an impurity density of 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less is formed on a substrate 11 made of silicon of the first conductivity type (n-type). The charge generation layer 12 made of a second conductivity type (π-type) epitaxial layer close to an intrinsic semiconductor of 10 ¹⁴ cm ⁻³ or less and 1 × 10 ¹¹ cm ⁻³ or more is formed so that the thickness a becomes 10 μm or more and 50 μm or less. The R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} are configured to form one unit of the RGB periodic array of the color imaging apparatus according to the third embodiment. Yes. In the R pixel X _ij−1 , the charge generation layer 12 close to the second conductivity type (p-type) intrinsic semiconductor is used as an anode region, and the first conductivity type (n-type) surface buried region 13R is used as a cathode region. A 4-transistor type R pixel X _ij-1 is configured, which includes a diode PD _ij-1 and in which one transfer transistor and a three-transistor amplifier circuit A _ij-1 are arranged in one pixel region (FIG. 5). reference.). In the G pixel X _ij , a photodiode PD _ij is configured with the charge generation layer 12 as an anode region and the first conductivity type surface buried region 13G as a cathode region, and one transfer transistor and 3 A 4-transistor type G pixel X _{ij in} which the transistor amplification circuits A _ij are respectively arranged is configured. In the B pixel X _{ij + 1} , a photodiode PD _{ij + 1} is configured with the charge generation layer 12 as an anode region and the first conductivity type surface buried region 13B as a cathode region, and one pixel region includes one photodiode PD _{ij + 1} . A four-transistor type B pixel X _{ij + 1} in which a transfer transistor and a three-transistor amplification circuit A _{ij + 1} are respectively arranged is configured. Then, R photodiode PD _ij-1, the R color filter 31R is formed on the, G color filters 31R on top of G photodiode PD _ij is, B photodiode PD _{ij + 1} of B color filter 31R is formed on Is provided.

As shown in FIG. 17, the second conductivity type ( ^{p.sup. +} Type) pinning layer 14R is formed on the surface buried regions 13R, 13G, and 13B of the photodiodes _PD.sub.ij-1 , _PD.sub.ij , and _{PD.sub.ij + 1.} , 14G, 14B are formed. The pinning layers 14R, 14G, and 14B are layers that suppress the generation of carriers on the dark surface. As indicated by the hidden lines in FIG. 16, the surface buried regions 13R, 13G, and 13B are located on the left side of the lower surfaces of the pinning layers 14R, 14G, and 14B below the pinning layers 14R, 14G, and 14B, respectively. The pinning layers 14R, 14G, and 14B are in contact with the lower surfaces of the pinning layers 14R, 14G, and 14B so as to be partially exposed.

In the R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} of the color imaging device according to the third embodiment shown in FIGS. 16 and 17, the entire charge generation layer 12 is made to have an extremely low impurity density. The depletion layer extends toward the substrate 11 from the interface between the first conductivity type surface buried regions 13R, 13G, and 13B and the second conductivity type charge generation layer 12 because it is in a state close to an intrinsic semiconductor. Deep. That is, the impurity density of the charge generation layer 12 forming the photodiodes PD _ij−1 , PD _ij , PD _{ij + 1} of the R pixel X _ij−1 , G pixel X _ij , and B pixel X _{ij + 1} is 1 ×. In a state close to an intrinsic semiconductor of 10 ¹³ cm ⁻³ or less, the depth of the depletion layer end is 15 μm or more, so that most of the charge generation layer 12 is depleted. Therefore, as shown in FIG. 7, sufficient sensitivity can be maintained even with near-infrared light having a wavelength of 800 nm or more that penetrates 10 μm or more into silicon.

As described above, the color imaging device according to the third embodiment employs the charge generation layer 12 close to an intrinsic semiconductor, as in the color imaging devices according to the first and second embodiments, and thus a photodiode. A depletion layer in the PD _ij−1 , PD _ij , and PD _{ij + 1} regions is formed deeply to ensure high infrared sensitivity and low crosstalk, and then the potential of the substrate 11 is changed to the first potential (low potential) VL, And substrate potential switching means for switching to a second potential (high potential) VH that is higher than the first potential. Various semiconductor switches such as transistors can be used for switching the substrate potential, but mechanical switches may be used.

  In the color imaging device according to the third embodiment, the potential for preventing the injection of electrons formed in the charge generation layer 12 when the potential of the substrate 11 is the first potential (low potential) VL. Of the first potential VL, the impurity density of the substrate 11, the impurity density of the charge generation layer 12 and its thickness d3, the impurity density of the pinning layers 14R, 14G and 14B and its thickness d1, Impurity density and thickness d2 of the surface buried regions 13R, 13G, and 13B, impurity density and thickness d7 of the amplifier circuit forming wells 18R, 18G, and 18B, impurity density of the transfer channel forming wells 19R, 19G, and 19B and the thickness thereof It depends on the thickness d7 and the planar layout.

Further, when the potential of the substrate 11 is the second potential (high potential) VH, the potential barrier heights VB1 and VB3 are the values of the second potential (high potential) VH, the impurity density of the substrate 11, and Impurity density of charge generation layer 12 and its thickness d3, impurity density of pinning layers 14R, 14G and 14B, its thickness d1, impurity density of surface buried regions 13R, 13G and 13B and its thickness d2, formation of amplifier circuit It depends on the impurity density and thickness d7 of the wells 18R, 18G and 18B, the impurity density and thickness d7 of the transfer channel forming wells 19R, 19G and 19B, and the planar layout. The planar layout, spacing w ₁ of the amplifier circuit forming well 18B and the transfer channel forming wells 19R shown in FIG. 17, the interval w ₁ between the amplifier circuit forming well 18R and the transfer channel formation well 19G, the amplifier circuit forming well 18G Although not shown, the interval w ₁ between the amplifying circuit forming well 18G and the amplifying circuit forming well 18R, the interval l ₁ between the amplifying circuit forming well 18G and the amplifying circuit forming well 18G along the column direction is omitted. distance l ₁ between the distance l ₁ and the amplification circuit forming well 18B of the amplifier circuit forming well 18R and amplifier circuit forming well 18B is important. The well interval w _{1 in the} row direction and the well interval l _{1 in the} column direction are set to a distance within twice the Debye length of electrons in the charge generation layer 12, and the amplification circuit formation wells 18R, 18G, 18B and the transfer channel formation well 19R , 19G, 19B is the same as the color imaging device according to the first and second embodiments that the effect of the electrostatic potential should not be screened by electrons.

  As described above, in the color imaging device according to the third embodiment, the barrier height VB1, which prevents electrons from flowing out from the surface buried regions 13R, 13G, 13B to the substrate 11 in the charge generation layer 12. By forming the peak of the potential of VB3, it becomes possible to change the effective depth during infrared imaging and color imaging while maintaining the accumulation operation by changing the potential of the substrate 11.

  The description of the color imaging device according to the third embodiment is intended to achieve both color imaging and infrared imaging, but the color imaging device according to the third embodiment is limited to this. However, the present invention can be applied to a case where only color imaging is intended. Others are substantially the same as those of the color imaging apparatus according to the first and second embodiments, and thus redundant description is omitted.

(Other embodiments)
As described above, the present invention has been described according to the first to third embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In the description of the first to third embodiments already described, the first conductivity type is n-type and the second conductivity type is p-type. However, the second conductivity type is n-type and the first conductivity type is first-type. Even in the case of the p-type, it can be easily understood that the same effect can be obtained if the electrical polarity is reversed (in this case, if attention is paid to the photodiodes PD _ij , PD _{ij + 1,.} It will not be necessary to explain that the first main electrode region of the mold becomes the cathode region and the second main electrode region of the p type becomes the anode region.

  1 illustrates a three-color stripe type color filter array, but a Bayer type checkered color filter array as shown in FIG. 18 or a checkered color filter array as shown in FIG. 19 may be used. Further, as shown in FIG. 20, a color filter array using complementary color filters such as cyan (Cy), magenta (Mg), and yellow (Ye) may be used, and includes white (W) pixels as shown in FIG. It can be easily understood that the technical idea of the present invention can be applied to a color filter array.

  Furthermore, in the description of the first to third embodiments, the case of silicon as the semiconductor material has been described. However, even in the case of other semiconductors such as germanium (Ge) and gallium arsenide (GaAs), the semiconductor material The technical idea of the present invention can be similarly applied if the relative dielectric constant is appropriately modified in consideration of the impurity density of the intrinsic semiconductor.

  Further, for example, in the description of the first embodiment, the two-dimensional solid-state imaging device (area sensor) has been exemplarily described. However, in the two-dimensional matrix shown in FIG. It should be easily understood from the contents of the above disclosure that a plurality of semiconductor light receiving elements may be arranged one-dimensionally as pixels of a three-dimensional solid-state imaging device (line sensor).

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a schematic plan view illustrating a layout on a semiconductor chip of a color imaging device (two-dimensional solid-state imaging device) according to a first embodiment of the present invention. It is a top view which paid its attention to six pixels of the color imaging device concerning a 1st embodiment. It is a figure which shows the structure of the pixel part of the color imaging device which concerns on 1st Embodiment shown in FIG. 1 in a cross section (it corresponds to sectional drawing along the III-III direction of FIG. 2). It is sectional drawing along the IV-IV direction of FIG. 3 is a circuit diagram showing a specific example of a three-transistor amplifier circuit arranged in each pixel of the color imaging device according to the first embodiment. FIG. It is a potential diagram explaining the peak of a potential formed in a depletion layer at the time of infrared imaging and color imaging, respectively. It is a figure which shows the relationship between an incident light wavelength and the penetration depth in a silicon | silicone. It is a figure which shows potential distribution in the path | route from the photodiode which comprises the pixel of the color imaging device which concerns on 1st Embodiment to an electric charge detection area | region. It is a figure which shows the difference in the spectral characteristics at the time of changing the electric potential of a board | substrate in the color imaging device which concerns on 1st Embodiment. In the color imaging device according to the first embodiment, it is a diagram illustrating spectral characteristics in which infrared components that are still slightly remaining in the color signals R, G, and B at the time of color imaging are completely suppressed. It is a top view which paid its attention to six pixels of the color imaging device which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the pixel part of the color imaging device which concerns on 2nd Embodiment shown in FIG. 11 in one cross section (it corresponds to sectional drawing along the XII-XII direction of FIG. 11). It is sectional drawing along the XIII-XIII direction of FIG. In order to study a color imaging device according to the second embodiment of the present invention, a one-dimensional model of a p ⁺ -n-π-n structure formed by a pinning layer / surface buried region / charge generation layer / substrate is used. FIG. 6 is a potential diagram showing a peak of potential formed in a depletion layer. In order to study a color imaging device according to the second embodiment of the present invention, a p ⁺ -np-π-n structure in which a p layer is inserted into the p ⁺ -n-π-n structure of FIG. 2 is a potential diagram showing a potential peak formed in a depletion layer using a one-dimensional model. It is a top view which paid its attention to six pixels of the color imaging device which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structure of the pixel part of the color imaging device which concerns on 3rd Embodiment shown in FIG. 16 in one cross section (it is equivalent to sectional drawing along the XVII-XVII direction of FIG. 16). FIG. 5 is a schematic plan view for explaining a layout on a semiconductor chip of a color imaging device having a Bayer checkered color filter array. It is a schematic diagram explaining another checkered color filter array. It is a schematic diagram explaining the color filter array using complementary color filters, such as cyan (Cy), magenta (Mg), and yellow (Ye). It is a schematic diagram explaining a checkered color filter array including white (W) pixels. It is sectional drawing of the pixel part of the conventional amplification type solid-state imaging device. It is sectional drawing of the pixel part of the conventional color imaging device which arranged three primary color filters of red (R), green (G), and blue (B) on each pixel. This is the spectral characteristic of the three primary color filters of red (R), green (G), and blue (B). It is a schematic diagram explaining the system which inserts IRC in the front of an image sensor at the time of color imaging, and removes IRC from the front of an image sensor at the time of infrared imaging.

Explanation of symbols

A _ij ... Amplifier circuit B _j ... Vertical signal line CS _ij ... Charge storage diode (charge storage element)
CTP ... Charge drift path D _ij ... Detection circuit PD _ij ... Photodiode (embedded photodiode)
Qj: column processing circuit TR _ij ... reset transistor TS _ij ... switching transistor TR _ij ... reset transistor T _LNj ... constant current transistor 1 ... pixel array section 4 ... timing generation circuit 5 ... signal processing section 7 ... bias generation circuit 10G ... p layer DESCRIPTION OF SYMBOLS 11 ... Substrate 12 ... Charge generation layer 13R, 13G, 13B ... Surface embedding region 14R, 14G, 14B ... Pinning layer 15R, 15G, 15B ... Transfer gate electrode 16R, 16G, 16B ... Charge detection region 18R, 18G, 18B ... Amplification circuit forming wells 19R, 19G, 19B ... Transfer channel forming wells 20R, 20G, 20B ... Top contact regions 21R, 21G, 21B ... Block layers 31R, 31G, 31B ... Color filters 51R, 51G, 51B ... Gate electrodes 52R, 52G , 52B ... Source regions 53R, 53G, 53B ... Drain regions 54R, 54G, 54B ... Drain regions 55R, 55G, 55B ... Gate electrodes 56R, 56G, 56B ... Source / drain shared regions 57R, 57G, 57B ... Gate electrodes 58R, 58G , 58B ... Source region 61 ... Image sensor 62 ... Imaging lens 63 ... IRC
64 ... Detachable device 111 ... Substrate 113 ... N-type surface buried region 114 ... Pinning layer 115 ... Transfer gate electrode 116 ... Charge detection floating diffusion region 117 ... Transistor amplifier circuit 118 ... Well 151 ... Gate electrode 152 ... Source region 153 ... Drain region 312... Π epi layer 401R, 401G, 401B... Primary color filter

Claims (8)

A color imaging device in which color filters having different wavelength characteristics are arranged on a plurality of adjacent pixels, each of the plurality of pixels,
A substrate made of a semiconductor of the first conductivity type and having an impurity density of 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less;
A charge generation layer provided on the substrate and comprising a semiconductor layer of a second conductivity type and having an impurity density of 1 × 10 ¹⁴ cm ⁻³ or less and 1 × 10 ¹¹ cm ⁻³ or more, and a thickness of 10 μm or more and 50 μm or less;
A surface buried region composed of a semiconductor region of a first conductivity type embedded in a part of an upper portion of the charge generation layer so as to constitute the photoelectric conversion element and the charge generation layer;
A planar pattern embedded in another part of the upper portion of the charge generation layer to a position deeper than the lower surface of the surface buried region so as to function as an inter-pixel separation region for electrically separating the plurality of pixels. A transfer channel forming well and an amplifier circuit forming well having a second conductivity type and an impurity density of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less surrounding the surface buried region;
A charge detection region comprising a first conductivity type semiconductor region embedded in a part of an upper portion of the transfer channel formation well, wherein a signal charge is transferred from the photoelectric conversion element;
An amplification circuit configured to amplify and read out the potential of the charge detection region, the charge generation layer being a common layer of the plurality of pixels, and the substrate By applying a first electric potential and a second electric potential higher than the first electric potential to each pixel, the position of the potential barrier generated in the charge generation layer in each pixel is embedded in the surface from the substrate side. A color imaging apparatus, characterized by being moved to an area side. The pixel is
An insulating film provided on the surface of the transfer channel forming well;
A transfer gate electrode provided on the insulating film between the photoelectric conversion element and the charge detection region;
The surface buried region, the charge detection region, and the transfer gate electrode transfer signal charges from the surface buried region to the charge detection region via a transfer channel provided above the transfer channel formation well. The color imaging device according to claim 1, wherein a transfer transistor is configured.   3. The color imaging device according to claim 1, wherein a junction depth of the amplification circuit formation well and the transfer channel formation well is 2 to 5 times a junction depth of the surface buried region.   4. The color imaging device according to claim 1, wherein junction depths of the amplification circuit formation well and the transfer channel formation well are equal. 5.   5. The color imaging device according to claim 1, wherein an impurity density of the amplification circuit formation well is higher than an impurity density of the transfer channel formation well. 6.   An interval between the amplification circuit formation well and the transfer channel formation well sandwiching the surface buried region, or an interval between the amplification circuit formation well and the amplification circuit formation well is determined by the amplification circuit formation well and the transfer channel formation well. The color imaging apparatus according to claim 4, wherein the color imaging apparatus has a junction depth of 3 to 6 times or less.   The color imaging apparatus according to claim 2, wherein the transfer channel has a positive potential when the transfer transistor is off.   The color imaging device according to claim 2, further comprising a contact region for fixing a potential of the transfer channel in the transfer channel formation well.