JP2010087345A - Manufacturing method of semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a semiconductor substrate for an SOI substrate or laminated substrate, which prevents an unbonded region from being formed, and to reduce the unbonded region in a manufacturing process of the SOI substrate or the laminated substrate. <P>SOLUTION: A peripheral region of a first single crystal semiconductor substrate (s101) having an edge roll off region at the peripheral part is so cut that the edge roll off region is removed, and a second single crystal semiconductor substrate (s102) having a vertical edge form is formed, to provide a semiconductor substrate for SOI substrate. The single crystal semiconductor substrate having the vertical edge form and a base substrate are bonded while interposing a buffer layer between them, and the single crystal semiconductor substrate on the base substrate is made thinner, to manufacture the SOI substrate. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate. In particular, the present invention relates to a substrate bonding technique and relates to a method for manufacturing an SOI (Silicon On Insulator) substrate.

  Applications of substrate bonding technology are expanding. In particular, the bonded SOI technology is attracting attention as a key to the development of VLSI technology.

  In the bonded SOI technology, a bond substrate and a base substrate are bonded together, and the bond substrate is thinned to form a semiconductor thin film on the base substrate. A buffer layer such as an insulating layer is provided between the bond substrate and the base substrate. Substrates manufactured by the bonded SOI technology have already been put into practical use and mass-produced. Among them, Smartcut (registered trademark) technology and ELTRAN (registered trademark) technology have an advantage that the bond substrate can be reused. For example, the Smartcut (registered trademark) technology forms a microbubble layer by ion-implanting hydrogen into a single crystal silicon substrate which is a bond substrate. In this technique, the bond substrate is cleaved by the microbubble layer by heat treatment, and the single crystal silicon thin film is bonded to the single crystal silicon substrate which is a base substrate (see Patent Document 1).

  A new bonded SOI technology using a substrate different from a single crystal silicon substrate, such as a glass substrate, as a base substrate is also being researched and developed. For example, a technique for forming a single crystal silicon thin film on a crystallized glass substrate which is a high heat resistant glass has been developed (see Patent Document 2).

  Also disclosed is a technique for manufacturing a large-area thin-film single-crystal silicon substrate using a composite substrate in which a plurality of silicon substrates are arranged and bonded on a large-area carbon-based substrate. A porous Si layer is formed on the silicon substrate of the composite substrate, an epitaxial growth layer is formed on the porous Si layer, and a thermal oxide film is formed on the epitaxial growth layer. A thermal oxide film and a glass substrate are bonded together to bond the composite substrate and the glass substrate, and the porous Si layer is peeled off as a peeling layer to produce a large-area thin-film single crystal silicon substrate composed of an epitaxial growth layer ( (See Patent Document 3).

  By the way, in the manufacturing process of the SOI substrate, the bonding strength at the bonding interface between the bond substrate and the base substrate is one of important factors. In particular, in a manufacturing process of an SOI substrate in which a surface thin film layer of a bond substrate typified by Smartcut (registered trademark) technology is fixed to a base substrate, in order to obtain sufficient bonding strength, a bonding surface on the bond substrate side and a base It is necessary that the surface flatness of the bonding surface on the substrate side is excellent.

  In general, polishing is performed to planarize the substrate surface. In particular, when excellent surface flatness is required, such as a substrate used in a substrate bonding technique, polishing is performed by chemical mechanical polishing. Chemical mechanical polishing is a polishing method suitable for improving the flatness of the substrate surface. However, on the other hand, after chemical mechanical polishing, an edge roll-off (ERO) edge region is formed at the peripheral edge of the substrate, and the flatness of the peripheral edge of the substrate is said to be lower than at the center of the substrate. The edge roll-off region is formed with a width of several mm (for example, 2 mm to 3 mm) at the peripheral edge of the substrate. As a main factor for forming the edge roll-off region, polishing sagging caused by chemical mechanical polishing is cited.

  Since the edge of the substrate on which the edge roll-off region is formed has low flatness, it is difficult to form a bond. Therefore, in the manufacturing process of the SOI substrate, there is a problem that an unbonded region is generated at the peripheral portion of the substrate having low flatness. In addition, even when bonded, there is a problem that the bonding strength tends to be weak compared to other regions (for example, the central portion of the substrate having good flatness).

Therefore, a method of devising a polishing process and a chamfering process for substrates used for bonding in order to reduce unbonded regions has been disclosed (see Patent Document 4). Here, it is disclosed that after the chamfered substrate is mirror-polished, the chamfering is performed again to incorporate the polishing sag into the chamfering width, thereby reducing the polishing sag.
JP-A-5-211128 JP 11-163363 A JP 2003-257804 A JP 2001-345435 A

  The planarization of the substrate surface by chemical mechanical polishing and the formation of the edge roll-off region are in a trade-off relationship. In order to obtain excellent surface flatness, a flattening process by chemical mechanical polishing is suitable. However, an edge roll-off region is formed at the peripheral edge of the substrate by chemical mechanical polishing. By chemical mechanical polishing, the flatness is improved when viewed from the entire surface of the substrate, but the flatness is degraded when the peripheral edge of the substrate is viewed.

  The edge roll-off region becomes a factor that causes an unbonded region in manufacturing an SOI substrate and a bonded substrate. The unbonded region is generated in a bonding step or a division step in the manufacturing process of the SOI substrate or the bonded substrate, and the unbonded region is a trigger and causes film peeling. When a bonding failure such as film peeling occurs, the yield of the SOI substrate and the bonded substrate is lowered. Furthermore, when an element is formed using such an SOI substrate or the like, film peeling or the like may occur even during the formation of the element, which causes a decrease in the yield of the element.

  In view of the above problems, an object of the present invention is to provide a semiconductor substrate for an SOI substrate or a bonded substrate that prevents formation of an unbonded region. Another object is to provide a semiconductor substrate for an SOI substrate or a bonded substrate which prevents a decrease in yield. Another object is to reduce an unbonded region in a manufacturing process of an SOI substrate or a bonded substrate. Another object is to manufacture an SOI substrate or a bonded substrate with high yield.

  The gist of the present invention is to provide a semiconductor substrate for an SOI substrate or a bonded substrate which prevents an unbonded region from being formed in the peripheral portion in the manufacturing process. Another gist of the present invention is to provide an SOI substrate or a bonded substrate in which the unbonded region at the peripheral portion is reduced.

  Note that an unbonded region in this specification refers to a poor adhesion portion that occurs in a step of bonding a bond substrate and a base substrate, a step of dividing the bonded bond substrate, and the like.

  In the present invention, a single crystal semiconductor substrate is used as an SOI substrate or a bond substrate for manufacturing an SOI substrate. By improving the flatness of the peripheral edge of the single crystal semiconductor substrate, bonding failure with the base substrate is suppressed, and the unbonded region is reduced.

  The single crystal semiconductor substrate is formed by removing a region with low flatness such as an edge roll-off region after surface polishing by chemical mechanical polishing (CMP; Chemical Mechanical Polishing), thereby forming a single crystal semiconductor substrate having a vertical edge shape. Improves the flatness of the peripheral edge.

  Note that preferably, when the single crystal semiconductor substrate is formed into a desired shape, the single crystal semiconductor substrate is cut so that the edge roll-off region is removed, so that the single crystal semiconductor substrate has a vertical edge shape. Alternatively, chamfering is performed on an edge portion of a single crystal semiconductor substrate having a vertical edge shape. By doing so, it is possible to provide a bond substrate having a desired shape and improved flatness up to the peripheral edge of the substrate. Then, a bonded substrate or an SOI substrate is manufactured by bonding the bond substrate to a base substrate and performing thinning or the like as appropriate.

  According to one aspect of the present invention, a peripheral region of a first single crystal semiconductor substrate having an edge roll-off region at a peripheral portion is cut so that the edge roll-off region is removed, and a second single unit having a vertical edge shape is cut. This is a method for manufacturing a semiconductor substrate for an SOI substrate for manufacturing a crystalline semiconductor substrate.

  In the above structure, chamfering can be performed on an edge portion which is perpendicular to the second single crystal semiconductor substrate.

  The second single crystal semiconductor substrate is cut into a vertical edge shape so that the angle of the edge portion is in the range of 90 ° ± 10 °.

  The second single crystal semiconductor substrate is preferably a quadrangular shape in plan view.

  Another aspect of the present invention is an SOI in which a single crystal semiconductor substrate having a vertical edge shape and a base substrate are bonded to each other with a buffer layer interposed therebetween, and the single crystal semiconductor substrate over the base substrate is thinned. This is a method for manufacturing a substrate.

  In the above structure, the single crystal semiconductor substrate can be thinned by forming an embrittlement layer inside the single crystal semiconductor substrate and dividing the single crystal semiconductor substrate with the embrittlement layer as a boundary.

  In addition, the single crystal semiconductor substrate is cut into a vertical edge shape so that the edge portion has an angle of 90 ° ± 10 °.

  In the above structure, the edge portion which is perpendicular to the single crystal semiconductor substrate is chamfered, and the single crystal semiconductor substrate which has been chamfered can be used for bonding to the base substrate.

  In the above structure, a single crystal semiconductor substrate having a vertical edge shape is obtained by cutting a peripheral region of a single crystal semiconductor substrate having an edge roll-off region at a peripheral portion so that the edge roll-off region is removed. Can be done.

  Note that the single crystal semiconductor substrate having a vertical edge shape is preferably square.

  Further, a glass substrate is preferably used as the base substrate.

  Further, in this specification, “single crystal” refers to a crystal having a crystal plane and a crystal axis that are aligned, and atoms or molecules constituting the crystal are spatially ordered. However, a single crystal is composed of regularly arranged atoms, but also includes those that include lattice defects that have some disorder in this arrangement, and those that intentionally or unintentionally have lattice distortion. .

  In addition, the “brittle layer” in this specification refers to a region where a single crystal semiconductor substrate is divided and its vicinity in a division step. Although the state of the “brittle layer” varies depending on the means for forming the “brittle layer”, for example, the “brittle layer” is a region where the crystal structure is locally disturbed and weakened. In some cases, the region from the surface side of the single crystal semiconductor substrate to the “brittle layer” may be somewhat weakened, but the “brittle layer” in this specification refers to the region to be divided later and its vicinity. Shall be pointed to.

  In addition, in this specification, terms with numerals such as “first”, “second”, or “third” are given for convenience in order to distinguish elements and are limited numerically. It is not intended to limit the order of arrangement and steps.

  According to the present invention, a semiconductor substrate for an SOI substrate or a bonded substrate that can suppress formation of an unbonded region or a decrease in yield can be provided. In addition, in the manufacturing process of the SOI substrate or the bonded substrate, it is possible to prevent an unbonded region from being formed in the peripheral portion, and it is possible to suppress defects such as bonding failure and film peeling. As a result, an SOI substrate and a bonded substrate can be manufactured with high yield.

  Embodiments of the present invention will be described below with reference to the drawings. However, it will be readily understood by those skilled in the art that the present invention can be implemented in many different modes, and that the forms and details can be changed without departing from the spirit and scope of the present invention. . Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
FIG. 1 shows a flow of processing steps of a semiconductor substrate for an SOI substrate or a bonded substrate according to the present invention and a flow of manufacturing steps of the SOI substrate or the bonded substrate.

  First, a flow of processing steps of a semiconductor substrate for an SOI substrate or a bonded substrate will be described.

  A first single crystal semiconductor substrate having a polished surface and an edge roll-off region at the peripheral edge (in FIG. 1, (s101), the edge roll-off region is removed from the peripheral region of the first single crystal semiconductor substrate. By cutting, a second single crystal semiconductor substrate having a vertical edge shape is manufactured ((s102) in FIG. 1).

  At least one surface of the first single crystal semiconductor substrate is polished by chemical mechanical polishing. In addition, the first single crystal semiconductor substrate has an edge roll-off region in the peripheral portion on the polished surface side. Note that a polycrystalline semiconductor substrate may be used instead of the single crystal semiconductor substrate. In that case, “single crystal” in the following description is replaced with “polycrystal”.

  A peripheral region of the first single crystal semiconductor substrate having the edge roll-off region is cut so that the edge roll-off region is removed, and a second single crystal semiconductor substrate having a vertical edge shape is manufactured. The flatness can be improved up to the peripheral edge of the substrate.

  In this specification, “vertical” means that the angle of the edge portion is in the range of 90 ° ± 10 °, preferably 90 ° ± 5 °.

  FIG. 2A illustrates an example in which the first single crystal semiconductor substrate 1003 having an edge roll-off region is cut to manufacture a second single crystal semiconductor substrate 1005 having a vertical edge shape. FIG. 2B is an enlarged cross-sectional view between line segments XY on the side surface of the peripheral edge portion of the second single crystal semiconductor substrate 1005 illustrated in FIG. FIGS. 2C and 2D are enlarged cross-sectional views taken along a line segment OP on the side surface in the peripheral portion of the first single crystal semiconductor substrate 1003 shown in FIG.

  The first single crystal semiconductor substrate 1003 has a polished surface and an edge roll-off region. As shown in FIGS. 2C and 2D, the peripheral edge portion of the first single crystal semiconductor substrate 1003 is thinner than the center side of the substrate and has a shape leaning from the center of the substrate to the side surface. A region 1015 is an edge roll-off region, and is a region that is thinner and less flat than the substrate center side. The length Le and the shape from the side surface of the region 1015 vary depending on the conditions of the polishing process.

  Note that a commercially available silicon wafer can be used as the first single crystal semiconductor substrate. In the conventional manufacturing method, a distributed silicon wafer is cut out of a disk-shaped wafer from a semiconductor ingot, then chamfered and then mirror-polished (polished by CMP). For this reason, in many commercially available silicon wafers, a chamfered portion and an edge roll-off region are formed on the periphery of the substrate. For this reason, as shown in FIG. 2D, a region 1016 having low flatness in which a chamfered portion and an edge roll-off region are formed is provided. Depending on the conditions of the chamfering process and the polishing process, the length Le ′ from the side surface of the region 1016 and the shape change. In a commercially available silicon wafer or the like, the chamfered portion is formed with a width of approximately 0.2 mm to 0.5 mm, and the edge roll-off region is formed with a width of approximately 2 mm to 3 mm.

  On the other hand, in the present invention, as shown in FIG. 2B, the angle of the edge portion 1012 of the side surface 1011 at the peripheral edge portion of the second single crystal semiconductor substrate 1005 is vertical (90 ° ± 10 °, preferably 90 ° The first single crystal semiconductor substrate 1003 is cut so as to be in a range of ± 5 °. By cutting the peripheral region of the first single crystal semiconductor substrate 1003 having an edge roll-off region so that the edge roll-off region is removed, a region with low flatness is eliminated or a single crystal semiconductor substrate with a reduced level is obtained. Can be produced.

  The second single crystal semiconductor substrate 1005 is planarized because the substrate surface is polished by chemical mechanical polishing, and further planarized to the peripheral portion in order to remove regions with low flatness such as edge roll-off regions. As a result, the flatness of the entire substrate surface is improved. The flatness of the substrate surface is an important parameter related to the possibility of bonding and bonding strength in the production of SOI substrates and bonded substrates. By improving the flatness of the substrate surface, formation of an unbonded region can be prevented in manufacturing an SOI substrate and a bonded substrate, and the substrate can be preferably used as an SOI substrate or a semiconductor substrate for a bonded substrate. it can.

  Further, by improving the flatness of the substrate surface, the bonding strength of the manufactured SOI substrate and the bonded substrate is increased, and deterioration in quality and yield due to poor adhesion can be suppressed during and after the production.

  Here, an example until a first single crystal semiconductor substrate having a polished surface and an edge roll-off region at the peripheral edge is obtained will be described with reference to FIGS.

  As the first single crystal semiconductor substrate, a single crystal semiconductor substrate made of a group 14 element of the periodic table, such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate, can be given. In addition, a compound semiconductor substrate such as gallium arsenide or indium can be used.

  As the first single crystal semiconductor substrate, a disk-shaped substrate cut out from a semiconductor ingot to a predetermined thickness can be used. Many of the semiconductor ingots serving as a base are cylindrical, and a disk-shaped single crystal semiconductor substrate is manufactured by cutting the cylindrical semiconductor ingot to a predetermined thickness.

  In addition, the disc shape in this specification is not limited to a perfect circle, but is a substantially circular shape such as a part lacking (including an orientation flat (orientation flat), a notch, etc.) or an ellipse. Some are included in the category.

  A semiconductor ingot (typically, a single crystal silicon ingot or a polycrystalline silicon ingot) is manufactured by a CZ method or an FZ method. For example, a cylindrical single crystal silicon ingot is pulled up by the CZ method or the FZ method. A columnar single crystal silicon ingot is appropriately cut into blocks, and then cut out with a predetermined thickness to obtain a disk-shaped single crystal silicon substrate. Specifically, as shown in FIG. 3A, by cutting out with a predetermined thickness on a plane parallel to the short axis direction (bottom surface) of the cylindrical single crystal silicon ingot 101, FIG. As shown, a disk-shaped first single crystal silicon substrate 103 (first single crystal silicon substrate 103m, first single crystal silicon substrate 103m + 1... First single crystal silicon substrate 103n) is obtained. The semiconductor ingot is cut out using a cutting device such as a wire saw or an inner peripheral cutting machine.

  A single crystal semiconductor substrate cut out from a semiconductor ingot using a cutting device does not have good surface flatness. In manufacturing an SOI substrate and an SOI substrate, required flatness of a bonding surface is severe. Therefore, it is essential that the single crystal semiconductor substrate at the stage of being cut out from the semiconductor ingot be subjected to surface planarization treatment. As the planarization treatment, chemical mechanical polishing is performed. By performing chemical mechanical polishing, the flatness of the surface of the first single crystal semiconductor substrate is improved, but an edge roll-off region including polishing sagging is formed at the peripheral edge of the substrate.

  The “bonding surface” refers to a surface that forms a bond with an object such as a material layer or a material substrate. In this embodiment, since the base substrate and the bond substrate are attached to each other, a base substrate-side bonding surface and a bond substrate-side bonding surface exist.

  At least one surface of the first single crystal semiconductor substrate is polished by chemical mechanical polishing. For example, as shown in FIG. 3C, one surface of the first single crystal silicon substrate 103 is polished by a CMP apparatus 181. Here, the first single crystal silicon substrate 103 is held by the substrate holding portion (polishing head), and one surface of the first single crystal silicon substrate 103 is rotationally fixed while supplying an abrasive (slurry) at a predetermined flow rate. An example is shown in which surface polishing is performed by pressing against a pad (polishing cloth) affixed to a board. The substrate holding part and the rotating surface plate can rotate respectively. Further, the rotating surface plate can be swung. An edge roll-off region including a polishing sag is formed at the peripheral portion on the surface side pressed against the pad of the first single crystal silicon substrate 103 and polished. The configuration of the CMP apparatus that performs chemical mechanical polishing is not limited to the configuration shown in FIG.

  An edge roll-off region including a polishing sag generated by chemical mechanical polishing is formed at the peripheral edge of the first single crystal semiconductor substrate. A second single crystal semiconductor substrate having a vertical edge shape is obtained by appropriately cutting a peripheral region of the first single crystal semiconductor substrate having a polished surface and having an edge roll-off region so that the edge roll-off region is removed. It is manufactured (FIG. 3D).

  In Patent Document 3, it is assumed that a silicon substrate disposed on a carbon-based substrate is a silicon substrate whose side surface is polished vertically. The main purpose of this is to align the surface orientation of the side surfaces of adjacent silicon substrates placed on a carbon-based substrate, and the purpose is to remove peripheral portions with low flatness such as polishing sagging in this process. is not. In the first place, the silicon substrate is bonded to the carbon-based substrate for anodizing, and not directly bonded to the base substrate. The epitaxial growth layer is bonded to the base substrate. Therefore, no consideration is given to bonding failure when the bond substrate is bonded to the base substrate.

  In addition, by reducing the region with low flatness at the periphery of the substrate and improving the flatness of the entire substrate surface, the bonding strength of the entire bonding surface of the SOI substrate and the bonded substrate can be made uniform. As a result, in an SOI substrate in which two substrates (a base substrate and a bond substrate) are bonded and the bond substrate is divided into thin films, the peripheral portion of the thin film layer of the bond substrate fixed to the base substrate has a jagged shape. Can be prevented. For example, if the edge roll-off region or the like is in a shape that is inclined from the center of the substrate to the peripheral edge of the substrate, the bonding strength tends to be weakened from the peripheral edge of the substrate. When the bonding strength is weak, when the bond substrate is divided, the peripheral edge portion of the substrate cannot withstand the dividing process, and cannot be bonded to the base substrate and is easily peeled off. Also, unevenness is likely to occur in the bonding strength in regions where the flatness is low. For this reason, a region that is not bonded to the region that is bonded in the dividing step and is peeled off may appear, and the peripheral portion of the thin film layer of the bonded substrate substrate may have a jagged shape. Therefore, it is possible to prevent the peripheral portion of the thin film layer of the bond substrate from having a jagged shape by increasing the flatness to the peripheral portion of the substrate and making the bonding strength uniform. By preventing the peripheral portion of the thin film layer of the bond substrate from having a jagged shape, peeling from the peripheral portion can be suppressed.

  For example, in FIG. 3D, as shown in FIG. 2A, the first single crystal silicon substrate 103 that is disk-shaped is cut so as to remove the peripheral portion of the second single crystal. An example in which the silicon substrate 105 is formed in a rectangular shape is shown. Note that the cut edge of the first single crystal silicon substrate 103 is formed so that the edge portion of the side surface in the peripheral edge portion of the second single crystal silicon substrate 105 has a vertical shape.

  The shape of the second single crystal semiconductor substrate is not a disk shape that directly reflects the shape of the single crystal semiconductor substrate obtained by cutting a cylindrical semiconductor ingot to a predetermined thickness, but is typically a polygonal shape. It is preferable to form in a quadrangular shape. The reason why it is preferable to process the second single crystal semiconductor substrate into a quadrangular shape is that, when a SOI substrate or a bonded substrate is manufactured later, the general shape of a glass substrate that is preferably used as a base substrate is a quadrangular shape. Is mentioned. In consideration of the handling properties (handling properties) of the substrates, the configuration of the manufacturing apparatus and the conveyance line, it is preferable that the substrates to be bonded have similar shapes. Further, when forming an element, a polygonal shape is easier to take a wider effective area for forming the element than a circular shape. Even if the pattern shape exposed by an exposure apparatus (for example, a stepper using a step-and-scan method or an MPA (Mirror Projection Mask Aligner) using a mirror projection method) necessary for forming a fine element is considered. A quadrangular shape is preferable.

  In addition, the “polygonal shape” in the present specification includes shapes such as a quadrilateral, pentagon, hexagon and the like that are more than a triangle. “Rectangle” includes rectangular shapes such as a square and a rectangle. In addition, what has a hypotenuse in the corner | angular part (corner part) in a plane is also included in a category.

  Further, as shown in FIGS. 3A and 3B, a disk-shaped first single crystal semiconductor substrate is cut out by cutting a cylindrical semiconductor ingot along a plane parallel to the minor axis direction. It is preferable to cut a single single crystal semiconductor substrate to produce a rectangular second single crystal semiconductor substrate. Thus, a plurality of second single crystal semiconductor substrates having the same shape and the same dimensions can be obtained from the semiconductor ingot. In Patent Document 3 described above, the Si ingot is cut into a plurality of blocks along a plane parallel to the minor axis direction (bottom surface) to form a cylindrical cut piece. A long silicon divided substrate raw material is obtained by cutting a cylindrical cut piece in the longitudinal direction (direction perpendicular to the bottom surface). The long silicon divided substrate raw material is polished so that the edge of the peripheral edge becomes a vertical flat surface and is washed to form a long silicon substrate divided piece. Since the long silicon divided substrate raw material has a circular arc as a side surface, the plurality of cut out substrates have different widths. Accordingly, silicon substrates having different dimensions are formed. In addition, if an attempt is made to obtain a long silicon substrate divided piece having the same dimensions, it is necessary to align the divided pieces with small dimensions, resulting in an increase in wasted silicon material.

  4A to 4C, the first single crystal semiconductor substrate 1003 having a disk shape is cut to form second single crystal semiconductor substrates 1005 (1005a to 1005c) having a polygonal shape. An example is shown. 4A to 4C show a planar shape.

  For example, FIG. 4A illustrates an example in which the first single crystal semiconductor substrate 1003 is cut to form a second single crystal semiconductor substrate 1005a in a rectangular shape. Here, an example is shown in which the second single crystal semiconductor substrate 1005a having a rectangular shape is formed so as to have the maximum size inscribed in the first single crystal semiconductor substrate 1003 having a disk shape. The angle of the apex of the corner (four corners) of the second single crystal semiconductor substrate 1005a is approximately 90 °.

  In FIG. 4B, the first single crystal semiconductor substrate 1003 is cut so that the distance between opposite sides is longer than the largest rectangular region inscribed in the disc-shaped first single crystal semiconductor substrate 1003. An example in which the second single crystal semiconductor substrate 1005b is formed is shown. The peripheral edge portion of the first single crystal semiconductor substrate 1003 is cut so as to be removed. Further, here, the second single crystal semiconductor substrate 1005b has a hypotenuse (eg, a region 1030) at corners (four corners). A shape similar to a quadrangular shape as shown in FIG.

  Note that the corners (four corners) of the rectangular second single crystal semiconductor substrate 1005a illustrated in FIG. 4A are chamfered into corners (four corners) as illustrated in FIG. It is good also as a shape which has a hypotenuse.

  In FIG. 4C, the first single crystal semiconductor substrate 1003 is cut to form a hexagonal second single crystal semiconductor substrate 1005c from the disc-shaped first single crystal semiconductor substrate 1003. Is shown. The peripheral edge portion of the first single crystal semiconductor substrate 1003 is cut so as to be removed. When the shape of the second single crystal semiconductor substrate 1005c is a hexagon, a semiconductor material that becomes a cutting margin and is wasted can be reduced.

  After polishing the substrate surface by chemical mechanical polishing, the peripheral region of the substrate is cut so that the edge roll-off region of the polishing substrate is removed, thereby forming a polishing substrate having a vertical edge shape. In addition, the polishing substrate is cut to have a desired shape while removing the edge roll-off region. That is, after polishing the surface by chemical mechanical polishing, the polishing substrate is cut to form a single crystal semiconductor substrate having a desired shape and good flatness to the peripheral edge. Preferably, the disc-shaped substrate cut out from the semiconductor ingot is cut into a desired shape to form a quadrangle substrate, so that the substrate handling property is good in bonding with a base substrate typified by a glass substrate, and the periphery It is possible to manufacture a bond substrate that can be bonded to even a portion. Accordingly, it is possible to provide a bond substrate in which formation of an unbonded region is suppressed.

  Conventionally, a wafer cut out from an ingot is chamfered, and then mirror polished by CMP to produce a silicon wafer. Therefore, an edge roll-off region including polishing sagging is formed at the peripheral edge of the silicon wafer. In this embodiment, after the substrate cut out from the ingot is polished by CMP, the substrate is formed into a desired shape, and the edge roll-off region of the substrate that has been polished and formed into the desired shape is removed, so that a vertical edge shape is obtained. A single crystal semiconductor substrate is formed. Accordingly, formation of an unbonded region can be prevented, and a single crystal semiconductor substrate suitable as a bond substrate for an SOI substrate and a bonded substrate can be provided.

  Next, a flow of manufacturing steps of the bonded substrate substrate and the SOI substrate will be described.

  The second single crystal semiconductor substrate having a vertical edge shape whose surface obtained in (s102) is polished is bonded to the base substrate ((s121) in FIG. 1). Thus far, a bonded substrate is manufactured.

  In the case of manufacturing an SOI substrate, the second single crystal semiconductor substrate which is a bond substrate is thinned, and the thin film layer on the surface of the second single crystal semiconductor substrate is fixed to the base substrate ((s122) in FIG. 1).

  As the base substrate, a substrate made of an insulator such as a glass substrate, a quartz substrate, a ceramic substrate, or a sapphire substrate is used. The cost can be reduced by using a glass substrate, and specifically, a substrate used for the electronic industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass is used. preferable. Further, a metal substrate can be used as the base substrate depending on the use of the semiconductor substrate to be manufactured. The planar shape of the base substrate is a polygonal shape, and is preferably a rectangular (quadrangle) shape.

  The surface of the second single crystal semiconductor substrate which is a bond substrate is polished and has a vertical edge shape. Therefore, it is possible to prevent a non-bonded region from being generated in a manufacturing process of a bonded substrate and an SOI substrate, compared to the case where a substrate having a conventional edge roll-off region is used as a bond substrate. As a result, it is possible to improve the yield in manufacturing a bonded substrate and an SOI substrate.

  Here, an example of manufacturing an SOI substrate will be described with reference to FIGS.

  As shown in FIG. 5, the bonding surface on the second single crystal silicon substrate 105 side which is a bond substrate and the bonding surface on the base substrate 111 side are bonded and bonded together. In the case of manufacturing an SOI substrate, a buffer layer is interposed between the second single crystal silicon substrate 105 and the base substrate 111 and then bonded to each other. The buffer layer is formed on one or both of the polished surface of the second single crystal silicon substrate 105 and the surface of the base substrate 111. In any case, the polished surface of the second single crystal silicon substrate 105 is set to the bonding surface side.

  In the case of manufacturing an SOI substrate, the second single crystal silicon substrate 105 which is a bond substrate is thinned, and a thin film layer on the surface of the second single crystal silicon substrate 105 is fixed to the base substrate 111. Here, the second single crystal silicon substrate 105 is divided and a single crystal silicon layer 120 is formed over the base substrate 111. Further, the single crystal silicon substrate 130 from which the single crystal silicon layer 120 is separated is obtained.

  Since the bond substrate has improved flatness up to the peripheral portion, the bond substrate can be brought into close contact with the base substrate to form a bond. Therefore, unbonded regions are hardly formed in the bonding step and the dividing step, and an SOI substrate or a bonded substrate can be manufactured with high yield.

  In addition, by reducing the region with low flatness at the periphery of the substrate and improving the flatness of the entire substrate surface, the bonding strength of the entire bonding surface of the SOI substrate and the bonded substrate can be made uniform. As a result, in an SOI substrate in which two substrates (a base substrate and a bond substrate) are bonded and the bond substrate is divided into thin films, the peripheral portion of the thin film layer of the bond substrate fixed to the base substrate has a jagged shape. Can be prevented. For example, if the edge roll-off region or the like is in a shape that is inclined from the center of the substrate to the peripheral edge of the substrate, the bonding strength tends to be weakened from the peripheral edge of the substrate. When the bonding strength is weak, when the bond substrate is divided, the peripheral edge portion of the substrate cannot withstand the dividing process, and cannot be bonded to the base substrate and is easily peeled off. Also, unevenness is likely to occur in the bonding strength in regions where the flatness is low. For this reason, a region that is not bonded to the region that is bonded in the dividing step and is peeled off may appear, and the peripheral portion of the thin film layer of the bonded substrate substrate may have a jagged shape. Therefore, it is possible to prevent the peripheral portion of the thin film layer of the bond substrate from having a jagged shape by increasing the flatness to the peripheral portion of the substrate and making the bonding strength uniform. By preventing the peripheral portion of the thin film layer of the bond substrate from having a jagged shape, peeling from the peripheral portion can be suppressed. As a result, the yield can be improved.

  Note that the structure described in this embodiment can be combined as appropriate with any structure described in the other embodiments in this specification.

(Embodiment 2)
In this embodiment, an example of a process for processing an SOI substrate or a semiconductor substrate for a bonded substrate, which is different from that in Embodiment 1, is described with reference to FIGS. Specifically, an example in which chamfering is performed on a vertical edge portion of a bond substrate (second single crystal semiconductor substrate) having a vertical edge shape will be described.

  A first single crystal semiconductor substrate having a polished surface and an edge roll-off region at the peripheral edge (in FIG. 6, (s201), the edge roll-off region is removed from the peripheral region of the first single crystal semiconductor substrate. A second single crystal semiconductor substrate having a vertical edge shape is manufactured by cutting (FIG. 6 (s202)), and chamfering is performed on the edge portion which is perpendicular to the second single crystal semiconductor substrate (FIG. 6). (S203)).

  The details of FIG. 6 (s201) and (s202) are the same as FIG. 1 (s101) and (s102) of the first embodiment. The second single crystal semiconductor substrate having a vertical edge shape is formed by cutting the peripheral region of the first single crystal semiconductor substrate having the edge roll-off region so that the edge roll-off region is removed. .

  In the second single crystal semiconductor substrate 1005 described in Embodiment Mode 1, the edge portion of the side surface in the peripheral edge portion has a vertical shape. In this embodiment, a vertical edge portion of the second single crystal semiconductor substrate having a vertical edge shape is chamfered to form an SOI substrate or a semiconductor substrate (bond substrate) for a bonded substrate. As chamfering, there are C chamfering and R chamfering, and either chamfering may be performed.

  FIG. 7A illustrates an example in which a chamfering process is performed on a vertical edge portion in the second single crystal silicon substrate 2005 having a vertical edge shape. FIGS. 7B and 7C are enlarged cross-sectional views taken along a line QR on the side surface of the second single crystal silicon substrate 2005 shown in FIG. 7A.

  The edge portion which is perpendicular to the second single crystal silicon substrate 2005 is chamfered. FIG. 7B shows an example in which the edge portion 1013 is chamfered. The edge portion is chamfered so as to have a flat inclined cross section. The chamfer width (the length Lc between the surface and the side surface) is about 0.1 mm to 0.5 mm.

  FIG. 7C shows an example in which the edge portion 1014 is R-chamfered. The edge portion is chamfered so as to have an arc cross section. The chamfer width (the length Lr between the surface and the side surface) is about 0.1 mm to 0.5 mm.

  As in this embodiment, by chamfering the vertical edge portion of the second single crystal semiconductor substrate to be a bond substrate, the substrate can be transported or aligned, or the substrate can be affected by external impact in other manufacturing processes. Chipping and cracking can be prevented.

  The second single crystal semiconductor substrate whose surface obtained in (s203) is polished and whose vertical edge portion is chamfered is bonded to the base substrate ((s221) in FIG. 6). Further, in the case of manufacturing an SOI substrate, the second single crystal semiconductor substrate which is a bond substrate is thinned, and the thin film layer on the surface of the second single crystal semiconductor substrate is fixed to the base substrate ((s222) in FIG. 6). ).

  The details of FIGS. 6 (s221) and (s222) are the same as those of FIGS. 1 (s121) and (s122) of the first embodiment.

  In the second single crystal semiconductor substrate in this embodiment, a vertical edge portion is chamfered. Therefore, the handleability of the substrate is good, and it is possible to suppress the occurrence of defects such as chipping and cracking during the manufacturing process and the substrate transport. Therefore, a semiconductor substrate to which the substrate bonding technique is applied can be manufactured with high yield. Further, after the substrate surface is polished by chemical mechanical polishing, regions having low flatness, such as edge roll-off regions, are removed, so that the peripheral edge can be bonded to the base substrate with good adhesion to the chamfered region.

  Conventionally, silicon wafers are manufactured in the order of cutting out a wafer from an ingot, chamfering, and mirror polishing by CMP. In this embodiment, the substrate is cut out from the ingot, polished by CMP, the peripheral region of the substrate is cut so that the edge roll-off region is removed, and a substrate having a vertical edge shape is formed. Bond substrates are manufactured in the order of chamfering the parts. By applying the order and method shown in this embodiment mode, a suitable bond substrate can be provided in which the flatness of the entire surface of the substrate is good and the handleability of the substrate is good.

  Note that the structure described in this embodiment can be combined as appropriate with any structure described in the other embodiments in this specification.

(Embodiment 3)
In this embodiment mode, a specific manufacturing method of manufacturing an SOI substrate using the bond substrate according to the present invention formed in Embodiment Mode 1 or 2 will be described in detail with reference to FIGS. In this embodiment mode, as one of means for thinning an SOI substrate, accelerated ions are irradiated to form an embrittled layer whose crystal structure is damaged inside the single crystal semiconductor substrate, and heat treatment is performed. An example of fixing the thin film layer on the surface of the single crystal semiconductor substrate to the base substrate by dividing the single crystal semiconductor substrate with the embrittlement layer as a boundary will be described.

  A single crystal semiconductor substrate 601 is prepared (FIG. 8A-1). In addition, a base substrate 611 is prepared (FIG. 8B).

  The single crystal semiconductor substrate 601 is a bond substrate and corresponds to the second single crystal semiconductor substrate described in Embodiment 1 or 2. The single crystal semiconductor substrate 601 is formed by polishing at least one surface by chemical mechanical polishing, and then cutting a peripheral region of the substrate having the edge roll-off region so that the edge roll-off region is removed, so that a vertical edge is removed. It is made to have a shape.

  For example, as the single crystal semiconductor substrate 601, a single crystal silicon substrate having a rectangular shape and having a vertical edge portion chamfered is used. Specifically, a single crystal silicon ingot is cut into a predetermined thickness (for example, several hundred μm) to obtain a disk-shaped single crystal silicon substrate. Next, the surface of the disk-shaped single crystal silicon substrate is polished by chemical mechanical polishing. Next, the peripheral region of the disk-shaped single crystal silicon substrate having a surface-polished edge roll-off region is cut so that the edge roll-off region is removed, so that a single unit having a vertical edge shape and a planar rectangular shape is obtained. A crystalline silicon substrate is formed. If necessary, chamfering is performed on the vertical edge portion at the peripheral edge portion of the substrate.

  As the base substrate 611, a substrate made of an insulator such as a glass substrate, a quartz substrate, a ceramic substrate, or a sapphire substrate is used. For example, as the base substrate 611, a glass substrate used for the electronic industry such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used.

  The surfaces of the single crystal semiconductor substrate 601 and the base substrate 611 are made of sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), hydrochloric acid / hydrogen peroxide (HPM), noble hydrofluoric acid (DHF), or the like from the viewpoint of contamination removal. It is preferable to wash appropriately. Alternatively, the surface of the single crystal semiconductor substrate 601 or the base substrate 611 may be cleaned by alternately discharging dilute hydrofluoric acid and ozone water.

  An embrittlement layer 603 is formed inside the single crystal semiconductor substrate 601. In addition, a buffer layer 605 is formed over the surface of the single crystal semiconductor substrate 601 (FIG. 8A-2).

  An embrittlement layer 603 having a damaged crystal structure is formed in a region having a predetermined depth from the polished surface side of the single crystal semiconductor substrate 601. The embrittlement layer 603 can be formed by irradiating the single crystal semiconductor substrate 601 with ions such as hydrogen having kinetic energy.

  The buffer layer 605 is formed with a single-layer structure or a stacked structure including two or more layers using an insulating layer such as a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a silicon nitride oxide layer. The insulating layer for forming the buffer layer 605 is formed by a CVD method, a sputtering method, an atomic layer epitaxy (ALE) method, a thermal oxidation method, or the like.

  Here, the silicon oxynitride layer in this specification has a higher oxygen content than nitrogen, and preferably Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS: Hydrogen Forward Scattering). ), The composition ranges from 50 atoms% to 70 atoms%, nitrogen from 0.5 atoms% to 15 atoms%, silicon from 25 atoms% to 35 atoms%, and hydrogen from 0.1 atoms% to 10 atoms%. It means what is included. The silicon nitride oxide layer has a nitrogen content higher than that of oxygen as a composition. When measured using RBS and HFS, oxygen is 5 atoms% to 30 atoms%, nitrogen is 20 atoms% to 55 atoms%, and silicon is This means that 25 to 35 atoms% and hydrogen is contained in the range of 10 to 30 atoms%.

  Note that the buffer layer 605 may be provided on the surface of one of the single crystal semiconductor substrate 601 and the base substrate 611 or on the surfaces of both substrates. The buffer layer is formed on the single crystal semiconductor substrate 601 side before the embrittlement layer 603 is formed, after the embrittlement layer 603 is formed, or before the embrittlement layer 603 is formed and after the embrittlement layer 602 is formed. Form. Further, the buffer layer may be formed only on the base substrate 611 side, or the buffer layer may be formed on the single crystal semiconductor substrate 601 side and the base substrate 611 side. Each buffer layer to be formed may have a single layer structure or a stacked structure of two or more layers.

  For example, thermal oxidation treatment (for example, HCl oxidation treatment) is performed on the single crystal semiconductor substrate 601 in an oxidizing atmosphere to which chlorine (Cl) is added, and silicon oxide containing chlorine atoms on the surface of the single crystal semiconductor substrate 601 is obtained. A layer (first buffer layer) can be formed. Since the first buffer layer contains chlorine atoms, it can quickly absorb and diffuse moisture. Further, heavy metals (eg, Fe, Cr, Ni, Mo, etc.) that are exogenous impurities are collected, and the single crystal semiconductor substrate 601 is prevented from being contaminated. Here, the single crystal semiconductor substrate 601 with the first buffer layer is irradiated with accelerated ions to form the embrittlement layer 603, so that the surface roughness of the single crystal semiconductor substrate 601 due to ion irradiation is reduced. Can be prevented. Further, a nitrogen-containing layer (second buffer layer) such as a silicon nitride layer or a silicon nitride oxide layer is formed over one surface of the base substrate 611. Since a glass substrate is preferably used for the base substrate 611, an impurity such as Na can be prevented from diffusing to the single crystal semiconductor substrate 601 side by providing the second buffer layer which is a nitrogen-containing layer. .

  The single crystal semiconductor substrate 601 and the base substrate 611 are attached to each other with the buffer layer 605 interposed therebetween (FIG. 6C).

  In the case where the buffer layer is formed only on the surface of the single crystal semiconductor substrate 601, the surface of the buffer layer and the surface of the base substrate 611 are bonded. In the case where the buffer layer is formed only on the surface of the base substrate 611, the surface of the buffer layer and the surface of the single crystal semiconductor substrate 601 are bonded. When the buffer layer is formed on the surface of the single crystal semiconductor substrate 601 and the buffer layer is formed on the surface of the base substrate 611, the surface of the buffer layer on the single crystal semiconductor substrate 601 side and the buffer layer on the base substrate 611 side And the surface of each other.

Here, the single crystal semiconductor substrate 601 and the base substrate 611 are opposed to each other, the buffer layer 605 over the surface of the single crystal semiconductor substrate 601 and the surface of the base substrate 611 are closely attached, and then the single crystal semiconductor substrate 601 is provided at one place. ^{1N / cm 2 ~500N / cm 2} , preferably ^{1N / cm 2 ~20N / cm 2} , for example, apply a pressure of about 17N / cm ^2. The buffer layer 605 and the base substrate 611 start to be joined from the portion where the pressure is applied, and spontaneously joined to the entire surface. Joining can be performed at room temperature without van der Waals force or hydrogen bonding and without heat treatment. Therefore, a substrate having a low heat resistant temperature such as a glass substrate can be used for the base substrate 611.

  Note that the single crystal semiconductor substrate 601 side bonding surface and the base substrate 611 side bonding surface may be bonded together after surface treatment. Examples of the surface treatment include plasma treatment, ozone treatment, megasonic cleaning, two-fluid cleaning (a method in which functional water such as pure water or hydrogenated water is sprayed together with a carrier gas such as nitrogen), or a combination of these methods. After performing plasma treatment on the bonding surface, ozone treatment, megasonic cleaning, two-fluid cleaning, and the like can be performed to remove dust such as organic substances attached to the bonding surface and to make the surface hydrophilic. As a result, the bonding strength at the bonding interface between the single crystal semiconductor substrate 601 and the base substrate 611 can be improved.

  In addition, it is preferable to increase the bonding strength of the bonding interface by performing heat treatment after the surface of the buffer layer 605 and the surface of the base substrate 611 are brought into close contact with each other and bonded. The heat treatment is performed at a temperature that does not cause cracks in the embrittlement layer 603, for example, in a temperature range from room temperature to less than 410 ° C. Further, the surface of the buffer layer 605 and the surface of the base substrate 611 may be brought into close contact with each other in an atmosphere heated in a temperature range of room temperature or higher and lower than 410 ° C. For the heat treatment, a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used. The heat treatment for increasing the bonding strength is preferably performed continuously as it is in the apparatus or place where the bonding is performed. Alternatively, heat treatment for dividing the single crystal semiconductor substrate 601 with the embrittlement layer 603 as a boundary may be performed continuously from the heat treatment for increasing the bonding strength.

  By dividing the single crystal semiconductor substrate 601 with the embrittlement layer 603 formed inside the single crystal semiconductor substrate 601 as a boundary, the single crystal semiconductor layer 620 is formed over the base substrate 611 with the buffer layer 605 interposed therebetween. The formed SOI substrate is manufactured (see FIG. 8D).

  For example, the single crystal semiconductor substrate 601 can be divided along the embrittlement layer 603 by performing heat treatment. This is because a change in volume of a minute cavity formed in the embrittlement layer 603 occurs due to a temperature rise due to heat treatment, and a crack occurs in the embrittlement layer 603. Since the buffer layer 605 and the base substrate 611 are bonded to each other, the single crystal semiconductor layer 620 separated from the single crystal semiconductor substrate 601 is formed over the base substrate 611. Note that the heat treatment here is performed at a temperature that does not exceed the strain point of the base substrate 611.

  Here, the surface of the single crystal semiconductor substrate 601 on the bonding surface side is polished by chemical mechanical polishing. Also, regions with low flatness such as edge roll-off regions are removed. In other words, since the flatness of the bonding surface is good up to the peripheral edge, sufficient bonding strength can be obtained even at the bonding interface of the peripheral edge. As a result, resistance to impact in the step of dividing the single crystal semiconductor substrate 601 is increased, and the single crystal semiconductor layer 620 can be fixed to the base substrate 611 up to the peripheral edge.

  In addition, since the single crystal semiconductor substrate 601 that is a bond substrate has good flatness to the periphery, the uniformity of bonding strength at the bonding interface of the periphery can be improved. Accordingly, the outer peripheral end of the single crystal semiconductor layer 620 fixed over the base substrate 611 can be prevented from being jagged. The reason why the outer peripheral edge of the single crystal semiconductor layer has a jagged shape is that if the bonding strength is not sufficient due to factors such as low flatness, the bonding cannot be endured in the dividing step, and the single crystal semiconductor layer is peeled off without being fixed to the base substrate. This is because the area appears. Since the bonding strength at the peripheral portion becomes nonuniform, the region fixed to the base substrate and the region that is peeled off without being fixed appear irregularly. Therefore, the outer peripheral end of the single crystal semiconductor layer fixed over the base substrate often has a jagged shape. When the outer peripheral edge of the single crystal semiconductor layer constituting the SOI substrate has a jagged shape, film peeling is likely to occur during a manufacturing process, an element formation step using the SOI substrate, or the like. Therefore, by using the bond substrate according to the present invention, the single crystal semiconductor layer 620 can be prevented from being peeled off, and an SOI substrate can be manufactured with high yield.

  Note that for the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used. For example, when an RTA apparatus is used, the single crystal semiconductor substrate 601 can be divided at a heating temperature of 550 ° C. to 730 ° C. and a processing time of 0.5 minutes to 60 minutes.

  Further, the heat treatment for increasing the bonding strength between the buffer layer 605 and the base substrate 611 is not performed, and the heat treatment process for dividing the single crystal semiconductor substrate 601 may also serve as a heat treatment for increasing the bonding strength at the bonding interface. Good.

  Through the above steps, an SOI substrate in which the single crystal semiconductor layer 620 is fixed over the base substrate 611 with the buffer layer 605 interposed therebetween can be manufactured.

  Note that the single crystal semiconductor layer included in the SOI substrate may be subjected to treatment for improving crystallinity and planarity.

  For example, the crystallinity is improved and planarized by irradiating a single crystal semiconductor layer formed by dividing a bond substrate with a laser beam. Specifically, the single crystal semiconductor layer is partially melted by irradiation with a laser beam from the separation surface side of the single crystal semiconductor layer. By partially melting the single crystal semiconductor layer, crystal growth proceeds from a solid phase portion that is not melted, and crystal defects can be repaired without reducing crystallinity. In this specification, partial melting means that a part of the single crystal semiconductor layer (for example, the upper layer part) is melted to be in a liquid phase state, but the other part (for example, the lower layer part) is not melted but remains in a solid state. It means that. On the other hand, complete melting means that the single crystal semiconductor layer is melted to the vicinity of the lower interface to be in a liquid phase state. Note that a laser beam applied to a process for improving crystallinity or planarity is selected with a wavelength that is absorbed by the single crystal semiconductor layer. Further, RTA or flash lamp irradiation may be performed instead of laser beam irradiation.

  Improvement of crystallinity by laser beam irradiation is suitable when a substrate having low heat resistance such as a glass substrate is used. This is because even when a single crystal semiconductor layer is irradiated with a laser beam, the glass substrate is not directly heated, and heat applied to the glass substrate can be suppressed.

  Further, by performing etching treatment from the separation surface side of the single crystal semiconductor layer, removal and planarization of crystal defects can be achieved. Etching is performed by dry etching, wet etching, or a combination of both. Further, removal of crystal defects and planarization may be achieved by performing a polishing process such as CMP instead of the etching process.

  Further, laser treatment and etching treatment may be combined. As an example, the separation surface of the single crystal semiconductor layer is dry-etched and then irradiated with a laser beam. Then, dry etching (or wet etching) is performed again. By doing so, it is possible to prevent crystal defects from being taken into the single crystal semiconductor layer. Further, by dividing the etching process into two stages, film skipping due to the laser process can be suppressed and the film thickness can be reduced.

  Further, as illustrated in FIG. 8D, the single crystal semiconductor layer 620 is separated from the single crystal semiconductor substrate 601, and the single crystal semiconductor substrate 640 remains. The single crystal semiconductor substrate 640 can be reused by performing a regeneration process. Examples of the regeneration process include an etching process and a laser process.

  Note that the structure described in this embodiment can be combined as appropriate with any structure described in the other embodiments in this specification.

(Embodiment 4)
In this embodiment mode, an example of manufacturing a semiconductor element using an SOI substrate according to the present invention will be described. Here, an example in which an n-channel field effect transistor and a p-channel field effect transistor are manufactured as semiconductor elements will be described with reference to cross-sectional views in FIGS.

  First, an SOI substrate manufactured using the present invention is prepared. In the SOI substrate, a single crystal semiconductor layer 620 is formed over a base substrate 611 with a buffer layer 605 interposed therebetween.

The single crystal semiconductor layer 620 includes a p-type impurity element such as boron, aluminum, or gallium, or an n-type impurity element such as phosphorus or arsenic, in accordance with the formation region of the n-channel field effect transistor and the p-channel field effect transistor. Is preferably added. For example, a so-called well region is formed by adding a p-type impurity element corresponding to the formation region of the n-channel field effect transistor and adding an n-type impurity element corresponding to the formation region of the p-channel field effect transistor. To do. The dose of impurity ions may be about 1 × 10 ¹² ions / cm ^{2 to} 1 × 10 ¹⁴ ions / cm ² . Furthermore, when controlling the threshold voltage of the field effect transistor, an n-type impurity element or a p-type impurity element may be added to these well regions.

  Next, as illustrated in FIG. 9B, the single crystal semiconductor layer 620 is etched to form a single crystal semiconductor layer 620 c and a single crystal semiconductor layer 620 d which are separated into island shapes in accordance with the arrangement of elements. In this embodiment, an n-channel field effect transistor is manufactured from the single crystal semiconductor layer 620c, and a p-channel field effect transistor is manufactured from the single crystal semiconductor layer 620d.

  Next, as illustrated in FIG. 9C, a gate insulating layer 310, a conductive layer 312 for forming a gate electrode, and a conductive layer 314 are formed in this order over the single crystal semiconductor layer 620c and the single crystal semiconductor layer 620d.

  The gate insulating layer 310 is formed using a single layer structure or a stacked layer structure using an insulating layer such as a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a silicon nitride oxide layer by a CVD method, a sputtering method, an ALE method, or the like. Form with.

The gate insulating layer 310 may be formed by oxidizing or nitriding the surface by performing plasma treatment on the single crystal semiconductor layer 620c and the single crystal semiconductor layer 620d. The plasma treatment in this case also includes plasma treatment using plasma excited using microwaves (typical frequency is 2.45 GHz). For example, a treatment using plasma excited by microwaves and having an electron density of 1 × 10 ¹¹ / cm ^{3 to} 1 × 10 ¹³ / cm ³ and an electron temperature of 0.5 eV to 1.5 eV is also included. A thin and dense film can be formed by performing oxidation treatment or nitridation treatment on the surface of the semiconductor layer by applying such plasma treatment. In addition, since the surface of the semiconductor layer is directly oxidized, a film having good interface characteristics can be obtained. Alternatively, the gate insulating layer 310 may be formed by performing plasma treatment using a microwave on a film formed by a CVD method, a sputtering method, or an ALE method.

  Note that since the gate insulating layer 310 forms an interface with the semiconductor layer, the gate insulating layer 310 is preferably formed so that the silicon oxide layer or the silicon oxynitride layer serves as the interface. This is because when a film containing more nitrogen than oxygen is formed, such as a silicon nitride layer or a silicon nitride oxide layer, trap levels are formed and interface characteristics may become a problem.

  The conductive layer forming the gate electrode is made of an element selected from tungsten, tantalum, titanium, molybdenum, aluminum, copper, chromium, niobium, an alloy material containing the above element, or a compound material containing the above element. A single layer structure or a stacked layer structure is formed using a conductive material by a sputtering method or a CVD method. In addition, as the conductive layer for forming the gate electrode, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used. When the gate electrode has a stacked structure, it can be formed using different conductive materials or can be formed using the same conductive material. In this embodiment, an example in which a conductive layer for forming a gate electrode is formed to have a two-layer structure of a conductive layer 312 and a conductive layer 314 is described.

  In the case where the gate electrode is formed with a two-layer structure of the conductive layer 312 and the conductive layer 314 as in this embodiment mode, for example, a tantalum nitride layer and a tungsten layer, a titanium nitride layer and a tungsten layer, a molybdenum nitride layer and a molybdenum layer are used. A laminated structure such as can be formed. It is preferable to form a stacked structure of a tantalum nitride layer and a tungsten layer because the etching rate between the two is easily different and the etching selectivity can be increased. Note that in the two-layer structure illustrated as an example, the above-described layer (eg, a tantalum nitride layer) is preferably formed in contact with the gate insulating layer 310. For example, the conductive layer 312 is formed with a thickness of 20 nm to 100 nm, and the conductive layer 314 is formed with a thickness of 100 nm to 400 nm. Needless to say, the gate electrode can have a structure in which three or more conductive layers are stacked.

  Next, a resist mask 320c and a resist mask 320d are selectively formed over the conductive layer 314. Then, a first etching process and a second etching process are performed using the resist mask 320c and the resist mask 320d.

  First, the conductive layer 312 and the conductive layer 314 are selectively etched by a first etching process using the resist mask 320c, so that the conductive layer 316c and the conductive layer 318c are formed over the single crystal semiconductor layer 620c. At the same time, the conductive layer 312 and the conductive layer 314 are selectively etched by the first etching treatment using the resist mask 320d, so that the conductive layer 316d and the conductive layer 318d are formed over the single crystal semiconductor layer 620d (FIG. 9 ( D)).

  Next, the end portion of the conductive layer 318c is etched by a second etching process using the resist mask 320c, so that the conductive layer 322c is formed. At the same time, an end portion of the conductive layer 318d is etched by a second etching process using the resist mask 320d to form a conductive layer 322d (see FIG. 9E). Note that the conductive layer 322c is formed to have a smaller width (length in a direction parallel to a direction in which carriers flow in a channel formation region (a direction connecting a source region and a drain region)) than the conductive layer 316c. Similarly, the conductive layer 322d is formed to have a smaller width than the conductive layer 316d. In this manner, a two-layer gate electrode 324c including the conductive layer 316c and the conductive layer 322c, and a two-layer gate electrode 324d including the conductive layer 316d and the conductive layer 322d are formed.

  An etching method applied to the first etching process and the second etching process may be selected as appropriate. A high-density plasma source such as an ECR (Electron Cyclotron Resonance) method or an ICP (Inductively Coupled Plasma) method may be used. The dry etching apparatus used is preferable because the etching rate can be improved. Etching conditions for the first etching process and the second etching process (the amount of power applied to the coil-type electrode and the parallel plate-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) By adjusting appropriately, the side surfaces of the conductive layers 316c and 316d and the conductive layers 322c and 322d can be formed into a desired tapered shape. After the desired gate electrodes 324c and 324d are formed, the resist masks 320c and 320d may be removed.

  Next, a resist mask 381 is selectively formed so as to cover the single crystal semiconductor layer 620c. Then, the impurity element 380 is added to the single crystal semiconductor layer 620d using the resist mask 381 as a mask. The single crystal semiconductor layer 620d includes a pair of first impurity regions 328d, a pair of second impurity regions 330d, a channel formation region in a self-alignment manner using the conductive layer 316d and the conductive layer 322d formed above as a mask. 326d is formed (see FIG. 10A).

As the impurity element 380, a p-type impurity element such as boron, aluminum, or gallium, or an n-type impurity element such as phosphorus or arsenic is added. Here, boron, which is a p-type impurity element, is added as the impurity element 380 in order to form a p-channel field effect transistor. Further, boron is contained in the first impurity region 328d at a concentration of about 1 × 10 ²⁰ atoms / cm ^{3 to} 5 × 10 ²¹ atoms / cm ³ . The first impurity region 328d functions as a source region or a drain region.

  In the single crystal semiconductor layer 620d, a first impurity region 328d is formed in a region that does not overlap with the conductive layer 316d, a second impurity region 330d is formed in a region that overlaps with the conductive layer 316d and does not overlap with the conductive layer 322d, and the conductive layer 322d A channel formation region 326d is formed in the overlapping region. The second impurity region 330d has a lower impurity concentration than the first impurity region 328d.

  After the resist mask 381 is removed, a resist mask 382 is selectively formed so as to cover the single crystal semiconductor layer 620d. Then, the impurity element 384 is added to the single crystal semiconductor layer 620c using the resist mask 382 as a mask. The single crystal semiconductor layer 620c includes a pair of third impurity regions 328c, a pair of fourth impurity regions 330c, a channel formation region in a self-aligning manner using the conductive layer 316c and the conductive layer 322c formed above as a mask. 326c is formed (see FIG. 10B).

Here, an n-type impurity element is added as the impurity element 384 in order to form an n-channel field effect transistor. For example, phosphorus is added as the impurity element 384 so that the third impurity region 328c contains phosphorus at a concentration of about 5 × 10 ¹⁹ atoms / cm ^{3 to} 5 × 10 ²⁰ atoms / cm ³ . The third impurity region 328c functions as a source region or a drain region.

  In the single crystal semiconductor layer 620c, a third impurity region 328c is formed in a region not overlapping with the conductive layer 316c, a fourth impurity region 330c is formed in a region overlapping with the conductive layer 316c and not overlapping with the conductive layer 322c, and the conductive layer 322c A channel formation region 326c is formed in the overlapping region. The fourth impurity region 330c has a lower impurity concentration than the third impurity region 328c.

  Note that the first impurity region 328d, the second impurity region 330d, and the channel formation region 326d are formed in the single crystal semiconductor layer 620d, and the third impurity region 328c, the fourth impurity region 330c, and the channel formation region 326c are formed in the single crystal semiconductor layer 620c. The order of forming the layers is not limited to this embodiment, and can be changed as appropriate. Further, after the impurity regions (first impurity region 328d to fourth impurity region 330c) are formed in the single crystal semiconductor layers 620c and 620d, activation (low resistance) is performed by appropriately performing heat treatment, laser beam irradiation, or the like. .

  Next, an insulating layer covering the gate electrode 324c, the gate electrode 324d, and the gate insulating layer 310 is formed with a single-layer structure or a stacked structure. The gate insulating layer 310 and the upper insulating layer reach the pair of third impurity regions 328c formed in the single crystal semiconductor layer 620c and the pair of first impurity regions 328d formed in the single crystal semiconductor layer 620d, respectively. A contact hole is formed. A conductive layer 336c and a conductive layer 336d functioning as a source electrode or a drain electrode are formed in the contact holes.

  First, the insulating layer 331 which covers the gate electrode 324c, the gate electrode 324d, and the gate insulating layer 310 is formed (see FIG. 11A). As the insulating layer 331, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride oxide layer, a silicon nitride oxide layer, or the like is formed by a CVD method or a sputtering method. For example, a silicon oxynitride layer (with a thickness of 50 nm) is formed as the insulating layer 331 by a plasma CVD method. Next, the impurity regions (the first impurity region 328 d to the fourth impurity region 330 c) can be activated by performing heat treatment at 400 ° C. or higher and below the strain point temperature of the base substrate 611. For example, heat treatment is performed at 480 ° C. for 1 hour in a nitrogen atmosphere. By performing heat treatment after the insulating layer 331 is formed, oxidation of the gate electrode due to the heat treatment can be prevented. Note that by controlling the atmosphere during heat treatment, the gate electrode can be prevented from being oxidized without the insulating layer 331 being formed.

  Next, the insulating layer 332 and the insulating layer 334 are formed over the insulating layer 331 (see FIG. 11B).

  As the insulating layer 332 and the insulating layer 334, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon nitride oxide layer, or the like can be formed by a CVD method or a sputtering method. Alternatively, an organic material such as polyimide, polyamide, polyvinyl phenol, benzocyclobutene, acrylic or epoxy, a siloxane material such as a siloxane resin, or an oxazole resin can be used by a coating method such as a spin coating method. Note that the siloxane material corresponds to a material including a Si—O—Si bond.

  Note that as the insulating layer formed over the gate electrodes 324c and 324d, at least one insulating layer containing hydrogen is formed, and heat treatment is performed, so that dangling bonds existing in the single crystal semiconductor layer are hydrogen-terminated. It is preferable to aim for. After forming the insulating layer containing hydrogen, heat treatment is performed at a processing temperature of, for example, 350 ° C. or higher and 480 ° C. or lower, preferably 400 ° C. or higher and 450 ° C. or lower. Excited and diffused, passes through the insulating layer and reaches the single crystal semiconductor layer. Then, dangling bonds existing in the single crystal semiconductor layer are terminated with hydrogen by the reached hydrogen. If dangling bonds are present in the semiconductor layer, particularly in the channel formation region, the electrical characteristics of the completed transistor may be adversely affected, so that hydrogen termination is effective as in this embodiment. By performing hydrogen termination, interface characteristics between the gate insulating layer and the single crystal semiconductor layer can be improved.

  The insulating layer containing hydrogen can be formed by a plasma CVD method using a process gas for film formation containing H. In addition, even when an insulating layer containing hydrogen is not formed, hydrogen termination of the single crystal semiconductor layer can be performed by performing heat treatment in an atmosphere containing hydrogen. For example, after an insulating layer containing hydrogen is formed as the insulating layer 332 and the insulating layer 334 is formed thereover, heat treatment for hydrogen termination is performed. In this case, the insulating layer 334 is formed at a temperature at which hydrogen contained in the insulating layer 332 is not dehydrogenated.

  For example, a silicon nitride oxide layer (film thickness of 300 nm) as the insulating layer 332 and a silicon oxynitride layer (film thickness of 450 nm) as the insulating layer 334 are continuously formed by a plasma CVD method. The silicon nitride oxide layer uses monosilane, ammonia, hydrogen, and nitrogen oxide as process gases for film formation. The silicon oxynitride layer uses monosilane and nitrous oxide as process gases for film formation. In addition, when the treatment temperature is approximately 200 ° C. to 300 ° C., an insulating layer can be formed without dehydrogenating hydrogen contained in the silicon nitride oxide layer. Then, after the insulating layer 334 is formed, the single crystal semiconductor layer is subjected to hydrogen termination by performing heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere.

  Next, contact holes are formed in the insulating layer 334, the insulating layer 332, the insulating layer 331, and the gate insulating layer 310, and conductive layers 336c and 336d are formed so as to fill the contact holes (see FIG. 11C). ). Here, a pair of contact holes reaching each of the pair of first impurity regions 328d is formed, and a pair of conductive layers 336c reaching the first impurity regions 328d through the contact holes are formed. At the same time, a pair of contact holes reaching each of the pair of third impurity regions 328c is formed, and a pair of conductive layers 336d reaching the third impurity regions 328c through the contact holes are formed. The conductive layer 336c and the conductive layer 336d function as a source electrode or a drain electrode. The conductive layer 336c is electrically connected to the third impurity region 328c. The conductive layer 336d is electrically connected to the first impurity region 328d.

  The conductive layer 336c and the conductive layer 336d are formed using an element selected from aluminum, tungsten, titanium, tantalum, molybdenum, nickel, neodymium, copper, or the like, an alloy material containing the above element, or a compound material containing the above element It forms using. Examples of the alloy material containing the above-described element include an aluminum alloy containing titanium, an aluminum alloy containing neodymium, and an aluminum alloy containing silicon (also referred to as aluminum silicon). In addition, examples of the compound containing the element include nitrides such as tungsten nitride, titanium nitride, and tantalum nitride. The conductive layers 336c and 336d are formed over the entire surface by a sputtering method or a CVD method using the above materials, and then selectively etched and processed into a desired shape. The conductive layer 336c and the conductive layer 336d can be formed to have a single-layer structure or a stacked structure including two or more layers. For example, a structure in which a titanium layer, a titanium nitride layer, an aluminum layer, and a titanium layer are sequentially stacked can be employed. By adopting a configuration in which the aluminum layer is sandwiched between titanium layers, heat resistance can be improved. Further, the titanium nitride layer formed between the titanium layer and the aluminum layer can function as a barrier layer.

  Through the above, an n-channel field effect transistor and a p-channel field effect transistor can be manufactured using an SOI substrate having a single crystal semiconductor layer.

  In this embodiment mode, a photolithography method and an etching method are applied in order to form a fine pattern such as a semiconductor element. An exposure apparatus such as a stepper or MPA is generally used for forming a resist mask for forming a desired pattern shape. The pattern shape of one shot exposed by an exposure apparatus such as a stepper or MPA is typically a square shape. The semiconductor layer of the SOI substrate used in this embodiment has a polygonal shape, typically a quadrangular shape. Since the semiconductor layer has a quadrangular shape rather than a circular shape, the pattern can be efficiently formed.

  In addition, the SOI substrate according to the present invention is fixed to the base substrate with high bonding strength up to the peripheral portion of the single crystal semiconductor layer. In addition, the outer peripheral end of the single crystal semiconductor layer is manufactured so as to be prevented from being a jagged shape. Therefore, defects such as film peeling during the manufacturing of the semiconductor element can be prevented, and the semiconductor element can be manufactured with high yield.

  Note that the n-channel field effect transistor and the p-channel field effect transistor can be electrically connected by electrically connecting the conductive layer 336c and the conductive layer 336d, whereby a CMOS transistor can be obtained.

  In this embodiment mode, an example in which the gate electrode has a stacked structure of two conductive layers and each layer has a different width has been described, but the present invention is not particularly limited. For example, the gate electrode may be formed with a single layer structure of a conductive layer, or the conductive layer may have a stacked structure of three or more layers. In addition, in the stacked structure of the conductive layers, the widths of the layers may be formed so as to be substantially the same, or the taper shapes of the layers may be different. Further, an insulating layer called a sidewall may be formed in contact with the side surface of the gate electrode.

  A semiconductor device having various functions can be provided by combining a plurality of transistors described in this embodiment mode. Further, the structure of the transistor described in this embodiment mode is an example, and the structure is not limited to the illustrated structure.

  Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments in this specification.

(Embodiment 5)
By using the SOI substrate according to the present invention and forming various semiconductor elements such as a capacitor and a resistor in addition to the transistor described in Embodiment Mode 4, a high-value-added semiconductor device can be manufactured. it can. In this embodiment mode, specific modes of a semiconductor device will be described with reference to the drawings.

  Note that a semiconductor device in this specification refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices (including EL display devices and liquid crystal display devices), semiconductor circuits, and electronic devices are all categories. To include.

  First, a microprocessor will be described as an example of a semiconductor device. FIG. 12 is a block diagram illustrating a configuration example of the microprocessor 200. The microprocessor 200 includes an arithmetic circuit 201 (also referred to as ALU), an arithmetic circuit controller 202 (ALU Controller), an instruction analyzer 203 (Instruction Decoder), an interrupt controller 204 (Interrupt Controller), and timing control. A unit 205 (Timing Controller), a register 206 (Register), a register control unit 207 (Register Controller), a bus interface 208 (Bus I / F), a read-only memory 209, and a memory interface 210 are provided.

  An instruction input to the microprocessor 200 via the bus interface 208 is input to the instruction analysis unit 203, decoded, and then input to the arithmetic circuit control unit 202, the interrupt control unit 204, the register control unit 207, and the timing control unit 205. Is done. The arithmetic circuit control unit 202, the interrupt control unit 204, the register control unit 207, and the timing control unit 205 perform various controls based on the decoded instruction. Specifically, the arithmetic circuit control unit 202 generates a signal for controlling the operation of the arithmetic circuit 201. The interrupt control unit 204 processes an interrupt request from an external input / output device or a peripheral circuit based on its priority or mask state during execution of the program of the microprocessor 200. The register control unit 207 generates an address of the register 206, and reads and writes the register 206 according to the state of the microprocessor 200. The timing control unit 205 generates a signal for controlling the operation timing of the arithmetic circuit 201, the arithmetic circuit control unit 202, the instruction analysis unit 203, the interrupt control unit 204, and the register control unit 207. For example, the timing control unit 205 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits. Note that the microprocessor 200 illustrated in FIG. 12 is only an example in which the configuration is simplified, and actually, the microprocessor 200 may have various configurations depending on the application.

  Next, an example of a semiconductor device having an arithmetic function capable of transmitting and receiving data without contact will be described with reference to FIGS. FIG. 13 illustrates an example of a computer (hereinafter referred to as “RFCPU”) that operates as a semiconductor device by transmitting and receiving signals to and from an external device by wireless communication. The RFCPU 211 has an analog circuit unit 212 and a digital circuit unit 213. The analog circuit unit 212 includes a resonance circuit 214 having a resonance capacitance, a rectifier circuit 215, a constant voltage circuit 216, a reset circuit 217, an oscillation circuit 218, a demodulation circuit 219, and a modulation circuit 220. The digital circuit unit 213 includes an RF interface 221, a control register 222, a clock controller 223, a CPU interface 224, a central processing unit (CPU) 225, a random access memory (RAM) 226, and a read only memory (ROM) 227. .

  The operation of the RFCPU 211 is as follows. A signal received by the antenna 228 generates an induced electromotive force by the resonance circuit 214. The induced electromotive force is charged in the capacitor unit 229 through the rectifier circuit 215. Capacitance portion 229 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitor portion 229 does not need to be integrally formed with the RFCPU 211, and may be attached to a substrate having an insulating surface constituting the RFCPU 211 as a separate component.

  The reset circuit 217 generates a signal that resets and initializes the digital circuit unit 213. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 218 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 216. The demodulating circuit 219 formed of a low-pass filter binarizes fluctuations in the amplitude of an amplitude modulation (ASK) reception signal, for example. The modulation circuit 220 transmits transmission data by changing the amplitude of an amplitude modulation (ASK) transmission signal. The modulation circuit 220 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 214. The clock controller 223 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the central processing unit 225. The power supply management circuit 230 monitors the power supply voltage.

  A signal input from the antenna 228 to the RFCPU 211 is demodulated by the demodulation circuit 219 and then decomposed into a control command and data by the RF interface 221. The control command is stored in the control register 222. The control command includes reading of data stored in the read-only memory 227, writing of data to the random access memory 226, calculation instructions to the central processing unit 225, and the like. The central processing unit 225 accesses the read only memory 227, the random access memory 226, and the control register 222 via the CPU interface 224. The CPU interface 224 has a function of generating an access signal for any of the read-only memory 227, the random access memory 226, and the control register 222 from an address requested by the central processing unit 225.

  As a calculation method of the central processing unit 225, a method in which an OS (operating system) is stored in the read-only memory 227, and a program is read and executed together with activation can be adopted. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the method using both hardware and software, a method in which a part of processing is performed by a dedicated arithmetic circuit and the remaining processing is executed by the central processing unit 225 using a program can be applied.

  A semiconductor device such as the microprocessor 200 or the RFCPU 211 can be manufactured by applying a circuit having various functions in which a plurality of transistors are combined. The transistor can be manufactured using the single crystal semiconductor layer of the SOI substrate according to the present invention. In addition, since an inexpensive substrate such as a glass substrate can be used as the base substrate, cost reduction can be achieved. By manufacturing an integrated circuit by combining such transistors, it is possible to realize higher performance, higher processing speed, and lower cost of a semiconductor device such as a microprocessor or an RFCPU. Although FIG. 13 shows the form of the RFCPU, an IC tag may be used as long as it has a communication function, an arithmetic processing function, and a memory function.

  Next, a display device using an SOI substrate according to the present invention will be described with reference to FIGS.

  FIG. 14 is a diagram illustrating a configuration example of a liquid crystal display device. 14A is a plan view of a pixel of the liquid crystal display device, and FIG. 14B is a cross-sectional view of FIG. 14A taken along the line JK. In FIG. 14A, a single crystal semiconductor layer 511 forms a transistor 525 of a pixel. The pixel includes a single crystal semiconductor layer 511, a scan line 522 that intersects with the single crystal semiconductor layer 511, a signal line 523 that intersects with the scan line 522, a pixel electrode 524, the pixel electrode 524, and the single crystal semiconductor layer An electrode 528 which electrically connects 511 is provided. The single crystal semiconductor layer 511 is a layer formed from the single crystal semiconductor layer included in the SOI substrate according to the present invention. Note that the substrate 510 is a base substrate, and a glass substrate can be preferably used.

  As shown in FIG. 14B, a buffer layer 605 and a single crystal semiconductor layer 511 are stacked over a substrate 510. The single crystal semiconductor layer 511 is a layer in which the single crystal semiconductor layer 620 is formed by element isolation by etching. In the single crystal semiconductor layer 511, a channel formation region 512 and an n-type impurity region 514 are formed. A gate electrode of the transistor 525 is included in the scan line 522, and one of the source electrode and the drain electrode is included in the signal line 523.

  A signal line 523, a pixel electrode 524, and an electrode 528 are provided over the interlayer insulating layer 527. A columnar spacer 529 is formed over the interlayer insulating layer 527, and an alignment film 530 is formed to cover the signal line 523, the pixel electrode 524, the electrode 528, and the columnar spacer 529. The counter substrate 532 is provided with a counter electrode 533 and an alignment film 534 that covers the counter electrode 533. The columnar spacer 529 is formed to maintain a gap between the substrate 510 and the counter substrate 532. A liquid crystal layer 535 is formed in the gap between the alignment film 534 on the counter substrate 532 side and the alignment film 530 on the substrate 510 side maintained by the columnar spacer 529. Since a connection portion between the signal line 523 and the impurity region 514 and between the electrode 528 and the impurity region 514 has a step due to the interlayer insulating layer 527, the signal line 523, and the electrode 528, the liquid crystal orientation of the liquid crystal layer 535 is easily disturbed at the connection portion. . For this reason, columnar spacers 529 are formed in the stepped portion to prevent liquid crystal alignment disorder.

  Note that a glass substrate can be used as the substrate 510. In other words, the substrate 510 can be a light-transmitting substrate, and a liquid crystal display device to which the present invention is applied is not limited to a reflective liquid crystal display device, but can be a transmissive liquid crystal display device or a transflective liquid crystal display device. can do.

  Next, an electroluminescence display device (hereinafter referred to as an EL display device) will be described. FIG. 15A is a plan view of a pixel of an EL display device, and FIG. 15B is a cross-sectional view of the pixel. As shown in FIG. 15A, the pixel includes a selection transistor 401 which is a transistor, a display control transistor 402, a scanning line 405, a signal line 406, a current supply line 407, and a pixel electrode 408. Each pixel is provided with a light-emitting element having a structure in which a layer containing an electroluminescent material (EL layer) is sandwiched between a pair of electrodes. One electrode of the light emitting element is a pixel electrode 408.

  The single crystal semiconductor layer 403 included in the selection transistor 401 and the semiconductor layer 404 included in the display control transistor 402 are layers formed from the single crystal semiconductor layer included in the SOI substrate according to the present invention. Note that a glass substrate can be preferably used as the substrate 400.

  In the selection transistor 401, the gate electrode is included in the scanning line 405, one of the source electrode and the drain electrode is included in the signal line 406, and the other is formed as the electrode 411. In the display control transistor 402, the gate electrode 412 is electrically connected to the electrode 411, one of the source electrode and the drain electrode is formed as an electrode 413 electrically connected to the pixel electrode 408, and the other is supplied with current. Included in line 407.

  The display control transistor 402 is a p-channel field effect transistor. As shown in FIG. 15B, a channel formation region 451 and a p-type impurity region 452 are formed in the semiconductor layer 404. An interlayer insulating layer 427 is formed to cover the gate electrode 412 of the display control transistor 402. Over the interlayer insulating layer 427, a signal line 406, a current supply line 407, an electrode 411, an electrode 413, and the like are formed. A pixel electrode 408 that is electrically connected to the electrode 413 is formed over the interlayer insulating layer 427. The peripheral portion of the pixel electrode 408 is surrounded by an insulating partition layer 428. An EL layer 429 is formed over the pixel electrode 408, and a counter electrode 430 is formed over the EL layer 429. A counter substrate 431 is provided as a reinforcing plate, and the counter substrate 431 is fixed to the substrate 400 with a resin layer 432.

  Note that a glass substrate can be used as the substrate 400 and a light-transmitting substrate can be used. In other words, the EL display device to which the present invention is applied is not limited to the top emission structure in which light is extracted from the counter substrate side, but may be a bottom emission structure in which light is extracted from the base substrate side.

  The transistor using the single crystal semiconductor layer of the SOI substrate according to the present invention can be applied to the liquid crystal display device shown in FIG. 14 or the EL display device shown in FIG. Since a channel of a transistor can be formed using a single crystal semiconductor layer, high performance can be realized. In addition, as described above, a glass substrate can be used as the base substrate, and light can be transmitted unlike a case where a semiconductor substrate is used as the base substrate. Therefore, a configuration for extracting light from the base substrate side (configuration for transmitting light to the base substrate side), a configuration for extracting light from the counter substrate side (configuration for transmitting light to the counter substrate side), and a configuration for extracting light from both substrates The practitioner can appropriately select such as (a configuration in which light is transmitted from both substrate sides).

  In addition, a semiconductor device can be manufactured using the SOI substrate according to the present invention and applied to various electronic devices. Electronic devices include portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), sound playback devices (car audio, audio components, etc.), computers, video cameras, digital cameras, navigation systems, game devices In addition, an image reproducing device including a recording medium (specifically, a device including a display device for displaying image data such as a DVD (digital versatile disc)) is included.

  A specific aspect of the electronic device will be described with reference to FIG. FIG. 16A is an external view illustrating an example of a mobile phone 900. The mobile phone 900 includes two housings, a housing 901 and a housing 902, which are foldably connected by a connecting portion 903. A display portion 904 is incorporated in the housing 901. An operation key 906 is provided on the housing 902. Note that there is no particular limitation on the structure of the mobile phone 900, and any structure can be used as long as it includes at least an element manufactured using the SOI substrate according to the present invention, and any other accessory can be provided as appropriate. For example, by applying the display device described in FIG. 14 or 15 to the display portion 904, high image quality can be realized. In addition, since defects in a semiconductor element manufacturing process using an SOI substrate can be prevented, the yield of a display device incorporated in a mobile phone can be improved.

  FIG. 16B is an external view illustrating an example of a PDA (Personal Digital Assistance) 920. The PDA 920 includes an operation button 923, an external connection port 924, a speaker 925, a microphone 926, and the like in addition to the display portion 922 incorporated in the housing 921. The PDA 920 may have a function of a mobile phone. The configuration of the PDA 920 is not particularly limited as long as the PDA 920 includes at least an element manufactured using the SOI substrate according to the present invention, and other auxiliary equipment may be appropriately provided. For example, by applying the display device described in FIG. 14 or FIG. 15 to the display portion 922, high image quality can be realized.

  The PDA 920 illustrated in FIG. 16B can input information by touching the display portion 922 with a finger or the like. In addition, an operation of making a call or typing an e-mail can be performed by touching the display portion 922 with a finger or the like.

  There are mainly three screen modes of the display portion 922. The first is a display mode mainly for displaying images, and the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the display mode and the input mode are mixed.

  For example, when inputting information, making a call, or creating an e-mail, the display unit 922 may be set to a character input mode mainly for inputting characters and an operation for inputting characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display portion 922.

  In addition, by providing a detection device having a sensor for detecting the inclination, such as a gyroscope or an acceleration sensor, in the PDA 920, the orientation (vertical or horizontal) of the PDA 920 is determined, and the screen display of the display unit 922 is automatically displayed. Can be switched.

  Further, the screen mode is switched by touching the display portion 922 or operating the operation button 923 of the housing 921. In addition, switching can be performed depending on the type of image displayed on the display portion 922. For example, if the image signal to be displayed on the display unit is moving image data, the display mode is switched, and if the image signal is text data, the mode is switched to the input mode.

  In addition, in the input mode, when a signal detected by the optical sensor of the display unit 922 is detected and there is no input by a touch operation of the display unit 922 for a certain period, the screen mode is switched from the input mode to the display mode. You may control.

  The display portion 922 can also function as an image sensor. For example, by touching the display unit 922 with a palm or a finger, an image of a palm print, a fingerprint, or the like can be captured to perform personal authentication. In addition, if a backlight that emits infrared light or a sensing light source that emits infrared light is used for the display portion, finger veins, palm veins, and the like can be imaged.

  FIG. 16C illustrates an example of an electronic book 970. For example, the e-book reader 970 includes two housings, a housing 971 and a housing 973. The housing 971 and the housing 973 are integrated with a shaft portion 978 and can be opened and closed with the shaft portion 978 as an axis. With such a configuration, an operation like a paper book can be performed.

  A display portion 975 is incorporated in the housing 971, and a display portion 977 is incorporated in the housing 973. The display unit 975 and the display unit 977 may be configured to display a continuation screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, a sentence can be displayed on the right display unit (display unit 975) and an image can be displayed on the left display unit (display unit 977).

  There is no particular limitation on the structure of the e-book reader 970, and any structure including at least an element manufactured using the SOI substrate according to the present invention may be used, and another accessory may be appropriately provided.

  FIG. 16C illustrates an example in which the housing 971 is provided with an operation portion and the like. For example, the housing 971 includes a power supply 974, operation keys 972, a speaker 976, and the like. Pages can be sent with the operation keys 972. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, and the like may be provided on the back and side surfaces of the housing. . Further, the electronic book 970 may have a structure having a function as an electronic dictionary.

  Further, the e-book reader 970 may have a configuration capable of transmitting and receiving information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

  Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments in this specification.

  Hereinafter, the surface of the single crystal silicon substrate is polished by chemical mechanical polishing, and the peripheral region of the single crystal silicon substrate having a polished surface and having an edge roll-off region is cut so that the edge roll-off region is removed. It will be described that by using a substrate as a bond substrate, an unbonded region in a peripheral portion can be reduced in a manufacturing process of a bonded substrate substrate and an SOI substrate. Further, it will be described that by manufacturing an SOI substrate using the above bond substrate, the peripheral portion of the single crystal silicon layer can be prevented from having a jagged shape.

  In this example, a single crystal silicon substrate which is a bond substrate and a glass substrate which is a base substrate are bonded to produce Sample A and Sample B which are bonded substrates.

(Sample A)
FIG. 17A-1 shows an appearance photograph in which a part of the plane of the sample A is observed. (A-2) is a schematic diagram of an appearance photograph shown in (A-1). Sample A was prepared by the following procedure. A peripheral region of the disc-shaped single crystal silicon substrate whose surface was polished by chemical mechanical polishing was cut and formed into a quadrangular shape, whereby a single crystal silicon substrate 2005 was manufactured. By cutting, the edge roll-off region of the disc-shaped single crystal silicon substrate is removed, and a single crystal silicon substrate 2005 having a vertical edge shape is formed. Then, the single crystal silicon substrate 2005 was overlaid on the glass substrate 2011, and the glass substrate 2011 and the single crystal silicon substrate 2005 were bonded. Note that the polished surface of the single crystal silicon substrate 2005 was used as a bonding surface.

(Sample B)
FIG. 17B-1 shows an appearance photograph in which a part of the plane of the sample B is observed. (B-2) is a schematic diagram of an appearance photograph shown in (B-1). Sample B was produced by the following procedure. A disk-shaped single crystal silicon substrate was cut to form a square shape, and then a single crystal silicon substrate 2103 having a surface polished by chamfering and chemical mechanical polishing was used. The single crystal silicon substrate 2103 was overlapped with the glass substrate 2111 so that the glass substrate 2111 and the single crystal silicon substrate 2103 were bonded. The polished surface of the single crystal silicon substrate 2103 was used as a bonding surface.

  From FIG. 17, in the sample B of (B-1), a region 2120 having a lighter color than the center of the substrate is observed at the peripheral portion of the single crystal silicon substrate 2103. A light-colored region 2120 indicates an unbonded region that is not bonded to the glass substrate 2111. On the other hand, in the sample A of (A-1), a region with a light color as in (B-1) is not observed. It can be seen that the sample A is bonded to the glass substrate 2011 up to the periphery of the single crystal silicon substrate 2005. From this, it can be seen that polishing by chemical mechanical polishing has a factor of forming an unbonded region at the peripheral edge of the substrate. That is, it can be confirmed that by removing the peripheral region of the polishing substrate after polishing by chemical mechanical polishing, it is possible to suppress the formation of an unbonded region in the peripheral portion in the manufacturing process of the bonded substrate.

  In this embodiment, a single crystal silicon substrate which is a bond substrate and a glass substrate which is a base substrate are bonded together with a buffer layer interposed therebetween, and the bond substrate is thinned to form a single crystal silicon on the glass substrate. An SOI substrate on which a layer was formed and a bond substrate on which the single crystal silicon layer was separated were manufactured. Samples I and II, which are bond substrates from which the single crystal silicon layer was separated by thinning, were prepared.

(Sample I)
FIG. 18A is an optical micrograph obtained by observing a part of the peripheral edge of Sample I. 18B is a schematic cross-sectional view of Sample I in FIG. 18A, and FIG. 18C is a schematic top view thereof. FIG. 18D is a schematic cross-sectional view illustrating a manufacturing method of Sample I.

  Sample I was prepared by the following procedure. A disk-shaped single crystal silicon substrate whose surface was polished by chemical mechanical polishing was cut and formed into a quadrangular shape to produce a single crystal silicon substrate. A single crystal silicon substrate having a vertical edge shape was formed so that the edge roll-off region of the disk-shaped single crystal silicon substrate was removed by cutting. Next, a chamfered edge portion of the single crystal silicon substrate was chamfered to form a chamfered single crystal silicon substrate 1805.

A buffer layer 1815 was formed on the polished surface of the single crystal silicon substrate 1805. As the buffer layer 1815, a silicon oxynitride layer, a silicon nitride oxide layer, and a silicon oxide layer were formed in this order from the single crystal silicon substrate 1805 by a plasma CVD method. In addition, an embrittlement layer was formed inside the single crystal silicon substrate 1805. Specifically, a silicon oxynitride layer and a silicon nitride oxide layer were formed over the single crystal silicon substrate 1805. The single crystal silicon substrate 1805 was irradiated with hydrogen from the surface of the silicon nitride oxide layer using an ion doping apparatus, so that an embrittlement layer was formed in a region with a predetermined depth of the single crystal silicon substrate 1805. Formation of the embrittlement layer using an ion doping apparatus was performed under conditions of an acceleration voltage of 35 kv and a dose of 2.2 × 10 ¹⁶ ions / cm ² . Then, a silicon oxide layer was formed over the silicon nitride oxide layer.

  A single crystal silicon substrate 1805 was overlapped with the glass substrate 1811, and the silicon oxide layer which is the outermost surface layer of the buffer layer 1815 and the glass substrate 1811 were bonded to each other. The single crystal silicon layer 1820 was separated by heat treatment so that the single crystal silicon substrate 1805 was divided with the embrittlement layer as a boundary, whereby Sample I was manufactured. The heat treatment was performed in a furnace at 200 ° C. for 2 hours, then heated to near 600 ° C., held for 2 hours, and lowered to a temperature range from 400 ° C. to room temperature. The single crystal silicon layer 1820 is bonded to the glass substrate 1811 with the buffer layer 1815 interposed therebetween, and an SOI substrate in which the single crystal silicon layer 1820 was formed over the glass substrate 1811 was manufactured. FIG. 18D schematically illustrates division of the single crystal silicon substrate 1805 with the embrittlement layer as a boundary.

  In FIG. 18A, a boundary 1850 extending in the vertical direction from the left of the photograph is observed. A boundary 1850 indicates a boundary of a region where the single crystal silicon layer 1820 is separated in the divided single crystal silicon substrate 1805. Further, the single crystal silicon substrate 1805 used for the sample I is chamfered, and the boundary 1850 substantially coincides with the boundary of the chamfered region.

(Sample II)
FIG. 19A is an optical micrograph obtained by observing a part of the peripheral edge of Sample II. 19B is a schematic cross-sectional view of the sample II in FIG. 19A, and FIG. 19C is a schematic top view of the sample II. FIG. 19D is a schematic cross-sectional view illustrating a method for manufacturing Sample II.

  Sample II uses a single crystal silicon substrate 1903 that has been cut into a square shape by cutting a disk-shaped single crystal silicon substrate whose surface has been polished by chemical mechanical polishing, and then has its surface polished by chamfering and chemical mechanical polishing. It was.

  The following was prepared in the same procedure as Sample I. A buffer layer 1915 and a brittle layer were formed inside the single crystal silicon substrate 1903 over the single crystal silicon substrate 1903. The single crystal silicon substrate 1903 and the glass substrate 1911 were overlapped, and the buffer layer 1915 and the glass substrate 1911 were bonded. The single crystal silicon substrate 1920 was divided by dividing the single crystal silicon substrate 1903 with the embrittlement layer as a boundary, so that Sample II was manufactured. In addition, an SOI substrate in which a single crystal silicon layer 1920 was formed over a glass substrate 1911 was manufactured. FIG. 19D schematically illustrates division of the single crystal silicon substrate 1903 with the embrittlement layer as a boundary.

  In FIG. 19A, a boundary 1950 that jaggedly extends in the vertical direction on the right side of the photograph, and a boundary 1955 that extends in the vertical direction on the left side thereof are observed. A boundary 1950 indicates a boundary of a region where the single crystal silicon layer 1920 is separated in the divided single crystal silicon substrate 1903. The boundary 1955 substantially coincides with the chamfered region. Further, the single crystal silicon substrate 1903 used in Sample II is polished by chemical mechanical polishing after formation, and the distance between the boundary 1950 and the boundary 1955 is almost the same as the length in which the edge roll-off region is formed. .

  As shown in FIG. 18, in Sample I, the boundary of the region where the single crystal silicon layer is separated and the boundary of the chamfered region almost coincide with each other, and the single crystal silicon layer is separated to the vicinity of the boundary of the chamfered region. You can see that On the other hand, from FIG. 19, sample II was separated from the boundary of the region where the single crystal silicon layer was separated from the boundary of the chamfered region, and the peripheral portion was peeled off without being able to form a bond with the glass substrate. I understand. Further, the distance between the boundary of the region where the single crystal silicon layer is separated and the boundary of the chamfered region is substantially the same as the length in which the edge roll-off region is formed. From this, it can be seen that the edge roll-off region becomes a factor for forming an unjoined region. From the comparison between Sample I and Sample II, by forming a single crystal silicon substrate in which the peripheral region of the polishing substrate is cut so that the edge roll-off region is removed after polishing by chemical mechanical polishing, an unbonded region is formed in the dividing step. It can be seen that separation from the single crystal silicon substrate can be suppressed, and that the periphery of the bond substrate can be separated as a single crystal silicon layer.

  In Sample II in FIG. 19A, a jagged boundary 1950 is observed. On the other hand, in the sample I of FIG. 18A, a substantially straight boundary 1850 is observed. A boundary 1950 and a boundary 1850 are boundaries of regions where the single crystal silicon layer is separated from the single crystal silicon substrate which is the respective sample. From the comparison between Sample I and Sample II, a single crystal silicon substrate is formed by cutting the peripheral region of the polishing substrate so that the edge roll-off region is removed after polishing by chemical mechanical polishing. It can be seen that the boundary (peripheral edge) of the single crystal silicon layer can be prevented from having a jagged shape.

FIG. 9 is a flow diagram illustrating a method for manufacturing an SOI substrate and a bonded substrate stack. FIGS. 7A and 7B are a perspective view and an enlarged cross-sectional view illustrating a peripheral portion of a single crystal semiconductor substrate. FIGS. Formula diagram. FIG. 10 is a schematic diagram illustrating a method for manufacturing an SOI substrate and a bonded substrate stack. The top view explaining the example of a cutting process of a single-crystal semiconductor substrate. FIG. 10 is a schematic diagram illustrating a method for manufacturing an SOI substrate and a bonded substrate stack. FIG. 9 is a flow diagram illustrating a method for manufacturing an SOI substrate and a bonded substrate stack. FIGS. 7A and 7B are a perspective view and an enlarged cross-sectional view illustrating a peripheral portion of a single crystal semiconductor substrate. FIGS. 10 is a cross-sectional view illustrating a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 1 is a block diagram illustrating an example of a configuration of a microprocessor. The block diagram which shows an example of a structure of RFCPU. The top view and sectional drawing of the pixel of a liquid crystal display device. The top view and sectional drawing of the pixel of an electroluminescent display apparatus. FIG. 6 is an external view illustrating an example of an electronic device. The external appearance photograph which observed a part of sample A and sample B, and its schematic diagram. The optical microscope photograph which observed the peripheral part of sample I, and its schematic diagram. The optical microscope photograph and schematic diagram which observed the peripheral part of sample II.

Explanation of symbols

1003 Single crystal semiconductor substrate 1005 Single crystal semiconductor substrate 1011 Side surface 1012 Edge portion 1013 Edge portion 1014 Edge portion 1015 Region 1016 Region 1030 Region

Claims (11)

A second single crystal having a vertical edge shape by cutting a peripheral region of the first single crystal semiconductor substrate having a polished surface and having an edge roll-off region at a peripheral edge so as to remove the edge roll-off region. A method for manufacturing a semiconductor substrate for an SOI substrate, comprising manufacturing a semiconductor substrate. In claim 1,
A method for manufacturing a semiconductor substrate for an SOI substrate, wherein chamfering is performed on the vertical edge portion of the second single crystal semiconductor substrate having the vertical edge shape. In claim 1 or claim 2,
A method for manufacturing a semiconductor substrate for an SOI substrate, wherein an angle of an edge portion of the second single crystal semiconductor substrate is 90 ° ± 10 ° to be the vertical edge shape. In any one of Claim 1 thru | or 3,
The method for manufacturing a semiconductor substrate for an SOI substrate, wherein the second single crystal semiconductor substrate has a quadrangular shape. A single crystal semiconductor substrate having a vertical edge shape with a polished surface and a base substrate are bonded together with a buffer layer interposed therebetween,
A method for manufacturing an SOI substrate, comprising: thinning the single crystal semiconductor substrate over the base substrate. In claim 5,
As the thinning of the single crystal semiconductor substrate,
A manufacturing method of an SOI substrate, wherein an embrittlement layer is formed inside the single crystal semiconductor substrate, and the single crystal semiconductor substrate is divided with the embrittlement layer as a boundary. In claim 5 or claim 6,
A method for manufacturing an SOI substrate, wherein an angle of an edge portion of the single crystal semiconductor substrate is 90 ° ± 10 ° to be the vertical edge shape. In any one of Claims 5 thru | or 7,
The vertical edge portion of the single crystal semiconductor substrate having the vertical edge shape is chamfered, and the single crystal semiconductor substrate subjected to the chamfering process is used for bonding to the base substrate. A method for manufacturing an SOI substrate. In any one of Claims 5 thru | or 8,
A peripheral region of a single crystal semiconductor substrate having an edge roll-off region at a peripheral edge is cut so that the edge roll-off region is removed to produce a single crystal semiconductor substrate having the vertical edge shape,
A method for manufacturing an SOI substrate, which is used for bonding to the base substrate. In any one of Claims 5 thru | or 9,
The method for manufacturing an SOI substrate, wherein the single crystal semiconductor substrate having the vertical edge shape is formed in a quadrangular shape. In any one of Claims 5 thru | or 10,
A method for manufacturing an SOI substrate, wherein a glass substrate is used as the base substrate.