JP2010087162A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To suppress junction leakage current.
A silicon nitride film 16 is formed above the source region 2b around the common source line contact CSL and at the top of the drain region 2a around the bit line contacts CBa and CBb. ing. The formation height H1 of the silicon nitride film 16b around the common source line contact CSL is higher than the formation height H2 of the silicon nitride film 16a around the bit line contacts CBa and CBb. It functions as a stopper for the hour. For this reason, the depth of the trench and the hole at the time of anisotropic etching with respect to the surface of the semiconductor substrate 2 can be adjusted to be substantially the same on the source region 2b side and the drain region 2a side.
[Selection] Figure 5

Description

  The present invention relates to a semiconductor device such as a semiconductor memory device such as a NAND flash memory device and a manufacturing method thereof.

  In the development of semiconductor memory devices, miniaturization of elements has been promoted year by year in order to achieve large capacity and low cost. For example, in a NAND flash memory device, the wiring pitches such as bit lines and word lines have been miniaturized. When miniaturizing each wiring pitch, it is difficult to open a contact hole miniaturized to the same degree as the line wiring at a high aspect. Therefore, every other bit line contact and source line contact should be arranged as a bit line. A so-called plover arrangement shifted in the direction has been proposed (see, for example, Patent Document 1).

  In the configuration in which the bit line contact and the source line contact are arranged in a staggered manner, when further miniaturization is performed, the common source line is formed by focusing on the source line contact and forming the source line contact in the groove in common. A configuration has been proposed in which the width of a region in which a contact is provided (region between select gates) is further narrowed (see, for example, Patent Document 2).

  When manufacturing a semiconductor memory device having such a configuration, when performing processing for simultaneously opening a hole on the bit line contact side and a groove on the common source line contact side, for example, an RIE (Reactive Ion Etching) method or the like is used. Processed by anisotropic etching. In general, for example, when holes and grooves having substantially the same hole diameter and groove width are formed at the same time, the groove etching rate is high.

For this reason, when the hole on the bit line contact side and the groove on the common source line contact side are opened simultaneously, the etching rate of the groove on the common source line contact side is increased, the depth of the groove is increased, and the amount of substrate scraping Increase. As described above, when the amount of chipping of the substrate increases, the barrier metal film such as titanium (Ti) or the like to be formed later and the diffusion layer are more likely to react during the silicidation, resulting in a junction leak. is there.
JP 2005-354003 A JP 2006-303009 A

  It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can suppress the occurrence of junction leakage current.

  According to one embodiment of the present invention, a semiconductor substrate, a plurality of source regions formed apart from the surface layer of the semiconductor substrate, and a plurality of drain regions formed apart from the plurality of source regions on the surface layer of the semiconductor substrate A first interlayer insulating film formed on each of the plurality of source regions and a plurality of drain regions, a second interlayer insulating film formed on the first interlayer insulating film, and the first and second interlayers A common source line contact formed in a groove that penetrates the insulating film and crosses over the plurality of source regions, and a hole in the plurality of drain regions that penetrates the first and second interlayer insulating films, respectively. A drain contact; a first stopper portion formed between the first and second interlayer insulating films around the common source line contact; and the drain contact around the first contact portion. And an etching stopper film having an etching selectivity with respect to the second interlayer insulating film, the second stopper portion being interposed between the second interlayer insulating films. And an etching stopper film formed at a position higher than the second stopper portion.

  One embodiment of the present invention includes a step of forming a gate electrode over a semiconductor substrate through a gate insulating film, a step of dividing the gate electrode into a plurality of portions, and a source / drain region on both sides of the plurality of gate electrodes. A step of forming a first interlayer insulating film in the divided region of the gate electrode, a step of forming a position adjusting film on the first interlayer insulating film on the source / drain region, A step of removing the position adjustment film on the first interlayer insulating film, and a step of forming an etching stopper film directly on the upper surface of the first interlayer insulating film on the drain side, on the position adjustment film on the source side Forming an etching stopper film; forming a second interlayer insulating film on the etching stopper film; forming a hole on the drain side of the second interlayer insulating film; and A step of forming a groove on the source side until the etching stopper film is exposed; and simultaneously forming the hole and the groove until the surface of the semiconductor substrate is exposed in the etching stopper film and the first interlayer insulating film. And a process.

  According to the present invention, generation of junction leakage current can be suppressed.

  Hereinafter, an embodiment of the present invention applied to a NAND flash memory device will be described with reference to the drawings. In the following description in the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

FIG. 1 shows an equivalent circuit of a part of a memory cell array in a NAND flash memory device.
As shown in FIG. 1, NAND cell units UC are arranged in a matrix in the memory cell array Ar of the NAND flash memory device 1. In this NAND cell unit UC, two (a plurality of) select gate transistors Trs1, Trs2 and adjacent ones located between the two select gate transistors Trs1, Trs2 share a source / drain region in series. A plurality of (for example, 32) memory cell transistors Trm are connected.

  In FIG. 1, the memory cell transistors Trm arranged in the X direction (word line direction, channel width direction) are commonly connected by a word line (control gate line) WL. Further, the select gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a common select gate line SGL1. Further, the selection gate transistors Trs2 are commonly connected by a common selection gate line SGL2.

  FIG. 2 shows a partial layout pattern of the memory cell region. As shown in FIG. 2, the plurality of NAND cell units UC are formed in an active area Sa separated from each other by an element isolation region Sb having an STI (Shallow Trench Isolation) structure extending in the Y direction. A selection gate electrode SGD is formed in a planar intersection region between the selection gate line SGL1 and the active area Sa. A selection gate electrode SGS is formed in a planar intersection region between the selection gate line SGL2 and the active area Sa. A memory cell gate electrode MG is formed in a planar intersection region between the word line WL and the active area Sa.

  Bit line contacts CBa and CBb are formed as drain contacts on the drain region 2a (see FIG. 5B) of the select gate transistor Trs1, and these bit line contacts CBa and CBb are orthogonal to the X direction in FIG. Connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction). The bit line contacts CBa and CBb are arranged in a zigzag and zigzag pattern on each active area Sa spaced in the X direction between the select gate lines SGL1 and SGL1.

  The select gate transistor Trs2 is connected to a common source line contact CSL extending in the X direction in FIG. 1 via a source region 2b (see FIG. 5A). The common source line contact CSL is located between the select gate lines SGL2 and SGL2 and extends along the X direction.

  FIG. 3 schematically shows the extending direction of the bit line. As shown in FIG. 3, the bit line BL is configured to be positioned above the bit line contacts CBa and CBb and above the active area Sa. Note that the common source line contact CSL in FIG. 3 is not structurally connected to the bit line BL.

  4A shows a schematic longitudinal sectional view on the source side along the line AA in FIG. 2, and FIG. 4B shows the drain side along the line BB in FIG. The schematic longitudinal cross-sectional view of is shown. FIG. 5 is a schematic longitudinal sectional view of the cell unit along the line CC in FIG.

  As shown in FIGS. 4A and 4B, the first conductive type (P-type) semiconductor substrate 2 is formed with a plurality of element isolation grooves 3 along the Y direction, and the active area Sa. Is divided into a plurality of sections in the X direction. These active areas Sa indicate a region including a drain region 2a and a source region 2b formed in the surface layer of the semiconductor substrate 2, and a channel region (not indicated) sandwiched between the drain region 2a and the source region 2b. Yes. An element isolation insulating film 4 is embedded in the element isolation trench 3. The element isolation insulating film 4 is formed of, for example, a silicon oxide film.

  On the source side (the side where the common source line contact CSL is formed) shown in FIG. 4A, a source region 2b that becomes an impurity diffusion region of a second conductivity type (N type) opposite to the first conductivity type. Are formed on the surface layer of the semiconductor substrate 2, and a plurality of the source regions 2b are arranged in parallel at equal intervals in the X direction with the element isolation insulating film 4 interposed therebetween. The element isolation insulating film 4 is formed such that its upper surface is located below the upper surface of the active area Sa and is located above the lowermost end of the source region 2b.

  As shown in FIG. 4A, one common source line contact CSL is formed on the plurality of source regions 2b spaced in the X direction. The common source line contact CSL includes a metal layer such as tungsten (W), for example, and the lower end thereof is formed above the lowermost end of the source region 2b. The common source line contact CSL is formed in direct contact over the upper surface of the element isolation insulating film 4, over the upper side surfaces of the plurality of source regions 2b, and over the upper surface.

  In addition, on the drain side (the formation region side of the bit line contacts CBa and CBb) shown in FIG. 4B, the second conductivity type (N-type) impurity introduction region and the drain region 2a serving as the impurity diffusion region are provided on the semiconductor substrate. The drain regions 2a are arranged in parallel at equal intervals while being spaced apart from each other across the element isolation insulating film 4 in the X direction. The element isolation insulating film 4 is formed such that its upper surface is located below the upper surface of the active area Sa and is located above the lower end of the drain region 2a.

  Bit line contacts CBa are formed on every other active area Sa spaced apart in the X direction. These bit line contacts CBa are configured to include a metal layer such as tungsten (W). Although not shown in FIG. 4B, every other bit line contact CBb is formed on a plurality of active areas Sa where no bit line contact CBa is formed. In the same manner as the above, it is configured to include a metal layer such as tungsten (W).

  FIG. 4B schematically shows a formation state of the bit line contact CBa particularly when an alignment shift occurs in the X direction. As shown in FIG. 4B, the bit line contact CBa is formed in a state where the center in the X direction is shifted by a dimension δ in the X direction from the center in the X direction of the active area Sa. Although the upper surface of the drain region 2a formed on the surface layer of the semiconductor substrate 2 is substantially flat, the upper surface of the drain region 2a on the bit line contact CBa formation side is formed to be curved, and the bit line contact CBa is formed in the drain region. It is formed along the upper portion of 2a and the upper portion of the element isolation insulating film 4 located beside the drain region 2a.

  As shown in FIG. 5, a well (not shown) is formed on the surface layer of a semiconductor substrate 2 (for example, a p-type silicon substrate), and a gate insulating film 5 is formed on the upper surface of the semiconductor substrate 2. On the upper surface of the gate insulating film 5, two (plural) gate electrodes SGD and SGS are formed apart from each other. In addition, between the two select gate electrodes SGD-SGS, a gate insulating film 5 is formed on the upper surface of the semiconductor substrate 2, and a plurality (for example, 32 pieces) of the gate insulating film 5 are separated from each other on the upper surface of the gate insulating film 5. , 64) memory cell gate electrodes MG are formed. The semiconductor substrate 2 may be an n-type silicon substrate.

  The memory cell gate electrode MG is configured by stacking a floating gate electrode FG, an inter-gate insulating film 7, and a control gate electrode CG. The selection gate electrodes SGD and SGS are substantially the same structure and made of the same material as that of the memory cell gate electrode MG. However, an opening is formed in the center of the inter-gate insulating film 7. The floating gate electrode FG and the control gate electrode CG are configured as a gate electrode integrally formed.

  The floating gate electrode FG is composed of, for example, the polycrystalline silicon layer 6 and functions as a charge storage layer. The inter-gate insulating film 7 is formed of, for example, an ONO film (silicon oxide film-silicon nitride film-silicon oxide film). The NONON film (silicon nitride film-silicon oxide film-silicon nitride film-silicon oxide film-silicon nitride film) may be formed by performing radical nitriding before and after the ONO film is formed, or alumina may be used. You may form with the film | membrane containing. The control gate electrode CG is a silicide in which, for example, the polycrystalline silicon layer 8 and the upper portion of the polycrystalline silicon layer 8 are silicided with any one kind of metal such as cobalt (Co), nickel (Ni), tungsten (W), etc. The layer 9 is laminated. Note that the control gate electrode CG may be applied to a poly gate or a metal gate.

  These memory cell gate electrode MG and select gate electrodes SGD, SGS are configured by dividing the layers 6 to 9 into a plurality in the Y direction. Source / drain regions 2a to 2c serving as impurity introduction layers and impurity diffusion layers are formed on the surface layer of the semiconductor substrate 2 along the Y direction side of the memory cell gate electrode MG and the selection gate electrodes SGD and SGS. These source / drain regions 2a to 2c are regions where the second conductivity type (N-type) impurity is introduced and diffused, but in the notation in the drawing, between the select gate electrodes SGD-SGD. The surface layer region of the semiconductor substrate 2 positioned is the drain region 2a, the surface layer region of the semiconductor substrate 2 positioned between the select gate electrodes SGS-SGS is the source region 2b, and the select gate electrodes SGS-MG, SGD-MG, MG A surface layer region of the semiconductor substrate 2 located between −MG is a source / drain region 2c.

  A silicon oxide film 10 is formed as a sidewall insulating film along both side surfaces of each gate electrode MG, SGD, SGS. The silicon oxide film 10 is formed along the surface of the semiconductor substrate 2 between the adjacent gate electrodes MG-MG, between SGD-MG, and between SGS-MG. In the present embodiment, the silicon oxide film 10 is formed directly on the upper surface of the semiconductor substrate 2 between adjacent gate electrodes MG-MG, SGD-MG, and SGS-MG. A gate insulating film 5 may be formed on the upper surface of the gate insulating film 5, and a silicon oxide film 10 may be formed on the upper surface of the gate insulating film 5.

  A silicon oxide film 11 is embedded and formed as an insulating film inside the silicon oxide film 10 between the gate electrodes MG-MG, SGD-MG, and SGS-MG. The silicon oxide films 10 and 11 are formed such that their upper surfaces (upper ends) are located below the upper surface of the silicide layer 9 and above the upper surface of the intergate insulating film 7. The silicon oxide film 11 is formed between the adjacent selection gate electrodes SGD-SGD and between the SGS-SGS with the silicon oxide film 10 interposed along the side wall surfaces of the selection gate electrodes SGD, SGS. However, the Y-direction width is processed and formed into a spacer shape so that the upper side is thinner than the lower side.

  The common source line contact CSL described above is formed between the selection gate electrode SGS and the selection gate electrode SGS of an adjacent block on the side of the source region 2b side. The common source line contact CSL is configured to be located near the center of the selection gate electrodes SGS-SGS. The common source line contact CSL extends upward from the upper surface of the semiconductor substrate 2 and is formed in a rectangular column shape in the printing surface and the depth direction. On the side of the selection gate electrode SGD on the drain region 2a side, a bit line contact CBa is formed between the selection gate electrode SGD of an adjacent block and close to one side of one of the selection gate electrodes SGD. . The bit line contact CBa extends upward from the upper surface of the semiconductor substrate 2 and is formed, for example, in a columnar shape or an elliptical column shape.

  On the side of the common source line contact CSL, insulating films 12 to 17 are sequentially stacked on the upper surface of the semiconductor substrate 2 from the lower layer side. In other words, the common source line contact CSL is formed so as to penetrate the insulating films 12 to 17. On the other hand, insulating films 12 to 14, 16, and 17 are sequentially stacked on the upper surface of the semiconductor substrate 2 from the lower layer side beside the bit line contact CBa. In other words, the bit line contact CBa is formed so as to penetrate the insulating films 12 to 14, 16 and 17.

  The silicon oxide film 12 is formed along the upper surface of the semiconductor substrate 2 and is formed along the outer surface of the insulating film 11 facing between the adjacent select gate electrodes SGD-SGD and between SGS-SGS. ing. The silicon nitride film 13 is formed along the upper surface and the inner surface of the silicon oxide film 12 along the upper surface of the semiconductor substrate 2 and functions as a barrier film for suppressing the passage of impurities and also serves as an etching stopper. Function. A BPSG (Boro-phospho silicate glass) film 14 is embedded and formed as an interlayer insulating film inside the silicon nitride film 13.

  When the formation states of the insulating films 12 to 14 are compared between the periphery of the common source line contact CSL and the periphery of the bit line contact CBa, the upper surface position is closer to the periphery of the bit line contact CBa than the periphery of the common source line contact CSL. It is formed low.

  A silicon oxide film 15 is formed directly over the upper surfaces of the silicon oxide films 10 and 11, over the entire upper surface of the selection gate electrode SGS, over the entire upper surface of the memory cell gate electrode MG, and over a partial upper surface of the selection gate electrode SGD. ing. This silicon oxide film 15 functions as a position adjusting film. In the cross section shown in FIG. 5, the silicon oxide film 15 is not formed on a part of the upper surface of the selection gate electrodes SGD-SGD that are adjacent to each other, and a silicon nitride film 16 is formed instead.

  The silicon nitride film 16 is formed on the upper surface of the silicon oxide film 15 and functions as a stopper film. In the peripheral region of the bit line contact CBa, the silicon nitride film 16 is formed on the silicon oxide films 10 to 12, 14 and the silicon nitride film 13 between the upper side surfaces of the adjacent selection gate electrodes SGD-SGD. Yes.

  In the peripheral region of the common source line contact CSL, the silicon oxide film 15 is formed on the upper surface of the insulating films 10 to 14, and the upper surface of the insulating film 10 to 14 is more common than the peripheral region of the bit line contact CBa. It is formed low in the peripheral region of the line contact CSL. Therefore, when the peripheral region of the bit line contact CBa and the peripheral region of the source line contact CSL are compared, the silicon nitride film 16 has a difference in film thickness between the silicon oxide film 15 and the insulating films 10 to 14. It is formed at a low position in the peripheral region of the bit line contact CBa by the film thickness obtained by adding together.

  The upper surface height H1 of the silicon nitride film 16b (corresponding to the stopper portion) in the peripheral region of the common source line contact CSL, and the upper surface height H2 of the silicon nitride film 16a (corresponding to the stopper portion) in the peripheral region of the bit line contact CBa Are compared, the height H1 is higher than the height H2.

  A silicon oxide film 17 is formed directly on the upper surface of the silicon nitride film 16 as an interlayer insulating film. The silicon oxide film 17 is formed by d-TEOS, for example. The silicon nitride film 16 functions as a stopper film when the silicon oxide film 17 is subjected to anisotropic etching. However, by adjusting the height position of the stopper film, the groove for the common source line contact CSL and the bit line contact are formed. It is possible to adjust the depth position when the CBa hole is simultaneously opened.

  A manufacturing process of the structure in the memory cell region of the NAND flash memory device will be described. In addition, the characteristic part which concerns on this embodiment is mainly demonstrated, and description of the process before and behind is abbreviate | omitted. If the problem of the present invention can be solved, it may be added if it is a general process, may be omitted as necessary, and the process may be replaced.

  6 to 8 schematically show cross-sectional views of one manufacturing stage around the memory cell gate electrode. 9 and 10 schematically show perspective views of one manufacturing stage in the vicinity of the bit line contact formation region or the common source line contact formation region, and FIGS. FIG. 6 schematically shows a cross-sectional view corresponding to FIG. 5.

  As shown in FIG. 6, ion implantation for forming well and channel regions is performed on the surface layer of the semiconductor substrate 2, and a silicon oxide film, for example, is formed as a gate insulating film 5 on the semiconductor substrate 2 by thermal oxidation treatment. Then, amorphous silicon for the floating gate electrode FG is deposited by the LP-CVD method. Since amorphous silicon for the floating gate electrode FG is polycrystallized by a subsequent heat treatment, the reference numerals are given as the polycrystal silicon layer 6 in the drawings subsequent to FIG. The silicon layer 6 will be described.

Next, a mask material (not shown) is formed on the polycrystalline silicon layer 6 and patterned by a lithography technique. As shown in FIG. 7, a plurality of element isolation grooves are provided along the Y direction and spaced apart in the X direction. 3 is formed, and the element isolation insulating film 4 is embedded in the element isolation trench 3. At this time, the element isolation insulating film 4 is formed so that its upper surface is located below the upper surface of the polycrystalline silicon layer 6 and above the upper surface of the gate insulating film 5.

  Next, as shown in FIG. 8, an intergate insulating film 7 made of an ONO film (a laminated film of silicon oxide film-silicon nitride film-silicon oxide film), amorphous silicon for the control gate electrode CG, and gate processing A silicon nitride film 18 is sequentially deposited as a mask material. Since amorphous silicon for the control gate electrode CG is polycrystallized by a subsequent heat treatment, the drawings after FIG. 8 are labeled as the polycrystal silicon layer 8, and in the following description The crystal silicon layer 8 will be described. Further, the inter-gate insulating film 7 may be formed as a NONON film by performing radical nitriding before and after the ONO film is formed, or may be formed of a film containing alumina. FIG. 9 schematically shows a perspective view in this manufacturing stage.

  Next, a resist (not shown) is patterned on the silicon nitride film 18, and as shown in FIG. 10, the silicon nitride film 18, the polycrystalline silicon layer 8, the intergate insulating film 7, and the polycrystalline are formed by RIE. The silicon layer 6 and, if necessary, the gate insulating film 5 are sequentially anisotropically etched to divide the layers 6 to 8 constituting the selection gate electrodes SGD and SGS and the memory cell gate electrode MG into a plurality of layers. As shown in FIG. 10, the element isolation insulating film 4 is formed so that the central portion between the adjacent active areas Sa-Sa is recessed.

  FIG. 11 schematically shows a cross section along the line CC in this manufacturing stage. As shown in FIG. 11, the polycrystalline silicon layers 6 and 8 for the selection gate electrodes SGD and SGS are structured and electrically connected through openings formed in the intergate insulating film 7. . This is because amorphous silicon is thinly deposited on the inter-gate insulating film 7 before the polycrystalline silicon layer 8 is thickly deposited, and then holes are formed in the formation regions of the selection gate electrodes SGD and SGS by RIE (Reactive Ion Etching) method. This is because the polycrystalline silicon layer 8 is deposited thick after the provision of.

  Next, as shown in FIG. 12, a silicon oxide film 10 is formed along the sidewalls of the films 6, 7, 8, and 18, and low concentration impurities for forming the source / drain regions 2a, 2b, and 2c are ion-implanted. To do. This impurity is activated by a subsequent heat treatment. In the drawings after FIG. 12, the low concentration impurity introduction region introduced into the drain region 2a is shown as a region 2ba, and the low concentration impurity introduction region introduced into the source region 2b is shown as a region 2ba. The impurity introduction region 2aa indicates a part of the drain region 2a, and the impurity introduction region 2ba indicates a part of the source region 2b.

  Next, as shown in FIG. 13, a silicon oxide film 11 is deposited between the laminated films 6 to 8 and 18 by the LP-CVD method, and the silicon oxide film 11 is etched by the RIE method. The upper surface of the silicon oxide film 11 between the films 6 to 8 and 18 is dropped, and the silicon oxide film 11 between adjacent select gate electrodes SGD-SGD is processed as a spacer 11a for LDD (Lightly Doped Drain) formation. Using the spacer 11a as a mask, high-concentration impurities for making contact with the source / drain regions 2a and 2b are ion-implanted. This impurity is activated by a subsequent heat treatment. In the drawings subsequent to FIG. 13, the low concentration impurity introduction region introduced into the drain region 2a is shown as a region 2ab, and the high concentration impurity introduction region introduced into the source region 2b is shown as a region 2bb. The impurity introduction region 2bb shows a part of the source region 2b, and the impurity introduction region 2ab becomes a part of the drain region 2a.

  Next, as shown in FIG. 14, a silicon oxide film 12 and a silicon nitride film 13 are sequentially formed in a liner shape, and then a BPSG film 14 is deposited, and the BPSG film 14 is flattened by CMP using the silicon nitride film 13 as a stopper. By performing the conversion process, the BPSG film 14 is embedded inside the silicon nitride film 13 in the formation region of the common source line contact CSL, the formation region of the bit line contacts CBa and CBb, and the peripheral region thereof.

  Next, as shown in FIG. 15, the silicon nitride films 13 and 18 and the silicon oxide films 11, 12, and 14 are etched by the RIE method to expose the upper surface of the polycrystalline silicon layer 8, and the natural oxide film on the exposed surface The silicide layer 9 is formed on the polycrystalline silicon layer 8 by repeatedly performing a lamp annealing process and an unreacted metal stripping process by forming a metal such as cobalt using a sputtering technique and removing the metal by sputtering. Thus, the electrical configuration of the gate electrodes MG, SGD, and SGS is completed.

  Next, as shown in FIG. 16, on the upper surfaces of the gate electrodes MG, SGD, and SGS, between the upper portions of the gate electrodes MG-MG, between the upper portions of the gate electrodes SGD-SGD, between the upper portions of the gate electrodes SGS-SGS, A silicon oxide film 15 of, eg, about 50 nm is formed by LP-CVD using TEOS gas between the upper portions of the gate electrodes MG-SGD and between the upper portions of the gate electrodes MG-SGS. Thereby, the silicon oxide film 15 is buried between the upper portions of the adjacent gate electrodes MG-MG, and the parasitic capacitance between the adjacent gate electrodes MG-MG can be suppressed.

  Next, as shown in FIG. 17, a resist 19 is applied, and the bit line contact CBa, CBb formation region and the peripheral region between the select gate electrodes SGD-SGD (between the select gate lines SGL1-SGL1) are applied by lithography. Then, patterning is performed so as to form an opening 19a, and a region other than the region where the opening 19a is formed is covered with a resist 19. Next, the upper portion of the silicon oxide film 15 is etched by RIE using the resist 19 as a mask. By this process, the upper part of the BPSG film 14 is also slightly removed. The removal process of the upper part of the BPSG film 14 may be performed as necessary. Further, in the present embodiment, as shown in FIG. 17, the etching process is performed so that a part of the upper surface and a part of the upper side surface of the selection gate electrode SGD are exposed, but the bit line contacts CBa and CBb are formed. If it is included, it is not always necessary to expose and process.

  Next, as shown in FIG. 18, the resist 19 is removed by ashing or the like, and a silicon nitride film 16 is formed with a thickness of about 50 nm by LP-CVD. The silicon nitride film 16 is formed along the upper surface of the silicon oxide film 15 on the source region 2b side. On the drain region 2a side, the silicon nitride film 16 is formed on the top surfaces of the silicon oxide films 11a and 12, the silicon nitride film 13 and the BPSG film 14 and on the pair of select gate electrodes SGD and SGD, particularly between the select gate electrodes SGD and SGD. Are formed along part of the upper surface and upper side surface of the bit line contact CBa, CBb formation region side, and the side surface of the silicon oxide film 15 facing each other across the formation region of the bit line contacts CBa, CBb.

  The silicon nitride film 16 has a higher position on the side where the common source line contact CSL is formed (between the selection gate electrodes SGS and SGS) than on the side where the bit line contacts CBa and CBb are formed (between the selection gate electrodes SGD and SGD). The film is formed at heights H1 and H2 in FIG. This is because the silicon nitride film 16 is formed at different heights by the removal region above the silicon oxide film 15 and the BPSG film 14.

  Next, as shown in FIG. 19, a silicon oxide film 17 is deposited as an interlayer insulating film to a thickness of, for example, about 300 nm by plasma CVD. Next, as shown in FIG. 20, a resist 19 is applied and the resist 19 is patterned. The opening area of the resist 19 is a formation area of the common source line contact CSL and formation areas of the bit line contacts CBa and CBb, and is formed by a groove along the X direction and a staggered hole, respectively.

  Next, as shown in FIG. 21, the silicon oxide film 17 is anisotropically etched to reach the upper surface of the silicon nitride film 16 by RIE to form a hole DH between the select gate electrodes SGD-SGD and at the same time select gate electrode A trench (groove) SH is formed between SGS and SGS, and is temporarily stopped. This etching condition is set such that the etching selectivity of the silicon oxide film is high with respect to the silicon nitride film. The reason for once stopping is to consider in advance the difference in the etching rate between the formation process of the trench SH and the formation process of the hole DH. In the manufacturing stage shown in FIG. 21, the etching target film (BPSG film 14 and the like) located below the silicon nitride film 16 has a relatively thick etching target film thickness on the common source line contact CSL side. It is formed relatively thin on the CBa and CBb sides.

  Next, as shown in FIG. 22, the processing conditions are changed, and the hole DH and the trench SH are simultaneously formed by the RIE method so as to reach the upper surface of the semiconductor substrate 2. When the trench SH and the hole DH having substantially the same width and size are formed at the same time, the etching rate is relatively high in the formation region of the trench SH, and the etching rate is relatively low in the formation region of the hole DH. Further, in this second stage etching process, the silicon nitride film 16 needs to be etched, so that it is difficult to adjust the processing conditions that can sufficiently secure the selection ratio of silicon to the semiconductor substrate 2. It will be shaved at the same time.

  However, as shown in FIG. 22, when the processing time is adjusted by the RIE method and the hole DH and the trench SH are simultaneously formed, the depth of the trench SH formed between the select gate electrodes SGS-SGS with respect to the surface of the semiconductor substrate 2 and the selection are selected. The depth of the hole DH formed between the gate electrodes SGD-SGD with respect to the surface of the semiconductor substrate 2 can be adjusted to substantially the same depth.

  FIG. 23A and FIG. 23B schematically show the formation state of the trench SH on the source region 2b side and the hole DH on the drain region 2a side at this time point corresponding to FIG. As shown in FIGS. 23 (a) and 23 (b), the processing steps can be formed substantially the same on the source region 2b side and the drain region 2a side. Thereby, the etching rate difference can be eliminated.

  Next, as shown in FIG. 4, by forming a metal layer such as a barrier metal or tungsten in the hole DH and in the trench SH, the bit line contacts CBa and CBb are formed at the same time as the common source line contact CSL. A material such as titanium (Ti) is used for the barrier metal. When the silicon substrate 2 is silicided with the barrier metal, depending on the formation depth of the trench SH and the hole DH in the previous stage, the source / drain region 2a The silicide reaction is promoted to the deep position of the diffusion layer 2b, and the generation of the junction leakage current is not hindered.

  In this embodiment, since the etching depth can be adjusted to be substantially the same on the drain region 2a side and the source region 2b side, the silicidation reaction depth can be limited by adjusting the etching adjustment time and the like. Generation of leakage current can be suppressed. In the second-stage etching process, it is desirable to make the cut depth of the semiconductor substrate 2 on the source region 2b side coincide with the cut depth of the semiconductor substrate 2 on the drain region 2a side. It can be easily adjusted by changing the film thickness. Since the subsequent steps shift to a step of forming the upper layer side bit line BL, the description thereof is omitted.

  According to the present embodiment, the silicon nitride film 16 is formed above the source region 2b in the peripheral (surrounding) region of the common source line contact CSL, and in the periphery (surrounding) of the bit line contacts CBa and CBb. The silicon nitride film 16b formed above the drain region 2a and serving as a stopper around the common source line contact CSL has a height H1 of silicon nitride serving as a stopper around the bit line contacts CBa and CBb. Since the film 16a is formed at a position higher than the formation height H2, the depth with respect to the surface of the semiconductor substrate 2 during anisotropic etching can be adjusted to be substantially the same, and the junction can be adjusted by adjusting the etching time. Generation of leakage current can be suppressed.

  Further, after forming the BPSG film 14 on the drain region 2a side and the source region 2b side, a silicon oxide film 15 is formed on the BPSG film 14 as a position adjusting film, and the bit line contacts CBa, CBb on the drain region 2a side are formed. And the silicon oxide film 15 in the periphery thereof are removed to form a BPSG film 14 above the source region 2b and a silicon nitride film 16 via the silicon oxide film 15, and at the same time, a BPSG film 14 above the drain region 2a. The silicon nitride film 16 is formed through the silicon nitride film 16, the silicon oxide film 17 is formed on the silicon nitride film 16, and the grooves SH and holes DH are formed until the silicon nitride film 16 is exposed to the silicon oxide film 17 by anisotropic etching. The etching process is temporarily stopped, the processing conditions are changed, and the silicon nitride film 16 and the BPSG film 14 are switched. Drain region 2a side and the groove SH to the source region 2b side to form a hole DH simultaneously. For this reason, the etching depth can be formed at substantially the same depth on the drain region 2a side and the source region 2b side, and reacts to a deep position of the diffusion layer during the barrier metal film formation and silicidation. This can prevent the occurrence of junction leak.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.
Although applied to a NAND flash memory device, the present invention can be applied to other semiconductor memory devices such as a NOR flash memory device and other semiconductor devices.
The semiconductor substrate 2 is not limited to a p-type silicon substrate, and may be a substrate in which a p-well is formed on an n-type silicon substrate, or a semiconductor substrate made of another material. The silicon oxide film 12 and the silicon nitride film 13 may be provided as necessary. When the trench SH and the hole DH are formed in the silicon oxide film 17 up to the upper surface of the silicon nitride film 16, the trench SH and the hole DH are formed at the same time, but may be formed in separate steps.

  The silicon nitride film 16 is applied as the etching stopper film, and the BPSG film 14 and the d-TEOS silicon oxide film 17 are applied as the interlayer insulating film. However, the materials are not limited to these combinations, and are materials having etching selectivity with each other. Any film may be applied as long as it is present.

Electrical configuration diagram showing an embodiment of the present invention Plan view schematically showing the main part A plan view schematically showing a formation state of a bit line which is an upper layer wiring (A) is a cutaway view schematically shown along line AA in FIG. 2, and (b) is a cutaway view schematically shown along line BB in FIG. Cutaway view schematically shown along line CC in FIG. Cutaway view schematically showing one manufacturing stage (Part 1) Cutaway view schematically showing one manufacturing stage (Part 2) Cutaway view schematically showing one manufacturing stage (Part 3) Perspective view schematically showing one manufacturing stage (Part 1) Perspective view schematically showing one manufacturing stage (No. 2) Cutaway view schematically showing one manufacturing stage (Part 4) Cutaway view schematically showing one manufacturing stage (Part 5) Cutaway view schematically showing one manufacturing stage (Part 6) Cutaway view schematically showing one manufacturing stage (Part 7) Sectional view schematically showing one manufacturing stage (No. 8) Sectional view schematically showing one manufacturing stage (No. 9) Cutaway view schematically showing one manufacturing stage (No. 10) Sectional view schematically showing one manufacturing stage (Part 11) Cutaway view schematically showing one manufacturing stage (No. 12) Cutaway view schematically showing one manufacturing stage (No. 13) Cutaway view schematically showing one manufacturing stage (No. 14) Cutaway view schematically showing one manufacturing stage (No. 15) Sectional view schematically showing one manufacturing stage (No. 16)

Explanation of symbols

  In the drawing, 2 is a semiconductor substrate, 2a is a drain region, 2b is a source region, 14 is a BPSG film (interlayer insulating film), 16 is a silicon nitride film (etching stopper film), 16a is a silicon nitride film (stopper portion), 16b Denotes a silicon nitride film (stopper portion), 17 denotes a silicon oxide film (interlayer insulating film), CBa and CBb denote bit line contacts (drain contacts), and CSL denotes a common source line contact.

Claims (4)

A semiconductor substrate;
A plurality of source regions spaced apart from the surface layer of the semiconductor substrate;
A plurality of drain regions formed on a surface layer of the semiconductor substrate apart from the plurality of source regions;
A first interlayer insulating film formed on each of the plurality of source regions and the plurality of drain regions;
A second interlayer insulating film formed on the first interlayer insulating film;
A common source line contact configured in a trench that penetrates the first and second interlayer insulating films and crosses over a plurality of source regions;
Drain contacts respectively formed in holes on a plurality of drain regions penetrating the first and second interlayer insulating films;
A first stopper portion formed between the first and second interlayer insulating films around the common source line contact and a first stopper portion formed between the first and second interlayer insulating films around the drain contact. An etching stopper film having an etching selectivity with the second interlayer insulating film, wherein the first stopper part is configured to be higher than the second stopper part. A semiconductor device comprising an etching stopper film.   2. The semiconductor device according to claim 1, wherein the second interlayer insulating film is formed of a silicon oxide film, and the etching stopper film is formed of a silicon nitride film. Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Dividing the gate electrode into a plurality of parts;
Forming a first interlayer insulating film in a divided region of the gate electrode located on a source / drain region on both sides of the plurality of gate electrodes;
Forming a position adjusting film on the first interlayer insulating film on the source / drain region;
Removing the position adjustment film on the first interlayer insulating film on the drain region side;
Forming an etching stopper film directly on the upper surface of the first interlayer insulating film on the drain side, and forming an etching stopper film on the position adjustment film on the source side;
Forming a second interlayer insulating film on the etching stopper film;
Forming a hole on the drain side of the second interlayer insulating film, and forming a groove on the source side of the second interlayer insulating film until the etching stopper film is exposed;
And a step of simultaneously forming the hole and the groove until the surface of the semiconductor substrate is exposed in the etching stopper film and the first interlayer insulating film.   4. The semiconductor device according to claim 3, wherein the etching stopper film is formed of a silicon nitride film, the second interlayer insulating film is formed of a silicon oxide film, and the position adjusting film is formed of a silicon oxide film. Production method.

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