JP2010081747A - Control circuit and method for dc/dc converter - Google Patents

Abstract

The present invention relates to a DC / DC converter control capable of limiting a coil current during a transient response by limiting a high-side voltage level of an error amplifier for a predetermined period according to an increase in a set terminal voltage. It is an object to provide a circuit and a DC / DC converter control method.
A DC / DC converter control circuit includes a detection circuit that detects an increase in a set voltage of an output voltage in the DC / DC converter, a clock circuit that clocks a predetermined time from detection by the detection circuit, and a clock circuit And a clamp circuit that clamps the output voltage level of the error amplifier during the time measurement period. Even when the coil current increases during a transient response that increases the set voltage, the peak current value can be limited.
[Selection] Figure 1

Description

  The present invention relates to control of a coil current at the time of a transient response when a setting terminal voltage for setting an output voltage of a DC / DC converter is switched, and in particular, the peak of the coil current when the setting terminal voltage increases. It relates to control for limiting the value.

  The background art DC / DC converter control circuit shown in FIG. 5 is a current control type DC / DC converter control circuit. In the background art shown in FIG. 5, 1 is a DC / DC converter control circuit, but the NMOS transistor FET1, NMOS transistor FET2, and sense resistor RS may be configured outside the DC / DC converter control circuit.

  The current control type DC / DC converter control circuit includes an error amplifier ERA1. The non-inverting input terminal of the error amplifier ERA1 is connected to the setting terminal (REFIN), and the inverting input terminal is connected to the voltage dividing point of the voltage dividing resistor circuit. The voltage dividing resistor circuit is configured by connecting a resistor element R1 and a resistor element R2 in series, and a connection point between the resistor element R1 and the resistor element R2 is a voltage dividing point. A feedback terminal (FB) is connected to the voltage dividing resistor circuit. Here, the feedback terminal (FB) is connected to the output voltage terminal (VOUT) of the DC / DC converter.

  The error amplifier ERA1 amplifies the voltage difference between the setting terminal voltage VREFIN input to the setting terminal (REFIN) and the divided voltage of the output voltage VOUT output from the voltage dividing resistor circuit.

  The DC / DC converter control circuit includes an amplifier AMP1. Both ends of the sense resistor RS are connected to the amplifier AMP1. The amplifier AMP1 converts the coil current IL1 flowing through the coil L1 via the sense resistor RS into a voltage and detects it.

  Further, the DC / DC converter control circuit includes a comparator COMP1. The output voltage V2 of the error amplifier ERA1 is input to the inverting input terminal of the comparator COMP1, and the output voltage of the amplifier AMP1 is input to the non-inverting input terminal.

  Further, the DC / DC converter control circuit includes a flip-flop circuit FF. The oscillator OSC is connected to the set terminal (S) of the flip-flop circuit FF, and the output voltage of the comparator COMP1 is connected to the reset terminal (R). The flip-flop circuit FF is set every cycle of the oscillation signal OSC output from the oscillator OSC, and the NMOS transistor FET1 is turned on, whereby one end of the coil L1 is connected to the input power source VIN. Thereby, the coil current IL1 increases with time. The increasing coil current IL1 is detected by the amplifier AMP1. The detected coil current IL1 is compared with the output voltage V2 of the error amplifier ERA1, and as it increases beyond the output voltage V2, the flip-flop circuit FF is reset.

  In the current control type DC / DC converter control circuit, the peak value of the coil current IL1 is controlled in accordance with the output voltage V2 of the error amplifier ERA1.

JP 2007-295759 A JP-A-6-121528

  Here, consider a case where the setting terminal voltage VREFIN changes. The setting terminal voltage VREFIN determines the setting voltage of the output voltage VOUT in the equilibrium state. Accordingly, when the set terminal voltage VREFIN changes, the output voltage VOUT shifts to an unbalanced state that deviates from the set value. For this reason, for example, when the set terminal voltage VREFIN increases, the output voltage VOUT is in a state where the voltage value is insufficient with respect to the set value. In the error amplifier ERA1, the voltage input to the non-inverting input terminal increases as compared with the voltage input to the inverting input terminal, and the output voltage V2 of the error amplifier ERA1 becomes a high voltage level. Until the output voltage of the amplifier AMP1 increasing with time exceeds the output voltage V2 of the error amplifier ERA1, the output voltage of the comparator COMP1 is maintained at a low level. Meanwhile, the flip-flop circuit FF is not reset and the coil current IL1 continues to flow. As a result, the peak current IL1 becomes large.

  Since the coil current IL1 is supplied from the input power supply VIN, if the coil current IL1 increases beyond the voltage supply capability of the input power supply VIN, the power to be supplied from the input power supply VIN becomes excessive, and sufficient power supply cannot be performed. There is a risk that the voltage of the input power source VIN will drop. Then, when the voltage drops, another device connected to the input power source VIN may be down, which is a problem.

  The present invention has been proposed in view of the above problems, and limits the coil current at the time of transient response by limiting the high-side voltage level of the error amplifier for a predetermined period according to the increase of the set terminal voltage. It is an object of the present invention to provide a DC / DC converter control circuit and a DC / DC converter control method capable of performing the above-described operation.

  A DC / DC converter control circuit according to the present invention includes a detection circuit that detects an increase in the set voltage of the output voltage in the DC / DC converter, a clock circuit that counts a predetermined time from detection by the detection circuit, and a clock circuit And a clamp circuit that clamps the output voltage level of the error amplifier during the time measurement period.

  In addition, the DC / DC converter control method according to the present invention detects an increase in the set voltage for setting the output voltage in the DC / DC converter, measures a predetermined time from the detection, and outputs the error amplifier output voltage during the time period. Clamp the level.

    According to the DC / DC converter control circuit and the DC / DC converter control method of the present invention, the period of the predetermined time from the detection in response to detecting the increase of the set voltage for setting the output voltage of the DC / DC converter Clamp the output voltage level of the error amplifier. As a result, the switching duty in the DC / DC converter can be limited regardless of the transient state in which the error voltage between the output voltage and the set voltage increases as the set voltage increases.

  The peak current value can be limited by controlling the increase of the coil current due to the response in the transient state. Even when the coil current increases during a transient response that increases the set voltage, the peak current value is limited, so that the coil current can be supplied within the range of the voltage supply capability of the input voltage source.

  First, the circuit configuration of the first embodiment will be described with reference to FIG. The set terminal (S) of the flip-flop circuit FF is connected to the output terminal of the oscillator OSC. The reset terminal (R) of the flip-flop circuit FF is connected to the output terminal of the comparator COMP1. The output terminal (Q) of the flip-flop circuit FF is connected to the gate terminal of the NMOS transistor FET1. The inverting output terminal (Q_) of the flip-flop circuit FF is connected to the gate terminal of the NMOS transistor FET2.

  The drain terminal of the NMOS transistor FET1 is connected to the input power supply VIN, and the source terminal is connected to the drain terminal of the NMOS transistor FET2 and one terminal of the sense resistor RS. The source terminal of the NMOS transistor FET2 is grounded.

  One terminal of the sense resistor RS is connected to the non-inverting input terminal of the amplifier AMP1. The other terminal of the sense resistor RS is connected to one terminal of the coil L1 via an inverting input terminal of the amplifier AMP1 and an external output terminal (LX). The output terminal of the amplifier AMP1 is connected to the non-inverting input terminal of the comparator COMP1.

  The other terminal of the coil L1 is connected to the resistance element R1 via an output voltage terminal (VOUT), an output capacitor C1 having one terminal grounded, and a feedback terminal (FB). The resistor element R2 having one terminal grounded is connected in series with the resistor element R1, and the resistor elements R1 and R2 form a voltage dividing circuit. A connection point between the resistance element R1 and the resistance element R2 is connected to an inverting input terminal of the error amplifier ERA1. The setting terminal (REFIN) is connected to the non-inverting input terminal of the error amplifier ERA1. The output terminal of the error amplifier ERA1 is connected to the inverting input terminal of the comparator COMP1.

  The setting terminal (REFIN) is further connected to one terminal of the switch element S1 and the non-inverting input terminal of the comparator COMP2. The other terminal of the switch element S1 is a capacitor C3 whose one terminal is grounded via the resistor element R3, the other terminal of the switch element S2 whose one terminal is connected to the constant current source I1, and the comparator COMP2. Is connected to the inverting input terminal.

  The output terminal of the comparator COMP2 is connected to a control terminal that switches the conduction state of the switch element S1 via the inverter INV1. The output terminal of the comparator COMP2 is connected to a control terminal that switches the conduction state of the switch element S2 and a control terminal that switches the conduction state of the switch element S4.

  Here, an offset voltage is set in the comparator COMP2. The voltage applied to the non-inverting input terminal of the comparator COMP2 is balanced with the voltage input to the inverting input terminal in a state where the voltage applied to the inverting input terminal is higher than the voltage applied to the inverting input terminal by an offset voltage.

  The switch element S4 connects one of the two terminals to the other terminal. The first one terminal of the switch element S4 is connected to the constant voltage source E1 via the resistor element R5. The second one terminal is connected to the constant voltage source E2. Here, the voltage VE1 output from the constant voltage source E1 has a higher voltage value than the voltage VE2 output from the constant voltage source E2 (VE1> VE2). The other terminal of the switch element S4 is connected to the capacitor C5 whose one terminal is grounded and the gate terminal of the PMOS transistor FET3.

  The PMOS transistor FET3 and the PMOS transistor FET5 constitute a differential pair. The source terminals of the PMOS transistor FET3 and the PMOS transistor FET5 are connected to each other and further connected to the constant current source I2. The drain terminal of the PMOS transistor FET3 is connected to the gate terminals of the NMOS transistor FET4 and the NMOS transistor FET6 and to the drain terminal of the NMOS transistor FET4. The source terminals of the NMOS transistor FET4 and the NMOS transistor FET6 are grounded.

  The gate terminal of the PMOS transistor FET5 is connected to the output terminal of the error amplifier ERA1. The drain terminal of the PMOS transistor FET5 is connected to the drain terminal of the NMOS transistor FET6 and the base terminal of the transistor TR1. The emitter terminal of the transistor TR1 is connected to the output terminal of the error amplifier ERA1. The collector terminal of the transistor TR1 is grounded.

  Next, the operation of the first embodiment will be described. In a state where the setting terminal voltage VREFIN is maintained at a constant voltage level, the comparator COMP2 is stable in a state of outputting a low level. At the time of start-up, even if the output voltage V3 of the comparator COMP2 is at a high level, the switch element S2 becomes conductive and the capacitor C3 is charged. As a result, the voltage level of the inverting input terminal of the comparator COMP2 rises and the output voltage of the comparator COMP2 becomes low level. At this time, the switch element S1 connected via the inverter INV1 is in a conductive state, the switch element S2 is in a non-conductive state, and the switch element S4 is connected to the constant voltage source E1. At this time, due to the action described later, the upper limit value of the output voltage V2 of the error amplifier ERA1 is the voltage VE1 of the constant voltage source E1.

  When the setting terminal voltage VREFIN increases, the setting terminal voltage VREFIN is directly applied to the non-inverting input terminal of the comparator COMP2, but a time constant circuit constituted by the resistor element R3 and the capacitor C3 is provided at the inverting input terminal. Applied. For this reason, the voltage value applied to the inverting input terminal is lower than the voltage applied to the non-inverting input terminal. When the voltage applied to the non-inverting input terminal exceeds the offset voltage set in the comparator COMP2 with respect to the voltage applied to the inverting input terminal, the output terminal of the comparator COMP2 outputs a high level.

  When the comparator COMP2 outputs a high level, the switch element S1 connected via the inverter INV1 is turned off and the switch element S2 is turned on. The switch element S4 is connected to a constant voltage source E2 instead of the constant voltage source E1.

  When the switch element S1 is turned off and the switch element S2 is turned on, a constant current flows from the constant current source I1 to the capacitor C3 and charging of the capacitor C3 is started. In addition, the capacitor C3 is charged by a current through the resistance element R3. Thereby, the voltage between terminals of the capacitor C3 increases with time. When the inter-terminal voltage of the capacitor C3 approaches the set terminal voltage VREFIN and the difference becomes equal to or less than the offset voltage of the comparator COMP2, the output voltage V3 of the comparator COMP2 is inverted to a low level. Then, the switch element S1 becomes conductive, and the switch element S2 becomes nonconductive. The switch element S4 is connected to the constant voltage source E1 instead of the constant voltage source E2. A predetermined time T (see FIG. 2) during which the comparator COMP2 outputs a high level is determined by the current value of the constant current source I1, the capacitance value of the capacitor C3, the increment of the setting terminal voltage VREFIN, and the offset voltage of the comparator COMP2. .

  The switch element S4 connects the constant voltage source E2 and the gate terminal of the PMOS transistor FET3, whereby the voltage VE2 is applied to the gate terminal of the PMOS transistor FET3. Here, the PMOS transistor FET3 constitutes a differential pair with the PMOS transistor FET5, and constitutes a differential amplifier together with the NMOS transistors FET4 and FET6. The output of the differential amplifier is fed back to the gate terminal of the PMOS transistor FET5, that is, the output terminal of the error amplifier ERA1 via the PNP transistor TR1.

  With this configuration, when the output voltage V2 exceeds the voltage VE2 applied to the PMOS transistor FET3 by the output operation of the error amplifier ERA1, the current is drawn through the PNP transistor TR1. As a result, regardless of the output operation of the error amplifier ERA1, the output voltage V2 of the error amplifier ERA1 is lowered to the voltage VE2. That is, the output voltage V2 of the error amplifier ERA1 is clamped to the voltage VE2. When the output voltage V2 is lower than the voltage VE2 applied to the PMOS transistor FET3 due to the output operation of the error amplifier ERA1, the current extraction operation of the PNP transistor TR1 stops but the output voltage of the error amplifier ERA1. Since there is no circuit configuration for raising V2, the voltage value obtained by the output operation of the error amplifier ERA1 is output as it is as the output voltage V2 of the error amplifier ERA1.

  In a state where the current value of the constant current source I1, the capacitance value of the capacitor C3, and the offset voltage of the comparator COMP2 are set, the switch element S4 is connected to the constant voltage source E2 by the increase of the setting terminal voltage VREFIN. Time is set. In this predetermined time, the output voltage of the error amplifier ERA1 is clamped to the voltage VE2. Immediately after a predetermined time T (see FIG. 2) when the switch element S4 is connected to the constant voltage source E2, the output voltage V2 of the error amplifier ERA1 is set by the capacitor C5 and the resistance element R5 from the voltage VE2. It increases according to the time constant and is finally clamped at the voltage VE1.

  The voltage input to the non-inverting input terminal of the comparator COMP1 is a voltage amplified by the amplifier AMP1 after voltage conversion of the coil current IL1 via the sense resistor RS. That is, the voltage is proportional to the coil current IL1. The output voltage V2 of the error amplifier ERA1 is input to the inverting input terminal of the comparator COMP1. Therefore, when the output voltage V2 of the error amplifier ERA1 is clamped to the voltage VE2 having a voltage value lower than the voltage VE1 that is the normal clamping voltage, the output voltage of the comparator COMP1 is reduced with respect to the smaller coil current IL1. Invert and output high level.

  When the output voltage of the comparator COMP1 outputs a high level, the flip-flop circuit FF is reset. The output terminal (Q) is reset to low level, and the NMOS transistor FET1 is turned off. During a predetermined time T (see FIG. 2) when the setting terminal voltage VREFIN increases and the switch element S4 is connected to the constant voltage source E2, the output voltage V2 of the error amplifier ERA1 is a voltage VE2 that is lower than the voltage VE1. Therefore, the coil current IL1 is clamped to a peak current value smaller than that in the normal operation state. Here, the normal operation state refers to an equilibrium state in which the output voltage VOUT is controlled to a voltage set by the setting terminal voltage VREFIN.

  After a predetermined time T (see FIG. 2), the output voltage V3 of the comparator COMP2 returns to the low level. The switch element S1 returns to the conductive state, and the switch element S2 returns to the nonconductive state. As a result, the output voltage V3 of the comparator COMP2 returns to the low level and returns to the normal operation state. The switch element S4 connects the PMOS transistor FET3 and the constant voltage source E1. Thus, a time constant circuit is configured by the resistor element R5 and the capacitor C5. The capacitor C5 charged to the voltage VE2 is discharged with a time constant set by the resistance element R5 and the capacitor C5, and reaches the voltage VE1.

  Next, the effect of the first embodiment will be described with reference to FIG. When the setting terminal voltage VREFIN increases, a predetermined time T during which the comparator COMP2 outputs a high level is determined according to the increased voltage width. At a predetermined time T, the output voltage V2 of the error amplifier ERA1 is clamped with a voltage VE2 lower than the voltage VE1. As a result, the output voltage of the comparator COMP1 is inverted and outputs a high level at a coil current IL1 smaller than that in the normal operation state. The comparator COMP1 compares the voltage proportional to the coil current IL1 flowing through the coil L1 with the output voltage V2 of the error amplifier ERA1, and the voltage proportional to the coil current IL1 exceeds the voltage VE2 which is lower than the voltage VE1. This is because the comparator COMP1 outputs a high level.

  When the output voltage of the comparator COMP1 is inverted and outputs a high level, the flip-flop circuit FF is reset, the output terminal (Q) outputs a low level, and the NMOS transistor FET1 is turned off. Thereby, the coil current IL1 flowing through the coil L1 is limited. As a result, the supply of power from the input power source VIN is restricted, and the risk that the voltage value of the input power source VIN will be reduced can be prevented. It is possible to prevent other devices connected to the input power source VIN from going down.

  Further, after a predetermined time T (see FIG. 2), the voltage across the capacitor C5 charged to the voltage VE2 is discharged with the time constant of the time constant circuit constituted by the resistor element R5 and the capacitor C5. It reaches the voltage VE1. As a result, the clamp voltage of the output voltage V2 of the error amplifier ERA1 continuously changes, and a stable operation can be ensured.

  Next, the circuit configuration of the second embodiment will be described with reference to FIG. In the second embodiment, a resistance element R4, capacitors C2, C4, amplifiers AMP2, AMP3, and a switch element S3 are provided instead of the constant voltage source E2 in the first embodiment. In addition, about the structure to which the same code | symbol as 1st Embodiment is attached | subjected, since it is the same structure as 1st Embodiment and has the same effect, description here is abbreviate | omitted.

  An inverting input terminal of the amplifier AMP2 and one terminal of the resistance element R4 are connected to a setting terminal (REFIN).

  The other terminal of the resistor element R4 is connected to the capacitor C2 whose one terminal is grounded and the non-inverting input terminal of the amplifier AMP2. The output terminal of the amplifier AMP2 is connected to one terminal of the switch element S3. The other terminal of the switch element S3 is connected to a capacitor C4 whose one terminal is grounded and a non-inverting input terminal of the amplifier AMP3. The output terminal of the amplifier AMP3 is connected to the inverting input terminal of the amplifier AMP3 and the second one terminal of the switch element S4.

  Next, the operation of the second embodiment will be described. When the set terminal voltage VREFIN increases, the voltage applied to the inverting input terminal of the comparator COMP2 becomes lower than the voltage applied to the non-inverting input terminal. When the voltage applied to the non-inverting input terminal exceeds the offset voltage set in the comparator COMP2 with respect to the voltage applied to the inverting input terminal, the output terminal of the comparator COMP2 outputs a high level.

  Further, when the setting terminal voltage VREFIN increases, the setting terminal voltage VREFIN is directly applied to the non-inverting input terminal of the amplifier AMP2, but the time constant circuit configured by the resistor element R4 and the capacitor C2 is provided to the inverting input terminal. Applied. Thereby, when the setting terminal voltage VREFIN increases, the voltage difference between the voltage input to the inverting input terminal and the voltage input to the non-inverting input terminal increases as the increasing voltage value increases. Furthermore, with the passage of time, the voltage difference decreases according to the time constant of the time constant circuit constituted by the resistor element R4 and the capacitor C2. When the set terminal voltage VREFIN increases, the output voltage of the amplifier AMP2 shows a low voltage level according to the magnitude of the voltage difference between the input terminals, and is configured by the resistor element R4 and the capacitor C2 over time. It increases with the time constant specified by the constant circuit. As the setting terminal voltage VREFIN is charged into the capacitor C2, the output voltage of the amplifier AMP2 approaches the operating point voltage.

  As the setting terminal voltage VREFIN increases, the comparator COMP2 outputs a high level, so that the switch element S1 connected via the inverter INV1 is non-conductive, the switch element S2 is conductive, and the switch element S3 is conductive. , And the switch element S4 are connected to the output terminal of the amplifier AMP3 in place of the constant voltage source E1.

  When the switch element S3 becomes conductive, the output terminal of the amplifier AMP2 is connected to the non-inverting input terminal of the amplifier AMP3. The amplifier AMP3 constitutes a voltage follower circuit. As a result, the output voltage of the same voltage as the output voltage of the amplifier AMP2 is output from the amplifier AMP3.

  For a predetermined time during which the comparator COMP2 outputs a high level, the switch element S4 connects the output terminal of the amplifier AMP3 and the gate terminal of the PMOS transistor FET3. As a result, the output voltage V1 of the amplifier AMP3 is applied to the gate terminal of the PMOS transistor FET3. Here, the PMOS transistor FET3 constitutes a differential pair with the PMOS transistor FET5, and constitutes a differential amplifier together with the NMOS transistors FET4 and FET6. The output of the differential amplifier is fed back to the gate terminal of the PMOS transistor FET5, that is, the output terminal of the error amplifier ERA1 via the PNP transistor TR1.

  With this configuration, when the output voltage of the error amplifier ERA1 exceeds the output voltage V1 of the amplifier AMP3 applied to the PMOS transistor FET3, the current is drawn through the PNP transistor TR1. As a result, the output voltage V2 of the error amplifier ERA1 is reduced to the output voltage V1 of the amplifier AMP3 regardless of the output operation of the error amplifier ERA1. That is, the output voltage V2 of the error amplifier ERA1 is clamped to the output voltage V1 of the amplifier AMP3. If the output voltage of the error amplifier ERA1 is lower than the output voltage V1 of the amplifier AMP3 applied to the PMOS transistor FET3 by the output operation of the error amplifier ERA1, the current extraction operation of the PNP transistor TR1 is stopped, but the error amplifier ERA1 Since there is no circuit configuration for increasing the output voltage V2, the voltage value obtained by the output operation of the error amplifier ERA1 is output as it is as the output voltage V2 of the error amplifier ERA1.

  In a state where the current value of the constant current source I1, the capacitance value of the capacitor C3, and the offset voltage of the comparator COMP2 are set, the switch element S4 is connected to the output voltage V1 of the amplifier AMP3 due to the increase of the setting terminal voltage VREFIN. A predetermined time is set. During this predetermined time, the output voltage V2 of the error amplifier ERA1 is clamped to the output voltage V1 of the amplifier AMP3. After a lapse of a predetermined time when the switch element S4 is connected to the output terminal of the amplifier AMP3, the output voltage V2 of the error amplifier ERA1 increases from the output voltage V1 of the amplifier AMP3 according to the time constant, and finally the voltage VE1. To be clamped. This is because when the switch element S4 connects the constant voltage source E1 and the PMOS transistor FET3, the resistor element R5 and the capacitor C5 constitute a time constant circuit.

  The output voltage V2 of the error amplifier ERA1 is clamped to the output voltage V1 of the amplifier AMP3, which is a voltage value lower than the voltage VE1 that is a clamp voltage during normal operation, and the peak current value of the coil current IL1 can be limited. In this case, the voltage value of the output voltage V1 of the amplifier AMP3 increases with time due to the time constant circuit constituted by the resistor element R4 and the capacitor C2. Accordingly, the output voltage V1 of the amplifier AMP3 shows a minimum value immediately after the setting terminal voltage VREFIN increases, and thereafter increases with time. Therefore, the clamp level of the output voltage V2 of the error amplifier ERA1 increases with time. The peak current value of the coil current IL1 is limited to the minimum value immediately after the setting terminal voltage VREFIN increases, and thereafter, the limit current value increases with time.

  Next, effects of the second embodiment will be described. When the setting terminal voltage VREFIN increases, a predetermined time T during which the comparator COMP2 outputs a high level is determined according to the increased voltage width. At a predetermined time, the output voltage V2 of the error amplifier ERA1 is clamped to the output voltage V1 from the amplifier AMP3 that is lower than the voltage value VE1. After the set terminal voltage VREFIN increases, the output voltage V1 increases in voltage value with a time constant determined by a time constant circuit composed of the resistor element R4 and the capacitor C2, and approaches the operating point voltage of the amplifier AMP2. . As a result, the output voltage of the comparator COMP1 is inverted and a high level is output when the coil current IL1 is smaller than that in the normal operation state. In this case, the peak current value of the coil current IL1 is minimized when the set terminal voltage VREFIN is increased, and thereafter increases with a time constant set by the resistor element R4 and the capacitor C2 with the passage of time.

Here, the resistor element R3, the capacitor C3, and the comparator COMP2 shown in FIGS. 1 and 3 correspond to the detection circuit described in the claims. Among these, the resistor element R and the capacitor C3 are claimed. This corresponds to the first time constant circuit described in FIG.
Further, the resistor element R3 and the capacitor C3, and the capacitor C3 and the constant current source I1 shown in FIGS. 1 and 3 correspond to a time measuring circuit described in the claims.
Further, the constant voltage source E2, the constant voltage source E1, the capacitor C5, the switch element S4, and the resistance element R5 shown in FIG. 1 correspond to a clamp circuit described in the claims. In this case, instead of the constant voltage source E2, a resistor element R4, a capacitor C2, an amplifier AMP2, a switch element S3, a capacitor C4, and an amplifier AMP3 may be provided. Among these, the constant voltage source E2 corresponds to the first constant voltage source, the constant voltage source E1 corresponds to the second constant voltage source, the capacitor C5 corresponds to the second capacitor element, and the switch element S4 corresponds to the switch circuit. Further, the resistor element R4, the capacitor C2, the amplifier AMP2, the switch element S3, the capacitor C4, and the amplifier AMP3 correspond to the voltage adjustment circuit described in the claims. Further, the resistor element R4 and the capacitor C2 correspond to the second time constant circuit recited in the claims, and the amplifier AMP2 corresponds to the amplifier circuit recited in the claims.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. For example, in the present invention, the constant voltage sources E1 and E2 are fixed in FIG. 1, and the constant voltage source E1 is also fixed in FIG. However, the present invention is not limited to this embodiment. By making the constant voltage sources E1 and E2 variable, the current limit value of the coil current IL1 can be made variable.

It is a circuit diagram of a 1st embodiment of the present invention. It is an operation | movement waveform diagram which shows operation | movement of 1st Embodiment. It is a circuit diagram of a 2nd embodiment of the present invention. It is an operation | movement waveform diagram which shows operation | movement of 2nd Embodiment. It is a circuit diagram of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC / DC converter control circuit of prior art 2 DC / DC converter control circuit of Embodiment 1 3 DC / DC converter control circuit of Embodiment 2 AMP1, AMP2, AMP3 Amplifier C1 Output capacitor C2, C3, C4, C5 Capacitor COMP1 , COMP2 comparator ERA1 error amplifier E1, E2 constant voltage source FET1, FET2, FET4, FET6 NMOS transistor FET3, FET5 PMOS transistor FF flip-flop circuit (FB) feedback terminal (GND) reference potential terminal I1, I2 constant current source INV1 inverter L1 coil (LX) external output terminal OSC oscillator R1, R2, R3, R4, R5 resistance element RS sense resistor (REFIN) setting terminal S1, S2, S3, S4 switch element TR1 PNP transistor VIN Input power supply (VOUT) Output voltage terminal IL1 Coil current V1 Output voltage of amplifier AMP3 V2 Output voltage of error amplifier ERA1 V3 Output voltage of comparator COMP2 VE1 Voltage output from constant voltage source E1 VE2 Output from constant voltage source E2 Voltage VREFIN Setting terminal voltage VOUT Output voltage

Claims (8)

A detection circuit for detecting an increase in the set voltage of the output voltage in the DC / DC converter;
A timing circuit that counts a predetermined time from detection by the detection circuit;
A DC / DC converter control circuit comprising: a clamp circuit that clamps an output voltage level of the error amplifier during a time measurement period of the time measurement circuit. The detection circuit includes:
A first time constant circuit to which the set voltage is input;
2. The DC / DC converter control circuit according to claim 1, further comprising a comparison circuit to which a signal output from the first time constant circuit and the set voltage are input.   The DC / DC converter control circuit according to claim 2, wherein the time measuring circuit is the first time constant circuit.   3. The DC / DC converter control according to claim 2, wherein the time measuring circuit includes a first capacitive element constituting the first time constant circuit, and a current source circuit connected to the first capacitive element. circuit. The clamp circuit is
A first voltage source for supplying a first voltage for clamping the output voltage level of the error amplifier;
A second voltage source for supplying a second voltage that exceeds the first voltage and widens the output voltage level of the error amplifier;
A second capacitive element that holds the first voltage or the second voltage;
A switch circuit for switching the second capacitive element between the first voltage source and the second voltage source;
5. The DC / DC converter control circuit according to claim 1, further comprising: a resistance element that connects between the switch circuit and the second voltage source. 6. The clamp circuit is
6. A voltage adjustment circuit that reduces and outputs a first voltage that clamps an output voltage level of the error amplifier according to an increased voltage width of the set voltage. The DC / DC converter control circuit according to 1. The voltage adjustment circuit includes:
A second time constant circuit to which the set voltage is input;
The DC / DC converter control circuit according to claim 6, further comprising: an amplifier circuit to which a signal output from the second time constant circuit and the set voltage are input. Detecting an increase in the set voltage that sets the output voltage in the DC / DC converter,
Timing a predetermined time from the detection,
A method for controlling a DC / DC converter, wherein the output voltage level of the error amplifier is clamped during the time period.

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