JP2010080827A - Nonvolatile semiconductor memory, and method of manufacturing the same - Google Patents

Abstract

A nonvolatile semiconductor memory capable of increasing the capacity or miniaturization by increasing the number of charge trap sites of semiconductor particles that accumulate charges and a method for manufacturing the nonvolatile semiconductor memory are provided.
A semiconductor substrate of a first conductivity type, a source / drain region of a second conductivity type provided in the semiconductor substrate so as to be spaced apart from each other, a channel region formed between the source / drain regions, and a channel region A first insulating film formed thereon, a semiconductor particle formed on the first insulating film and containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, and Y, and a semiconductor A non-volatile semiconductor memory comprising a second insulating film formed on a particle and a control gate electrode formed on the second insulating film, and a method for manufacturing the non-volatile semiconductor memory.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory that accumulates electric charges in semiconductor particles and a method for manufacturing the nonvolatile semiconductor memory.

  As a memory cell of a NAND type nonvolatile semiconductor memory device, research and development of a MONOS (Metal Oxide Nitride Oxide Silicon) type memory cell has been actively conducted. The MONOS type memory cell is formed by forming a tunnel insulating film (Oxide) and a charge trapping film (Nitride) on a semiconductor substrate (Silicon), and further controlling a control gate electrode (Metal) via a charge blocking film (Oxide) thereon. ) Is a semiconductor device having a stack structure. In the memory cell of the MONOS type nonvolatile semiconductor memory device, a threshold voltage shift caused by applying a high voltage to the tunnel insulating film and injecting electrons from the silicon substrate side into the charge trapping film is used for storing information. .

  Further, with the recent increase in memory capacity, it is essential to reduce the thickness of EOT (Equivalent Oxide Thickness). Instead of SiN, which is a conventional charge trapping film, single crystal or polycrystal Si or Ge nanocrystals ( A memory (hereinafter also referred to as NC memory) that accumulates charges in semiconductor particles (hereinafter also referred to as semiconductor nanoparticles) such as NC) has been studied (for example, Patent Document 1).

In addition, by adding Hf to Si, it is investigated by DLTS measurement that four defect levels are formed on the upper end side of the valence band and six defect levels on the lower end side of the conduction band from the mid gap of Si. (Non-Patent Document 1).
JP 2006-120663 A R. Sachdeva et al, Physica B 376-377, 420 (2006)

  In the current NC memory using a semiconductor NC such as single crystal or polycrystal Si or Ge, the average number of electrons trapped in one NC is about one, and the conventional SiN is trapped in charge. The problem is that there are fewer trap sites than the MONOS type memory used for the layer.

  The present invention has been made in view of the above circumstances, and the object of the present invention is non-volatile that can be increased in capacity or miniaturized by increasing the number of charge trap sites of semiconductor particles that accumulate charges. An object of the present invention is to provide a method for manufacturing a semiconductor memory and a nonvolatile semiconductor memory.

  A nonvolatile semiconductor memory according to a first aspect of the present invention includes a first conductive type semiconductor substrate, a second conductive type source / drain region provided in the semiconductor substrate so as to be spaced apart from each other, and the source / drain A channel region formed between the regions, a first insulating film formed on the channel region, and formed on the first insulating film, from a group of Hf, Zr, Ti, Ta, Nb, W, Y It has semiconductor particles containing at least one element selected, a second insulating film formed on the semiconductor particles, and a control gate electrode formed on the second insulating film.

  Here, in the nonvolatile semiconductor memory of the first aspect, it is preferable that an oxide layer of the semiconductor particles is formed on the surface of the semiconductor particles.

  Here, in the nonvolatile semiconductor memory according to the first aspect, it is desirable that the second insulating film is an oxide of the element contained in the semiconductor particles.

Here, in the nonvolatile semiconductor memory of the first aspect, the particle size of the semiconductor particles is 3 nm or more and 10 nm or less, and the atomic density of the element contained in the semiconductor particles is 2 × 10 ¹⁸ cm ⁻³ or more and 1 × is desirably ¹⁰ 20 ^{cm -3} or less.

  Here, in the nonvolatile semiconductor memory of the first aspect, it is preferable that the semiconductor particles are Si particles.

  A nonvolatile semiconductor memory according to a second aspect of the present invention includes a first conductive type semiconductor substrate, a second conductive type source / drain region provided in the semiconductor substrate so as to be spaced apart from each other, and the source / drain A channel region formed between the regions, a first insulating film formed on the channel region, and formed on the first insulating film, from a group of Hf, Zr, Ti, Ta, Nb, W, Y Semiconductor particles containing at least one selected element, a second insulating film formed on the semiconductor particles and being an oxynitride of the element contained in the semiconductor particles, and formed on the second insulating film And a control gate electrode formed on the third insulating film.

  The non-volatile semiconductor memory manufacturing method according to the third aspect of the present invention includes a step of forming a first insulating film on a first conductivity type semiconductor substrate, and a step of forming semiconductor particles on the first insulating film. Forming a metal layer containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, and Y on the surface of the semiconductor particles, and heat-treating the element contained in the metal layer Diffusing into the semiconductor particles, forming a second insulating film by oxidizing the metal layer, forming a control gate electrode on the second insulating film, and Forming a source / drain region.

  Here, in the method for manufacturing the nonvolatile semiconductor memory according to the third aspect, it is desirable that in the step of forming the second insulating film, an oxide layer of the semiconductor particles is formed on the surface of the semiconductor particles.

  Here, in the method of manufacturing the nonvolatile semiconductor memory according to the third aspect, it is preferable that the heat treatment is performed in an inert gas atmosphere.

  Here, in the method of manufacturing the nonvolatile semiconductor memory according to the third aspect, the element is introduced into the first insulating film in the step of forming the metal layer, and the element is added to the semiconductor substrate and the first by the heat treatment. It is desirable to diffuse to the interface with the insulating film.

  Here, in the method of manufacturing the nonvolatile semiconductor memory according to the third aspect, it is desirable that the semiconductor particles are Si particles.

  A method for manufacturing a nonvolatile semiconductor memory according to a fourth aspect of the present invention includes a step of forming a first insulating film on a first conductivity type semiconductor substrate, and a step of forming semiconductor particles on the first insulating film. Forming a metal layer containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, and Y on the surface of the semiconductor particles, and heat-treating the element contained in the metal layer Diffusing into the semiconductor particles, forming a second insulating film by oxynitriding the metal layer, forming a third insulating film on the second insulating film, 3. A step of forming a control gate electrode on the insulating film and a step of forming a source / drain region in the semiconductor substrate.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory that can be increased in capacity or miniaturized by increasing the number of charge trap sites of semiconductor particles that accumulate charges, and a method for manufacturing the nonvolatile semiconductor memory. Become.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

(First embodiment)
A nonvolatile semiconductor memory according to a first embodiment of the present invention includes a first conductive type semiconductor substrate, a second conductive type source / drain region provided in the semiconductor substrate so as to be spaced apart from each other, and a source / drain A channel region formed between the regions, a first insulating film formed on the channel region, and formed on the first insulating film, and selected from the group of Hf, Zr, Ti, Ta, Nb, W, and Y Semiconductor particles containing at least one element, a second insulating film formed on the semiconductor particles, and a control gate electrode formed on the second insulating film are included.

  Here, a NAND type nonvolatile memory having nano-order size single crystal or polycrystalline Si particles (hereinafter also referred to as Si nanoparticles) as semiconductor particles for accumulating charges will be described as an example. The NAND type nonvolatile semiconductor memory is configured by arranging a bit line, a selection gate transistor connected to the bit line, and a plurality of memory cells in series with the selection gate transistor.

  FIG. 1 is a cross-sectional view of a memory cell of the nonvolatile semiconductor memory according to the present embodiment. 1A is a cross-sectional view in a direction parallel to the bit line, FIG. 1B is a cross-sectional view in a direction parallel to the word line, and FIG. 1A and FIG. 1B are orthogonal to each other. A cross section is shown.

As shown in FIG. 1A, source / drain regions 12 are formed in a p-type silicon substrate 10 so as to be separated from each other. For example, SiO ₂ and SiON are formed as the tunnel insulating film 16 on the channel region 14 formed between the n-type source / drain regions 12 in the p-type silicon substrate 10. Here, the tunnel insulating film 16 may be a laminated film of SiO ₂ , SiN, and SiO ₂ (hereinafter referred to as an ONO film).

On the tunnel insulating film 16, a plurality of Si nanoparticles 18 are formed as a charge storage layer. Each Si nanoparticle 18 contains Hf. Further, an oxide layer 18 a of the Si nanoparticles 18, that is, SiO ₂ is formed on the surface of the Si nanoparticles 18.

On the Si nanoparticles 18, a block insulating film 20 made of the oxide HfO ₂ of Hf contained in the Si nanoparticles 18 is formed. On the block insulating film 20, a control gate electrode 22 made of, for example, TaN and a mask material 24 for controlling the flow of electrons and holes between the channel region 14 and the Si nanoparticles 18 are sequentially formed. Laminated. Note that the mask material 24 is not necessarily essential.

  The tunnel insulating film 16 functions as an electron / hole transfer path between the channel region and the Si nanoparticles due to a tunneling phenomenon during writing / erasing of the memory cell. In addition, it has a function of suppressing electron / hole transfer between the channel region and the Si nanoparticles by the barrier height during reading and standby. The block insulating film 20 has a function of blocking the flow of electrons / holes between the Si nanoparticles 18 serving as a charge storage layer and the control gate electrode 22.

  The top and side surfaces of these laminates are covered with a silicon oxide film 26 called an electrode side wall oxide film. Further, an interlayer insulating film 28 is formed so as to cover the entire surface. Further, as shown in FIG. 1B, the channel region 14 of adjacent memory cells and the stacked portion from the tunnel insulating film 16 to the block insulating film 20 are separated from each other by an element isolation region 30 formed of a silicon oxide film. It has been. Each memory cell arranged in the word line direction has a common control gate electrode 22, which extends on the element isolation region 30.

  When Hf enters the bulk of the Si crystal, a plurality of localized levels due to Hf are formed in the energy gap. Charges can be trapped at levels in the energy gap. Therefore, the charge trapping efficiency can be increased without increasing EOT by adding Hf to the Si nanoparticles as in the present embodiment.

  As described above, when Hf is added to Si, it is possible to form four defect levels on the upper end side of the valence band and six defect levels on the lower end side of the conduction band from the mid gap of Si. It is revealed by Deep Level Transient Spectroscopy) measurement.

  In general, the levels near the upper end of the valence band and the lower end of the conduction band function as trap levels for holes and electrons, respectively. Therefore, in the Si nanoparticles 18 doped with Hf, Pore coexistence is possible. Here, in a trap type flash memory such as a MONOS or NC memory, when a sufficiently small number of holes are allowed to coexist with electrons, charge retention characteristics are improved. This mechanism is because when the trapped electrons escape through the insulating film, the holes are similarly removed, so that the charge is compensated.

  Therefore, also in the present embodiment, by adding Hf to the Si nanoparticles 18, the charge trapping efficiency can be improved and the charge retention characteristics can be improved. In addition, the presence of a hole trap site due to the addition of Hf has the effect of increasing the threshold window on the erase side.

Further, in this embodiment, oxide layer 18a is SiO ₂ on Si nanoparticle 18 surface is formed. According to the results of the first principle calculation, Hf in SiO ₂ has positive energy and is unstable, while it has negative energy in Si and can exist more stably than in SiO ₂ . Therefore, this SiO ₂ layer has a role of preventing Hf from diffusing out of the Si nanoparticles 18 by heat treatment such as source / drain activation annealing. Therefore, Hf exists inside the Si nanoparticles 18 and also piles up at the interface between the Si nanoparticles 18 and the SiO ₂ layer.

2, in the case where Hf to SiO ₂ and Si interface were piled up, in the mid-gap energy following areas of Si, is a graph showing a distribution of interface state density D _it for electrons of energy E. The horizontal axis represents the electron energy, and the vertical axis represents the interface state density _Dit . At the interface between the Si and the SiO ₂ layer on the surface of the Si nanoparticles 18, charges can be trapped at the localized levels as shown in FIG. As described above, in the present embodiment, Hf is added to the Si nanoparticles 18 to form the SiO ₂ oxide layer 18a on the surface of the Si nanoparticles 18 so that the interface between the bulk of the Si nanoparticles 18 and the SiO ₂ layer can be obtained. Trap sites will be formed on both.

As described above, it is preferable that SiO ₂ that is an oxide layer of the Si nanoparticles 18 is formed on the surface of the Si nanoparticles 18. However, even if there is no oxide layer, since there are trap sites in the bulk of the Si nanoparticles 18, it is not always necessary that SiO ₂ that is the oxide layer of the Si nanoparticles 18 exists in the present embodiment.

  The particle size of the Si nanoparticles is not necessarily limited as long as it is nano-order, but is desirably 3 nm or more and 10 nm or less. Here, the particle size of the Si nanoparticles refers to the average value of the long and short diameters of individual particles existing in a 100 nm square region by plane TEM and AFM, and the value is further calculated for all particles. Defined as an averaged value.

  If the thickness is less than 3 nm, the clonal blockade phenomenon becomes remarkable at room temperature, and electrons may not be trapped in the Si nanoparticles. On the other hand, if the thickness exceeds 10 nm, the EOT increases as compared to the MONOS currently used, so that the feature that it can be made smaller than the MONOS of the NC memory is lost.

And it is desirable that the atomic density of Hf contained in the Si nanoparticles is 2 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. The atomic density of Hf can be measured by energy dispersive X-ray (EDX) analysis combined with TEM. The atomic density of Hf in a nanoparticle is determined from an EDX spectrum obtained by irradiating an electron beam to a single nanoparticle observed with a high-resolution TEM, and this is repeated for a plurality of nanoparticles. Determine the composition.

  In general, in an Si-NC memory, an average of one electron is trapped per Si nanoparticle. Therefore, in order to obtain the effect of increasing the charge trap density by adding Hf to the Si nanoparticles, it is desirable to increase one or more electrons trapped per Si nanoparticle. In order to estimate the amount of Hf required for this purpose, it is necessary to calculate the increase in the amount of charge that can be trapped by adding one Hf atom.

Since the number of localized levels formed in the band gap and the number of electrons / holes that can be accommodated by one localized level differs depending on the site in Hf in Si, the amount of charge that can be trapped for one Hf atom Is also different. Here, the effect of being able to trap at least one electron for one Hf atom is approximated. When the diameter of the Si nanoparticles is 10 nm, the effect of trapping one or more electrons with respect to the Si nanoparticles by adding Hf with an atomic density of 2 × 10 ¹⁸ cm ⁻³ appears. Therefore, it is desirable that the atomic density of Hf contained in the Si nanoparticles is 2 × 10 ¹⁸ cm ⁻³ or more. An atomic density of 7 × 10 ¹⁹ cm ⁻³ or more is more preferable because an effect of trapping one or more electrons with respect to Si nanoparticles having a diameter of 3 nm appears.

  It is possible to increase the number of charge trap sites by increasing the amount of Hf added. As will be described later, in the process of the present embodiment, Hf is diffused into Si by heat treatment. Therefore, when the addition amount increases to some extent, a part of Si nanoparticles may be silicided due to a solid phase reaction between Hf and Si.

In silicidation by solid phase reaction, it is difficult to uniformly silicidize the entire Si nanoparticles, and there is a high possibility that voids are generated. In addition, Hf silicide may take from Hf-rich Hf ₂ Si phase to Si-rich HfSi ₂ phase, and it is difficult to form only a single structure by solid-phase reaction. Therefore, it is considered that in a realistic Hf silicide, several phases are mixed. Since the work functions in the respective phases are greatly different, the charge trapping susceptibility varies depending on each Si nanoparticle, and it becomes difficult to uniformly write all the Si nanoparticles.

Therefore, when adding Hf, it is necessary to isolate Hf atoms to such an extent that silicidation does not change the band structure of the nanoparticles. From this viewpoint, it is desirable that the atomic density of Hf contained in the Si nanoparticles is 1 × 10 ²⁰ cm ⁻³ or less.

  Next, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described. The method for manufacturing a nonvolatile semiconductor memory according to the present embodiment includes a step of forming a first insulating film on a first conductivity type semiconductor substrate, a step of forming semiconductor particles on the first insulating film, and a semiconductor particle Forming a metal layer containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, and Y on the surface, and diffusing the elements contained in the metal layer into the semiconductor particles by heat treatment A step of forming a second insulating film by oxidizing the metal layer, a step of forming a control gate electrode on the second insulating film, a step of forming source / drain regions in the semiconductor substrate, Have

  Here, a method for manufacturing the nonvolatile semiconductor memory shown in FIG. 1 will be described as an example. 3 to 8 are cross-sectional views showing the manufacturing process of the memory cell of the present embodiment. 5 to 8, as in FIG. 1, (a) shows a cross-sectional view in the direction parallel to the bit line, and (b) shows a cross-sectional view in the direction parallel to the word line.

First, as shown in FIG. 3, a thermally oxidized SiO ₂ film to be a tunnel insulating film 16 is formed on the surface of the p-type silicon substrate 10 to 3 to 10 nm. Here, the tunnel insulating film 16 may be an EOT: 3 to 10 nm SiON or ONO film formed by a CVD method or the like.

Next, Si nanoparticles 18 having a diameter of 3 nm to 10 nm are formed on the tunnel insulating film 16 at a surface density of 1 × 10 ¹² cm ⁻² or more by LPCVD or the like. The surface density of the Si nanoparticles 18 is obtained by observing a planar TEM image in a 100 nm square region, counting the number of particles, and then converting the surface density. Next, a 0.5 nm Hf metal layer (Hf metal layer) 32 is formed on the Si nanoparticles 18 by sputtering, PVD, or electron beam evaporation.

Next, as shown in FIG. 4, annealing is performed at 700 ° C. to 1000 ° C. for 10 to 60 seconds in an inert gas atmosphere such as a nitrogen atmosphere. Here, for example, heat treatment is performed at 800 ° C. for 30 seconds. As shown in the result of the first principle calculation described above, Hf is easily diffused into Si but relatively difficult to diffuse into SiO ₂ . Most of the Hf metal layer 32 diffuses into the Si nanoparticles 18. Next, the HfO ₂ layer 20a is formed by completely oxidizing the excess Hf metal layer 32 by heat treatment in an oxidizing atmosphere. At the same time, the Si nanoparticles 18 are oxidized through the HfO ₂ layer 20a, and SiO ₂ is formed as the oxide layer 18a. Due to the presence of the oxide layer 18a, Hf is confined inside the Si nanoparticles 18 even after a subsequent heat treatment step.

Subsequently, as shown in FIG. 5, ALD or sputtering a HfO ₂ film 10~20nm on the HfO ₂ layer 20a, formed by electron beam method, a block insulating film 20 together with the HfO ₂ layer 20a Is formed. Here, the insulating film formed on the HfO ₂ layer 20a may be an SiO ₂ film or an Al ₂ O ₃ film. In this case, the block insulating film 20 is a laminated film with the HfO ₂ layer 20a.

  Next, a mask material 34 for element isolation is deposited by the CVD method, and then the mask material 34, the block insulation 20, the Si nanoparticles 18, and the tunnel insulating film by the RIE method using a resist mask (not shown). 16 are sequentially etched, and the exposed region of the silicon substrate 10 is further etched to form an element isolation trench 36 having a depth of about 60 nm.

  Next, as shown in FIG. 6, a silicon oxide film 38 to be an element isolation region is deposited on the entire surface to completely fill the element isolation groove 36, and then the silicon oxide film 38 on the surface portion is removed by a CMP method. To flatten the surface. At this time, the material used for the element isolation region 30 is not limited to the silicon oxide film, and may be an insulator containing silicon and oxygen, for example, a silicon oxynitride film.

  Next, as shown in FIG. 7, after the exposed mask material 34 is selectively removed by etching, the exposed surface of the silicon oxide film 38 is removed by etching with a diluted hydrofluoric acid solution, and the silicon oxide film 38 and the block insulating film 20 are removed. Flatten the surface. After forming the flat surface, as the control gate electrode 22, a metal such as n + polysilicon or TaN is formed to 100 nm by sputtering or the like on the entire surface. Subsequently, a mask material 24 for element isolation is deposited by a CVD method.

  Thereafter, as shown in FIG. 8, the mask material 24, the control gate electrode 22, the block insulating film 20, the Si nanoparticles 18, and the tunnel insulating film 16 are sequentially etched by RIE using a resist mask (not shown). The slit portion 40 is formed in the direction along the word line by processing.

  Finally, as shown in FIG. 1, a silicon oxide film 26 called an electrode sidewall oxide film is formed on the exposed surface by a CVD method, and then an n-type source / drain region is formed on the silicon substrate 10 using an ion implantation method. 12, and an interlayer insulating film 28 is formed by CVD so as to cover the entire surface. Thereafter, a wiring layer and the like are formed by a well-known method to complete the nonvolatile semiconductor memory.

  Note that when the Hf metal layer 32 is formed, Hf is introduced into the tunnel insulating film 16, and then Hf is diffused into the Si nanoparticles 18, whereby Hf is interfaced between the silicon substrate 10 and the tunnel insulating film 16. It is desirable to diffuse to For example, Hf can be introduced into the tunnel insulating film 16 by controlling the energy when the Hf metal layer 32 is formed by the electron beam evaporation method. Further, it is possible to diffuse Hf to the interface between the silicon substrate 10 and the tunnel insulating film 16 by adjusting the heat treatment conditions. Hf in the thermally unstable tunnel insulating film 16 is likely to diffuse to the silicon substrate 10 by heat treatment. Further, part of Hf in the Hf metal layer 32 is also diffused in the direction of the silicon substrate 10 through the tunnel oxide film 20 by adjusting the heat treatment conditions.

  This diffusion of Hf into the silicon substrate 10 can improve the reliability of the manufactured nonvolatile memory.

Generally, the interface between the SiO ₂ and SiON and Si substrate constituting the tunnel insulating film, there are defects such as _{P b} centers. In normal memory formation process, for example, in the process, such as an electrode sidewall oxide film or an interlayer insulating film formed, for using the CVD process, P _b centers are terminated with hydrogen. On the other hand, the repetition of writing and erasing the memory cell, the defect site is formed in the hydrogen tunneling film deviated from _{P b} centers, may cause SILC (Stress Induced Leakage Current) in question.

FIG. 9 shows a sample in which a SiO ₂ film having a thickness of 4 nm is formed on a Si substrate, a 0.5 nm Hf film is formed thereon by electron beam evaporation, and then a post-deposition heat treatment at 800 ° C. for 30 seconds in nitrogen. It is a SIMS profile of the sample which gave. By performing the heat treatment, Hf in the Si substrate and SiO ₂ is reduced. Considering the results of the above first principle calculation together, Hf in the Si substrate diffuses to the back side of the Si substrate where no Hf exists, whereas Hf in SiO ₂ is unstable, so the Si substrate side or the SiO ₂ surface side It is thought that it has spread.

Figure 10 when the sample and without the presence of Hf in the tunnel insulating film and the Si substrate interface was observed by an electron spin resonance method (ESR), shows the signal P _b centers. P _b centers observed when Hf is not present, it can be seen that almost disappeared by introducing Hf in the interface. Therefore, by diffusing Hf to the interface, the sites where H can be adsorbed at the interface decrease. As a result, the amount of H at the interface is reduced, and SILC can be suppressed. Therefore, the reliability of the nonvolatile memory can be improved.

  In the present embodiment, Hf has been described as an example of the element contained in the Si nanoparticles. However, the element to be included in the Si nanoparticles is not limited to Hf, but is a metal element having a d orbital such as Zr, Ti, Ta, Nb, W, and Y and the number of electrons occupying the d orbital being close to Hf. If it exists, since it has a property comparatively close to Hf, it is thought that an equivalent effect | action and effect are acquired.

In the present embodiment, the Si nanoparticles are described as an example of the semiconductor particles. However, even if Ge particles or Si _x Ge _1-x (0 <x <1) particles are applied, the same operation and effect are achieved. Can be obtained.

(Second Embodiment)
The nonvolatile semiconductor memory according to the second embodiment of the present invention is a film in which Si nanoparticles and a charge trapping film used in MONOS or the like, for example, HfON, which is an oxynitride of Hf, are combined as a charge storage layer. It is characterized by having.

  FIG. 11 is a cross-sectional view of the Si-NC memory cell of the nonvolatile semiconductor memory according to the present embodiment. 11A is a cross-sectional view in a direction parallel to the bit line, FIG. 11B is a cross-sectional view in a direction parallel to the word line, and FIG. 11A and FIG. 11B are orthogonal to each other. A cross section is shown.

  Unlike the first embodiment, a charge trap film 42 made of HfON is formed between the block insulating film 20 and the Si nanoparticles 18. With this configuration, it is possible to further increase the charge trapping efficiency relative to the charge trap of the Si nanoparticles 18 alone.

As for the method of manufacturing the memory cell of FIG. 11, basically, the process described in the manufacturing method of the first embodiment (FIGS. 3 to 8) can be applied. Below, only the parts different from the manufacturing method of the first embodiment are shown. As in the first embodiment, the Hf metal layer 32 of FIG. 3 is oxidized to form the HfO ₂ layer 20a shown in FIG. 4, and then the HfO ₂ layer 20a is nitrided to form the HfON ₂ layer as the charge trapping film 42. A membrane is obtained. That is, the Hf oxynitride is formed by oxynitriding the Hf metal layer 32. Thereafter, the block insulating film 20 is formed on the charge trapping film 42, and the memory cell shown in FIG. 11 can be manufactured by the same method as the manufacturing method of the first embodiment.

(Third embodiment)
The nonvolatile semiconductor memory according to the third embodiment of the present invention is characterized in that the uppermost surface of the tunnel insulating film is an HfSiO film. In the first and second embodiments, the description has been given of the case where the tunnel insulating film is a SiO ₂ film, a SiON or an ONO film. However, the HfSiO (hafnium silicate) film is only provided on the SiO ₂ film and the ONO film. May be laminated.

  FIG. 12 is a cross-sectional view of the memory cell of the nonvolatile semiconductor memory according to the present embodiment. 12A is a cross-sectional view in a direction parallel to the bit line, FIG. 12B is a cross-sectional view in a direction parallel to the word line, and FIG. 12A and FIG. 12B are orthogonal to each other. A cross section is shown.

Unlike the first embodiment, the top surface of the tunnel insulating film 16 is an HfSiO film 44. By making the uppermost surfaces of the SiO ₂ film and the ONO film into an HfSiO film, the energy at the upper end of the conduction band is lowered, so that the barrier height against electrons is lowered and the effect of increasing the writing efficiency of the tunnel film can be obtained.

Regarding the method of manufacturing the memory cell of FIG. 12, basically, the process described in the manufacturing method (FIGS. 3 to 8) of the first embodiment can be applied. Below, only the parts different from the manufacturing method of the first embodiment are shown. As the tunnel insulating film 16, an SiO ₂ film or an ONO film is formed. Thereafter, up to the Hf metal layer 32 shown in FIG. 3 is formed in the same manner as in the first embodiment.

At this point, Hf is present in the SiO ₂ layer above the tunnel insulating film 16. Therefore, after that, by performing a heat treatment at 800 ° C. for 30 seconds in oxygen, Hf present in the SiO ₂ layer in the tunnel insulating film 16 causes a silicate reaction with the SiO ₂ layer, and the HfSiO film 44 is formed. The At the same time, the surface of the Si nanoparticles 18 is oxidized, and the Hf metal layer 32 is changed to the HfO ₂ layer 20a. Thereafter, the memory cell shown in FIG. 12 can be manufactured by the same method as the manufacturing method of the first embodiment.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments.

1 is a cross-sectional view of a memory cell according to a first embodiment. It shows the distribution of the interface state density D _it for electrons of energy E. Sectional drawing which shows the manufacturing process of the memory cell of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory cell of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory cell of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory cell of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory cell of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory cell of 1st Embodiment. The figure which shows a SIMS profile. The figure which shows the measurement result by an electron spin resonance method. Sectional drawing of the memory cell of 2nd Embodiment. Sectional drawing of the memory cell of 3rd Embodiment.

Explanation of symbols

10 silicon substrate 12 source / drain region 14 channel region 16 tunnel insulating film 18 Si nanoparticle 18a oxide layer 20 block insulating film 20a HfO ₂ layer 22 control gate electrode 24 mask material 26 silicon oxide film 28 interlayer insulating film 30 element isolation region 32 Hf metal layer 34 Mask material 36 Element isolation trench 38 Silicon oxide film 40 Slit portion 42 Charge trap film 44 HfSiO film

Claims (12)

A first conductivity type semiconductor substrate;
A source / drain region of a second conductivity type provided in the semiconductor substrate so as to be spaced apart from each other;
A channel region formed between the source / drain regions;
A first insulating film formed on the channel region;
Semiconductor particles formed on the first insulating film and containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, and Y;
A second insulating film formed on the semiconductor particles;
A control gate electrode formed on the second insulating film;
A non-volatile semiconductor memory comprising:   The nonvolatile semiconductor memory according to claim 1, wherein an oxide layer of the semiconductor particles is formed on the surface of the semiconductor particles.   The nonvolatile semiconductor memory according to claim 1, wherein the second insulating film is an oxide of the element contained in the semiconductor particles. The particle size of the semiconductor particles is 3 nm or more and 10 nm or less, and the atomic density of the element contained in the semiconductor particles is 2 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. The nonvolatile semiconductor memory according to any one of claims 1 to 3.   The nonvolatile semiconductor memory according to claim 1, wherein the semiconductor particles are Si particles. A first conductivity type semiconductor substrate;
A source / drain region of a second conductivity type provided in the semiconductor substrate so as to be spaced apart from each other;
A channel region formed between the source / drain regions;
A first insulating film formed on the channel region;
Semiconductor particles formed on the first insulating film and containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, and Y;
A second insulating film formed on the semiconductor particles and being an oxynitride of the element contained in the semiconductor particles;
A third insulating film formed on the second insulating film;
A control gate electrode formed on the third insulating film;
A non-volatile semiconductor memory comprising: Forming a first insulating film on a first conductivity type semiconductor substrate;
Forming semiconductor particles on the first insulating film;
Forming a metal layer containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, Y on the surface of the semiconductor particles;
Diffusing the elements contained in the metal layer into the semiconductor particles by heat treatment;
Forming a second insulating film by oxidizing the metal layer;
Forming a control gate electrode on the second insulating film;
Forming source / drain regions in the semiconductor substrate;
A method for manufacturing a non-volatile semiconductor memory, comprising:   8. The method of manufacturing a nonvolatile semiconductor memory according to claim 7, wherein, in the step of forming the second insulating film, an oxide layer of the semiconductor particles is formed on the surface of the semiconductor particles.   9. The method for manufacturing a nonvolatile semiconductor memory according to claim 7, wherein the heat treatment is performed in an inert gas atmosphere. Introducing the element into the first insulating film in the step of forming the metal layer;
10. The method for manufacturing a nonvolatile semiconductor memory according to claim 7, wherein the element is diffused to an interface between the semiconductor substrate and the first insulating film by the heat treatment. 11.   The method for manufacturing a nonvolatile semiconductor memory according to claim 7, wherein the semiconductor particles are Si particles. Forming a first insulating film on a first conductivity type semiconductor substrate;
Forming semiconductor particles on the first insulating film;
Forming a metal layer containing at least one element selected from the group of Hf, Zr, Ti, Ta, Nb, W, Y on the surface of the semiconductor particles;
Diffusing the elements contained in the metal layer into the semiconductor particles by heat treatment;
Forming a second insulating film by oxynitriding the metal layer;
Forming a third insulating film on the second insulating film;
Forming a control gate electrode on the third insulating film;
Forming source / drain regions in the semiconductor substrate;
A method for manufacturing a non-volatile semiconductor memory, comprising:

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