JP2010079600A - Microcomputer and method for protecting sram data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve user's convenience and to surely hold safety in a microcomputer using a SRAM (Static Random Access Memory) for storing setup data or the like to be held. <P>SOLUTION: In the microcomputer 100 of a remote controller, a setup data protection part 140 stops the operation of the SRAM 110 synchronously with a reset signal S1 output from a reset control part 130 when asynchronous reset is generated, delays the reset signal S1 until after stopping the operation of the SRAM 110, and outputs the delayed reset signal S1 to a CPU 120. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a microcomputer provided with SRAM (Static Random Access Memory), and more particularly, to a data protection technique of SRAM at the time of asynchronous reset of such a microcomputer.

  An SRAM is a volatile semiconductor memory in which stored contents are lost when a supplied voltage becomes lower than a predetermined voltage (hereinafter referred to as a RAM holding voltage). Therefore, the SRAM is generally used as a temporary data storage device.

  On the other hand, SRAM has advantages of high response and low cost. In addition, in the case of a remote controller that is powered by a battery, a power supply voltage higher than the RAM holding voltage is usually supplied, and various settings, etc., except when the battery is replaced or when the voltage drops due to battery life Even if the content to be stored in the storage device is lost, it can be reset by the user. Therefore, in a microcomputer (hereinafter referred to as a microcomputer) constituting a remote controller, an SRAM is used not only for storing temporary data but also for storing the above-described setting contents.

  In such a microcomputer, the SRAM is usually divided into a setting data area and a temporary data area. The setting data area is used to store the above-described setting contents, that is, once set, it does not need to be changed during subsequent operations, and is used only for reading data. The temporary data area stores temporary data during microcomputer operation. And read / write.

  Since SRAM is a volatile memory that does not assume data retention, in a system provided with SRAM, when an asynchronous reset occurs, assuming that stored data is normally destroyed when an asynchronous reset occurs, Addresses are initialized. However, if the same is applied to the microcomputer of the remote controller, resetting is required every time an asynchronous reset occurs, which is cumbersome for the user. In order to improve the convenience of the user while maintaining safety, various ideas have been made regarding the handling of the SRAM in the microcomputer of the remote controller.

  For example, using the fact that the data stored in the SRAM is held as long as the power supply voltage is equal to or higher than the RAM holding voltage, the RAM holding flag indicating whether or not the SRAM data is destroyed in the register of the CPU Central Processing Unit) There is a method for determining whether or not to initialize an address by referring to this RAM holding flag after asynchronous reset. This will be described with reference to FIG.

  FIG. 6 shows an example of voltage change after the remote controller is powered on. The operation of the microcomputer will be described for each period. In the following description, the POC (Power On Clear) voltage is the lowest voltage for normal operation of the microcomputer, and a system reset occurs when the power supply voltage supplied to the remote controller becomes lower than the POC voltage. The system reset in this case is called POC. The RAM holding voltage is the lowest voltage for the SRAM in the microcomputer to hold the stored contents.

<Period (1)>
The power supply voltage rises due to the setting of the dry battery, but the microcomputer does not operate because it is lower than POC (Power On Clear). The RAM holding flag also remains “0” in the initial state.

<Period (2)>
The power supply voltage becomes POC or higher. Thereby, the reset is released and the microcomputer operates. When the setting is made by the user, the setting content is stored in the setting data area, and the RAM holding flag is rewritten from “0” in the initial state to “1”.

  During this period, the power supply voltage drops for some reason, but since it is equal to or higher than the POC voltage, the microcomputer continues normal operation and the RAM holding flag remains “1”. The CPU performs processing according to an operation instruction (such as pressing a button) from the user. In the processing, the setting data is read from the setting data area, and the temporary data area is used for reading / writing the temporary data.

<Period (3)>
The power supply voltage becomes lower than the POC voltage, and POC that is an asynchronous reset occurs. However, since the lowest voltage (the voltage at the point A) is higher than the RAM holding voltage, the RAM holding flag is maintained at “1”.
Thereafter, the power supply voltage increases, but the microcomputer does not operate because it is lower than the POC voltage.

<Period (4)>
Since the power supply voltage becomes equal to or higher than the POC voltage, the reset is released. Since the RAM holding flag is “1”, the CPU does not initialize the SRAM address. Therefore, there is no need for resetting by the user.

  After that, although the power supply voltage decreases, the asynchronous reset does not occur because it is equal to or higher than the POC voltage. The RAM holding flag remains “1”.

<Period (5)>
Asynchronous reset occurs when the power supply voltage further decreases and becomes lower than the POC voltage. In addition, the power supply voltage continues to drop and becomes lower than the RAM holding voltage at point B. At this time, the RAM holding flag is set to “0”.
Thereafter, the power supply voltage increases, but the microcomputer does not operate because it is lower than the POC voltage.

<Period (6)>
Since the power supply voltage becomes equal to or higher than the POC voltage, the reset is released. However, since the RAM holding flag is “0”, the CPU initializes the SRAM address. Therefore, resetting by the user is required.

  In this way, if the power supply voltage is not lower than the RAM holding voltage, it is possible to eliminate the need for resetting by the user even if an asynchronous reset occurs.

  By the way, when an asynchronous reset occurs while the CPU is writing or erasing the temporary data area of the SRAM, the address selection of the SRAM may become unstable, and erroneous writing to an area of another address Or erroneous erasure may occur. In this case, erroneous erasure or erroneous writing of the setting data area may occur. Therefore, as a specification of a microcomputer for a remote controller, even if a RAM holding flag is provided, if an asynchronous reset occurs during writing or erasing by the CPU, the data holding state of the SRAM is often “undefined”. . The developer falls into the safety and user convenience dilemma regarding the handling of data stored in the SRAM when a system reset occurs during the writing or erasing of the SRAM by the CPU.

On the other hand, Patent Document 1 discloses a technique for avoiding erroneous erasure and erroneous writing when a system reset occurs during execution of a write and erase sequence in the field of flash memory.
JP 2003-131951 A

  However, from the viewpoint of responsiveness, cost, circuit scale, etc., it is unrealistic to use a flash memory on the premise that data is retained for a microcomputer of a remote controller. There is a demand for a technology that can improve the convenience for the user and can ensure safety while using the SRAM for storing the setting data to be held.

  One embodiment of the present invention is a microcomputer. The microcomputer includes an SRAM, a CPU, and an SRAM data protection unit.

  The SRAM data protection unit stops the operation of the SRAM in synchronization with the asynchronous reset signal, and outputs the asynchronous reset signal to the CPU with a delay until after the SRAM operation stops.

  It is also effective as an aspect of the present invention to replace the microcomputer of the above aspect with a method for protecting data stored in an apparatus, system, or SRAM.

  According to the technology of the present invention, in the microcomputer, while using the SRAM for storing setting data to be held, the convenience of the user can be improved and the safety can be reliably maintained.

Embodiments of the present invention will be described below with reference to the drawings. In order to clarify the explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals, and description thereof is omitted.
Each of the following embodiments can avoid erroneous writing and / or erasure of the SRAM when an asynchronous reset occurs while the CPU is writing to and / or erasing the SRAM. For convenience, the “writing” and “erasing” of the SRAM by the CPU will be generally described as “writing”. Therefore, in the following description and the drawings used for the description, “writing” includes “erasing”.
<First Embodiment>

  FIG. 1 shows a microcomputer 100 according to a first embodiment of the present invention. The microcomputer 100 is provided in a remote controller of an electronic device such as a television, and includes an SRAM 110, a CPU 120, a reset control unit 130, and a setting data protection unit 140.

  In the microcomputer 100, the SRAM 110, the CPU 120, and the reset control unit 130 are the same as those provided in the microcomputer for the same application, and the setting data protection unit 140 is a characteristic part of the present invention.

  The SRAM 110 is divided into a setting data area 112 and a temporary data area 114. The setting data area 112 stores setting data that is set by the user and does not need to be changed during the operation of the remote controller after the setting. The temporary data area 114 is a temporary storage area during the operation of the remote controller.

  The CPU 120 writes the setting made by the user via the user input unit (for example, a button) of the remote controller to the setting data area 112 of the SRAM 110, and then performs processing according to the input from the user input unit of the remote controller. . During processing, the CPU 120 reads the setting data area 112 of the SRAM 110 and reads / writes the temporary data area 114.

  The reset control unit 130 controls asynchronous reset of the microcomputer 100, and outputs a reset signal S1 when it is necessary to perform asynchronous reset. In the present embodiment, the reset signal S1 is normally High, and becomes Low when an asynchronous reset occurs. As a case where asynchronous reset is necessary, for example, when a runaway is detected by a watchdog timer (runaway detection timer) (not shown), when POC (Power On Clear) occurs, a reset input is performed from a reset terminal (not shown). This can be the case when

  The setting data protection unit 140 protects the setting data by preventing erroneous writing to the setting data area 112 by the CPU 120 when an asynchronous reset occurs, and includes an AND gate 150, a delay unit 160, and a clock control unit 170. And an AND gate 180.

  The operation of the setting data protection unit 140 will be described in detail with reference to FIG. 2 showing an example of changes in each signal in the microcomputer 100.

  The delay unit 160 includes a delay element 162 and an OR gate 164. The delay element 162 delays the reset signal S1 from the reset control unit 130 and outputs the delayed signal to the OR gate 164. The OR gate 164 receives the output of the delay element 162 and the reset signal S1 from the reset control unit 130, and outputs a CPU reset signal S2 that is a logical sum of them to the CPU 120. In the present embodiment, the delay element 162 delays the reset signal S1 until the end of the next cycle. As a result, the delay unit 160 delays the fall of the reset signal S1 until the end of the next cycle, and then raises the CPU reset signal S2 in accordance with the rise of the reset signal S1.

  As shown in FIG. 2, the reset signal S1 falls due to the occurrence of an asynchronous reset at timing t0, but the CPU reset signal S2 falls at the end timing t1 of the next cycle.

  The clock controller 170 supplies a clock and an address to the SRAM 110 in accordance with the writing to the SRAM 110 by the CPU 120. Hereinafter, a signal provided to the SRAM 110 by the clock controller 170 is referred to as an SRAM write signal W.

  In a conventional microcomputer of the same type, the clock controller normally stops its operation when an asynchronous reset occurs, and simultaneously stops the clock supply to the CPU and SRAM. For this reason, if an asynchronous reset occurs during the writing of the SRAM by the CPU, the address selection of the SRAM becomes unstable, and the setting data area may be erroneously written.

  In the present embodiment, the clock control unit 170 receives the CPU reset signal S2 from the delay unit 160 instead of the reset signal S1, and performs the same operation as the conventional clock control unit when no asynchronous reset occurs. To do. When the asynchronous reset occurs, the supply of the SRAM write signal W is stopped not at the falling edge of the reset signal S1 but at the falling edge of the CPU reset signal S2 obtained by delaying the falling edge of the reset signal S1. As shown in FIG. 2, the SRAM write signal W becomes Low at timing t1.

  The AND gate 150 functions as an SRAM control unit, receives the reset signal S1 and the SRAM write signal W, and outputs an SRAM write_reset signal WR, which is a logical product of them, to the SRAM 110. Thus, as shown in FIG. 2, when the asynchronous reset has not occurred, the SRAM write_reset signal WR becomes High / Low in synchronization with the SRAM write signal W, and when the asynchronous reset occurs, that is, the reset It becomes Low at timing t0 when the signal S1 falls. Thereafter, until the end timing t1 of the next cycle, even if the SRAM write signal W becomes High, the SRAM write_reset signal WR is maintained low, and the supply of the clock signal to the SRAM 110 is stopped and the stopped state is maintained. Is done.

With this configuration of the setting data protection unit 140, when an asynchronous reset occurs and the reset signal S1 falls (timing t0 shown in FIG. 2), the clock supply to the SRAM 110 is immediately stopped and the SRAM 110 stops operating. The CPU 120 and the clock control unit 170 continue to operate until the end timing t1 of the next cycle. Therefore, even if an asynchronous reset occurs during the writing of the SRAM 110 by the CPU 120, it is possible to prevent the data in the setting data area 112 from being destroyed due to the unstable address selection of the SRAM 110.
<Second Embodiment>

  FIG. 3 shows a microcomputer 200 according to the second embodiment of the present invention. Similarly to the microcomputer 100, the microcomputer 200 is also provided in the remote controller. Parts having the same configuration or function as those of the microcomputer 100 shown in FIG. 1 in the microcomputer 200 are given the same reference numerals as those of the microcomputer 100, and detailed descriptions thereof are omitted.

  As illustrated in FIG. 3, the microcomputer 200 includes an SRAM 110, a CPU 120, a reset control unit 130, and a setting data protection unit 240. In the microcomputer 200, the other functional blocks are the same as those of the microcomputer 100, except that the setting data protection unit 240 is different from the setting data protection unit 140 in the microcomputer 100. The setting data protection unit 240 is the same as the setting data protection unit 140 except that an AND gate 252 and an OR gate 254 are provided instead of the AND gate 150 of the setting data protection unit 140. is there.

  The AND gate 252 receives the SRAM write signal W from the AND gate 180 and the output of the OR gate 254, and outputs a logical product of these to the SRAM 110 as an SRAM write_reset signal WR. The OR gate 254 receives the reset signal S 1 from the reset control unit 130 and the output of the AND gate 252, that is, the SRAM write_reset signal WR, and outputs a logical sum of them to the AND gate 252.

  FIG. 4 shows a change example of each signal in the microcomputer 200 of the present embodiment. As can be seen from comparison with FIG. 2, each signal in the microcomputer 200 is the same as each signal in the microcomputer 100 when an asynchronous reset has not occurred. When an asynchronous reset occurs and the reset signal S1 falls, the CPU reset signal S2 and the SRAM write signal W are the same as the corresponding signals in the microcomputer 100, but the SRAM write_reset signal WR In the case of 100, the fall is delayed from the SRAM write_reset signal WR, and falls at the end timing of the current cycle.

With such a configuration of the setting data protection unit 240 of the microcomputer 200, the SRAM write_reset signal WR falls at the end timing of the current cycle, and thereafter, until the end timing t1 of the next cycle. Even when the signal W becomes High, the SRAM write_reset signal WR is maintained Low, and the supply of the clock signal to the SRAM 110 is stopped and the stopped state is maintained. Therefore, the same effect as that of the setting data protection unit 140 in the microcomputer 100 can be obtained.
<Third Embodiment>

  FIG. 5 shows a microcomputer 300 according to the third embodiment of the present invention. Similarly to the microcomputer 100, the microcomputer 300 is also provided in the remote controller. Parts having the same configuration or function as those of the microcomputer 100 shown in FIG. 1 in the microcomputer 300 are given the same reference numerals as those of the microcomputer 100, and detailed descriptions thereof are omitted.

  As shown in FIG. 5, the microcomputer 300 includes an SRAM 110, a CPU 120, a reset control unit 130, and a setting data protection unit 340. In the microcomputer 300, the other functional blocks are the same as those of the microcomputer 100, except that the setting data protection unit 340 is different from the setting data protection unit 140 in the microcomputer 100. The setting data protection unit 340 is the same as the setting data protection unit 140 except that either the reset signal S1 or the signal from the delay unit 160 is selected and output to the CPU 120 and the clock control unit 170. .

  The selector 350 receives the SRAM write signal W, the reset signal S1, and the signal delayed by the delay unit 160 (same as the CPU reset signal S2 in FIG. 1), and based on the SRAM write signal W, Either the reset signal S1 or the signal from the delay unit 160 is selected and output to the CPU 120 and the clock control unit 170 as the CPU reset signal S2. Specifically, when the SRAM write signal W indicates that the CPU 120 is writing to the SRAM 110, the signal from the delay unit 160 is selected, and the CPU 120 sends the signal to the SRAM 110. The reset signal S1 is selected to indicate that writing is not in progress.

  That is, in this embodiment, when an asynchronous reset occurs when the CPU 120 is not writing to the SRAM 110, the CPU reset signal S2 output to the CPU 120 and the clock control unit 170 is delayed. On the other hand, when an asynchronous reset occurs while the CPU 120 is writing to the SRAM 110, the CPU reset signal S2 output to the CPU 120 and the clock control unit 170 is the delay unit 160. This is the reset signal S1 whose falling is delayed by. Therefore, the same effect as that of the microcomputer 100 shown in FIG. 1 can be obtained, and when the CPU 120 is not writing to the SRAM 110, the reset can be quickly performed.

  As can be seen from the above description, in the microcomputer according to the present invention, which uses the SRAM divided into the setting data area and the temporary data area, the clock supply to the SRAM is stopped when the asynchronous reset occurs. By resetting the CPU after stopping the operation, it is possible to prevent erroneous writing when an asynchronous reset occurs while the CPU writes to the SRAM. Therefore, as long as the power supply voltage does not become the SRAM holding voltage, it is not necessary to re-input the setting data stored in the SRAM, and safety can be reliably maintained while ensuring convenience.

  Here, the technique of the present invention and the technique of Patent Document 1 will be compared. The technique of Patent Document 1 is a technique related to avoiding erroneous writing of the flash memory. A flash memory is a non-volatile memory that retains stored data even when power supply is interrupted, whereas an SRAM targeted by the present invention is an SRAM that loses stored data when power supply is interrupted. For this reason, it is difficult to refer to the technology of the flash memory when considering data protection in the SRAM. The inventor of the present application also noticed Patent Document 1 for the first time when the technical field was expanded and research was conducted after the present invention was made. That is, since a person skilled in the field of the technology of the present invention cannot consider referring to the technology in the field of flash memory when developing technology related to data protection of SRAM, the technology disclosed in Patent Document 1 is Even if it is similar to the technology of the present invention, the patentability of the present invention cannot be denied.

  The flash memory is slower than the operation of the CPU, and requires a certain amount of time (usually about 100 counts) until the writing is completed in response to the writing by the CPU. Therefore, as in the technique disclosed in Patent Document 1, a system reset signal (corresponding to the reset signal S1 in the above-described embodiment) is delayed and output to the flash memory to complete the current writing. This makes it possible to avoid erroneous writing to the flash memory. On the other hand, unlike the flash memory, the SRAM targeted by the present invention has high responsiveness and can complete writing at almost the same speed as the operation of the CPU. Therefore, even if the technique of Patent Document 1 is applied and the reset signal S1 is delayed and output to the SRAM, it is difficult to prevent erroneous writing to the SRAM.

  The present invention has been described above based on the embodiment. The embodiment is an exemplification, and various changes and increases / decreases may be added without departing from the gist of the present invention. It will be understood by those skilled in the art that modifications to which these changes and increases / decreases are also within the scope of the present invention.

  For example, in the above-described embodiment, a microcomputer provided in a remote controller is taken as an example. In the case of household electronic devices such as a microwave oven (MICROWAVE OVEN), it is often connected to a power outlet at all times, and can be reset by the user even if settings such as timer settings are lost. . For this reason, in the control microcomputer provided in these home electronic devices, it is conceivable that the SRAM is used not only for storing temporary data but also for storing setting contents to be retained. The technology of the present invention can be applied to such a microcomputer, and the effects of the present invention can be obtained by applying the technology.

It is a figure which shows the microcomputer concerning the 1st Embodiment of this invention. It is a figure which shows the example of a change of each signal in the setting data protection part of the microcomputer shown in FIG. It is a figure which shows the microcomputer concerning the 2nd Embodiment of this invention. It is a figure which shows the example of a change of each signal in the setting data protection part of the microcomputer shown in FIG. It is a figure which shows the microcomputer concerning the 3rd Embodiment of this invention. It is a figure which shows the example of a voltage change after the power supply of a remote controller is turned ON.

Explanation of symbols

100 microcomputer 110 SRAM
112 Setting Data Area 114 Temporary Data Area 120 CPU 130 Reset Control Unit 140 Setting Data Protection Unit 150 AND Gate 160 Delay Unit 162 Delay Element 164 OR Gate 170 Clock Control Unit 180 AND Gate 200 Microcomputer 240 Setting Data Protection Unit 252 AND Gate 254 OR Gate 300 Microcomputer 340 Setting data protection unit 350 Selector S1 Reset signal S2 CPU reset signal W SRAM write signal WR SRAM write_reset signal

Claims (8)

SRAM (Static Random Access Memory),
CPU (Central Processing Unit),
An SRAM data protection unit that stops the operation of the SRAM in synchronization with an asynchronous reset signal and delays the asynchronous reset signal until after the operation of the SRAM is stopped, and outputs the SRAM data protection unit to the CPU. Microcomputer.   The SRAM is set by a user and is divided into a holding data area for storing data to be held even when an asynchronous reset occurs, and a temporary data area for holding other data. 2. The microcomputer according to 1. The SRAM data protection unit
A clock supply unit for supplying an operation clock to the SRAM in accordance with the access to the SRAM by the CPU;
An SRAM control unit that turns off the operation clock from the clock supply unit in response to the asynchronous reset signal;
The microcomputer according to claim 1, further comprising a delay unit that delays the asynchronous reset signal and outputs the delayed reset signal to the CPU. The asynchronous reset signal is a signal that becomes Low only when an asynchronous reset occurs,
4. The microcomputer according to claim 3, wherein the SRAM control unit is an AND gate that outputs a logical product of the asynchronous reset signal and an operation clock from the clock supply unit to the SRAM. The asynchronous reset signal is a signal that becomes Low only when an asynchronous reset occurs,
The SRAM control unit has an AND gate and an OR gate,
The AND gate outputs a logical product of the asynchronous reset signal and the output of the OR gate to the SRAM,
4. The microcomputer according to claim 3, wherein the OR gate outputs a logical sum of an operation clock from the clock supply unit and an output of the AND gate to the AND gate. The SRAM data protection unit further includes a selector that selects one of the asynchronous reset signal and the asynchronous reset signal delayed by the delay unit and outputs the selected signal to the CPU.
4. The selector selects an asynchronous reset signal delayed by the delay unit only when the CPU is writing or erasing the SRAM when an asynchronous reset occurs. 6. The microcomputer according to any one of items 1 to 5. In a microcomputer provided with SRAM (Static Random Access Memory) and CPU (Central Processing Unit),
An SRAM data protection method comprising: stopping the operation of the SRAM in synchronization with an asynchronous reset signal, and outputting the asynchronous reset signal to the CPU with a delay until after the operation of the SRAM is stopped.   When an asynchronous reset occurs, the operation clock supplied to the SRAM in accordance with the access to the SRAM by the CPU is turned off according to the asynchronous signal, and the asynchronous signal is delayed and output to the CPU. The SRAM data protection method according to claim 7, wherein:

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