JP2010074151A - Wiring board with built-in component - Google Patents

Abstract

An object of the present invention is to provide a component built-in wiring board capable of realizing high productivity and low cost and maintaining reliability even when plural types of components are embedded and mounted in a mixed manner.
A semiconductor device having a surface mount terminal and a chip-like component embedded in a first insulating layer and a second insulating layer embedded in the second insulating layer, and sandwiched between the first and second insulating layers. A wiring pattern having first and second lands, and first and second connecting members for electrically connecting the semiconductor element and component to the first and second lands, respectively. The connecting member 2 includes a cured resin portion, a metal having a melting point of 240 ° C. or less contained in the resin portion, and a first metal which is one of the metal components of the metal includes a second metal. A second metal particle whose surface is covered with the multi-element phase of the first metal having a melting point of 260 ° C. or more by changing to a phase; and the multi-element phase in the resin portion Are connected to each other to form a conductive skeleton structure.
[Selection] Figure 1

Description

  The present invention relates to a component built-in wiring board in which components are embedded and mounted in an insulating plate, and particularly to a component built-in wiring board in which a plurality of types of components are embedded and mounted in a mixed manner.

  An example of a component built-in wiring board in which a plurality of types of components are embedded and mounted in a mixed manner is disclosed in Japanese Patent Application Laid-Open No. 2003-197849. In the wiring board disclosed in this document, in addition to passive components such as a chip capacitor (chip capacitor), a semiconductor chip is a target component to be embedded. By embedding a semiconductor component such as a semiconductor chip, the added value as a component built-in wiring board is remarkably increased as compared with a case where only a passive component is provided.

  When embedding and mounting a semiconductor component in a wiring board, the wiring board itself is not so thick even in recent years even if it is a multi-layer board, and inevitably usually has as little thickness as a bare chip, for example. The form will be used. In the case of using a bare chip, as shown in the above-mentioned document, it is advantageous in terms of saving thickness that a face-down mounting is performed on the inner layer wiring pattern of the wiring board. In general, a technique for mounting a semiconductor chip face down on a wiring pattern is known as flip chip connection, and this technique can be used.

  Flip chip connection includes a technique for aligning fine-pitch connection pads formed on a semiconductor chip with respect to lands formed by a wiring pattern. To ensure positional accuracy, the size of a work having a wiring pattern is reduced. It can't be too big. On the other hand, a technique for mounting a passive component such as a chip capacitor on a wiring pattern is a so-called surface mounting technique that uses solder or a conductive adhesive as a connection member between the component and the wiring pattern. In this case, the positioning accuracy of the parts with respect to the wiring pattern may be coarser than that in the case of flip-chip connection, and therefore, the production equipment corresponding to a relatively large work can be used in consideration of productivity.

  In a wiring board with a built-in component in which multiple types of components such as passive components and semiconductor components are embedded and mounted in a wiring board, surface mounting technology is used for mounting passive components. For this purpose, flip-chip connection technology is used. Therefore, two processes having different properties are required, and one problem arises in improving productivity. Also, flip chip connection is disadvantageous in improving productivity because it cannot handle large workpieces.

  Further, in the structure shown in FIG. 1 of Japanese Patent Application Laid-Open No. 2003-197849, solder (or conductive adhesive) is used for electrical connection of electrical components to the wiring layer. In the manufacturing method, electrical components are electrically and mechanically connected to a wiring board serving as a core in advance using solder (or conductive adhesive). In addition, a hole is formed in another insulating resin layer, and the hole is filled with a conductive composition, aligned and arranged with the core plate on which the component has been previously mounted, and laminated and integrated.

  In the component built-in wiring board, when another component is externally mounted on this wiring board or when the component built-in wiring board itself is mounted on another wiring board (both referred to as secondary mounting), It is important that the connection reliability is not impaired. Specifically, for example, when solder is used as a connection material for a built-in component, it is necessary to prevent connection failure or short circuit due to remelting of the solder.

  This document describes the use of high-temperature solder having a high melting point in order to prevent such remelting (paragraph 0034 of the document). However, the specific components of solder are not clear. In general, Sn—Pb-based Pb-rich materials are known as high-temperature solders, including Pb-5Sn (melting point: 314 ° C. to 310 ° C.) and Pb-10 Sn (melting point: 302 ° C. to 275 ° C.). However, the soldering temperature requires a high temperature of 300 ° C. or higher. At such a high temperature, a general epoxy resin as an insulating plate material for a wiring board is insufficient in heat resistance and is difficult to apply.

JP 2003-197849 A

  The present invention has been made in consideration of the above-described circumstances, and even when a plurality of types of components are embedded and mounted in a mixed manner in a component built-in wiring board in which components are embedded and mounted in an insulating plate. An object of the present invention is to provide a component built-in wiring board capable of realizing high productivity and low cost and maintaining reliability.

  In order to solve the above-described problem, a component built-in wiring board according to the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, and the second insulating layer. A semiconductor element having a semiconductor chip embedded in an insulating layer and having a terminal pad; and a grid-arranged surface-mounting terminal electrically connected to the terminal pad; and the second insulating layer A kind of electrical / electronic component selected from the group consisting of embedded chip capacitors, chip resistors, and chip inductors, and the first insulating layer and the second insulating layer, A wiring pattern including a first mounting land for the semiconductor element and a second mounting land for the electric / electronic component; the surface mounting terminal of the semiconductor element; and the first mounting land; First connection to electrically connect And a second connecting member that electrically connects the terminal of the electric / electronic component and the second mounting land, and the first connecting member and the second connecting member At least the second connecting member includes a cured resin portion, a metal having a melting point of 240 ° C. or less contained in the resin portion, and a first metal that is one of the metal components of the metal. The second metal whose surface is covered with the multi-element phase of the first metal having a property of having a melting point of 260 ° C. or more by changing to a multi-element phase including a second metal different from the metal of And a conductive part in which the plural element phase is connected in the resin part to form a conductive skeleton structure.

  That is, this component built-in wiring board simultaneously embeds a semiconductor element as one of a plurality of types of components and a kind of electric / electronic component selected from the group consisting of a chip capacitor, a chip resistor, and a chip inductor at the same time. It is prepared. Here, the semiconductor element has a semiconductor chip and a surface mounting terminal in a grid-like arrangement, and the semiconductor chip has a terminal pad. The terminal pads of the semiconductor chip and the surface mounting terminals are electrically connected. Therefore, the semiconductor element can be mounted on the wiring board by the surface mounting terminals arranged in a grid pattern.

  In order to mount the semiconductor element on the wiring board by having the surface mounting terminal, the surface mounting technique can be used in the same manner as the chip capacitor. In addition, the surface mounting terminals are arranged in a grid pattern, that is, in a plane arrangement, so that it is possible to reduce the plane area as a semiconductor element as much as possible. Easy to manage. Therefore, even if a plurality of types of components are embedded and mounted in a mixed manner, the component-embedded wiring board achieves high productivity and low cost.

  In this component built-in wiring board, the connecting member for connecting the built-in chip capacitor or the like to the wiring pattern includes a cured resin portion, a metal having a melting point of 240 ° C. or less contained in the resin portion, The plurality of the first metals having the property of having a melting point of 260 ° C. or higher by changing the first metal, which is one of the composition metals, into a multi-element phase including a second metal different from the first metal. And a conductive portion containing the second metal particles whose surface is covered with an elemental phase and in which a plurality of elemental phases are connected in the resin portion to form a conductive skeleton structure. ing.

  In the connection member having such a configuration, in particular, a skeleton structure formed by connecting a plurality of elemental phases in the conductive portion bears the conductivity, and the plurality of elemental phases are formed by the first metal. And a second metal, and the melting point is selected to be 260 ° C. or higher. By selecting it as 260 ° C. or higher, melting during heating at the time of secondary mounting (for example, at most 250 ° C.) can be avoided, and poor connection and short circuit due to remelting can be prevented. In addition, this conductive skeleton structure is formed in the cured resin portion, and the gaps of the skeleton structure can be filled with resin. Therefore, voids are not generated in the connecting member, and reliability is not impaired. As described above, the reliability as the component built-in wiring board is maintained.

  Note that the connection member (first connection member) for connecting the built-in semiconductor element to the wiring pattern can also be a connection member having the same material and structure as described above. However, the necessity is relatively small compared to the case of a chip capacitor or the like. This is due to the difference in adhesion between the component and the second insulating layer. A component such as a chip capacitor is often a ceramic material except for its terminal portion, and has poorer adhesion to the insulating layer.

  On the other hand, in a semiconductor element having a surface mounting terminal, a resin layer is often disposed around the terminal, and adhesion with the second insulating layer is better. In the case of a ceramic material or the like having poor adhesion, the interface is easy to peel off, and if it is peeled off, remelted solder may enter during secondary mounting and lead to a short circuit failure. Therefore, at least a connection member (second connection member) for connecting a built-in chip capacitor or the like to the wiring pattern is made of a special material and structure as described above.

  According to the present invention, in a component built-in wiring board in which components are embedded and mounted in an insulating plate, high productivity and low cost are realized even when multiple types of components are embedded and mounted in a mixed manner. Reliability can be maintained.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. The bottom view and sectional drawing which show the semiconductor element 42 used for the component built-in wiring board shown in FIG. Process drawing which shows the example of a manufacturing process about the semiconductor element 42 used for the component built-in wiring board shown in FIG. Explanatory drawing which shows the fine structure of the connection member 51 used for the component built-in wiring board shown in FIG. The table | surface which shows the example of the material for obtaining the electroconductive part in the connection member shown in FIG. The table | surface which shows the material example of the multi-element phase which comprises the connection member shown in FIG. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. The graph which shows the example of the temperature profile in the mounting process shown in FIG.8 (f).

  As an embodiment of the present invention, the second connecting member has a thermosetting resin having a thermosetting temperature higher than the melting point of the metal of the second connecting member as the resin portion. it can. This resin part is a resin part which the result obtained by the manufacturing method described above has. That is, in this case, the metal contained therein can be melted before the resin portion is thermally cured. If the resin is thermally cured first, even if the metal is melted, the movement in the resin does not proceed smoothly, and the formation of a multi-element phase having a melting point of 260 ° C. or higher is reduced. By avoiding this, a multi-element phase having a melting point of 260 ° C. or higher can be formed as intended.

  As an embodiment, the first connecting member may be solder containing tin as a main component. As described above, the first connecting member is not limited as much as the second connecting member, and therefore, a commonly used solder is used. The cost can be reduced accordingly. A lead-free solder having a composition such as Sn-3Ag-0.5Cu can also be used.

  As an embodiment, the first connecting member can be a conductive composition. Even if a conductive composition is used as the first connecting member, the compatibility with the surface mounting terminals of the semiconductor element is not bad. For the second connecting member, when a conductive composition is used for this, when Sn plating is applied to the surface of the terminal of the chip capacitor, a chemical reaction occurs between the metal particles contained in the conductive composition. (Battery effect) may occur and lead to corrosion of the terminal. As the first connecting member, it is easy to avoid this by selecting a member having no tin plating layer on the surface of the surface mounting terminal of the semiconductor element.

  As an embodiment, the electrical connection between the surface mounting terminal and the terminal pad in the semiconductor element can be made by a rewiring layer formed on the semiconductor chip. When such a rewiring layer is used, a portion corresponding to the package of the semiconductor element can be made to have a slight thickness and volume, and is suitable by being incorporated in the wiring board.

  As an embodiment, the surface mounting terminal of the semiconductor element can be an LGA terminal. In surface mounting using LGA, it is possible to mount on a wiring board without using bumps such as solder balls, and the size in the height direction can be suppressed.

  As an embodiment, the surface mounting terminal of the semiconductor element may have a Ni / Au plating layer as a surface layer. When the surface mounting terminal has such a plating layer on the surface layer, for example, good soldering and high reliability of the connection can be obtained.

  As an embodiment, the surface mounting terminal of the semiconductor element may have a tin plating layer as a surface layer. Although cheaper, for example, good soldering and high reliability of the connection can be obtained.

  As an embodiment, the surface mounting terminal of the semiconductor element may be Cu as a surface layer. Even Cu, for example, can be soldered for connection, and in this case, there is a high possibility that the structure as a semiconductor element becomes simpler, and it can be manufactured at a lower cost.

  As an embodiment, the resin portion of the second connection member may be an epoxy-modified polyimide resin as a material thereof. By using an epoxy-modified polyimide resin, the thermosetting temperature can be made slightly higher than 240 ° C., for example. Thereby, before this resin part thermosets, the melting | fusing point contained in this can melt | dissolve the metal of 240 degrees C or less. If the resin is thermally cured first, even if a metal having a melting point of 240 ° C. or less is melted, the movement in the resin does not proceed smoothly, and the formation of a multi-element phase having a melting point of 260 ° C. or more is reduced. By avoiding this, a multi-element phase having a melting point of 260 ° C. or higher can be formed as intended.

  Further, as an embodiment, the metal having a melting point of 240 ° C. or lower is Sn—In composition system, Sn—Bi composition system, Sn—Zn—Bi composition system, Sn—Ag—In composition system, Sn—Ag—Cu. A composition system, a Sn—Ag composition system, a Sn—Cu composition system, a Sn—Sb composition system, and one composition system or metal selected from the group consisting of Sn, wherein the second metal is Ag, Au, Cu, Ni, and Fe, and one or more selected from the group consisting of a Cu—Ni composition system, a Cu—Sn composition system, an Ag—Sn composition system, a Cu—Zn composition system, and a Co—Sb composition system Or a compositional system.

According to this, Cu _x Sn _y (melting point: 640.4 ° C.), Co _x Sn _y (same as 525 ° C.), Cu _x Zn _y (same as 598.8 ° C.), Cu _x Sb _y (same as 586 ° C.), Co _x Sb _y (same as 770 ° C.), Ni _x Bi _y (same as 469 ° C.), Ag _x Sn _y (same as 480 ° C.), Fe _x Sn _y (same as 496 ° C.) .6 ° C.), Ag _x Cu _y Sn _z (same as 515 ° C.), or Au _x Sn _y (same as 278 ° C.). Therefore, a multi-element phase having a melting point of 260 ° C. or higher can be realized.

Further, as the embodiment, the multi-element system phase of the conductive portion of the second connection _{member, Cu x Sn y, Co x} Sn y, Cu x Zn y, Cu x Sb y, Co x Sb y, Ni _{x Bi y, Ag x Sn y} , Fe x Sn y, Ag x Cu y Sn z, and _Au x Sn is a phase by one or more selected from the group consisting of _y, can be. As described above, these are examples of phases having a melting point of 260 ° C. or higher.

  Further, as an embodiment, the metal having a melting point of 240 ° C. or lower includes a first alloy containing Sn and one or more selected from the group consisting of Ag, Bi, Cu, In, and Zn, and Sn And a second alloy containing Ag and one or more selected from the group consisting of Bi, Cu, In, and Zn, wherein the second metal is Cu, Ag, Bi, In , And one or more selected from the group consisting of Sn. This is an embodiment in which two types of alloys are used as the metal having a melting point of 240 ° C. or lower. There is a possibility that the melting point can be lowered, that is, a connection process at a lower temperature can be realized.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layer (wiring pattern) 21, 22, 23, 24, 25, 26 (= 6 layers in total), interlayer connector 31, 32, 34, 35, and through-hole conductor 33. , A chip component 41 (electric / electronic component), a semiconductor element (by wafer level / chip scale package) 42, a connection member 51, a connection member (solder) 52, and solder resists 61 and 62.

  That is, this wiring board has chip components 41 and semiconductor elements 42 which are different components from each other as built-in components. The chip component 41 is a so-called surface mounting chip component, and is, for example, a chip capacitor (or chip resistor or chip inductor) here. The planar size is, for example, 0.6 mm × 0.3 mm. Terminals 41 a are provided at both ends, and the lower side thereof is opposed to the mounting land formed by the wiring layer 22. The terminal 41a of the chip component 41 and the mounting land are electrically and mechanically connected by a connecting member 51 (feature will be described later).

  The semiconductor element 42 is an element based on a wafer level / chip scale package, and includes at least a semiconductor chip and a grid-like array of surface mounting terminals 42a formed on the semiconductor chip. Details of the structural example and the manufacturing process example will be described later (FIGS. 2 and 3). The surface mounting terminal 42a is a terminal provided by rearranging its position while being electrically conducted through a rewiring layer from a terminal pad that the semiconductor chip originally has. By such rearrangement, the arrangement density as a terminal is coarser than that of the terminal pad on the semiconductor chip. Thereby, the semiconductor element 42 can be mounted on the mounting land by the wiring layer 22 via the connection member (solder) 52 by the surface mounting technique.

  Describing another structure as a component built-in wiring board, the wiring layers 21 and 26 are wiring layers on both main surfaces as a wiring board, and various components (not shown) can be mounted thereon. Solder resist 61 is provided on both main surfaces except for the land portions of the wiring layers 21 and 26 on which solder (not shown) is to be mounted in mounting, so that the solder melted at the time of solder connection is held on the land portions and thereafter functions as a protective layer. , 62 (thickness is about 20 μm, for example). An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is insulated between the wiring layer 21 and the wiring layer 22, and the wiring layer 22 and the wiring layer 23 are insulated in this order. The insulating layer 13 is provided between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is provided between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is provided between the wiring layer 25 and the wiring layer 26. However, the wiring layers 21 to 26 are separated from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, for example, having a thickness of 100 μm, and the insulating layer 13 only having a thickness of, for example, 300 μm. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in chip component 41 and the semiconductor element 42, and provides a space for embedding the chip component 41 and the semiconductor element 42. The insulating layers 12 and 14 are deformed so as to fill the space inside the through-hole conductor 33 of the insulating layer 13 and the insulating layer 13 for the built-in chip component 41 and the semiconductor element 42, and the inside. There is no space for voids.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer connector 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

  The structure of the component built-in wiring board according to this embodiment has been described above. Next, the configuration of the semiconductor element 42 used in this component built-in wiring board will be described in some detail with reference to FIG. FIG. 2 is a bottom view (FIG. 2 (a)) and a cross-sectional view (FIG. 2 (b)) schematically showing the semiconductor element 42 used in the component built-in wiring board shown in FIG. FIG. 2B is a cross-sectional view in the arrow direction at the position A-Aa in FIG. In FIG. 2, the same components as those shown in FIG.

  As shown in FIG. 2A, the semiconductor element 42 has surface mounting terminals 42a arranged in a grid. The arrangement pitch of the terminals 42a is, for example, 0.2 mm to 1.0 mm. In the vicinity of the center of the surface on which the terminal 42a is disposed, when the number of terminals necessary for the semiconductor element 42 is small, the terminal 42a may not be disposed.

  The semiconductor element 42 is in the form of a so-called LGA (land grid array) in which there is no solder ball on the terminal 42a as a form before being mounted because it is built in the wiring board. By adopting such a configuration without solder balls, the mounting size in the height direction is suppressed and the suitability for incorporation is further improved. If the thickness of the built-in wiring board allows, a so-called BGA (ball grid array) in which solder balls are mounted on the terminals 42a can also be used.

  In the cross-sectional direction of the semiconductor element 42, as shown in FIG. 2B, the surface mounting terminal 42a is in contact with the rewiring layer 42b on the insulating layer 42e and through the portion penetrating the insulating layer 42e. It is formed to do. Further, the redistribution layer 42b is in contact with the terminal pad 42c on the semiconductor chip on the insulating layer 42d provided between the insulating layer 42e and the semiconductor chip and through a portion penetrating the insulating layer 42d. Is formed.

  Since the terminal pads 42c are usually arranged in a line along each side of the semiconductor chip, the arrangement pitch is relatively narrow. That is, the rewiring layer 42b is provided in order to mediate conduction between the arrangement pitch and the arrangement pitch of the surface mounting terminals 42a that are arranged in a grid and have a relatively large arrangement pitch. With this configuration, the semiconductor element 42 has a surface area that is the same as that of the semiconductor chip in spite of being capable of being mounted on the surface, and is slightly thicker than the semiconductor chip itself in the thickness direction. It has become. In order to make the semiconductor element 42 thinner, the back surface of the semiconductor chip may be ground by providing a grinding step. For example, the total thickness can be about 0.3 mm or less.

  Next, an example of a manufacturing process of such a semiconductor element 42 will be described with reference to FIG. FIG. 3 is a process diagram schematically showing a manufacturing process example of the semiconductor element 42 used in the component built-in wiring board shown in FIG. In FIG. 3, the same reference numerals are given to the same components as those already shown in the drawings.

  First, as shown in FIG. 3A, a semiconductor wafer 42w having a plurality of semiconductor devices already formed on its surface is prepared. On the surface of the semiconductor wafer 42w, terminal pads 42c are formed as external connection portions of the respective semiconductor devices. The terminal pads 42c usually have an area necessary for wire bonding and are provided along the four sides of each semiconductor device with an arrangement pitch that does not hinder wire bonding. ing. This arrangement pitch is narrower than the arrangement pitch of terminals for general surface mounting.

  Next, as shown in FIG. 3B, an insulating layer 42d is formed on the entire surface of the semiconductor wafer 42w so as to cover the pad 42c. As a forming method, a known method may be used. For example, a polyimide which is an insulating material is dropped on the semiconductor wafer 42w and spin-coated, and the thickness can be formed to about 1 μm, for example.

  Next, as shown in FIG. 3C, the insulating layer 42d on the pad 42c is selectively removed by etching to form an opening 71 leading to the pad 42c in the insulating layer 42d. For selective etching, a known method such as photolithography can be applied. Instead of the method shown in FIGS. 3B and 3C, a method of selectively forming the insulating layer 42d except on the pad 42c may be used. The insulating layer 42d can be selectively formed by a well-known method.

  After the opening 71 is formed, next, as shown in FIG. 3D, a rewiring layer 42b is formed on the insulating layer 42d with a conductive material so as to fill the opening 71 and have a necessary pattern. . For the rewiring layer 42b, for example, Al, Au, Cu, or the like can be used. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. For patterning, in consideration of the material to be used, unnecessary portions are etched away after being formed on the entire surface of the insulating layer 42d, or a resist mask having a predetermined pattern is formed on the insulating layer 42d and then re-applied. This can be done by forming a layer to be the wiring layer 42b. The thickness of the rewiring layer 42b can be set to about 1 μm, for example.

  After forming the rewiring layer 42b, next, as shown in FIG. 3E, an insulating layer 42e is formed so as to cover the rewiring layer 42b, and the insulating layer 42e is selectively removed by etching. An opening 72 leading to the rewiring layer 42b is formed in 42e. The step shown in FIG. 3E can be performed in the same manner as in FIG. 3B and FIG. 3C, which are steps for forming and processing the insulating layer 42d. The same applies when a method for selectively forming the insulating layer 42e is selected.

  After the opening 72 is formed, next, as shown in FIG. 3 (f), the surface mounting terminal 42a is made of a conductive material so as to fill the opening 72 and occupy a predetermined arrangement position on the insulating layer 42e. Form. For example, Al, Au, Cu, or the like can be used as the conductive material. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. In order to form it selectively, in consideration of the material to be used, an unnecessary portion is etched away after being formed on the entire surface of the insulating layer 42e, or a resist mask having a predetermined pattern is formed on the insulating layer 42d. This can be done by forming a layer to be the surface mounting terminal 42a. The layer of the surface mounting terminal 42a can have a thickness of about 1 μm, for example.

  If the conductive material is Cu or Al, the surface mounting terminal 42a may be further processed so that its surface layer is covered with a Ni / Au plating layer or a Sn (tin) plating layer. For example, an electroless plating process can be used to perform such plating. By having a plating layer of a predetermined material, it is possible to obtain good soldering and connection reliability in surface mounting for incorporation in a wiring board.

  When the surface mounting terminals 42a are formed, finally, as shown in FIG. 3G, the semiconductor wafer 42w is diced to obtain individual semiconductor elements 42. The semiconductor element 42 obtained in this way can be subjected to a surface mounting process in the same manner as the chip component as described above by the surface mounting terminal 42a.

  In FIG. 3, the method of forming the surface mounting terminals 42a using the wafer 42w before dicing has been described. However, this shows an example in which the surface mounting terminals 42a are formed with higher productivity. On the other hand, the surface mounting terminals 42a can be formed in the same manner on the individual semiconductor chips after dicing.

  As a modification of the semiconductor element 42 in the manufacturing process shown in FIG. 3, an example in which the rewiring layer 42b and the surface mounting terminal 42a are formed as the same layer can be given. In this case, a layer of a conductive material is formed on the insulating layer 42d so as to have a pattern necessary for rewiring and to have a pattern of the surface mounting terminals 42a in contact with this pattern. This conductive material layer fills the opening 71 formed in the insulating layer 42d. Then, the conductive material layer is formed so as to cover the entire surface with the insulating layer 42e except for the portion of the surface mounting terminal 42a. This also makes it possible to obtain a semiconductor element having the surface mounting terminals 42a in which the terminal pads 42c of the semiconductor device are rearranged.

  Next, the fine structure of the connecting member 51 shown in FIG. 1 will be described with reference to FIG. FIG. 4 is an explanatory view showing a fine structure of the connecting member 51 used in the component built-in wiring board shown in FIG. As shown on the right side of FIG. 4A, the connecting member 51 has a structure in which the skeleton structure of the conductive portion 505 is formed in the cured resin portion 503A as a fine structure. In this skeleton structure, the resin portion 503A is filled in the part where it has been removed, so that no void is formed.

  More specifically, as shown in the enlarged cross-sectional view shown in FIG. 4B, the conductive portion 505 includes a particulate metal seed portion 502A and a multi-element phase 512 covering this surface, A multi-element phase 512 covering the portion 502A is connected to each other to form a skeleton structure. In the connection member 51, there are some residual solder 501A in addition to the seed portion 502A and the multi-element phase 512. The multi-element phase 512 is a multi-element phase composed of the metal in the solder particles 501 (see the left side of FIG. 4A) and the metal in the seed portion 502A. The melting point of the solder particles 501 is 240 ° C. or less. The material of the solder particles 501 and the seed part 502A (seed particle 502) is selected so that the melting point of the elemental phase 512 is 260 ° C. or higher.

  The formation process of the connection member 51 is related to the fine structure. Schematically, as shown in the left side of FIG. 4A, the connection member 51 is in a state before being cured, in which solder particles 501 and seed particles 502 are dispersed in a paste-like thermosetting resin 503. (Connection member 51A [= conductive adhesive resin] before curing).

  When such a conductive adhesive resin is heated to dissolve the solder particles 501, the component metal and the metal contained in the seed particles 502 react to change the surface of the seed particles 502 into a multi-element phase 512, Due to the dissolution of the solder particles 501, the multi-element phases 512 are connected to each other. When the multi-element phase 512 is developed, the melting point thereof is higher than that of the solder particles 501, so that the skeleton structure becomes a solid phase at the heating temperature. The unreacted part (part close to the center) of the seed particle 502 becomes a seed in the multi-element phase 512 and becomes the remaining seed part 502A. A part of the solder particles 501 remaining in the change to the multi-element phase 512 is solidified to become a residual solder 501A.

  The material is selected so that the thermosetting resin 503 is not cured at the temperature at which the solder particles 501 are dissolved. Thereby, the reaction between the dissolved metal and the seed particles 502 is performed smoothly without hindering the movement of the solder particles 501 when they are dissolved. After causing such dissolution and reaction, the thermosetting resin 503 is thermoset by raising the heating temperature. By this thermosetting, a structure in which the resin portion 503A is filled in the gaps of the skeleton structure so as to fix the formed skeleton structure is completed.

  In the connection member 51 having such a configuration, in particular, a skeleton structure formed by connecting a plurality of elemental phases 512 in the conductive portion 505 bears the conductivity, and the plurality of elemental phases 512 has the above-described conductivity. As described above, the melting point is 260 ° C. or higher. By setting the temperature to 260 ° C. or higher, melting by heating at the time of secondary mounting (for example, at most 250 ° C.) can be avoided, and poor connection or short circuit due to remelting can be prevented.

  The conductive skeleton structure is formed in the cured resin portion 503A, and the gap between the skeleton structures is filled with the conductive skeleton structure. Therefore, voids are not generated in the connecting member 51 and reliability is not impaired. Furthermore, since the conductivity of the connecting member 51 is based on a skeleton structure made of a conductor, a low-resistance connecting portion can be obtained. Although the residual solder 501A may be remelted during the secondary mounting, the amount of the residual solder 501A remains small without changing to the multi-element phase 512, and the amount is small and is confined in the resin portion 503A. The impact on reliability can be minimized.

  Incidentally, the same connection member (solder) 52 that connects the semiconductor element 42 to the land by the wiring pattern 22 may be used. However, compared with the case of the chip component 41, the necessity is relatively small. This is due to the difference in adhesion between each component and the insulating layer 12. The chip component 41 is often a ceramic material except for the portion of the terminal 41a, and the adhesiveness with the insulating layer 12 is inferior.

  On the other hand, in the semiconductor element 42 having the surface mounting terminals 42a, the resin layer (in this case, the insulating layer 42e) is disposed around the terminals 42a, and the adhesion with the insulating layer 12 is better. In the case of a ceramic material or the like having poor adhesion, the interface is easy to peel off, and if it is peeled off, remelted solder may enter during secondary mounting and lead to a short circuit failure. Therefore, at least the connection member 51 for connecting the chip component 41 such as a chip capacitor to the land is effective in improving the reliability by using the above-mentioned special material and structure.

  Next, FIG. 5 is a table showing an example of a material for obtaining the conductive portion 505 in the connection member 51 shown in FIG. 4, and FIG. 5A is included in the connection member 51A before curing. A material example of the solder particles 501, FIG. 5B, is a material example of the seed particles 502. As shown in FIG. 5A, these solder particles 501 have a melting point of 240 ° C. or lower. By using a metal material having such a melting point as the solder particles 501, even if the insulating layers 11 to 15 are organic materials, it is possible to provide an allowance for the heat resistance temperature thereof. The composition system or metal shown in FIG. 5B is selected as a composition system or metal in which a multi-element phase formed by reacting with one of the composition metals of the solder particles 501 has a melting point of 260 ° C. or higher.

  Next, FIG. 6 is a table showing an example of the material of the multi-element phase 512 constituting the connecting member 51 shown in FIG. 4, and is formed from the solder particles 501 and seed particles 502 of the material shown in FIG. The resulting multi-element phase is shown. As shown in FIG. 6, these multi-element phases 512 have a melting point of 260 ° C. or higher. With such a multi-element phase 512, melting does not occur due to heating at the time of secondary mounting (for example, at most 250 ° C.), and it is possible to effectively prevent connection failure and short-circuiting due to remelting.

  Note that the ratio of x, y (, z) in the multi-element phase shown in FIG. 6 is not only a simple integer ratio (= stoichiometric composition; intermetallic compound), but deviates from this, for example, x In some cases, y (, z) can exist as a value having a width when the value of is fixed. For example, it is an alloy (solid solution) phase or a phase in which two or more intermetallic compounds having different composition ratios are mixed crystals.

For example, Cu ₆ Sn ₅ , CuZn ₃ , Cu ₂ Sb, Ag ₃ Sn, FeSn ₂ , and AuSn ₂ are known as intermetallic compounds in the multi-element phase shown in FIG. Cu ₆ Sn ₅ may be formed in combination with Cu ₃ Sn, which is a different type of intermetallic compound having the same compositional element and different composition ratio. Depending on this mixture ratio, x and y as a whole may be formed. The ratio is no longer a simple integer ratio. Cu ₃ Sn has fragile properties as compared with Cu ₆ Sn ₅ , but the melting point is 260 ° C. or higher, and the structure of the conductive part 505 is reinforced by the resin part 503A. , Its adverse effects can be kept small.

  As described above, the component built-in wiring board according to this embodiment includes the semiconductor element 42 as one of the plural types of components and the chip component 41 as the other embedded at the same time. Here, the semiconductor element 42 has a semiconductor chip and a surface mounting terminal 42a arranged in a grid. Therefore, since the semiconductor element 42 is built in the wiring board, surface mounting technology can be applied when mounting. Therefore, surface mounting technology can be used for mounting a plurality of types of components. At this time, relatively large workpieces can be used in consideration of productivity. Accordingly, the component built-in wiring board achieves high productivity and low cost.

  In addition, since the surface mounting terminals 42a are particularly arranged in a grid, that is, in a plane arrangement, the plane area of the semiconductor element 42 can be minimized. Further, since the electrical connection between the surface mounting terminal 42a and the terminal pad 42c on the semiconductor chip is made by the rewiring layer 42b formed on the semiconductor chip, the thickness of the semiconductor element 42 is also different from that of the semiconductor chip itself. Not so thick compared. That is, in terms of the area and thickness of the semiconductor element 42, the ease of incorporation similar to that of the semiconductor chip is ensured. On the other hand, it does not require a highly accurate alignment process as required for flip chip connection when a semiconductor chip is incorporated. Therefore, this also contributes to improvement of productivity and cost reduction.

  The semiconductor element 42 to be embedded or buried is not a wafer level chip scale package as described above, but another package product (for example, an interpose substrate is provided between the semiconductor chip and the surface mounting element 42a). Form). In this case, the area and thickness of the element are inevitably larger than those of the wafer level / chip scale package, but this can be dealt with depending on the specifications of the board side used for component incorporation. Also in this case, the advantage that the surface mounting technology can be applied to the semiconductor element 42 is maintained.

  In this component built-in wiring board, the connecting member 51 for connecting the built-in chip component 41 to the wiring layer 22 has a cured resin portion 503A and a residual resin having a melting point of 240 ° C. or less contained in the resin portion 503A. It has solder 501A and further has the following conductive portion 505. That is, the conductive portion 505 includes a multi-element phase 512 having a melting point of 260 ° C. or higher, which is formed by reacting a metal that is one of the constituent metals of the residual solder 501A with another metal (metal of the seed portion 502A). The other metal particles (seed part 502A) whose surface is covered with the elemental phase 512 are contained. Further, the conductive portion 505 has a conductive skeleton structure in which a plurality of elemental phases 512 are connected in the resin portion 503A.

  In the connection member 51 having such a configuration, in particular, the skeleton structure formed by connecting the multiple element phases 512 in the conductive portion 505 bears the conductivity, and the multiple element phases 512 are: The melting point is selected to be 260 ° C or higher. By selecting it as 260 ° C. or higher, melting during heating at the time of secondary mounting (for example, at most 250 ° C.) can be avoided, and poor connection and short circuit due to remelting can be prevented.

  The conductive skeleton structure is formed in the cured resin portion 503A, and the gap between the skeleton structures is filled with the resin portion 503A. Therefore, voids are not generated in the connecting member 51 and reliability is not impaired. Further, unlike the conductive composition such as silver paste, the connecting member 51 does not cause corrosion due to the battery effect even when the surface layer of the terminal 41a is a tin layer. As described above, the reliability as the component built-in wiring board is maintained. Furthermore, since the conductivity of the connecting member 51 is based on a skeleton structure made of a conductor, a low-resistance connecting portion can be obtained.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 7 to 9 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 7 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 7A, a paste-like conductive composition to be the interlayer connection body 31 is formed in a substantially conical shape by, for example, screen printing on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 7B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31 so that the head is exposed. To do. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 has an axis that coincides with the stacking direction, and the diameter changes in the axial direction). Subsequently, as shown in FIG. 7C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 7D, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into a wiring pattern 22 including mounting lands. And as shown in FIG.7 (e), the connection member 51A and the cream solder 52A before hardening are applied on the mounting land obtained by the process. The connection member 51A before curing can be applied on the land using, for example, screen printing. Screen printing can be easily and efficiently printed in a predetermined pattern. After this screen printing, cream solder 52A is applied on the land using, for example, a dispenser. The connection member 51A before curing can also be applied by a dispenser instead of screen printing.

  The cream solder 52A may be replaced with a conductive composition (for example, silver paste) before curing. When the conductive composition is used, heat resistance after curing is high, and it is possible to effectively prevent poor connection due to heat applied during component mounting as a wiring board after completion. It should be noted that it is relatively easy to select a semiconductor element 42 having no tin plating layer on the surface of the surface mounting terminal 42a, thereby avoiding corrosion due to the battery effect even if silver paste is used. it can.

  Subsequently, the chip component 41 and the semiconductor element 42 are mounted on the mounting land, for example, by a mounter through the connection member 51A or the cream solder 52A before being cured.

  As the connection member 51A before curing, here, for example, Sn which is a solder particle 501 (see FIG. 4) in a thermosetting resin 503 (see FIG. 4) which is, for example, an epoxy-modified polyimide resin having a curing temperature of 240 ° C. Particles having a composition of -3Ag-0.5Cu (melting point: 217 ° C.) and Cu particles as seed particles 502 (see FIG. 4) are used. As the composition ratio, for example, Cu is 30 wt% with respect to the entire Sn-3Ag-0.5Cu, and Cu and Sn-3Ag-0.5Cu are 75 wt% with respect to the entire thermosetting resin 503. can do. The solder particles 501 having a composition of Sn-3Ag-0.5Cu can have a particle size of, for example, 10 μm to 20 μm, and the Cu seed particles 502 can have a particle size of, for example, 3 μm to 40 μm.

  The connection member 51A before curing can contain a flux component having a property of activating the solder particles 501 when the solder particles 501 are heated and dissolved. According to such a connecting member 51A, it is not necessary to separately perform a step of applying a flux, which is preferable in improving productivity.

  After the chip component 41 and the semiconductor element 42 are placed on the mounting land via the connection member 51A or the cream solder 52A, heating is performed to melt the solder particles 501 dispersed in the connection member 51A (for example, 225). ℃). In this heating, the multi-element phase 512 (see FIG. 4) is generated by the reaction between the metal included in the solder particles 501 and the metal included in the seed particles 502 without curing the thermosetting resin 503 in the connection member 51A. Let Since the thermosetting resin 503 is not cured during this reaction, the movement of the metal in the resin 503 is not hindered and the reaction proceeds smoothly. The multi-element phase 512 appears as a solid phase at a temperature of about 225 ° C. The solid phases are connected to each other to form a skeleton structure.

  For example, the cream solder 52A may have a configuration in which Sn-3Ag-0.5Cu solder particles similar to the solder particles 501 are dispersed in the flux. According to this, it can be made to reflow by the above-mentioned heating of 225 degreeC, for example.

  Following the heating for generating the multi-element phase 512, the heating temperature is then slightly increased (for example, 250 ° C.), and the thermosetting resin 503 is thermoset. As a result, a cured resin portion 503A (see FIG. 4) is formed so as to fill the gaps of the conductive portion 505 (see FIG. 4) with the skeleton structure, and as a result, the connection member 51 is formed (FIG. 7 (f) )

  The temperature profile in the two-step heating process described above can be set as shown in FIG. 10, for example. FIG. 10 is a graph showing an example of a temperature profile in the mounting process shown in FIG. As shown in FIG. 10, when the temperature is gradually increased to reach about 225 ° C., this temperature is once maintained for several tens of seconds. Thereafter, the temperature is raised to 250 ° C. and this temperature state is maintained for several tens of seconds. Thus, the point which needs temperature maintenance of two steps is a different point from the reflow process of the general cream solder which has only the heating process which fuses a solder particle.

  As described above, as shown in FIG. 7F, the wiring board material 1 in a state in which the chip component 41 and the semiconductor element 42 are connected to the mounting land of the wiring layer 22 through the connecting members 51 and 52 is obtained. . The subsequent process using the wiring board material 1 will be described with reference to FIG.

  Next, a description will be given with reference to FIG. FIG. 8 shows a manufacturing process of a portion centering on the insulating layer 13 and the same 12 in each configuration shown in FIG. First, as shown in FIG. 8A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 83 for forming a through-hole conductor is formed at a predetermined position, and component openings 81 and 82 are formed in portions corresponding to the chip component 41 and the semiconductor element 42 incorporated therein.

  Next, electroless plating and electrolytic plating are performed to form a through-hole conductor 33 on the inner wall of the through-hole 83 as shown in FIG. At this time, a conductor is also formed on the inner walls of the openings 81 and 82. Further, as shown in FIG. 8C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner walls of the openings 81 and 82 is also removed.

  Next, as shown in FIG. 8 (d), conductive bumps (bottom diameter: 200 μm, height: 160 μm, for example) that become interlayer connectors 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 8E, FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press machine. In the prepreg 12 </ b> A, openings similar to the insulating layer 13 are provided in advance corresponding to the built-in chip component 41 and the semiconductor element 42.

  In the stacking step of FIG. 8 (e), the head of the interlayer connector 32 is made to penetrate the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 8 (e) indicates that there are both cases where the head part is plastically deformed and crushed at this stage, and where it is not plastically deformed. The wiring board material obtained as described above is referred to as a wiring board material 2.

  The steps shown in FIG. 8 can be performed as follows. In the stage of FIG. 8A, only the through hole 83 is formed, and the subsequent steps from FIG. 8B to FIG. 8D are performed without forming the openings 81 and 82 for the built-in components. Next, as a step corresponding to FIG. 8E, prepreg 12A (without opening) is stacked. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 9 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked. Here, the upper wiring board material 3 shown in the figure applies the same process as that of the lower wiring board material 1, and thereafter, the interlayer connector 34 and the prepreg 14A are connected to the interlayer connector in the intermediate wiring board material 2 shown in the figure. 32 and the prepreg 12A.

  However, the wiring board material 3 is configured without a component (chip component 41 and semiconductor element 42) and a portion (mounting land) for connecting the component, and the prepreg 14A has an opening for the chip component 41, An opening for the semiconductor element 42 is not provided. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12A and 14A obtained by heating, the prepregs 12A and 14A are deformed into the space around the chip component 41 and the semiconductor element 42 and the space inside the through-hole conductor 33, and no gap is generated. . The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively.

  In this pressing process, in order to relieve the pressing force applied to the semiconductor element 42 and suppress the occurrence of defects such as breakage, the height of the semiconductor element 42 is slightly lower than the height of the chip component 41. It is preferable. This is because in many applications, the number of the semiconductor elements 42 is small (for example, one), and the chip components 41 are often arranged so as to surround them. The chip component 41 disposed in such a manner bears more pressing force and the pressing force applied to the semiconductor element 42 becomes smaller.

  After the lamination step shown in FIG. 9, the metal foils 26A and 21A on the upper and lower surfaces are patterned by using well-known photolithography, and further layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained.

  As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 can naturally have a configuration similar to the interlayer connector 31 or 32. Further, for the interlayer connectors 31, 32, 34, and 35, in addition to those derived from the conductive bumps printed by the conductive composition described above, for example, metal bumps formed by metal plate etching, conductive composition filling It is also possible to appropriately select and employ a connection body obtained from the above, a conductor bump formed by plating, or the like. In addition, the outer wiring layers 21 and 26 are formed at the stage of each wiring board material 1 and 3 (for example, at the stage of FIG. 7D) other than patterning after the last lamination step. May be.

  In the laminating process shown in FIG. 9, for the wiring board materials 1 and 2, the prepreg 12 </ b> A and the interlayer connector 32 are provided not on the wiring board material 2 side but on the wiring board material 1 side. May be. That is, the formation of the interlayer connector 32 and the lamination of the prepreg 12A are performed in advance on the wiring layer 22 (on the insulating layer 11) of the wiring board material 1. In this case, the mounted chip component 41 and the semiconductor element 42 seem to be an interference factor when the interlayer connection body 32 is formed by screen printing at first glance, but the chip component 41 and the semiconductor element 42 are sufficiently thin components. The case is not actually an interference factor. In the step of laminating the prepreg 12A, the prepreg 12A can be uniformly laminated in the in-plane direction by pressing and heating with a cushioning material that can absorb the thickness of the chip component 41 and the semiconductor element 42 interposed therebetween.

  Heretofore, the component built-in wiring board according to the present embodiment has been described. In the manufacturing process described above, the connecting member 51A has a composition of Sn-3Ag-0.5Cu (melting point: 217 ° C.) as the solder particles 501 in a thermosetting resin 503 as an epoxy-modified polyimide resin having a curing temperature of 240 ° C., for example. Particles and seed particles 502 in which Cu particles were dispersed were used. Here, in order to make the setting of the temperature profile in the mounting process of the component 41 more rough (non-high accuracy), the connecting member 51A is set so that the melting point of the solder particles 501 and the curing temperature of the thermosetting resin 503 are further separated. The following materials can be used as the material.

  That is, as the solder particles 501 of the connecting member 51A, the first alloy particles including Sn and one or more selected from the group consisting of Ag, Bi, Cu, In, and Zn, Sn, and Ag , Bi, Cu, In, and Zn, and a second alloy particle including at least one selected from the group consisting of Zn is used. The seed particles 502 are alloy particles containing Cu and one or more selected from the group consisting of Ag, Bi, In, and Sn. As the thermosetting resin 503, an epoxy-modified polyimide resin having a curing temperature of 240 ° C., which is the same as the manufacturing process described above, is used. The above three types of alloys have a content of 80 wt% with respect to the entire thermosetting resin 503.

  When the melting point observation by DSC (differential scanning calorimetry) is performed on the above mixture of alloy particles and thermosetting resin, there are a plurality of melting points between 100 ° C. and 200 ° C., and 300 ° C. to 500 ° C. It can be seen that there are a plurality of melting points also between ° C. Therefore, when this alloy particle-dispersed thermosetting resin is used, generally called soldering is possible due to the melting point existing between 100 ° C. and 200 ° C.

  Further, when the solidification composition formed after melting at the melting point existing at 100 ° C. to 200 ° C. is similarly observed by DSC, the melting point existing between 100 ° C. and 200 ° C. is almost lost. It can be seen that the melting point remains only at 300 ° C. or higher (changed to a multi-element phase having a high melting point). Because of this property, the composition hardly melts during heating in the secondary mounting (for example, 250 ° C.). Therefore, the thermosetting resin in which the alloy particles are dispersed is the connecting member 51A shown in FIG. It can be used in the same way. Here, since the melting point of the first and second alloy particles and the curing temperature of the thermosetting resin 503 are farther from the case of the description in FIG. 7, the setting of the temperature profile in the mounting process of the component 41 is more. Rough.

  Next, in order to lower the temperature of the mounting process of the component 41, the material of the connecting member 51 </ b> A so as to lower the melting point of the solder particles 501 and also lower the curing temperature of the thermosetting resin 503. The following can be adopted.

  That is, as the connecting member 51A, the solder particles 501 are Sn-58Bi (melting point 138 ° C.) particles, the seed particles 502 are Sn plated Cu particles and Ni particles, and the thermosetting resin 503 has a curing temperature of 180. A metal particle-dispersed thermosetting resin such as an epoxy resin at 0 ° C. is used. According to this, the first stage heating can be performed at 150 ° C., for example, and then the second stage heating can be performed at 185 ° C., for example.

  After mounting the components 41 and 42 by actually carrying out such heating, a reliability test was performed by performing heating at 260 ° C. three times assuming secondary mounting, and there was no problem due to remelting. I understood. When the connection member 51 in this case was observed, it was found that a CuSn alloy (melting point: about 630 ° C.) and a NiBi alloy (melting point: about 469 ° C.) were generated.

  DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material, 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 14 ... Insulating layer, 14A ... Prepreg, DESCRIPTION OF SYMBOLS 15 ... Insulating layer, 21 ... Wiring layer (wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (wiring pattern), 22A ... Metal foil (copper foil), 23 ... Wiring layer (wiring pattern), 23A ... Metal foil (copper foil), 24 ... Wiring layer (wiring pattern), 24A ... Metal foil (copper foil), 25 ... Wiring layer (wiring pattern), 26 ... Wiring layer (wiring pattern), 26A ... Metal foil ( (Copper foil), 31, 32, 34, 35 ... interlayer connection (conductive bump by conductive composition printing), 33 ... through-hole conductor, 41 ... chip component (electric / electronic component), 41a ... terminal, 42 ... Semiconductor elements (wafer level chip) 42a ... terminal for surface mounting, 42b ... redistribution layer, 42c ... terminal pad, 42d, 42e ... insulating layer, 42w ... semiconductor wafer, 51 ... connecting member, 52 ... connecting member (solder or conductive composition) ), 51A ... Connection member before curing, 52A ... Cream solder or conductive composition before curing, 61, 62 ... Solder resist, 71, 72 ... Opening, 81, 82 ... Opening for parts, 83 ... Through hole 501 ... Solder particles, 501A ... Residual solder, 502 ... Seed particles, 502A ... Seed part, 503 ... Thermosetting resin, 503A ... Resin part (thermosetting resin after curing), 505 ... Conductive part, 512 ... Multiple elements Family phase.

Claims (13)

A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
A semiconductor element comprising a semiconductor chip embedded in the second insulating layer and having a terminal pad; and a grid-arranged surface mounting terminal electrically connected to the terminal pad;
A kind of electric / electronic component selected from the group consisting of a chip capacitor, a chip resistor, and a chip inductor, further embedded in the second insulating layer;
Including a first mounting land for the semiconductor element and a second mounting land for the electric / electronic component provided between the first insulating layer and the second insulating layer. A wiring pattern;
A first connecting member for electrically connecting the surface mounting terminal of the semiconductor element and the first mounting land;
A second connecting member for electrically connecting the terminal of the electric / electronic component and the second mounting land;
Of the first connecting member and the second connecting member, at least the second connecting member is a cured resin part, a metal having a melting point of 240 ° C. or less contained in the resin part, and the metal The first metal which is one of the compositional metals of the first metal having the property of having a melting point of 260 ° C. or higher by changing to a multi-element phase containing a second metal different from the first metal. A conductive portion containing particles of the second metal whose surface is covered with a multi-element phase and in which the multi-element phase is connected in the resin portion to form a conductive skeleton structure. Component built-in wiring board.   2. The component built-in according to claim 1, wherein the second connecting member includes a thermosetting resin having a thermosetting temperature higher than the melting point of the metal of the second connecting member as the resin portion. Wiring board.   2. The component built-in wiring board according to claim 1, wherein the first connecting member is a solder mainly composed of tin.   The component built-in wiring board according to claim 1, wherein the first connecting member is a conductive composition.   2. The component built-in wiring board according to claim 1, wherein the electrical connection between the surface mounting terminal and the terminal pad in the semiconductor element is made by a rewiring layer formed on the semiconductor chip. .   The component built-in wiring board according to claim 1, wherein the surface mounting terminal of the semiconductor element is an LGA terminal.   The component built-in wiring board according to claim 1, wherein the surface mounting terminal of the semiconductor element has a Ni / Au plating layer as a surface layer.   The component built-in wiring board according to claim 1, wherein the surface mounting terminal of the semiconductor element has a tin plating layer as a surface layer.   The component built-in wiring board according to claim 1, wherein the surface mounting terminal of the semiconductor element is Cu as a surface layer.   2. The component built-in wiring board according to claim 1, wherein the resin portion of the second connection member is an epoxy-modified polyimide resin as a material thereof. The metal having a melting point of 240 ° C. or lower is Sn—In composition system, Sn—Bi composition system, Sn—Zn—Bi composition system, Sn—Ag—In composition system, Sn—Ag—Cu composition system, Sn—Ag. A composition system, a Sn—Cu composition system, and a Sn—Sb composition system, and one composition system or metal selected from the group consisting of Sn,
The second metal is composed of Ag, Au, Cu, Ni, and Fe, and a Cu—Ni composition system, a Cu—Sn composition system, an Ag—Sn composition system, a Cu—Zn composition system, and a Co—Sb composition system. The component built-in wiring board according to claim 1, wherein the wiring board is one or more metals selected from the group or a composition system. The multi-element system phase of the conductive portion of the second connection _{member, Cu x Sn y, Co x} Sn y, Cu x Zn y, Cu x Sb y, Co x Sb y, Ni x Bi y, Ag x _{Sn y, Fe x Sn y,} Ag x Cu y Sn z, and _Au x Sn component built-in wiring board according to claim 1, wherein a from the group consisting of _y is a phase by one or more selected. A first alloy containing Sn and one or more selected from the group consisting of Ag, Bi, Cu, In, and Zn, Sn, Ag, Bi; And a second alloy containing one or more selected from the group consisting of Cu, In, and Zn,
The component built-in wiring board according to claim 1, wherein the second metal is an alloy containing Cu and at least one selected from the group consisting of Ag, Bi, In, and Sn.

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