JP2010074027A - Fet switch - Google Patents

Abstract

The present invention provides an FET switch capable of widening the bandwidth and reducing the size and cost as a 1-input multi-output switch and a multi-input 1-output switch.
As an SPnT switch for performing switching control between a first terminal and n (n: positive integer, n = 4 in FIG. 1) second terminals, wiring connected to the first terminal 21 ₀ to wiring ₂₁ 1 to 21 ₄ which has n branches at a branch point a, respectively, to connect the source or drain of the n FET 4 ₁ to 4 _4, the drain or source of the n FET 4 ₁ to 4 ₄ , respectively, with connecting the second terminal through the wiring ₂₂ 1-22 _4, at least, the wiring ₂₁ 1 to 21 _4, respectively, to form a straight line, and equal respective lengths.
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor (FET) switch, and more particularly to a high frequency FET switch suitable for wireless communication, broadband data transmission, and the like. It mainly relates to a 1-input multi-output switch and a multi-input 1-output switch that switch signal paths by turning on / off FETs.

  In recent years, a plurality of types of wireless communication systems such as mobile phones and wireless LANs have been put into practical use and have been used by many users. Therefore, each user does not have a plurality of different wireless terminals for each of these individual methods, but a single wireless terminal can support a plurality of types of wireless communication methods, so-called multimode / multiband terminals. Realization is strongly demanded. A multimode / multiband terminal basically includes a plurality of antennas corresponding to each wireless communication system (each radio frequency band), and is configured to switch antennas for transmitting and receiving wireless signals using a switch. Therefore, in order to realize these multimode / multiband terminals, it is essential to increase the number of ports of the switch.

  Conventionally, as a switch element for a wireless terminal, an FET switch that consumes almost no power, is small, and can be easily monolithically integrated has been widely used. To configure a single-pole n-throw (SPnT: single-pole n-throw) switch of 1 input and n output (or n input and 1 output, n: positive integer) using these FET switches, It is necessary to arrange single-pole single-throw (SPST) switches with 1 input and 1 output in parallel.

  However, in the configuration in which n SPST switches are arranged in parallel as unit switches, for example, as the number of ports n increases, the wiring length from the branch point where one input branches to n to each SPST switch becomes longer. The problem of being forced to occur arises.

The SPnT switch is controlled so that any one of the n SPST switches is turned on and the remaining (n-1) SPST switches are turned off. Therefore, for example, in a Single-Pole 8-Throw (SP8T: single pole 8 throw) switch, control as shown in FIG. 14 is performed. FIG. 14 is a circuit diagram showing a connection configuration of a conventional SP8T switch. A wiring from one common terminal is branched into eight at a branch point A, and eight SPST switches 9 are connected via eight wirings. It is connected to the _{1-9 8.} As shown in FIG. 14, in the SP8T switch, for example, a SPST switch _{9 1} to ON, is controlled so that the remaining seven SPST switch ₉ 2-9 ₈ turned OFF. As a result, 7 wires to SPST switch ₉ 2-9 ₈ in the OFF state as viewed from the branch point A point operates as an open stub. For this reason, the reflection loss of the switch is deteriorated, which causes a reduction in the operating band.

  FIG. 15 is a characteristic diagram showing the simulation result of the signal characteristics in the SP8T switch of FIG. 14, and shows the simulation result of the reflection loss when the electrical length of the wiring connected from the input branch point A to each SPST switch is used as a parameter. Show.

In the simulation of FIG. 15, it is assumed that the switch is opened and closed under ideal conditions (conditions that are short when ON and open when OFF), but the electrical length of the wiring from the branch point A to the SPST switch increases. The reflection loss deteriorates, and when the frequency f is set to a desired reference frequency f ₀ , it is necessary to reduce the effective electrical length to 5 degrees or less in order to secure the reflection loss to −10 dB or less. I understand that there is. In an actual switch, the deterioration becomes more remarkable due to the influence of the OFF capacitance of the FET.

  For wiring on a semiconductor substrate such as GaAs, the effective electrical length of the wiring to the SPST switch is about 180 μm at a frequency of 10 GHz and about 45 μm at 40 GHz, so an FET having a finite physical size is used. It is very difficult to realize a multi-port wideband switch using a plurality. In particular, when a compound semiconductor FET such as GaAs that is effective for wide band operation of the switch is used, the processing direction of the gate is limited, so that it becomes more difficult to arrange the wiring length to be equal and shorter. This is because, for example, a gate orientation capable of forming a high-performance FET on a GaAs wafer having a crystal plane orientation of [100] plane is in an orientation such as [011] that is horizontal with respect to an orientation flat. This is due to the fact that the gate orientation capable of forming FETs having the same characteristics is limited to [010] and [001] of 45 ° with respect to the orientation flat.

  As a conventional technique that can alleviate the problems as described above, there is a configuration example of an SP8T switch described in Non-Patent Document 1 below as shown in FIG. FIG. 16 is a circuit diagram showing a different configuration of the conventional SP8T switch from FIG.

In the configuration of the SP8T switch of FIG. 16, the first-stage SPST switches 10 ₁ , 10 ₂ , the second-stage SPST switches 10 ₁₁ , 10 ₁₂ , 10 ₂₁ , 10 ₂₂ , the third-stage SPST switch 10 ₁₁₁ , 10 ₁₁₂ , 10 ₁₂₁ , 10 ₁₂₂ , 10 ₂₁₁ , 10 ₂₁₂ , 10 ₂₂₁ , 10 ₂₂₂ , etc. A plurality of SPST switches are hierarchically connected to the first stage, the second stage, and the third stage. The so-called tournament-type multi-stage configuration. Since the open stub length can be shortened by using a multi-stage configuration as described above, it is possible to expect a wide band operation of the switch.

  However, on the other hand, the tournament type switch configuration as shown in FIG. 16 causes problems such as an increase in the size of the switch due to the multi-stage configuration, an increase in the number of control terminals, and an increase in insertion loss. The increase in the size of the switch not only increases the manufacturing cost due to the increase in the area occupied by the integrated circuit, but also reduces the size and the size of the multi-terminal switch matrix formed by using a plurality of SPnT switches such as SP8T switches. It also becomes a factor that hinders costing.

On the other hand, in the connection configuration of the SP8T switch of FIG. 14, the increase in the number of ports while keeping the connection wiring length short is limited by the physical size of the FET as described above. It is very difficult to realize a multi-port switch that can achieve both low loss characteristics.
MANFRED J. SCHINDLER, MEMBER, IEEE, MARY ELLEN MILLER, AND KEITH M. SIMON, “DC-20 GHz N × M Passive Switches”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL.36, N0.12, DECEMBER 1988, pp. 1604-1613

  As described above, in the conventional FET switch, as the number of ports of the switch increases, it becomes difficult to operate the broadband of the switch, and it becomes difficult to reduce the size and cost of the circuit. there were.

  The present invention has been made in view of such a problem. By realizing a wide band of SPnT (single-pole n-throw, n: positive integer) switch, downsizing and cost reduction, and using the SPnT switch, An object of the present invention is to provide an FET switch capable of realizing a wide band as a multi-port switch and a reduction in size and cost.

  The present invention comprises the following technical means in order to solve the above-mentioned problems.

  The first technical means includes one first terminal, n (n: positive integer) second terminals, n first FETs, and one first wiring on the substrate. And an n second wiring and an n third wiring, wherein one end of the first wiring is connected to the first terminal and the other end. Is connected to one end of the n second wirings connected to each other, and the other end of the n second wirings is connected to the source or drain of each of the n first FETs. The drains or sources of the n first FETs are respectively connected to one end of the n third wirings, and the other ends of the n third wirings are respectively n. The n second wirings connected to the second terminals of the first and second terminals are each formed in a straight line and have the same length. The features.

  According to a second technical means, in the FET switch according to the first technical means, the effective electrical lengths of the n second wirings are each 5 degrees or less at a predetermined desired operating frequency. It is characterized by that.

  According to a third technical means, in the FET switch according to the first or second technical means, each of the n number of first FETs has one gate finger.

  According to a fourth technical means, in the FET switch according to any one of the first to third technical means, the gate widths of the n first FETs are respectively the n second wirings. It is characterized by being less than the length.

  A fifth technical means includes the n first resistors respectively connected to the gates of the n first FETs in the FET switch according to any one of the first to fourth technical means. The n first resistors are arranged in the vicinity of the first FET to which they are connected or between the first FET and the adjacent first FET. And

  According to a sixth technical means, the FET switch according to any one of the first to fifth technical means further includes n second FETs, and the source or drain of the n second FETs. Is grounded, and the drains or sources of the n second FETs are directly joined to the drains or sources of the n first FETs, respectively.

  A seventh technical means is the FET switch according to the sixth technical means, further comprising n fourth wirings, wherein the drains or sources of the n second FETs are n pieces of the above-mentioned Instead of being directly joined to the drain or source of the first FET, they are respectively connected through the n fourth wirings.

  According to an eighth technical means, in the FET switch according to the seventh technical means, the n fourth wirings are each formed in a straight line, and the lengths thereof are equal to each other. .

  A ninth technical means comprises the second n resistors respectively connected to the gates of the n second FETs in the FET switch according to any one of the sixth to eighth technical means. The n second resistors are arranged in the vicinity of the second FET to which the n second resistors are connected, or between the second FET and the adjacent first FET or the second FET. It is characterized by being made.

  According to a tenth technical means, in the FET switch according to any one of the first to ninth technical means, n gate orientations of the first FET or n first FETs and n The gate orientations of the individual second FETs are parallel to each other or have a 90 ° positional relationship.

  The eleventh technical means is the FET switch according to any one of the first to tenth technical means, wherein n number of the first FETs or n number of the first FETs and n number of the second FETs. FET and at least n second wirings, and each of the first and second components excluding the first terminal and the first wiring is provided as two sets, the first set and the first set. The constituent elements belonging to each of the set and the second set are arranged at symmetrical positions on the substrate.

  A twelfth technical means is the FET switch according to any one of the first to eleventh technical means, wherein the substrate in a region where the n number of the second wirings are present has one or more dielectric layers. The layers are stacked, and in the region, the second wiring and the ground conductor are formed on any one of the layers including the substrate and the dielectric layer, which are different from each other. To do.

  A thirteenth technical means is the FET switch according to any one of the first to twelfth technical means, wherein the substrate in a region where the first wiring and the n second wirings exist is provided on the substrate. In order, one or more dielectric layers, a ground conductor, and one or more dielectric layers are stacked, and in the region, the first conductor and the n second wirings form the ground conductor. The other end of the first wiring and the other end of the second wiring connected to each other are formed on the substrate and the different layers of the layers including the dielectric layer. Are connected through a first through hole.

  A fourteenth technical means is the FET switch according to the twelfth or thirteenth technical means, wherein the other end of the n second wirings and the source or drain of the n first FETs are connected. , And connected directly or through a second through hole.

  A fifteenth technical means is the FET switch according to any one of the first to fourteenth technical means, wherein the substrate in a region where the n third wirings are present has one or more dielectric layers. Layers and / or ground conductors are stacked, and in this region, one end of the n third wirings and the drain or source of the n first FETs are directly or via a third through hole. It is characterized by being connected.

  Sixteenth technical means is the FET switch according to any one of the thirteenth to fifteenth technical means, wherein the first through hole and / or the second through hole and / or the third through hole. Are installed through the ground conductors that are sequentially stacked, the first through hole and / or the second through hole and / or the third through hole may be provided in a partial region of the ground conductor. Is provided with a gap through which it passes without contacting the ground conductor.

  According to a seventeenth technical means, in the FET switch according to any one of the first to sixteenth technical means, an arrangement region of the first FET, the first FET, or the second FET, and the first FET A layer on which a ground conductor is laminated in a region other than the wiring wiring region, and further including one or more dielectric layers on the ground conductor and / or below the ground conductor, The wiring and the third wiring are arranged on the substrate or on a layer different from the layer on which the ground conductor is laminated.

  According to an eighteenth technical means, in the FET switch according to any one of the first to seventeenth technical means, a characteristic impedance of a part or all of the first wiring and the second wiring is obtained. The input / output impedance of the FET switch is higher.

A nineteenth technical means comprises (n + 1) (n: positive integer) FET switches according to any one of the first to eighteenth technical means, and the second of the (n + 1) FET switches. The number of terminals is n, n ₁ , n ₂ , n ₃ ,..., N _n (n, n ₁ , n ₂ , n ₃ ,..., N _n : all of the same positive integer or respectively Are the same positive integers or different positive integers), and among the (n + 1) FET switches, the FET switch having n second terminals is designated as the first FET. As a switch, the first terminal of the first FET switch is used as a new common first terminal, and the remaining n pieces of n terminals are respectively connected to the n second terminals of the first FET switch. Connect the first terminal of the FET switch to N-number of each _{n 1,} n ₂ of said FET _switches, n 3, ..., _{n n-number} of the second terminal, the sum _{(n 1 + n 2 + n} 3 + ... + n n) pieces of the new second with the _terminal, characterized in that configured as _{SP (n 1 + n 2 +} n 3 + ... + n n) T switch.

  According to the FET switch of the present invention, each SPST switch (single pole single throw) switch composed of n (n: positive integer) FETs is connected to a common connection point (that is, the end of n wirings from each SPST switch). In the SPnT switch configured by connecting the connection portions to each other), a layout configuration that can make the n wires from each SPST switch to the common connection point the shortest and the same length is realized. The following effects can be obtained.

  That is, by making the distance from each SPST switch consisting of n FETs to the common connection point the shortest and the same length, the characteristics between the ports can be made uniform, and at the time of ON / OFF operation of the switch, The influence of the open stub caused by the wiring from the common connection point to each SPST switch in the OFF state can be greatly reduced. Therefore, wide-band operation of the FET switch can be realized, and the size and cost of the multiport switch can be reduced.

  Hereinafter, an example of the best embodiment of the FET switch according to the present invention will be described in detail with reference to the drawings.

[Features of the present invention]
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be briefly described first. The present invention relates to an FET switch that constitutes an SPnT (n: positive integer) switch using a plurality of FETs (Field Effect Transistors) as each SPST switch, and a common connection point (that is, each SPST switch) from each SPST switch. FETs constituting each SPST switch are arranged so that the length of each of the plurality of wirings up to (connection point connecting the ends of the plurality of wirings from each other) is the shortest and the same length. Therefore, it is possible to realize a wide band of FET switches and a reduction in size and cost as a multi-port switch.

[First Embodiment]
First, the FET switch according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a layout diagram showing a pattern layout of an SP4T (Single-Pole 4-Throw) switch which is an example of an FET switch according to the first embodiment of the present invention.

As shown in SP4T switch of FIG. 1, for example on the surface of a semiconductor substrate made of GaAs or the like, by laminating a grounding conductor 1, one of the first and the wiring is wiring 21 ₀ and one of the first terminal (Not shown) and n (n: positive integer; n = 4 in the case of FIG. 1) second wirings 21 _{1 to} 21 ₄ and n for forming n SPST switches By providing FETs 4 ₁ to 4 ₄ that are first FETs, wirings 22 _{1 to} 22 _{4 that} are n third wirings, and n second terminals (not shown), As a whole, an SPnT switch (that is, an SP4T switch in the case of FIG. 1) is configured.

Here, the wirings 21 _{1 to} 21 _{4 that} are n second wirings (n = 4 in the case of FIG. 1) are wirings whose one ends are connected to each other, and one ends connected to each other are the branching points A. (That is, a common connection point where n second wirings become one), and the other end is connected to n (n = 4) first FETs FETs 4 ₁ to 4 ₄ , respectively. It is connected.

The SP4T switch shown in FIG. 1, one common terminal which constitutes the first terminal wiring 21 ₀ first are wires (not shown), at a branch point A, n present (n = 4) the second is n branches in which the wiring ₂₁ 1 to 21 ₄ wires, through the n wirings ₂₁ 1 to 21 _4, n pieces (n = 4) is a first FET of FET 4 ₁ to 4 ₄ Connected to the source (or drain) of each. Further, n-number (n = 4) FET 4 ₁ to 4 ₄ in the drain (or source) is connected to the n (n = 4) third wiring ₂₂ 1-22 ₄ are wires of, n pieces It is connected to an individual terminal (not shown) constituting the second terminal (n = 4).

Accordingly, the branch point A connected to one common terminal (not shown) as the first terminal is changed to each of n (n = 4) SPSTs including the FETs 4 ₁ to ₄ 4 as the _first FETs. When viewed as a common terminal of the switch, a single-pole 4-throw (SP4T) switch composed of four SPST switches is formed. Thus, the branch point A is n (n = 4) second wirings when viewed from the n (n = 4) SPST switches including the first FETs FETs 4 ₁ to 4 _4. It is also a common connection point where a certain number of wirings 21 _{1 to} 21 ₄ become one.

Here, FET 4 ₁ to 4 ₄ are four of the first FET are each formed of a single gate finger, and, as shown in FIG. 1, is formed in the same direction, FET 4 ₁ ~ Each of the 4 ₄ gates is arranged to be parallel to each other.

In addition, each of the wiring 21 ₀ as _{one first} wiring and the wirings 22 _{1 to} 22 _{4 as} n third wirings (n = 4) includes a ground conductor 1 with a gap and a semiconductor conductor. It is a coplanar line formed on a substrate and does not require a complicated manufacturing process such as a multilayer wiring process including wirings 21 _{1 to} 21 ₄ which are n (n = 4) second wirings. It can be realized at a relatively low cost by a wiring process in a typical semiconductor integrated circuit. The separated ground conductors 1 are connected using an air bridge or a wire (not shown) so that unnecessary modes are not excited in the coplanar line.

Resistors 5 _{1 to} 5 ₄ as n (n = 4) first resistors are connected to the gates of the FETs 4 ₁ to 4 ₄ as n (n = 4) first FETs, respectively. terminal by via respective (not shown) resistor 5 ₁ to 5 ₄ for applying a gate control voltage of each FET, the common terminal wiring 21 ₀ is connected (not shown. in other words the first terminal) And four individual terminals (not shown, that is, four second terminals) to which the wirings 22 _{1 to} 22 ₄ are respectively connected are controlled.

Further, the resistors 5 _{1 to} 5 _{4 as the first} resistors are respectively in the immediate vicinity (near the vicinity) of each connected first FET, or the first FET adjacent to each connected first FET. in between, it arranged parallel to the FET 4 ₁ to 4 ₄ the gate is the first FET, and a respective first FET FET 4 ₁ to 4 ₄ are each formed of a single gate finger Therefore, interference between control signals can be avoided without increasing the FET interval. Narrowing the FET interval makes it possible to shorten the length of the wirings 21 _{1 to} 21 ₄ that are the second wirings, and directly leads to an increase in the operating band of the switch, as will be described later.

The feature of the pattern layout of the present embodiment illustrated in FIG. 1 is that among the _{four first} FETs, FETs 4 ₁ to 4 ₄ , the FETs 4 ₁ and 4 ₄ that are located farthest from the branch point A are 1 in that it is arranged so as to shift in a direction approaching the branch point A side with respect to the lateral direction of FIG. 1 in comparison with the FETs 4 ₂ , 4 ₃ .

By adopting such a layout, from the viewpoint of manufacturing high-performance FETs, etc., even when a multi-port switch is configured using a plurality of FETs whose gate processing directions are generally limited to one direction, as straight lines equal length each second the wiring is wiring 21 ₁ to 21 _4, the length of the wiring 21 ₁ to 21 ₄ will be able to shortest and equal lengths, greatly influence the open stub In addition to being able to reduce, the passage characteristics from the branch point A to the four FETs 4 ₁ to 4 ₄ can be made uniform. Therefore, in addition to widening the bandwidth of the multi-port switch, it is possible to make the characteristics between ports uniform.

In order to make the transmission characteristics uniform between the common terminal as the first terminal and each of the n individual terminals as n terminals (n = 4 in the case of FIG. 1), the n number of the first terminals. The lengths of the wirings 22 _{1 to} 22 ₄ that are the third wirings that connect the two terminals and the FETs 4 ₁ to 4 ₄ that are the n first FETs (n = 4) are also equal to each other. It is preferable to form.

  Next, a pattern layout of an SP4T switch different from the SP4T switch of FIG. 1 will be described with reference to FIG. FIG. 2 is a layout diagram showing a pattern layout of the SP4T switch different from the case of FIG. 1 of the FET switch according to the first embodiment of the present invention.

The SP4T switch shown in FIG. 2 differs from the SP4T switch shown in FIG. 1 in that a ground conductor (not shown) is provided on the back side instead of the front side of the semiconductor substrate 7 such as GaAs. Wirings 21 ₀ , 21 _{1 to} 21 ₄ , and 22 _{1 to} 22 ₄ arranged on the surface of 7 are all microstrip lines with the back surface of the substrate 7 as the ground.

  Here, the characteristic impedance of the microstrip line is determined by the thickness of the substrate 7, the dielectric constant, the wiring width, and the like. When the substrate 7 having the ground surface on the back surface is made thinner, mutual interference between adjacent lines can be suppressed and the line width can be narrowed. Therefore, a pattern layout like the SP4T switch of FIG. 2 is adopted. As in the case of the embodiment illustrated in FIG. 1, the multiport switch can be downsized and widened.

In the case of FIG. 2 as well, as in the case of FIG. 1, each of the wirings 21 _{1 to} 21 ₄ as the n second wirings (n = 4 in the case of FIG. 2) is an equal-length straight line. The lengths of the wirings 21 _{1 to} 21 ₄ are set to the shortest and the same length, and transmission is performed between each of the common terminals as the first terminals and n (n = 4) individual terminals as the second terminals. In order to make the characteristics uniform, it is preferable that the lengths of the wirings 22 _{1 to} 22 _{4 which} are n (n = 4) third wirings are also formed to be equal to each other.

Next, a pattern layout of an SP4T switch different from the SP4T switch of FIGS. 1 and 2 will be described with reference to FIG. FIG. 3 is a layout diagram showing a pattern layout of the SP4T switch different from that in FIGS. 1 and 2 of the FET switch according to the first embodiment of the present invention. Note that FIG. 3 does not show the resistors 5 _{1 to} 5 ₄ that are the first resistors to be connected to the gates of the FETs 4 ₁ to 4 ₄ that are the first FETs.

The difference between the SP4T switch of FIG. 3 and the SP4T switch shown in FIG. 1 is that the positional relationship between the n-th (n = 4 in the case of FIG. 3) first FETs 4 ₁ to 4 ₄ is different. The wirings 21 _{1 to} 21 ₄ that are the second wirings that are n-branched at the branch point A are different from each other, and the gates of the FETs 4 ₁ to 4 ₄ that are the first FETs Each width is shorter than the length of the wirings 21 _{1 to} 21 ₄ that are the second wirings.

That is, the SP4T switch of FIG. 3 is different from the SP4T switch shown in FIG. 1 in terms of the mutual arrangement of FETs 4 ₁ to 4 ₄ which are n (n = 4 in the case of FIG. 3) first FETs. The first FET is divided into four groups, and the gate relationship of each first FET belonging to each group is sequentially rotated by 90 °.

For example, as in the case of FETs 4 ₁ to 4 ₄ in FIG. 3, when the number n of the first FETs is four, each of the groups is divided into four groups to which each first FET belongs. As a unit, the first FET has a positional relationship in which the gate orientation of the first FET sequentially rotates by 90 °. As a result, among the _{four first} FETs, FETs 4 ₁ to 4 ₄ , the gate orientations of the _first and third groups of FETs 4 ₁ and 4 ₃ , and the gates of the second and fourth groups of FETs 4 ₂ and 4 ₄ . The azimuths are parallel to each other, and the gate azimuths of the FETs 4 ₁ , 4 ₃ and the FETs 4 ₂ , 4 ₄ are in a positional relationship of 90 °.

Further, unlike the case of the SP4T switch shown in FIG. 1, lines 21 ₀ first a wiring is at a branch point A, (case of FIG. 3, n = 4) n-number of FET 4 ₁ to 4 ₄ gate The wirings 21 _{1 to} 21 ₄ , which are n (n = 4) second wirings, are n-branched in a direction that is sequentially rotated by 90 ° according to the direction, and n wirings 21 _{1 to} 21 are included. ₄ are connected to the sources (or drains) of n (n = 4) FETs 4 ₁ to 4 ₄ , respectively.

For example, if the number n of the first FET is four in FIG. 3, the wiring 21 ₀ which is the first wiring, at a branch point A, FET 4 ₁ to 4 ₄ of 4 which were sequentially rotated by 90 ° According to the gate orientation, the four second wirings 21 _{1 to} 21 ₄ are branched in a 90 ° positional relationship with each other, and the sources of the _{four first} FETs FETs 4 ₁ to 44 ( Or drain).

Note that the wirings 22 _{1 to} 22 ₄ that are the _four third wirings are also arranged in accordance with the gate orientations of the _{four first} FETs FET 4 to 44 that are sequentially rotated by 90 °. By connecting the four second terminals (not shown) in a straight line, each first FET and each second terminal are connected with the shortest length and the same length.

Further, unlike the SP4T switch shown in FIG. 1, as described above, the gate widths of n (n = 4) FETs 4 ₁ to ₄ 4 are n (n = 4), respectively. is shorter than the second length of a is the wiring ₂₁ 1 to 21 ₄ wire 4).

  Here, the arrangement of the first FET as described above is, for example, an FET having characteristics equal to the crystal plane orientations of [010] and [001] which are 45 ° with respect to the orientation flat on the GaAs wafer. This can be realized by utilizing the fact that can be formed.

With the configuration as shown in FIG. 3, the lengths of the n (n = 4) second wirings 21 _{1 to} 21 ₄ can be further shortened, so that the characteristics between the ports are uniform at a high level. The operating range of a simple switch can be further expanded.

Further, here, the wiring 21 _{0 as} the _first wiring, 21 _{1 to} 21 ₄ as the second wiring (n = 4), 21 _{3 to} 21 ₄ as the second wiring, and 22 as the third wiring (n = 4) 22. _{1-22 4} are both with the ground conductor 1 ₁ to 1 ₅ across the gap, a coplanar line formed on a semiconductor substrate, a complex manufacturing process such as the multilayer wiring process is not required, very It can be realized at a relatively low cost by a wiring process in a general semiconductor integrated circuit. The separated ground conductors 1 ₁ to ₁₅ are connected using an air bridge or a wire (not shown) so that the unnecessary mode is not excited in the coplanar line.

By adopting the configuration as shown in FIG. 3, the wirings 21 _{1 to} 21 ₄ that are n (n = 4) second wirings can be made transmission lines with good high-frequency characteristics. The operating castle can be expanded. Further, the gate widths of the n (n = 4) _first FETs 4 ₁ to _{4 4} are set to be longer than the lengths of the n (n = 4) second wirings 21 _{1 to} 21 _4. By shortening the n number (n = 4) of the FETs 4 ₁ to 4 ₄ that are the first FETs, the wirings 21 _{1 to} 21 ₄ that are the n (n = 4) second wirings. At the same time, the influence of the physical length of the FETs 4 ₁ to 4 ₄ that are the first FETs that appear to be open stubs can be greatly reduced, and the operating range of the FET switch can be further expanded.

  For example, by applying a high electron mobility transistor (HEMT) having an InGaAs channel layer with excellent electron transport characteristics for the first FET, the ON resistance can be reduced even with a short gate width. It is also possible to easily achieve both reduction in insertion loss and wideband operation.

  Next, a pattern layout of an SP6T switch different from the SP4T switch of FIGS. 1 to 3 will be described with reference to FIG. FIG. 4 is a layout diagram showing a pattern layout of a single-pole 6-throw (SP6T) switch different from the case of FIGS. 1 to 3 of the FET switch according to the first embodiment of the present invention.

SP6T switch shown in FIG. 4, as compared to the SP4T switch of FIG. 1, a first FET direction and n pieces of wires 21 ₀ a first wiring (the case of FIG. 4, n = 6) FET 4 have different _{points 1-4 6} and the gate direction are at right angles, except that it is a likely configuration achieving multi-ported, as described below, substantially the SP4T switch of FIG. 1 It has the same configuration.

The SP6T switch of FIG. 4, line 21 ₀ first a wiring from one common terminal which constitutes the first terminal (not shown), at a branch point A, n book (n = 6) The second wirings 21 _{1 to} 21 ₆ are n-branched (n = 6), and n (n = 6) first FETs FET 4 through n wirings 21 _{1 to} 21 _6. They are respectively connected to _{1-4 6} source (or drain). The drains (or sources) of n (n = 6) FETs 4 ₁ to 4 ₆ are connected to n (n = 6) third wirings 22 _{1 to} 22 ₆ , respectively, and n pieces It is connected to an individual terminal (not shown) constituting the second terminal (n = 6).

Therefore, when the branch point A is viewed as a common terminal of each of n (n = 6) SPST switches composed of the FETs 4 ₁ to 4 ₆ as the first FET, as in the case of FIG. Single-Pole 6-Throw (SP6T) switch consisting of Thus, when viewed from each of n (n = 6) SPST switches including the first FETs FETs 4 ₁ to 4 ₆ , the branch point A is n (n = 6) second wirings. there wirings ₂₁ 1 to 21 ₆ is also the common connection point becomes one.

Here, FET 4 ₁ to 4 ₆ are six of the first FET are each formed of a single gate finger, and, as shown in FIG. 4, are formed in the same direction, FET 4 ₁ ~ 4 gates of ₆ are parallel to each other.

Similarly to the case of FIG. 1, the wiring 21 ₀ that is _{one first} wiring and the wirings 22 _{1 to} 22 _{6 that} are n (n = 6) third wirings have a gap therebetween. A coplanar line formed on a semiconductor substrate together with the ground conductor 1, and a complicated manufacturing process such as a multilayer wiring process including n (n = 6) second wirings 21 _{1 to} 21 ₆ Is not necessary, and can be realized at a relatively low cost by a wiring process in a very general semiconductor integrated circuit. The separated ground conductors 1 are connected using an air bridge or a wire (not shown) so that unnecessary modes are not excited in the coplanar line.

Resistors 5 _{1 to} 5 ₆ as n (n = 6) first resistors are connected to the gates of the FETs 4 ₁ to 4 ₆ as n (n = 6) first FETs, respectively, and controlled. terminal by via respective (not shown) resistor 5 ₁ to 5 ₆ to apply a gate control voltage of each FET, the common terminal wiring 21 ₀ is connected (not shown. in other words the first terminal) And six individual terminals (not shown, that is, six second terminals) to which the wirings 22 _{1 to} 22 ₆ are respectively connected are controlled.

Also, the resistors 5 _{1 to} 5 _{6 as the first} resistors are respectively in the immediate vicinity (near the vicinity) of the respective first FETs to be connected or the respective first FETs to be connected as in the case of FIG. and between the first FET of the adjacent, arranged parallel to the gate of the FET 4 ₁ to 4 ₆ are each first FET, and, FET 4 ₁ to 4 ₆ are each first FET, respectively, Since it is composed of one gate finger, interference between control signals can be avoided without widening the FET interval. Narrowing the FET interval makes it possible to shorten the length of the wirings 21 _{1 to} 21 ₆ that are the second wirings, and directly leads to an increase in the operating band of the switch, as will be described later.

The feature of the pattern layout of the present embodiment illustrated in FIG. 4 is located farthest from the branch point A among the _{six first} FETs FETs 4 ₁ to 4 ₆ as in the case of FIG. FET 4 ₃ and _{4 4} and _is in the FET 4 _1, 4 _2, 4 5, _{4 6} compared to the terms lateral direction in FIG. 1 that is disposed so as to shift toward the branching point a point side.

By adopting such a layout, from the viewpoint of manufacturing high-performance FETs, etc., even when a multi-port switch is configured using a plurality of FETs whose gate processing directions are generally limited to one direction, each as straight lines equal length of the second wiring 21 ₁ to 21 ₆ is a wiring, the length of the wiring 21 ₁ to 21 ₆ will be able to shortest and equal lengths, greatly influence the open stub In addition to being able to reduce, the passage characteristics from the branch point A to the six FETs 4 ₁ to 4 ₆ can be made uniform. Therefore, in addition to widening the bandwidth of the multi-port switch, it is possible to make the characteristics between ports uniform.

In order to make uniform transmission characteristics between the common terminal that is the first terminal and each of the n individual terminals that are n (in the case of FIG. 4, n = 6), The lengths of the wirings 22 _{1 to} 22 _6, which are the third wirings connecting the two terminals and the n (n = 6) first FETs FETs 4 ₁ to 4 ₆ , are also equal to each other. It is preferable to form.

In the FET switch illustrated in FIGS. 1 to 4, the wiring 21 ₀ that is the first wiring, the wirings 21 _{1 to} 21 ₄ that are the second wiring, or the wirings 21 _{1 to} 21 ₆ are used as signal lines. The characteristic impedance of the coplanar line or microstrip line is preferably less than the input / output impedance of the FET switch for some or all of the wiring by narrowing the wiring width or widening the gap with the ground. It is desirable to set a higher value. By using a wiring having a characteristic impedance like this, the influence of an open stub can be further offset and reflection loss can be improved.

Further, as shown in the characteristic diagram of FIG. 15, in order to secure the return loss below -10 dB, the effective electrical length of the wires ₂₁ 1 to 21 ₄ which is a second wiring of the n (n = 4) the It is desirable to set it to 5 degrees or less at a predetermined desired operating frequency.

In addition, regarding the arrangement of each component of the FET switch illustrated in FIGS. 1 to 4, as shown in each figure, one first terminal (not shown) and one first wiring are used. except for certain wiring 21 _0, n pieces of (n = 4 or n = 6) is a first FET of FET 4 ₁ to 4 ₄ or FET 4 ₁ to 4 _6, n present (n = 4 or n = 6) Each component including at least the wires 21 _{1 to} 21 ₄ or the wires 21 _{1 to} 21 ₆ as the second wires is divided into two groups as a first set and a second set, and each component belonging to each set is They are arranged at symmetrical positions on the substrate, for example, symmetrical positions on the upper and lower sides or right and left sides of the substrate.

  In the circuit configurations as shown in FIGS. 1 to 4, since the signal line is not connected to the ground, the input signal level can be output almost as it is. Therefore, it can be used as a high-speed data transmission switch that uses a wideband baseband signal independent of the signal DC logic level, in addition to a wireless communication application using an RF (Radio Frequency) band signal.

  The FET switch having the circuit configuration shown in FIGS. 1 to 4 is not limited to the SP4T switch or the SP6T switch, and can be applied to an SPkT switch (k: positive integer) having an arbitrary number of ports.

[Second Embodiment]
Next, an FET switch according to the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a layout diagram showing a pattern layout of an SP4T switch which is an example of an FET switch according to the second embodiment of the present invention. That is, FIG. 5 shows an example of a pattern rayant related to a series shunt-structured FET switch unlike the pattern layout of the SP4T switch of FIG. 1, and the SP4T illustrated in FIG. 1 as the first embodiment. The 1st modification of the pattern layout of a switch is shown.

In the configuration of the SP4T switch of FIG. 5, compared with the SP4T switch of FIG. 1, n (n: positive integer; n = 4 in FIG. 5) second FETs (shunt FETs). N FET4 _1S to 4 _4S , and n (n = 4) second FETs, FET4 _1S to 4 _4S (shunt FET), and n (n = 4) first (n = 4) first FETs. Wirings 23 ₁ to 23 ₄ , which are m (m = 4) fourth wirings for connecting FETs _{4 1} to 4 ₄ (series FETs), which are FETs, are provided.

That, SP4T switch shown in Figure 5, compared to the SP4T switch of FIG. 1, as in the case of FIG. 4 in that a gate direction of the first wiring in which wires 21 ₀ and FET are at right angles In addition to being different and having n pieces (n = 4) of FETs 4 ₁ to 4 ₄ which are the first FETs constituting the series FET as described above, the shunt FET is constituted. The difference is that a series shunt configuration switch is formed by adding n (n = 4) FETs 4 _1S to 4 _4S , which are the second FETs.

In SP4T switch series shunt configuration shown in FIG. 5, the respective source (or drain) ground, series FET 4 ₁ a first FET of each drain (or source) are n (n = 4) to ~ 4 ₄ of the drain (or source), n the (n = 4) of the wiring ₂₃ 1-23 ₄ (i.e. fourth wiring) shunt FET 4 _1S of n which are connected via a (n = 4) ~ _44S are arranged as the second FET.

The drains (or sources) of the series FETs 4 ₁ to 4 _{4 and} the drains (or sources) of the shunt FETs 4 _1S to 4 _4S are directly joined without passing through the wirings 23 ₁ to 23 ₄ that are the fourth wirings. Such a layout may be used, and such a case will be described later with reference to FIG.

In the series shunt configuration of FIG. 5, when the switch is turned ON / OFF, the series FETs 4 ₁ to 4 ₄ and the shunt FETs 4 _1S to ₄ connected to the _fourth wirings 23 ₁ to 23 ₄ respectively. The ON / OFF state with _4S is controlled to be opposite to each other.

Thus, for the path of OFF as the signal path, series FET e.g. FET 4 ₁ is OFF the first FET side, since the shunt FET for example FET 4 _1S of the second FET side is ON, the second FET side of the shunt FET for example, to the signal line for example lines 21 ₁ of the other end (terminal the branch point a opposite) is grounded through FET 4 _1S, isolation characteristics can be greatly improved, possible to switch broadband Can do.

Note that the gate orientations of n (n = 4) first FETs, series FETs 4 ₁ to 4 ₄ , and n (n = 4) shunt FETs 4 _1S to 4 _4S are shown in FIG. As shown in FIG. 4, they are formed so as to be parallel to each other. In addition, you may form so that it may become a 90 degree positional relationship.

However, although resistances to be connected to the gates of the first FET and the second FET are not shown, as in the case of FIG. 1, a series FET 4 that is n (n = 4) first FETs. ₁ to 4 ₄ are connected to n (n = 4) first resistors, respectively, and n (n = 4) second FETs, which are shunt FETs 4 _1S to 4 _4S , respectively. n (n = 4) second resistors are connected. Here, the n (n = 4) first resistors are in the vicinity of the first FET to which each is connected, or the first FET or the second adjacent to the first FET to which each is connected. N (n = 4) second resistors are arranged in the vicinity of the second FET to which each is connected or adjacent to the second FET to which each is connected. It arrange | positions between 1 FET or 2nd FET.

Here, as shown in FIG. 5, the series FETs 4 ₁ to 4 ₄ and the shunt FETs 4 _1S to 4 _4S connected by the _{four fourth} wirings 23 ₁ to 23 ₄ are identical to each other. The wirings 23 ₁ to 23 ₄ , which are _{four fourth} wirings that are arranged so as to line up on the line and connect the series FETs 4 ₁ to 4 ₄ and the shunt FETs 4 _1S to 4 _4S , respectively, are formed in a straight line. And are arranged so as to have the same length.

By adopting the pattern layout as described above, the four second connected respectively between the branch point A and the sources (or drains) of the series FETs 4 ₁ to ₄ 4 as the _{four first} FETs. the length of a is the wiring 21 ₁ to 21 ₄ lines, while maintaining the same as in the case of the embodiment was constituted of only the series FET in FIG. 1, it is possible to realize a switch of the series shunt configuration, port It is possible to increase the bandwidth of the switch having uniform characteristics.

  Next, a pattern layout of an SP4T switch different from the SP4T switch of FIG. 5 will be described with reference to FIG. FIG. 6 is a layout diagram showing a pattern layout different from the case of FIG. 5 of the SP4T switch which is an example of the FET switch according to the second embodiment of the present invention. That is, FIG. 4 shows a second modification of the pattern layout of the SP4T switch exemplified in FIG. 1 as the first embodiment.

In the configuration of the SP4T switch in FIG. 6, the wiring structure is different from the coplanar line illustrated in FIG. 1 and the like, and the ground conductor 1 and a dielectric layer and a ground conductor not shown are sequentially laminated on the surface of the semiconductor substrate. Furthermore, as compared with the case of the SP4T switch of FIG. 1, n pieces (n = 4 in the case of FIG. 6) of second FETs (shunt FETs) are provided as in the case of FIG. FET4 _1S to 4 _4S .

However, the connection form of the n (n = 4) first FETs and the n (n = 4) second FETs differs from the case of FIG. 5 in that the wiring 23 is the fourth wiring. Instead of providing ₁ to 23 ₄ , n (n = 4) first (n = 4) drains (or sources) of n (n = 4) second FETs FETs 4 _1S to 4 _4S (shunt FET) are provided. The FETs 4 ₁ to 4 ₄ (series FETs), which are FETs, are directly bonded to the drains (or sources) of the FETs _{4 1} to 4 ₄ (series FETs), respectively.

Also, as a wiring structure (type of wiring), unlike the coplanar line illustrated in FIG. 1 and the like, a ground conductor 1 and one or more dielectric layers (not shown) are sequentially stacked on the surface of a semiconductor substrate. The first wirings 21 ₀ , the wirings 21 _{1 to} 21 ₄ forming n (n = 4) second wirings, and the n (n = 4) second terminals are respectively provided. The wirings 22 _{1 to} 22 _{4 that} are n (n = 4) third wirings to be connected are formed on any one of the layers including the semiconductor substrate and each dielectric layer. Thus, a microstrip line with the ground conductor 1 as the ground is formed.

Here, it is preferable that at least the wiring 21 _{1 as} the second wiring so as to reduce the mutual interference among the wirings 21 _{1 to} 21 _{4 as} the n (n = 4) second wirings. to 21 ₄ and the ground conductor, so as to be formed in a different one of the layers on each other among the respective layers including the substrate and one or more dielectric layers of a semiconductor, the thickness of each dielectric layer, the number It is desirable to set to about 10 μm to 10 μm. Here, the wirings 21 _{1 to} 21 _{4 that} are the second wirings need not necessarily be formed on the same layer as the wirings 21 ₀ that are the first wirings and the wirings 22 _{1 to} 22 ₄ that are the third wirings. Alternatively, they may be formed on different layers.

Similarly, for the wiring 21 ₀ that is the first wiring and the wirings 22 _{1 to} 22 ₄ that are the third wiring, the wiring 21 ₀ that is the first wiring and the wirings 22 _{1 to} 22 ₄ that are the third wiring. However, it is desirable that the semiconductor layer is formed on a semiconductor substrate and on any one of different layers including one or more dielectric layers.

By adopting such a wiring structure, it becomes easy to reduce the interference between the wirings. Therefore, for example, the distance between the wirings 21 ₁ to 214 that are the _four second wirings can be reduced. As a result, the lengths of the _four wirings 21 _{1 to} 214 can be shortened and a transmission line having a good characteristic impedance and a high characteristic impedance can be obtained. Can be planned.

Note that each of the other end of the wirings 21 _{1 to} 21 ₄ that are n (n = 4) second wirings and the FETs 4 ₁ to 4 ₄ that are n (n = 4) first FETs, respectively. connection, n pieces (n = 4) takes place via the second through-hole ₃₁ 1-31 ₄ is a through hole, n the (n = 4) third wiring ₂₂ 1-22 are wires ₄ and n (n = 4) first FETs, which are FETs 4 ₁ to 4 ₄ , are connected to n (n = 4) third through holes, which are through holes 32 _{1 to} 32 _4. Is done through.

Here, n (n = 4) through-holes 31 _{1 to} 31 ₄ and n (n = 4) third through-holes are sequentially passed through the ground conductors stacked in sequence. When a certain through hole 32 _{1 to} 32 ₄ is installed, a part of the ground conductor has n (n = 4) second through holes 31 _{1 to} 31 ₄ , n ( A gap is provided for penetrating through holes 32 _{1 to} 32 ₄ , which are the third through holes of n = 4), without contacting the ground conductor.

On the other hand, regarding the method of arranging the FETs in the SP4T switch shown in FIG. 6, the drains (or sources) of the _first FETs FETs 4 ₁ to 4 _{4 and} the drains of the shunt FETs 4 _1S to 4 _4S (or the second FETs) (or Source) is directly joined without passing through the wiring (the wirings 23 ₁ to 23 _4, which are the fourth wirings in the case of FIG. 5), and further symmetrical in the vertical direction of the branch point A with respect to the horizontal direction. This is different from the SP4T switch illustrated in FIG. 5 in that the configuration is arranged at various positions.

That is, for example, in the upper right of the SPST switch branch point A, through a through hole 31 ₁ is one of the second one of the interconnection at a wiring 21 ₁ and the second through-hole, the first source connected in series FET4 ₁ which is one of the FET (or drain), series FET4 ₁ of the drain (or source), the shunt FET4 source (or drain) is one of the second FET, which is grounded while it is directly bonded to _1S drain (or source), through the through hole 32 ₁ is one of the third through hole, the third one a connected state to the wiring 22 ₁ is the line of Has been placed.

As a configuration similar to this pattern layout, for example, also for the SPST switch located in the lower right direction of the branch point A in FIG. 6, the wiring 21 ₂ , the through hole 31 ₂ , the FET 4 ₂ , the shunt FET 4 _2S , the through hole 32 ₂ , for each component of the wiring 22 _2, they are arranged in a symmetrical positional relationship in the vertical and the components that are located in the upper right of the branch point a.

By adopting such a configuration of the FET, the interval between the FETs can be further narrowed compared to the configuration illustrated in FIG. 5, and the effect of the wiring described above (that is, the wiring 21 as the second wiring). together with it) which is capable of shortening the length of ₁ to 21 _4, it is possible to further switch the broadband.

Also, in the case of the SP4T switch as shown in FIGS. 5 and 6, as shown in the characteristic diagram of FIG. 15, in order to ensure the reflection loss to be −10 dB or less, n (n = 4) second the effective electrical length of the wires 21 ₁ to 21 ₄ is a wiring in a desired operating frequency predetermined, it is desirable to 5 degrees or less.

It should be noted that the present invention is not limited to the SP4T switch illustrated in FIGS. 5 and 6. For example, as illustrated in FIG. 3, the first FETs FET 4 ₁ to 4 ₄ and the second FET FET 4 _1S to _{44 4S} gate orientations may be arranged parallel to each other or rotated by 90 °, or SPkT switches with an arbitrary number of ports (k: positive integer) such as the SP6T switch illustrated in FIG. A similar configuration can be applied to.

[Third Embodiment]
Next, an FET switch according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a layout diagram showing a pattern layout of an SP4T switch which is an example of an FET switch according to the third embodiment of the present invention. Further, FIG. 8 is an explanatory view for clearly showing pattern layout structure of FIG. 7, FIG. 8 (A) among the components of FIG. 7, the ground conductor 1 ₂ and the ground conductor 1 _1, 1 FIG. 8B is a layout diagram showing a pattern layout in a state in which the through holes 34 _{1 to} 34 ₃ connecting the _two are removed, and FIG. 8B shows a cross-sectional view along the YY ′ plane of FIG.

Figure 7, FET switch illustrated in FIG. 8 constitutes a SP4T switch, wiring 21 ₀ from the common terminal which constitutes one of the first terminal (not shown), similar to the case of FIG. 1 The first wiring is connected to the branch point A. At the branch point A, the wiring 21 is the second wiring of n (n: any positive integer; n = 4 in FIGS. 7 and 8). ₁ to 21 ₄ are n branched to through the n wirings ₂₁ 1 to 21 _4, respectively connected to n (n = 4) first FET 4 ₁ to 4 ₄ source is a FET (or drain) Is done. Further, n-number (n = 4) FET 4 ₁ to 4 ₄ in the drain (or source) is connected to the n (n = 4) third wiring ₂₂ 1-22 ₄ are wires of, n pieces It is connected to an individual terminal (not shown) constituting the second terminal (n = 4).

Accordingly, the branch point A connected to one common terminal (not shown) as the first terminal is changed to each of n (n = 4) SPSTs including the FETs 4 ₁ to ₄ 4 as the _first FETs. When viewed as a common terminal of the switch, a single-pole 4-throw (SP4T) switch composed of four SPST switches is formed. Thus, the branch point A is n (n = 4) second wirings when viewed from the n (n = 4) SPST switches including the first FETs FETs 4 ₁ to 4 _4. It is also a common connection point where a certain number of wirings 21 _{1 to} 21 ₄ become one.

Here, FET 4 ₁ to 4 ₄ are four of the first FET are each formed of a single gate finger, and, as shown in FIG. 7, are formed in the same direction, FET 4 ₁ ~ Each of the 4 ₄ gates is arranged to be parallel to each other.

Further, the region where the wiring 21 ₀ as the first wiring and the wirings 21 _{1 through} 21 _{4 as} the second wiring around the branch point A are present is performed by a process similar to the wiring structure illustrated in FIG. It is formed. That is, as shown in FIG. 8B, after the wiring 21 ₀ , the wirings 21 _{1 to} 21 ₄ and the ground conductor ₁₁ are formed on the surface of the semiconductor substrate 7 such as GaAs, one or more dielectric layers are formed. layer _{6 1,} the ground conductor _{1 2} are sequentially stacked. Here, the dielectric layer _61, in a part of the region, the gap for passing through holes ₃₄ 1 to 34 ₃ (holes) are bored, ground conductor _{1 2,} the through-holes 34 through _{1-34 3,} it is connected to the ground conductor _{1 1} on the semiconductor substrate 7.

Regarding the third is a wiring line 22 _{1-22 8} is formed similarly to the wiring structure illustrated in FIG. 6, the surface of the semiconductor substrate 7, one or more layers of dielectric ungrounded conductor and illustrated body layer are laminated in this order, the wiring 22 _{1-22 8,} among the respective layers including the substrate 7 and on the dielectric layer of the semiconductor, it is formed on any of the layers on.

With such structure of the nucleus, the second wiring 21 ₁ to 21 ₄ are wires formed on the substrate 7 becomes a reverse-type microstrip line and ground grounding conductor 1 _2, excellent characteristics of high-frequency characteristics It can operate as a transmission line with a fixed impedance.

Note that each of the wiring 21 ₀ as the first wiring and the wirings 21 _{1 to} 21 _{4 as} the second wiring is formed on the semiconductor substrate 7 together with the ground conductor ₁₁ with the gap interposed therebetween. and a coplanar line, between the separated ground conductor 1 ₁ required mode (not shown) that is connected by an air bridge or wires so as not to be excited to a coplanar line.

Here, preferably, the thickness of the dielectric layer 61 is set to about several μm to ₁₀ μm. With such a dielectric layer 6 ₁ of thickness, reverse-type signal microstrip line - for a spacing between the ground can be set to about several Myuemu～10myuemu, the n number of (n = 4) even to narrow the second wiring 21 ₁ to 21 ₄ mutual spacing a wiring, it is possible to reduce the unnecessary electromagnetic coupling with each other, it is easy to correspond to the number of ports increases.

7, in the SP4T switch shown in FIG. 8, the FET 4 ₁ to 4 ₄ the gate is the first FET, respectively, the first resistor is a resistor ₅ 1 to 5 ₄ are connected, a control terminal ( by via respective from not shown) resistor 5 ₁ to 5 ₄ for applying a gate control voltage of the FET, without a common terminal (illustrated wirings 21 ₀ is connected. that is, the first terminal) and the wiring Switching control between four individual terminals (not shown, that is, four second terminals) to which 22 _{1 to} 22 ₄ are respectively connected is performed.

In addition, the resistors 5 _{1 to} 5 _{4 as the first} resistors are arranged in the immediate vicinity (near each) of the connected first FETs or between the connected first FETs and the adjacent first FETs. Since the FETs are arranged in parallel with the gates of the FETs, interference between control signals can be avoided without increasing the FET interval. Narrowing the interval between the FETs makes it possible to shorten the lengths of the wirings 21 _{1 to} 21 ₄ as the second wirings, and is directly connected to expanding the operating band of the switch.

In addition, in order to make transmission characteristics between the common terminal (that is, the first terminal) and the four individual terminals (that is, the second terminals) uniform, the wirings 22 _{1 to} 22 that are four third wirings. The lengths of the _four are preferably equal to each other. The gates of the _{four first} FETs, FETs 4 ₁ to 4 ₄ , are arranged so as to be parallel to each other as described above.

A first wiring and a wiring 21 _0, the characteristic impedance of the transmission line using the second wiring 21 ₁ to 21 ₄ is a wiring as a signal line are preferably such as by thinning the wiring width, they It is desirable to set part or all of the wiring higher than the input / output impedance of the FET switch. By using a wiring having a characteristic impedance like this, the influence of an open stub can be further offset and reflection loss can be improved.

Further, as shown in the characteristic diagram of FIG. 15, in order to secure the return loss below -10 dB, the effective electrical length of the wires ₂₁ 1 to 21 ₄ which is a second wiring of the n (n = 4) the It is desirable to set it to 5 degrees or less at a predetermined desired operating frequency.

  In the circuit configurations as shown in FIGS. 7 and 8, since the signal line is not connected to the ground, the input signal level can be output almost as it is. Therefore, it can be used as a high-speed data transmission switch that uses a broadband baseband signal independent of the signal DC logic level, in addition to a wireless communication application using an RF band signal.

  7 and FIG. 8 may be applied to the FET switches shown in FIGS. 1 and 4 in the first embodiment and FIGS. 5 and 6 in the second embodiment. A similar configuration can be applied to any SPkT switch (k: positive integer) such as an SP8T switch.

[Fourth Embodiment]
Next, an FET switch according to a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a layout diagram showing a pattern layout of an SP8T switch which is an example of an FET switch according to the fourth embodiment of the present invention. FIG. 10 is an explanatory diagram for easy understanding of the pattern layout structure of FIG. 9, and FIG. 10 (A) shows the wiring 21 ₀ which is the first wiring among the components of FIG. FIG. 5 is a layout diagram showing a pattern layout in a state in which a conductor 1 ₂ , a through hole 33 that is a first through hole, and through holes 34 _{1 to} 34 ₄ that connect the ground conductors 1 ₁ and 1 ₂ are removed; 10 (B) shows a cross-sectional view taken along the plane XX 'of FIG.

9, the FET switch illustrated in FIG. 10 constitute a SP8T switch, wiring 21 ₀ from the common terminal which constitutes one of the first terminal (not shown), similar to the case of FIG. 1 The first wiring is connected to the branch point A, and at the branch point A, there are n (n: any positive integer; n = 8 in FIGS. 9 and 10) second wirings 21. ₁ to 21 ₈ are n branches, through the n wirings ₂₁ 1 to 21 _4, respectively connected to n (n = 8) first FET 4 ₁ to 4 ₈ source of a FET (or drain) Is done. Further, n-number (n = 8) the drain (or source) of the FET 4 ₁ to 4 ₈ of, respectively connected to the n (n = 8) third wiring ₂₂ 1-22 ₈ are wires of, n pieces It is connected to an individual terminal (not shown) constituting the second terminal (n = 8).

Accordingly, the branch point A connected to one common terminal (not shown) as the first terminal is changed to each of n (n = 8) SPSTs including the FETs 4 ₁ to 4 ₈ as the first FETs. When viewed as a common terminal of the switch, a single-pole 8-throw (SP8T) switch composed of eight SPST switches is formed. Thus, the branch point A, when viewed from each SPST switch of n consisting FET 4 ₁ to 4 ₈ a first FET (n = 8), the second wire n the (n = 8) there wirings ₂₁ 1 to 21 ₈ is also a common connection point becomes one.

Here, FET 4 ₁ to 4 ₈ is eight of the first FET are each formed of a single gate finger and are formed in the same direction, each of the gates of the FET 4 ₁ to 4 ₈ are Are arranged so as to be parallel to each other.

With respect to the n lines (n = 8) the third wiring is a wiring ₂₂ 1-22 ₈ are formed in the same manner as illustrated wiring structure in FIG. That is, the surface of the semiconductor substrate 7, one or more layers of the dielectric layer is not 1 ₁ and illustrated grounding conductor are laminated in this order, the wiring 22 _{1-22 8} also substrate 7 and on the dielectric layer of a semiconductor It is formed on one of the included layers. n present an (n = 8) of the third of the first FET 4 ₁ to 4 ₈ of the drain is a FET of the one end and the n lines ₂₂ 1 to 22 ₈ is a wiring (n = 8) (or source) , as in the case of FIG. 6, via n (n = 8) the third through-hole ₃₂ 1-32 ₈ is a through-hole, or directly connected.

In order to make the transmission characteristics between the common terminal (that is, the first terminal) and the eight individual terminals (that is, the second terminals) uniform, the wirings 22 _{1 to} 22 that are the eight third wirings. The lengths of the ₈ are preferably equal to each other. Further, the respective gates of the _{eight first} FETs, FETs 4 ₁ to 48, are arranged so as to be parallel to each other as described above.

As for the wiring 21 ₀ is a first wiring 10 as illustrated (B), the the surface of the semiconductor substrate 7, such as GaAs, the wiring ₂₁ 1 is the second wirings 8 to 21 _8, the dielectric layer _61, the ground conductor _{1 2,} the dielectric layer _{6 2} are laminated in this order, the wiring 21 ₀ has a formed structure on the dielectric layer _{6 2.} Here, in the ground conductor 1 ₂ and the dielectric layers 6 ₁ and 6 ₂ , a gap (hole) for allowing the through hole 33 which is the first through hole to pass through a partial region thereof, for example, the central portion is formed. are set, it can be connected without contacting the wiring 21 ₀ and the wiring ₂₁ 9-21 ₈ and the ground conductor _{1 2.} The dielectric layer _61, that part of the region, the gap for passing through holes ₃₄ 1 to 34 ₄ (holes) are bored, ground conductor _{1 2,} the through-hole 34 ₁ to 34 ₄ via is connected to the ground conductor _{1 1} on the semiconductor substrate 7.

That is, on the semiconductor substrate 7 of the region where the second wiring 21 ₀ interconnect 21 is ₁ to 21 ₈ and the first wiring is a wiring is present, turn one or more layers of the dielectric layers 6 _1, the ground conductor 1 _2, 1 or more dielectric layers _{6 2} is laminated, in the region, the second wiring ₂₁ 1 to 21 ₈ is a wiring and the wiring 21 ₀ which is the first wiring, a ground conductor _{1 1} formed in the upper semiconductor substrate 7 is not formed and the dielectric layer 6 _1, 6 different one of different layers of _two layers, including, and the second a wiring is wiring 21 ₁ to 21 ₈ mutually connected end and the other end of the wiring 21 ₀ a first wiring (i.e., opposite terminal of the terminal connected to the first terminal), the through-hole 33 is a first through hole Connected through.

Further, n is a first FET of the other end and the n (n = 8) of the second and the wiring is wiring _{21 1 ~21 8 (n = 8} ) FET4 1 ~4 8 sources (or 6 is connected via the second through hole in the example shown in FIG. 6, but in the case of this embodiment, as shown in FIG. 10A, it does not go through the through hole. Connected directly.

Here, in the configuration of the SP8T switch of FIG. 9 and FIG. 10, an arrangement region of n (n = 8) _first FETs 4 ₁ to 4 ₈ and n (n = 8) second (n = 8) second FETs. a region excluding the arrangement region of a wiring line ₂₁ 1 to 21 _8, a layer of the ground conductor _{1 2} is laminated further on the ground conductor _{1 2} and / or _{1 2} under the ground conductor, 1 with more dielectric layers ₆ 1, _{6 2} layers, one first and the third is a wiring line ₂₂ 1-22 ₈ is a wiring 21 ₀ and n lines (n = 8) of Although it is configured to be disposed on the substrate 7 or on a layer different from the layer in which the ground conductors 1 ₁ and 1 ₂ are laminated, for example, the second embodiment has a series shunt configuration as shown in FIG. A similar configuration can be adopted in the case of an FET switch.

That is, for example, when configuring the SP8T switch similar series shunt configuration and FET switch in Figure 6, layer ground conductor _{1 2} is stacked, a first FET of n above (n = 8) not only region excluding a certain FET 4 ₁ to 4 ₈ arrangement region of the second wiring and a wiring ₂₁ 1 to 21 ₈ of the arrangement region and n (n = 8), the first of the n (n = 8) It is laminated in a region excluding the region where the FETs 4 _1S to 4 _8S (shunt FET) which are the second FETs are arranged.

The structure shown in FIGS. 9 and 10 uses, for example, polyimide as an insulating interlayer film, and repeats the manufacturing process of polyimide coating, heat curing, and through-hole formation by dry etching on a semiconductor substrate 7. Can be realized. Incidentally, with regard dielectric layers applied to the area of the third and the wiring is 22 _{1-22 8,} by configuring the dielectric layer ₆₁ or dielectric layer ₆₁ and the dielectric layer 6 _2, 9 All the wiring structures shown in FIG. 10 can be realized by using a common manufacturing process.

  By adopting such a configuration, all signal wirings can be formed as transmission lines having predetermined characteristics as characteristic impedances suitable for transmission of high-frequency signals, except for through-hole portions, so that the broadband operation of the switch can be achieved. It becomes easy.

Furthermore, between the first wiring 21 ₀ is a wiring between the second wiring ₂₁ 1 to 21 ₈ is a wiring, it is possible to provide a ground conductor _{1 2,} therefore, the wiring 21 ₀ and the wiring 21 ₁ it is possible to eliminate the electromagnetic coupling between the to 21 _8, it is possible to lay without wires 21 ₁ to 21 ₈ to fear the adverse effect of electromagnetic coupling.

In other words, without worrying about the variations in the inter-port characteristic due to electromagnetic coupling, it can be optimized layout shortest and equal length of the wiring 21 ₁ to 21 _8.

On the other hand, when the ground conductor _{1 2} absent, electromagnetic by binding strength (e.g., FIG. 9, with respect to the wiring ₂₁ 1, 21 ₈ closer to the wiring 21 ₀ as shown in FIG. 10 (A), both the electromagnetic coupling becomes strong, the wiring 21 4 away from the wiring 21 _0, 21 with respect to _5, since the both of the electromagnetic coupling becomes weak), it is difficult to uniform inter-port characteristics, in order to reduce its influence The degree of freedom of layout will be limited.

Incidentally, the dielectric layer ₆ 1, _{6 2} of the thickness, respectively, the number by setting several Myuemu～10myuemu, wiring 21 _0, the distance from each of the wires ₂₁ 1 to 21 ₈ to the ground conductor _{1 2,} respectively it is possible to approximately Myuemu～10myuemu, even to narrow the wiring 21 ₁ to 21 ₈ mutual spacing, it is possible to reduce unnecessary electromagnetic coupling with each other, making it easy to correspond to the number of ports increases Become.

In the SP8T switch shown in FIG. 9, FIG. 10, to the gate of the first is a FET FET 4 ₁ to 4 _8, respectively, the first resistor is a resistor ₅ 1-5 ₈ is connected, a control terminal ( by via respective from not shown) resistor 5 _{1-5 8} applies a gate control voltage of the FET, without a common terminal (illustrated wirings 21 ₀ is connected. that is, the first terminal) and the wiring 22 _{1-22 8} (not shown. that is, the second terminal 8) eight individual terminals which are respectively connected switching control between performed.

In addition, the resistors 5 _{1 to} 5 _{8 as the first} resistors are provided in the immediate vicinity (near each) of the connected first FETs or between the connected first FETs and the adjacent first FETs. Since the FETs are arranged in parallel with the gates of the FETs, interference between control signals can be avoided without increasing the FET interval. Narrowing the FET interval makes it possible to shorten the length of the second and the wiring is wiring 21 ₁ to 21 _8, directly linked to expand the operating band of the switch.

Next, a pattern layout of an SP8T switch different from the SP8T switch of FIGS. 9 and 10 will be described with reference to FIGS. FIG. 11 is a layout diagram showing a pattern layout different from the case of FIG. 9 of the SP8T switch which is an example of the FET switch according to the fourth embodiment of the present invention. FIG. 12 is an explanatory diagram showing the pattern layout structure of FIG. 11 in an easy-to-understand manner. Among the components shown in FIG. 11, the wiring 21 _{0 as} the first wiring, the ground conductor 1 ₂ , the first The pattern layout in a state in which the through hole 33 which is a through hole and the through holes 34 _{1 to} 34 ₅ connecting the ground conductors 1 ₁ and 1 ₂ are removed is shown.

In FIGS. 11 and 12, the resistors 5 _{1 to} 5 ₈ that are the first resistors to be connected to the gates of the FETs 4 ₁ to 4 ₈ that are the first FETs are not shown. As in the case of FIGS. 9 and 10, each first resistor is arranged in the vicinity of the first FET to which the first resistor is connected or between the first FET and the adjacent first FET.

  The SP8T switch of FIGS. 11 and 12 is an SP8T switch similar to the SP8T switch of the present embodiment illustrated in FIGS. 9 and 10, and the following is the case of the SP8T switch shown in FIGS. The difference will be mainly described.

The SP8T switch shown in FIGS. 11 and 12 is different from the SP8T switch shown in FIGS. 9 and 10 in that FETs 4 ₁ to 4 that are n first FETs (n = 8 in FIGS. 11 and 12). the mutual positional relationship between the ₈ are different, the mutual positional relationship between the wiring 21 ₁ to 21 ₈ are different, which is the second wiring that n branched at the branch point a, and the first FET the gate width of the FET 4 ₁ to 4 ₈ are, respectively, in that is shorter than the length of the second and the wiring is wiring ₂₁ 1 to 21 _8.

That is, the SP8T switches in FIGS. 11 and 12 are different from the SP8T switches shown in FIGS. 9 and 10 in the same way as in the case of FIG. 3 in the first embodiment (see FIGS. 11 and 12). In the case of n = 8), the first FETs are divided into four groups with respect to the mutual arrangement of the FETs 4 ₁ to 4 ₈ which are the first FETs, and the gate orientation of each first FET belonging to each group Are sequentially rotated by 90 °.

For example, as in the case of FETs 4 ₁ to 4 ₈ in FIGS. 11 and 12, when the number n of the first FETs is 8, the first FETs are divided into four groups to which two first FETs belong. The first FET has a positional relationship in which the gate orientation of each first FET rotates sequentially by 90 °. As a result, among the _{eight first} FETs, FETs 4 ₁ to 4 ₈ , the FETs 4 ₁ , 4 ₂ belonging to the first group and the FETs 4 ₅ , 4 ₆ belonging to the third group have parallel gate orientations, respectively. The gate orientations of the FETs 4 ₃ , 4 ₄ belonging to the second group, the FETs 4 ₇ , 4 ₈ belonging to the fourth group are parallel to each other, and the FETs 4 ₁ , 4 ₂ belonging to the first group and A positional relationship of 90 ° between the gate orientations of the FETs 4 ₅ , 4 ₆ belonging to the third group and the gate orientations of the FETs 4 ₃ , 4 ₄ belonging to the second group and the FETs 4 ₇ , 4 ₈ belonging to the fourth group It has become.

Further, FIG. 9, unlike the SP8T switch shown in FIG. 10, lines 21 _0, which is the first wiring, at a branch point A, n pieces FET4 in (FIG. 11, in the case of FIG. 12, n = 8) towards _{1-4 8} direction sequentially rotated by 90 ° in accordance with the gate orientation, as the n (n = 8) the second wiring ₂₁ 1 to 21 ₈ are wires, the n branch, the n through the interconnection ₂₁ 1 to 21 ₈ are connected to the FET 4 ₁ to 4 ₈ sources of n (n = 8) (or the drain).

For example, in the case of FIGS. 11 and 12 where the number n of the first FETs is 8, two wirings 21 _{1 to} 21 ₈ that are _eight second wirings connected to each first FET are also provided. is divided into four groups, the wiring 21 ₀ first a wiring, at a branch point a, when it is 8 branched, a unit of four groups the first FET of the two by two belong, respectively, 90 Wirings 21 ₁ , 21 ₂ , and wirings 21 ₃ are arranged in a positional relationship that is sequentially rotated by 90 ° corresponding to each group in accordance with the gate orientations of the _eight FETs 4 ₁ to 48 rotated sequentially by °. , 21 _4, line ₂₁ 5, 21 _6, line ₂₁ 7, 21 ₈ via each of which is connected to the FET 4 ₁ to 4 ₈ source of which is eight first of the FET (or the drain).

Here, also for the eight third is a wiring line ₂₂ 1-22 _8, similarly to the wiring ₂₁ 1 to 21 ₈ is the second wirings 8 are divided into four groups of two, Eight second terminals (not shown) arranged in accordance with the gate orientations of the _{eight first} FETs, FETs 4 ₁ to 48, are sequentially rotated by 90 ° with each group as a unit. ) And each first FET are connected so as to have the same length.

Further, unlike the case of the SP8T switch shown in FIG. 9, FIG. 10, as described above, the gate width of n (n = 8) is a first FET of FET 4 ₁ to 4 _8, respectively, n the (n = 8) is shorter than the length of the second wiring and a wiring ₂₁ 1 to 21 _8.

  Here, the arrangement of the first FET as described above is, for example, to form an FET having the same characteristics in the crystal plane orientations of [010] and [001] that are 45 ° with respect to the orientation flat on the GaAs wafer. It can be realized by using what can be done.

11, by such arrangement of FIG. 12, further, it is possible to shorten the length of the n (n = 8) of the second wiring and a wiring ₂₁ 1 to 21 _8, it has superior characteristics between the ports It is possible to further expand the operating range of the switch that is uniform in level.

11, by adopting the configuration shown in FIG. 12, for the n lines (n = 8) the second wiring 21 ₁ to 21 ₈ are wires, it is possible to improve transmission line of the high-frequency characteristics Therefore, it is possible to further expand the operation zone.

Further, the gate width of n (n = 8) is a first FET of FET 4 ₁ to 4 _8, than the length of the n (n = 8) of the second wiring and a wiring ₂₁ 1 to 21 ₈ by being shortened, n pieces (n = 8) of the first OFF the FET 4 ₁ to 4 ₈ a FET sometimes, n the (n = 8) the second wiring ₂₁ 1 are wires to 21 ₈ with the influence of the FET 4 ₁ to 4 ₈ physical length is a first FET which would appear to the open stub can be significantly reduced, it is possible to further enlarge the operation Obijo FET switch.

  For example, by applying a high electron mobility transistor (HEMT) having an InGaAs channel layer with excellent electron transport characteristics for the first FET, the ON resistance can be reduced even with a short gate width. It is also possible to easily achieve both reduction in insertion loss and wideband operation.

  With the effects described above with respect to the SP8T switch having the pattern layout shown in FIGS. 11 and 12, it is possible to realize a wideband operation of the SP8T switch having uniform reflection characteristics and port-to-port characteristics, as well as miniaturization and low cost. Can also be achieved.

Note that the first wiring and is wiring 21 _0, the characteristic impedance of the transmission line using a second wiring and a wiring 21 ₁ to 21 ₈ as the signal lines, preferably such as by thinning the wiring width, they It is desirable to set part or all of the wiring higher than the input / output impedance of the FET switch. By using a wiring having a characteristic impedance like this, the influence of an open stub can be further offset and reflection loss can be improved.

Further, as shown in the characteristic diagram of FIG. 15, in order to secure the return loss below -10 dB, the effective electrical length of the n (n = 8) which is a second wiring lines ₂₁ 1 to 21 ₈ It is desirable to set it to 5 degrees or less at a predetermined desired operating frequency.

  Further, in the circuit configurations as shown in FIGS. 9 to 12, since the signal line is not connected to the ground, the input signal level can be output almost as it is. Therefore, it can be used as a high-speed data transmission switch that uses a broadband baseband signal independent of the signal DC logic level, in addition to a wireless communication application using an RF band signal.

Incidentally, may be a structure different from the structure shown in the sectional view of FIG. 10 (B), for example, by the positional relationship between the wiring 21 ₀ and the wiring ₂₁ 1 to 21 ₈ Conversely, the wiring 21 ₀ a semiconductor substrate 7 above may be wires ₂₁ 1 to 21 ₈ a configuration disposed on the dielectric layer _{6 2.}

  Also, the structure shown in FIGS. 9 to 12 is shown in FIGS. 1, 3, and 4 in the first embodiment, and in FIGS. 5, 6, and 3 in the second embodiment. 7 may be applied to the FET switch shown in FIG. 8, and the same configuration can be applied to an SPkT switch (k: positive integer) having an arbitrary number of ports such as an SP4T switch.

[Fifth Embodiment]
Next, an FET switch according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a layout diagram showing a pattern layout of an example of an FET switch according to the fifth embodiment of the present invention. FIG. 13, FIG. 2, FIG. 3, FIG. 5, FIG. An example is shown in which an SP16T switch is configured by adopting a two-stage switch configuration using five SP4T switches illustrated as examples.

For FET switch such as a SP16T switch illustrated in FIG. 13, the first end of the wiring 21 ₀ which is connected to the first terminal the new as the FET switch, SP4T switch to form a first stage 8 ₁ of the common terminal (i.e., the first terminal) is connected, each individual terminal (i.e. a second terminal) of the n SP4T switch 8 ₁ (n = 4), to form a second stage 4 pieces of the common terminal of the SP4T switch ₈ 1-8 ₅ (i.e. first terminals), respectively, are connected, respectively SP4T switch ₈ 1-8 ₅ individual terminal (i.e. a second terminal), the third wiring Are connected to a total of 16 new second terminals of the FET switch via the wirings 22 _{1 to} 22 ₄ , 22 _{5 to} 22 ₈ , 22 _{9 to} 22 ₁₂ , and 22 _{13 to} 22 ₁₆ . One first Switching control between the terminal and the sixteen second terminal is performed.

In the case of the SP16T switch illustrated in FIG. 13, although the first stage SP4T switch 8 ₁ and the second stage SP4T switches 8 ₁ to 8 ₅ have the disadvantage of the two-stage configuration, each SP4T switch is As described in each of the embodiments, since each of them has a small and wide band characteristic, the SP16T switch of FIG. 13 can also be small and have a wide band.

Instead of the SP4T switch, for example, seven SP6T switches (in the case of n = 6) illustrated in FIG. 4 (that is, in the case of (n + 1) = 7) are used to form an SP36T switch (in other words, n ² = 36). You may make it do. That is, in general, an SPn ² T switch may be configured by using (n + 1) SPnT switches having n ports (m: any positive integer).

  Alternatively, an SPmT switch having a different number of ports from the SPnT switch may be combined to form a multi-port switch having an arbitrary number of ports. For example, as (n + 1) FET switches, one SP4T switch and four SP6T switches are used, and the first stage switch for connecting to the new first terminal is the SP4T switch, and the second stage The eye switch may be configured as four SP6T switches, and may be configured as an SP24T switch having a total of 24 new second terminals. Alternatively, as (n + 1) FET switches, two SP4T switches, one SP5T switch, one SP6T switch and one SP7T switch are used to connect to a new first terminal. These switches are SP4T switches, and the four second-stage switches are SP4T switches, SP5T switches, SP6T switches, and SP7T switches, one each, for a total of 22 new second terminals as SP22T switches. It may be configured.

That is, for (n + 1) (n: positive integer) FET switches, the number of second terminals of (n + 1) FET switches is n, n ₁ , n ₂ , n _{3 ,.} (N, n ₁ , n ₂ , n ₃ ,..., N _n : each is the same positive integer or part of each is the same positive integer or each is a different positive integer) Of the (n + 1) FET switches, an FET switch having n second terminals is used as a first FET switch located in the first stage, and the first terminal of the first FET switch is shared. The first terminals of the remaining n FET switches are connected to the n second terminals of the first FET switch as new first terminals, and the remaining n FET switches are connected. N ₁ , n ₂ , n ₃ ,. The _n second terminal, by a total of _{(n 1 + n 2 + n} 3 + ... + n n) pieces of new second _{terminal, SP (n 1 + n 2} + n 3 + ... + n n) T Switch You may make it comprise as.

FIG. 3 is a layout diagram showing a pattern layout of an SP4T switch which is an example of an FET switch according to the first embodiment of the present invention. It is a layout figure which shows the pattern layout of SP4T switch different from the case of FIG. 1 of the FET switch concerning the 1st Embodiment of this invention. FIG. 4 is a layout diagram showing a pattern layout of an SP4T switch different from that in FIGS. 1 and 2 of the FET switch according to the first embodiment of the present invention. FIG. 5 is a layout diagram showing a pattern layout of an SP6T switch different from the case of FIGS. 1 to 3 of the FET switch according to the first embodiment of the present invention. It is a layout figure which shows the pattern layout of SP4T switch which is an example of the FET switch concerning the 2nd Embodiment of this invention. FIG. 6 is a layout diagram showing a pattern layout different from the case of FIG. 5 of an SP4T switch which is an example of an FET switch according to a second embodiment of the present invention. It is a layout figure which shows the pattern layout of SP4T switch which is an example of the FET switch concerning the 3rd Embodiment of this invention. FIG. 8 is an explanatory diagram for easy understanding of the pattern layout structure of FIG. 7. It is a layout figure which shows the pattern layout of SP8T switch which is an example of the FET switch concerning the 4th Embodiment of this invention. FIG. 10 is an explanatory diagram for easy understanding of the pattern layout structure of FIG. 9. FIG. 10 is a layout diagram showing a pattern layout different from the case of FIG. 9 of an SP8T switch which is an example of an FET switch according to a fourth embodiment of the present invention. It is explanatory drawing for showing the pattern layout structure of FIG. 11 clearly. It is a layout figure which shows the pattern layout of an example of the FET switch concerning the 5th Embodiment of this invention. It is a circuit diagram which shows the connection structure of the conventional SP8T switch. It is a characteristic view which shows the simulation result of the signal characteristic in SP8T switch of FIG. It is a circuit diagram which shows the structure different from FIG. 14 of the conventional SP8T switch.

Explanation of symbols

1, 1 ₁ to ₁₅ ... ground conductor, 21 ₀ , 21 _{1 to} 21 ₈ , 22 _{1 to} 22 ₁₆ , 23 _{1 to} 22 ₄ ... wiring, 31 _{1 to 3 14} , 32 _{1 to} 32 ₈ , 33, 34 ₁ ˜34 ₅ ... Through hole, 4 ₁ ˜4 ₈ ... FET, 4 _1S ˜4 _4S ... Shunt FET, 5 ₁ ˜5 _6, resistor, 6 ₁ , 6 _2, dielectric layer, 7, substrate, 8 ₁ ˜8 ₅ ... SP4T switch, 9 _{1 to} 9 ₈ ... SPST switch, 10 ₁ , 10 ₂ , 10 ₁₁ , 10 ₁₂ , 10 ₂₁ , 10 ₂₂ , 10 ₁₁₁ , 10 ₁₁₂ , 10 ₁₂₁ , 10 ₁₂₂ , 10 ₂₁₁ , 10 ₂₁₂ , 10 ₂₂₁ , 10 ₂₂₂ ... SPST switch.

Claims (19)

On the substrate, one first terminal, n (n: positive integer) second terminals, n first FETs, one first wiring, and n second terminals FET switch comprising n wirings and n third wirings,
One end of the first wiring is connected to the first terminal, and the other end is connected to one end of the n second wirings connected to each other.
The other ends of the n second wirings are respectively connected to the sources or drains of the n first FETs,
The drains or sources of the n first FETs are respectively connected to one end of the n third wirings, and the other ends of the n third wirings are respectively connected to the n number of the third wirings. Connected to the second terminal,
The FET switch, wherein the n second wirings are each formed in a straight line and have the same length. The FET switch of claim 1, wherein
An FET switch, wherein the effective electrical length of each of the n second wirings is 5 degrees or less at a predetermined desired operating frequency. The FET switch according to claim 1 or 2,
The FET switch, wherein each of the n first FETs has one gate finger. The FET switch according to any one of claims 1 to 3,
The FET switch, wherein the gate width of each of the n first FETs is less than or equal to the length of the n second wirings. The FET switch according to any one of claims 1 to 4,
n first resistors respectively connected to the gates of the n first FETs;
The n first resistors are arranged in the vicinity of the first FET to which each of the first resistors is connected, or between the first FET and the adjacent first FET. FET switch to do. The FET switch according to any one of claims 1 to 5,
Furthermore, it has n second FETs,
The sources or drains of the n second FETs are grounded, and the drains or sources of the n second FETs are directly joined to the drains or sources of the n first FETs, respectively. FET switch characterized by that. The FET switch of claim 6, wherein
Further, n fourth wirings are provided,
The drains or sources of the n second FETs are not directly joined to the drains or sources of the n first FETs, respectively, but are connected via the n fourth wirings, respectively. FET switch characterized by being connected. The FET switch of claim 7, wherein
The FET switch, wherein the n fourth wirings are each formed in a straight line and have the same length. The FET switch according to any one of claims 6 to 8,
a second n resistors respectively connected to the gates of the n second FETs;
The n second resistors are arranged in the vicinity of the second FET to which each of the second resistors is connected, or between the second FET and the adjacent first FET or the second FET. FET switch characterized by comprising. The FET switch according to any one of claims 1 to 9,
The gate orientations of the n first FETs or the gate orientations of the n first FETs and the n second FETs are parallel to each other or are in a positional relationship of 90 °. FET switch characterized by that. The FET switch according to any one of claims 1 to 10,
The first terminal and the first FET include at least the n first FETs or the n first FETs and the n second FETs, and the n second wirings. Each of the components excluding the wiring is provided in two sets as a first set and a second set, and the components belonging to each of the first set and the second set are arranged at symmetrical positions on the substrate. FET switch characterized by comprising. The FET switch according to any one of claims 1 to 11,
One or more dielectric layers are stacked on the substrate in the region where the n second wirings exist,
2. The FET switch according to claim 1, wherein in the region, the second wiring and the ground conductor are formed on the substrate and on different layers among the layers including the dielectric layer. The FET switch according to any one of claims 1 to 12,
One or more dielectric layers, a ground conductor, and one or more dielectric layers are sequentially stacked on the substrate in the region where the first wiring and the n second wirings exist.
In the region, the first wiring and the n second wirings are different from each other among the layers including the substrate and the dielectric layer on which the ground conductor is not formed. Formed on top
The FET switch, wherein the other end of the first wiring and the one end of the second wiring connected to each other are connected through a first through hole. The FET switch according to claim 12 or 13,
The FET switch, wherein the other end of the n second wirings and the source or drain of the n first FETs are connected directly or through a second through hole. The FET switch according to any one of claims 1 to 14,
One or more dielectric layers and / or ground conductors are laminated on the substrate in the region where the n third wirings are present,
In this region, one end of the n number of the third wirings and the drain or source of the n number of the first FETs are connected directly or via a third through hole. switch. The FET switch according to any one of claims 13 to 15,
When the first through hole and / or the second through hole and / or the third through hole are installed via the ground conductors that are sequentially stacked, in a partial region of the ground conductor, A FET switch comprising a gap for allowing the first through hole and / or the second through hole and / or the third through hole to pass through without contacting the ground conductor. The FET switch according to any one of claims 1 to 16,
A layer in which a ground conductor is stacked is provided in an area excluding the arrangement area of the first FET or the first FET and the second FET and the arrangement area of the second wiring, and further, the ground conductor Comprising one or more dielectric layers above and / or below the ground conductor;
The FET switch, wherein the first wiring and the third wiring are arranged on a layer different from the layer on which the ground conductor is laminated on the substrate. The FET switch according to any one of claims 1 to 17,
A FET switch characterized in that a characteristic impedance of a part or all of the first wiring and the second wiring is higher than an input / output impedance of the FET switch. (N + 1) FET switches according to any one of claims 1 to 18 (n: a positive integer),
The number of the second terminals of the (n + 1) FET switches is n, n ₁ , n ₂ , n ₃ ,..., n _n (n, n ₁ , n ₂ , n ₃ ,. n _n : all of the same positive integers or a part of each of them is the same positive integer or all of the different positive integers),
Of the (n + 1) FET switches, the FET switch having the n second terminals is used as a first FET switch, and the first terminal of the first FET switch is used as a new common first switch. The first terminals of the remaining n FET switches are connected to the n second terminals of the first FET switch, respectively, and the remaining n FET switches are connected. N ₁ , n ₂ , n ₃ ,..., N _n second terminals in total (n ₁ + n ₂ + n ₃ +... + N _n ) new second terminals, SP (n ₁ + n ₂ + n ₃ +... + N _n ) FET switch configured as a T switch.

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