JP2010073896A - Nonvolatile semiconductor storage device and method of manufacturing the same - Google Patents

Abstract

A nonvolatile semiconductor memory device formed by aligning positions of a gate electrode and an impurity diffusion region without reducing a coupling ratio, and a method of manufacturing the same are provided.
A semiconductor substrate, a plurality of impurity diffusion regions formed in the semiconductor substrate, an insulating film formed on the semiconductor substrate, and the impurity diffusion regions adjacent to each other are connected to the semiconductor substrate. A floating gate electrode formed through an insulating film, an inter-gate insulating film formed on the upper surface and side surfaces of the floating gate, and an upper surface and both side surfaces of the floating gate electrode through the inter-gate insulating film And a control gate electrode formed.
[Selection] Figure 3B

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a stacked gate structure and a manufacturing method thereof.

  Memory cells constituting a nonvolatile semiconductor memory device are formed so that a control gate is sandwiched between impurity diffusion layer regions (drain / source).

  As a method for preventing the positions of the control gate and the impurity diffusion region from being shifted from each other, there is a method called self-alignment. In this method, after depositing and processing a control gate, impurity implantation is performed using CG as a mask to form an impurity diffusion region (see, for example, Patent Document 1).

  However, when the height of the control gate serving as a mask increases, the shape of the control gate tends to become an abnormal shape. The abnormally shaped CG hinders the impurity implantation, further forms an abnormally shaped impurity diffusion region, and accelerates the deterioration of the characteristics of the memory cell in the write / erase operation.

  As a countermeasure, it is conceivable that the control gate is made a thin film and the floating gate is made a thin film.

  However, the thinning of the floating gate reduces the area where the control gate and floating gate are in contact with each other via an insulating film, thereby reducing the coupling ratio that affects the write / erase characteristics of the memory cell. was there.

Therefore, in the conventional technique, it has been difficult to provide a nonvolatile semiconductor memory device formed by matching the phases of the gate electrode and the impurity diffusion region without reducing the coupling ratio.
JP 2001-168215 A

  The present invention provides a nonvolatile semiconductor memory device formed by matching the phases of a gate electrode and an impurity diffusion region without reducing the coupling ratio, and a method for manufacturing the same.

  A nonvolatile semiconductor memory device according to one aspect of the present invention includes a semiconductor substrate, a plurality of impurity diffusion regions formed in the semiconductor substrate, an insulating film formed on the semiconductor substrate, and the adjacent impurity diffusion regions. A floating gate electrode formed on the semiconductor substrate via the insulating film, an inter-gate insulating film formed on an upper surface and a side surface of the floating gate, and the floating gate electrode via the inter-gate insulating film And a control gate electrode formed so as to be in contact with the upper surface and both side surfaces.

  A nonvolatile semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate, a plurality of impurity diffusion regions formed in the semiconductor substrate, an insulating film formed on the semiconductor substrate, and the adjacent impurity diffusion regions. A lower floating gate electrode formed on the semiconductor substrate via the insulating film, and an upper floating gate formed wider than the lower floating gate electrode and formed on the upper surface of the lower floating gate electrode An intergate insulating film formed on the upper surface of the upper floating gate electrode, a spacer insulating film formed on both side surfaces of the lower floating gate electrode, and the upper floating gate electrode via the intergate insulating film A control gate electrode formed in contact with the upper surface of The diffusion region is composed of a first impurity diffusion region having a first impurity concentration and a second impurity diffusion region having a second impurity concentration higher than the first impurity concentration. The second impurity diffusion region is formed so as to match with the spacer insulating film, and is formed so as to match with the lower floating gate electrode.

  According to one aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor device, comprising: forming a floating gate electrode on a semiconductor substrate; and implanting impurities into the semiconductor substrate using the floating gate electrode as a mask. Forming an insulating layer on the semiconductor substrate and on the floating gate electrode, processing the insulating layer to be lower than an upper surface of the floating gate electrode, and forming a gate on the entire surface of the semiconductor substrate. Forming an inter-layer insulating film; forming a control gate electrode on the inter-gate insulating film; and etching the control gate electrode and the inter-gate insulating film to thereby form the control electrode and the inter-gate insulating film. Forming a pattern of .

  According to another aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor device, comprising: forming a lower floating gate electrode on a semiconductor substrate; and implanting impurities into the semiconductor substrate using the lower floating gate electrode as a mask. A step of forming an impurity diffusion region, a step of forming a spacer insulating film on both side surfaces of the lower floating gate electrode, and implanting impurities into the semiconductor substrate using the spacer insulating film and the lower floating gate electrode as a mask. A step of forming the second impurity diffusion region, a step of depositing an insulating layer on the semiconductor substrate and the lower floating gate electrode, and an upper floating gate electrode on the lower floating gate electrode and the insulating layer. Forming and the upper layer floating Forming an intergate insulating film on the gate electrode, forming the control gate electrode on the intergate insulating film, the upper floating gate electrode, the lower floating gate electrode, and the intergate insulating film Forming a pattern of the upper layer floating gate electrode, the lower layer floating gate electrode, and the inter-gate insulating film.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device formed by matching the phases of the gate electrode and the impurity diffusion region without reducing the coupling ratio, and a method for manufacturing the same.

  Next, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

[Configuration of Nonvolatile Semiconductor Memory Device According to First Embodiment]
FIG. 1 is a block diagram showing a configuration of a main part of a nonvolatile semiconductor memory device (hereinafter referred to as flash memory) 100 according to the first embodiment of the present invention. As shown in FIG. 1, the flash memory 100 according to the present embodiment includes a memory cell array 10, a row decoder 30, a column decoder 40, a column selector 50, a source line driver 60, a write data buffer 70, a sense amplifier 80, a data input. An output circuit 90, an input buffer 110, an address buffer 120, an address register 130, a voltage generation circuit 140, a power supply circuit 150, and a control circuit 160 are provided.

  The memory cell array 10 includes a plurality of NOR type flash memory cells MC arranged in a matrix. Each memory cell MC is connected to a bit line BL (not shown in FIG. 1), a word line WL (not shown in FIG. 1), and a source line SL (not shown in FIG. 1).

  The row decoder 30 selects the row direction (second direction) of the memory cell array 10.

  The column decoder 40 selects the column direction (first direction) of the memory cell array 10.

  The column selector 50 selects the bit line BL based on the selection operation of the column decoder 40 and connects the bit line to the write data buffer 70 or the sense amplifier 80.

  Source line driver 60 applies a voltage to source line SL.

  The sense amplifier 80 senses and amplifies data read from the memory cell MC selected by the row decoder 30 and the column decoder 40.

  The write data buffer 70 holds data to be written to the memory cell MC, and writes data to the memory cell MC in batches in a predetermined memory cell MC unit.

  The input buffer 110 receives a control signal 111 given from a CPU (not shown) and outputs it to the control circuit 160. The control signal 111 is, for example, a chip enable signal, a write enable signal, an output enable signal, or the like. The chip enable signal is a signal that enables the flash memory 100 to operate. The write enable signal is a signal that enables writing of data to the flash memory 100. The output enable signal is a signal that enables data to be output to the flash memory 100.

  The address buffer 120 receives an address given from a CPU (not shown) and outputs it to the address register 130.

  The data input / output circuit 90 receives write data supplied from a CPU (not shown) and transfers it to the write data buffer 70. The data amplified by the sense amplifier 80 is continuously output to the CPU in synchronization with the clock.

  The address register 130 outputs the column address CA to the column decoder 40 and outputs the row address RA to the row decoder 30 according to the address given from the address buffer 120.

  The column decoder 40 and the row decoder 30 perform the selection operation of the bit line BL and the word line WL based on the column address CA and the row address RA, respectively.

  The voltage generation circuit 140 generates a voltage according to the setting. The voltage generated by the voltage generation circuit 140 is supplied to, for example, the row decoder 30, the memory cell array 10, the write data buffer 70, the sense amplifier 80, and the like.

  The power supply circuit 150 supplies the generated voltage to the data input / output circuit 90. The data input / output circuit 90 operates using the voltage V generated by the power supply circuit 22 as the power supply voltage. The control circuit 160 controls the circuit operation described above.

  As shown in FIG. 2, the memory cell array 10 includes a plurality of memory cells MCmn (m and n are natural numbers) arranged in the first direction and the second direction. The memory cell MCmn is composed of a memory transistor MTmn having a floating gate electrode FG and a control gate electrode CG.

  The memory cell array 10 constituting the flash memory 100 according to the first embodiment is formed of a NOR type as shown in FIG. The NOR type memory cell array 10 has the following configuration.

  The drains 11 of the plurality of memory transistors MTmn formed along the first direction are shared with the memory transistor MTm-1n and connected to the bit line BLn.

  The sources 12 of the plurality of memory transistors MTmn formed along the second direction are connected to a common source line SL, and another memory transistor MTm + 1n (not shown) is provided above the common source line SL. Are formed so as to share the source line SL. The control gate electrodes CG of the plurality of memory transistors MTmn formed along the second direction are commonly connected by the word line WLm.

  FIG. 2 shows an example of m = 2 and n = 3.

  When writing to the memory transistor MTmn, the bit line BLn is selected by the column decoder, the word line WLm is selected by the row decoder (not shown in FIG. 2), and the write voltage applied from the write data buffer 70 (not shown in FIG. 2) is applied. The voltage is applied to the gate electrode and drain electrode 11 of the memory transistor MTmn.

  Due to the write voltage, the charges that have become hot carriers move to the floating gate electrode FG of the memory transistor MTmn. Then, the charge is accumulated in the floating gate electrode FG, so that the threshold voltage of the memory transistor MTmn is increased.

  A state in which the threshold voltage of the memory transistor MTmn is increased is a “0” data state, and a state in which the threshold voltage of the memory transistor MTmn is decreased is a “1” data state. Therefore, in the flash memory 100 according to the present embodiment, data “1” and “0” are determined by the presence or absence of the electric charge accumulated in the floating gate electrode.

[Specific Configuration of Flash Memory 100 According to First Embodiment]
FIG. 3A is a top view of the memory cell array 10 according to the first embodiment shown in FIG. 3B is a cross-sectional view taken along the line AA in FIG. 3A. 3C is a cross-sectional view taken along line BB in FIG. 3A.

  As shown in FIG. 3A, two control gate electrodes CG extend in the second direction in the drawing. An element isolation region 31 extends in a first direction in the drawing orthogonal to the second direction, and separates the semiconductor substrate 20 into a plurality of element regions. A memory cell transistor MT is formed at the intersection of the element region and the control gate electrode CG. A source contact 29 extending in the second direction is disposed between the control gate electrodes CG, and commonly connects the sources 12 of the memory cell transistors MT. A drain contact 28 is formed at each drain 31 of the memory cell transistor MT.

  As shown in FIG. 3B, the memory cell array 10 forming the flash memory 100 according to the first embodiment includes a semiconductor substrate 20, a first insulating film (insulating film) 23, a floating gate electrode FG, a control gate electrode CG, It has an insulating layer 24, a second insulating film (inter-gate insulating film) 25, a third insulating film 26, and an interlayer insulating layer 27 (not shown in FIG. 3A).

  In the semiconductor substrate 20, a plurality of impurity diffusion regions 21 and impurity regions 22 formed so as to connect adjacent impurity diffusion regions 21 are formed.

The impurity diffusion region 21 is formed of, for example, an n ⁺ type and includes a drain 11 and a source 12. A drain contact 28 is formed on the drain 11 so as to extend in the stacking direction, and a source contact 29 is formed on the source 12 so as to extend in the stacking direction. The drain contact 28 is connected to the bit line BL (not shown in FIGS. 3A to 3C). Source contact 29 is connected to source line SL (not shown in FIGS. 3A to 3C).

The impurity region 22 is formed, for example, of a p ⁻ type and functions as a channel between the drain 11 and the source 12.

  The floating gate electrode FG is formed on the semiconductor substrate 20 between the adjacent impurity diffusion regions 21 (drain 11 and source 12) via the first insulating film 23, and has a function of accumulating charges.

  The first insulating film 23 is formed on the semiconductor substrate 20 and functions as a tunnel oxide film. Therefore, the charge accumulated in the floating gate electrode FG of the memory transistor MTmn can be held by the first insulating film 23 (tunnel oxide film) even when power is not supplied to the flash memory 100.

  As shown in FIG. 3B, the control gate electrode CG is formed so as to be in contact with the upper and upper surfaces of both side surfaces in the first direction of the floating gate electrode FG via the second insulating film 25. In other words, the control gate electrode CG is formed so as to cover the floating gate electrode FG via the second insulating film 25. In the first embodiment, the bottom surface portion of the control gate electrode CG formed on both side surfaces of the floating gate electrode FG is formed so as not to reach the first insulating film 23 formed on the semiconductor substrate 20. An insulating layer 24 is formed between the control gate electrode CG and the first insulating film 23 formed on the semiconductor substrate 20.

The second insulating film 25 is formed not only between the floating gate electrode FG and the control gate electrode CG but also between the bottom surface portion of the control gate electrode CG and the insulating layer 24. The second insulating film 25 is, for example, a silicon oxide film, or a laminated structure of a silicon oxide film and a silicon nitride film, an ON film, a NO film, an ONO film, a NONON film, a NOAON film (A is Al ₂ O ₃ or the like High dielectric film).

  The third insulating film 26 is formed on the upper surface and both side surfaces of the control gate electrode CG and the first insulating film 23.

  The interlayer insulating layer 27 (not shown in FIG. 3A) is formed so as to fill a gap on the semiconductor substrate 20 as shown in FIG. 3B.

  The characteristics of the flash memory 100 are as follows: the contact area between the semiconductor substrate 20 and the floating gate electrode FG of the memory transistor MTmn constituting the flash memory 100, the thickness of the tunnel oxide film (first insulating film), and the control with the floating gate electrode FG. It is influenced by the contact area with the gate electrode and the thickness of the second insulating film 25.

  The main characteristics of flash memory are program speed, erase speed, and the like. Further, the reliability-related characteristics include program / erase repetition characteristics and data retention characteristics.

Programming speed and erase speed, a capacitance (C ₁₎ between the semiconductor substrate and the floating gate electrode, the ratio of the capacitance (C ₂₎ between the floating gate electrode and control gate electrode (hereinafter, a coupling ratio Determined).

Here, the coupling ratio, the capacitance between the semiconductor substrate and the floating gate electrode (C _1), the capacitance between the floating gate electrode and control gate electrode (C ₂₎ and using, as follows It is known that it can be represented.

Coupling ratio = C ₂ / (C ₁ + C ₂ ) (1)
Or to obtain a fast programming speed and erase speed at a constant operating voltage, it is necessary to ensure a high coupling ratio, the order to achieve it, to reduce the C ₁ as shown in equation (1) , C ₂ needs to be increased.

In the first embodiment, in order to increase the C _2, rather than the control gate electrode CG only the upper surface of the floating gate electrodes are formed also on both sides. Thereby, the contact area between the floating gate electrode FG and the control gate electrode is increased, the coupling ratio is improved, and the program speed and the erase speed can be increased.

  In the first embodiment, the insulating layer 24 is formed between the lower surface of the control gate electrode CG formed on the side surface of the floating gate electrode FG and the drain 11 and the source 12 formed in the semiconductor substrate 20. Therefore, it is possible to prevent deterioration of the durability of the control gate electrode CG. The thickness of the insulating layer 24 is set to such a thickness that the second insulating film 25 is not destroyed even when the maximum voltage necessary for device operation is applied to the control gate electrode CG.

[Method of Manufacturing Flash Memory 100 According to First Embodiment]
Next, a method for manufacturing the flash memory 100 according to the first embodiment shown in FIGS. 3A to 3C will be described with reference to FIGS. 4A to 19A and FIGS. 4B to 19B. 4A to 19A are manufacturing flows of the AA cross section of FIG. 3A, and FIGS. 4B to 19B are manufacturing flows of the BB cross section of FIG. 3A. An example of self alignment using a pattern formed on the semiconductor substrate 20 as a mask will be described.

  Impurities are implanted into the semiconductor substrate 20 to form impurity regions 22 (channel regions) (FIGS. 4A and 4B).

  Next, the first insulating film 23 is formed on the surface of the semiconductor substrate 100 by using a plasma CVD (Chemical Vapor Deposition) method, a thermal CVD method, a photo CVD method, or the like (FIGS. 5A and 5B).

  Subsequently, a conductive layer 101 to be the floating gate electrode FG is deposited on the first insulating film (FIGS. 6A and 6B).

  Thereafter, a stopper material (for example, a silicon nitride film) 102 is deposited on the conductive layer 101 (FIGS. 7A and 7B). Note that the conductive layer 101 and the stopper material 102 can also be formed by using a plasma CVD method, a thermal CVD method, a photo CVD method, or the like, like the first insulating film 23.

  Further, using a resist pattern (not shown), the conductive layer 101 and the stopper material 102 are etched by an anisotropic etching technique or the like to form a pattern of the floating gate electrode FG (FIGS. 8A and 8B).

  Then, an n-type impurity such as phosphorus is implanted using the floating gate electrode FG as a mask to form the impurity diffusion region 21 (drain 11 / source 12) (FIGS. 9A and 9B). In the first embodiment, the impurity is not injected after the floating gate electrode FG and the control gate electrode CG are stacked, but the impurity is injected when only the floating gate electrode FG is stacked as described above. Therefore, since the impurity is implanted at a stage where the thickness of the pattern used as a mask is thinner than the case where the impurity is implanted after the two-layer gate electrodes (floating gate electrode FG and control gate electrode CG) are stacked, the floating gate electrode FG And the impurity diffusion region 21 can be formed with little positional deviation.

  Next, the insulating layer 24 is deposited on the entire surface of the semiconductor substrate 20 by using a plasma CVD method, a thermal CVD method, a photo CVD method, or the like (FIGS. 10A and 10B).

  Subsequently, the insulating layer 24 is polished to the height of the stopper material 102 by using a CMP method (Chemical Mechanical Polishing) (FIGS. 11A and 11B).

  Thereafter, the stopper material 102 is removed using an etching technique (FIGS. 12A and 12B).

  Further, the element isolation region 31 is formed using an STI (Shallow Trench Isolation) technique or the like (FIGS. 13A and 13B). The upper surface of the element isolation region 31 is adjusted to be lower than the upper surface of the floating gate electrode FG.

  Then, the insulating layer 24 is etched to be lower than the floating gate electrode FG using an anisotropic etching technique (FIGS. 14A and 14B). This step can be performed simultaneously with the formation of the element isolation region 31. In this case, the element isolation region 31 is formed before the insulating layer 24 is deposited (before FIG. 10) or before the pattern of the floating gate electrode FG is formed (before FIG. 8).

  Next, a second insulating film (inter-gate insulating film) 25 is formed on the entire surface of the semiconductor substrate 20 (FIGS. 15 and 15B).

  Subsequently, a conductive layer 103 to be the control gate electrode CG is deposited on the second insulating film 25 (FIGS. 16A and 16B). Note that the second insulating film and the conductive layer 103 can be formed by a plasma CVD method, a thermal CVD method, a photo CVD method, or the like.

  Thereafter, using a resist pattern (not shown), the conductive layer 103 and the second insulating film 25 are etched by an anisotropic etching technique or the like to form a pattern of the control gate electrode CG and the second insulating film 25 (FIG. 17A, FIG. 17B).

  Further, a third insulating film 26 is formed on the entire surface of the semiconductor substrate 20 by using a plasma CVD method, a thermal CVD method, a photo CVD method, or the like (FIGS. 18A and 18B).

  Then, an interlayer insulating layer 27 is deposited on the third insulating layer 26 using a plasma CVD method, a thermal CVD method, a photo CVD method, or the like, and then the upper surface is flattened using a CMP method (FIGS. 19A and 19B). .

  As described above, according to the manufacturing method of the first embodiment, the impurity is implanted when the gate serving as the mask is low, so that the positional deviation between the floating gate electrode FG and the impurity diffusion region 21 is reduced. be able to. Furthermore, since the contact area between the floating gate electrode FG and the control gate electrode CG is formed using the side surface of the floating gate electrode FG, the coupling ratio can be improved.

  Further, by forming the insulating layer 24 between the control gate electrode CG and the semiconductor substrate 20, it is possible to prevent dielectric breakdown between the control gate electrode and the semiconductor substrate 20 even when a high voltage is applied to the control gate electrode CG. it can.

[Specific Configuration of Flash Memory 100 According to Second Embodiment]
FIG. 20A is a top view of the flash memory 100 according to the second embodiment. 20B is a cross-sectional view taken along the line AA in FIG. 20A. 20C is a cross-sectional view taken along the line BB of FIG. 20A. 20A to 20C, the same reference numerals are given to the same portions as those in the first embodiment. Hereinafter, description of the same parts as those of the first embodiment will be omitted. The memory cell array 10 constituting the flash memory 100 according to the second embodiment is also formed of a NOR type as in the first embodiment.

  As shown in FIG. 20B, the configuration of the second embodiment is such that the second insulating film 25 is formed from the upper surface of the floating gate electrode FG and the side surface in the first direction to the upper surface of the first insulating film 23, and is floating. The side surface portion in the first direction of the control gate electrode CG formed so as to cover the gate electrode FG is formed so as to reach the surface of the second insulating film 25 formed on the first insulating film 23. That is, the control gate electrode CG is formed so as to cover almost the entire upper surface and side surfaces of the floating gate electrode FG. Therefore, the insulating layer 24 formed in the first embodiment is not formed in the second embodiment.

  The configuration of the flash memory 100 according to the second embodiment is different from that of the first embodiment only in the above points, and is otherwise the same as that of the first embodiment.

  As described in the first embodiment, the thickness required for the insulating layer 24 is determined by the breakdown voltage of the second insulating film 25. Therefore, depending on the relationship between the maximum voltage applied to the control gate electrode CG and the breakdown voltage of the second insulating film, the insulating layer 24 may be unnecessary. The second embodiment shown in FIGS. 20A to 20C is an embodiment in which the insulating layer 24 as described above is unnecessary.

  The configuration of the second embodiment is formed so that the side surface portion of the control gate electrode CG reaches the surface of the second insulating film 25 formed on the upper surface of the first insulating film 23 as described above. Therefore, in the second embodiment, the contact area between the floating gate electrode FG and the control gate electrode CG is formed to be larger than that of the configuration of the first embodiment, so that the coupling ratio is higher than that of the first embodiment. Highly formed.

[Method of Manufacturing Flash Memory 100 According to Second Embodiment]
Next, a method for manufacturing the flash memory 100 according to the second embodiment shown in FIGS. 20A to 20C will be described with reference to FIGS. 21A to 26A and FIGS. 21B to 26B. FIGS. 21A to 26A are manufacturing flows of the AA cross section of FIG. 20A, and FIGS. 21B to 26B are manufacturing flows of the BB cross section of FIG. 20A. In FIGS. 21A to 26A and FIGS. 21B to 26B, the same parts as those of the first embodiment are denoted by the same reference numerals. In addition, as in the first embodiment, self alignment using a pattern formed on the semiconductor substrate 20 as a mask will be described as an example, and the same steps as those in the first embodiment will be described. Omitted.

  The steps from FIG. 4A to FIG. 6A and FIG. 4B to FIG.

  Next, the element isolation region 31 is formed using the STI technique or the like (FIGS. 21A and 21B). The upper surface of the element isolation region 31 is adjusted to be lower than the upper surface of the floating gate electrode FG.

  Subsequently, using a resist pattern (not shown), the conductive layer 101 is etched by an anisotropic etching technique or the like to form a pattern of the floating gate electrode FG (FIGS. 22A and 22B).

  Thereafter, an n-type impurity such as phosphorus is implanted using the floating gate electrode FG as a mask to form an impurity diffusion region 21 (drain 11 / source 12) (FIGS. 23A and 23B). In the second embodiment, as in the first embodiment, the floating gate electrode FG and the control gate electrode CG are not stacked and then impurities are not implanted, but only the floating gate electrode FG is stacked as described above. Impurities are implanted at this stage. Therefore, since the impurity is implanted at a stage where the thickness of the mask pattern is thinner than when the impurity is implanted after the two layers of gate electrodes (floating gate electrode FG and control gate electrode CG) are stacked, the floating gate electrode FG And the impurity diffusion region 21 can be formed with little positional deviation.

  Further, a second insulating film 25 is formed on the entire surface of the semiconductor substrate 20 (FIGS. 24A and 24B).

  Then, a conductive layer 103 to be the control gate electrode CG is deposited on the second insulating film 25 (FIGS. 25A and 25B). Note that the second insulating film 25 and the conductive layer 103 can be formed by a plasma CVD method, a thermal CVD method, a photo CVD method, or the like.

  Next, using a resist pattern (not shown), the conductive layer 103 and the second insulating film 25 are etched by an anisotropic etching technique or the like to form a pattern of the control gate electrode CG and the second insulating film 25 (FIG. 26A, FIG. 26B).

  Since the subsequent steps are the same as those of the first embodiment (FIGS. 18A to 19A and 18B to 19B), the description thereof is omitted.

  As described above, according to the manufacturing method of the second embodiment, impurities are implanted when the gate serving as a mask is low, so that the positional deviation between the floating gate electrode FG and the impurity diffusion region 21 is reduced. be able to. Further, since the contact area between the floating gate electrode FG and the control gate electrode CG is formed using the side surface of the floating gate electrode FG, the coupling ratio can be improved as compared with the first embodiment.

[Specific Configuration of Flash Memory 100 According to Third Embodiment]
FIG. 27A is a top view of the flash memory 100 according to the third embodiment. 27B is a cross-sectional view taken along line AA in FIG. 27A. 27C is a cross-sectional view taken along the line BB of FIG. 27A. In FIGS. 27A to 27C, the same parts as those in the first embodiment are denoted by the same reference numerals. Hereinafter, description of the same parts as those of the first embodiment will be omitted. The memory cell array 10 constituting the flash memory 100 according to the third embodiment is also formed of a NOR type as in the first embodiment.

  As shown in FIG. 27B, in the third embodiment, the impurity diffusion region 21 includes a first impurity diffusion region 21A and a second impurity diffusion region 21B. Furthermore, the floating gate electrode FG includes a lower floating gate electrode FG1 and an upper floating gate electrode FG2 formed wider in the first direction than the lower floating gate electrode FG1 and formed on the upper surface of the lower floating gate electrode FG1. . In addition, spacer insulating films 104 are formed on both side surfaces of the lower floating gate electrode FG1 in the first direction. The control gate electrode CG is not formed so as to cover the floating gate electrode FG, is formed with the same width as the upper floating gate electrode FG2 in the first direction, and is stacked via the second insulating film 25. Hereinafter, the shapes of the floating gate electrode FG and the control gate electrode CG of the present embodiment are referred to as “T type” for convenience of description.

  The configuration of the flash memory 100 according to the third embodiment is different from that of the first embodiment only in the above points, and is otherwise the same as that of the first embodiment.

  As shown in FIG. 27B, the first impurity diffusion region 21A is formed so as to be aligned with the lower floating gate electrode, and becomes an extension portion of an LDD (Lightly Doped Drain) structure.

  The second impurity diffusion region 21B is formed so as to be aligned with the spacer insulating film and serves as the drain 11 or the source 12.

  The impurity concentration (first impurity concentration) of the first impurity diffusion region 21A is formed to be lower than the impurity concentration (second impurity concentration) of the second impurity diffusion region 21B. As described above, the LDD structure in which the first impurity diffusion region 21A having a low impurity concentration is disposed at the boundary between the drain 11 or the source 12 and the floating gate electrode FG has an effect of suppressing the short channel effect of the transistor. .

  Further, as shown in FIG. 27B, in the third embodiment, the control gate electrode CG is formed on the upper floating gate electrode FG2 having a large width.

  Thus, by forming the floating gate electrode FG and the control gate electrode in the “T type”, the spacer insulating film 104 necessary for forming the LDD structure is formed in the “T” umbrella. No need to remove. That is, the end of the spacer insulating film 104 opposite to the side in contact with the lower floating gate electrode FG1 is inside the end of the upper floating gate electrode FG2. Therefore, the limitation that the spacer insulating film 104 must be formed using a material that can be easily removed is eliminated, and the material selectivity of the spacer insulating film 104 can be widened.

  As described above, the third embodiment can suppress the short channel effect, reduce the number of manufacturing steps, and widen the material selectivity.

[Manufacturing Method of Flash Memory 100 According to Third Embodiment]
Next, a method for manufacturing the flash memory 100 according to the third embodiment shown in FIGS. 27A to 27C will be described with reference to FIGS. 28A to 39A and FIGS. 28B to 39B. FIGS. 28A to 39A are manufacturing flows of the AA cross section of FIG. 27A, and FIGS. 28B to 39B are manufacturing flows of the BB cross section of FIG. 27A.
In FIGS. 28A to 39A and FIGS. 28B to 39B, the same parts as those in the first embodiment are denoted by the same reference numerals. In addition, as in the first embodiment, self alignment using a pattern formed on the semiconductor substrate 20 as a mask will be described as an example, and the same steps as those in the first embodiment will be described. Omitted.

  The steps from FIG. 4A to FIG. 8A and FIG. 4B to FIG. However, in the third embodiment, the lower floating gate electrode FG1 is formed on the first insulating film 23 in the steps shown in FIGS. 8A and 8B.

Next, using the lower floating gate electrode FG1 as a mask, an n-type impurity such as phosphorus is implanted to form a first impurity diffusion region 21A (FIGS. 28A and 28B). The first impurity diffusion region 21A has a low concentration of phosphorus or the like to be implanted, or the implantation time is shortened so that it becomes an n ⁻ -type impurity diffusion region with a low impurity concentration (first impurity concentration). Done.

  Subsequently, a spacer insulating film 104 (for example, silicon nitride) is deposited on the entire surface of the semiconductor substrate 20 using a plasma CVD method, a thermal CVD method, a photo CVD method, or the like (FIGS. 29A and 29B).

  Thereafter, the spacer insulating film 104 is etched by an anisotropic etching technique or the like to form the spacer insulating film 104 on the side surface of the lower floating gate electrode FG1 (FIGS. 30A and 30B).

Further, using the lower floating gate electrode FG1 and the spacer insulating film 104 as a mask, an n-type impurity such as phosphorus is implanted to form a second impurity diffusion region 21B (drain 11 / source 12) (FIGS. 31A and 31B). The second impurity diffusion region 21B is an n ⁺ -type impurity diffusion region in which the impurity concentration (second impurity concentration) is higher than the impurity concentration (first impurity concentration) of the first impurity diffusion region 21A. The concentration of phosphorus or the like to be injected is increased, or the injection time is lengthened.

  In the third embodiment, as in the first embodiment, the floating gate electrode FG and the control gate electrode CG are not stacked and then impurities are not implanted, but only the floating gate electrode FG is stacked as described above. Impurities are implanted at this stage. Therefore, since the impurity is implanted at a stage where the thickness of the mask pattern is thinner than when the impurity is implanted after the two layers of gate electrodes (floating gate electrode FG and control gate electrode CG) are stacked, the floating gate electrode FG And the impurity diffusion region 21 can be formed with little positional deviation.

  Then, an insulating layer 24 is deposited on the entire surface of the semiconductor substrate 20 by using a plasma CVD method, a thermal CVD method, a photo CVD method, or the like (FIGS. 32A and 32B).

  Next, the insulating layer 24 is polished to the height of the stopper material 102 using CMP (FIGS. 33A and 33B).

  Subsequently, the stopper material 102 is removed by using an etching technique (FIGS. 34A and 34B).

  Thereafter, a conductive layer 105 to be the upper floating gate electrode FG2 is deposited on the entire surface of the semiconductor substrate 20 by using a plasma CVD method, a thermal CVD method, a photo CVD method, or the like (FIGS. 35A and 35B).

  Further, the element isolation region 31 is formed by using the STI technique or the like (FIGS. 36A and 36B). The upper surface of the element isolation region 31 is adjusted to be lower than the upper surface of the upper floating gate electrode FG2. Further, the upper surface of the element isolation region 31 can be made lower than the upper surface of the lower floating gate electrode FG1.

  Then, a second insulating film (inter-gate insulating film) 25 is formed on the entire surface of the semiconductor substrate 20 (FIGS. 37A and 37B).

  Next, a conductive layer 103 to be the control gate electrode CG is deposited on the second insulating film 25 (FIGS. 38A and 38B). Note that the second insulating film 25 and the conductive layer 103 can be formed by a plasma CVD method, a thermal CVD method, a photo CVD method, or the like.

  Subsequently, the conductive layers 103 and 105 and the second insulating film 25 are etched by an anisotropic etching technique or the like using a resist pattern (not shown), and the upper floating gate electrode FG2, the control gate electrode CG, and the second insulating film 25 are etched. Pattern is formed (FIGS. 39A and 39B).

  Since the subsequent steps are the same as those of the first embodiment (FIGS. 18A to 19A and 18B to 19B), the description thereof is omitted.

  As described above, according to the manufacturing method of the third embodiment, since the impurity is implanted when the gate serving as the mask is low, the misalignment between the floating gate electrode FG and the impurity diffusion region 21 is reduced. be able to. In addition, since the floating gate electrode and the control gate electrode are formed in a T shape, it is not necessary to remove the spacer insulating film 104, and the manufacturing process can be reduced and the material selectivity can be increased. Furthermore, since it is formed with an LDD structure, the short channel effect can be suppressed.

[Others]
Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various changes, substitutions, and the like are possible without departing from the spirit of the invention. For example, in the above embodiment, the flash memory 100 is formed in the NOR type. However, the nonvolatile semiconductor memory device according to the present invention includes a NAND type, a DINOR type (not shown), and an AND type as shown in FIG. (Not shown) may be used.

1 is a block diagram showing a configuration of a main part of a nonvolatile semiconductor memory device 100 according to an embodiment of the present invention. 2 is a partial circuit diagram of a memory cell array 10 included in the nonvolatile semiconductor memory device 100. FIG. FIG. 3 is a partial top view of the memory cell array 10 shown in FIG. 2. It is AA sectional drawing of FIG. 3A. It is BB sectional drawing of FIG. 3A. FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). FIG. 6A is a diagram showing the manufacturing method of the same nonvolatile semiconductor memory device 100 (AA sectional view). FIG. 3B is a diagram showing the method for manufacturing the same nonvolatile semiconductor memory device 100 (B-B cross-sectional view). 4 is a partial top view of a memory cell array 10 included in a nonvolatile semiconductor memory device 100 according to a second embodiment. FIG. It is AA sectional drawing of FIG. 20A. It is BB sectional drawing of FIG. 20A. It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 2nd Embodiment (BB sectional drawing). FIG. 6 is a partial top view of a memory cell array 10 included in a nonvolatile semiconductor memory device 100 according to a third embodiment. It is AA sectional drawing of FIG. 27A. It is BB sectional drawing of FIG. 27A. It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (AA sectional drawing). It is a figure which shows the manufacturing method of the non-volatile semiconductor memory device 100 of 3rd Embodiment (BB sectional drawing). 3 is a diagram showing another configuration of the memory cell array 10. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Memory cell array, 11 ... Drain, 12 ... Source, 20 ... Semiconductor substrate, 21 ... Impurity diffusion region, 21A ... Low concentration impurity diffusion region, 21B ... High concentration impurity diffusion region, 22 ... Impurity region (channel), DESCRIPTION OF SYMBOLS 23 ... 1st insulating film, 24 ... Insulating layer, 25 ... 2nd insulating film, 26 ... 3rd insulating film, 27 ... Interlayer insulating layer, 28 ... Drain contact, 29 ... Source contact, 30 ... Row decoder, 31 ... Element Separation region, 40 ... column decoder, 50 ... address buffer, 60 ... read circuit, 70 ... output buffer, 80 ... write circuit, 90 ... input buffer, 100 ... flash memory, 101, 103, 105 ... conductive layer, 102 ... stopper Material 104: spacer insulating film.

Claims (5)

A semiconductor substrate;
A plurality of impurity diffusion regions formed in the semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A floating gate electrode formed on the semiconductor substrate between the adjacent impurity diffusion regions via the insulating film;
An inter-gate insulating film formed on an upper surface and a side surface of the floating gate;
A non-volatile semiconductor memory device comprising: a control gate electrode formed so as to be in contact with an upper surface and both side surfaces of the floating gate electrode through the inter-gate insulating film. An insulating layer is formed between a bottom surface portion of the control gate electrode formed on both side surfaces of the floating gate electrode and the insulating film on the semiconductor substrate,
The nonvolatile semiconductor memory device according to claim 1, wherein the inter-gate insulating film is formed between a bottom surface portion of the control gate electrode and the insulating layer. The nonvolatile semiconductor memory device according to claim 1, wherein the inter-gate insulating film is formed between the insulating film on the semiconductor substrate and a bottom surface of the control gate electrode. A semiconductor substrate;
A plurality of impurity diffusion regions formed in the semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A lower floating gate electrode formed on the semiconductor substrate between the adjacent impurity diffusion regions via the insulating film;
An upper floating gate electrode formed wider than the lower floating gate electrode and formed on the upper surface of the lower floating gate electrode;
An intergate insulating film formed on the upper surface of the upper floating gate electrode;
Spacer insulating films formed on both side surfaces of the lower floating gate electrode;
A control gate electrode formed so as to be in contact with the upper surface of the upper floating gate electrode via the inter-gate insulating film,
The impurity diffusion region comprises a first impurity diffusion region having a first impurity concentration and a second impurity diffusion region having a second impurity concentration higher than the first impurity concentration.
The first impurity diffusion region is formed to match the lower floating gate electrode,
The non-volatile semiconductor memory device, wherein the second impurity diffusion region is formed so as to be aligned with the spacer insulating film. Forming a floating gate electrode on a semiconductor substrate;
Forming an impurity diffusion region by implanting impurities into the semiconductor substrate using the floating gate electrode as a mask;
Depositing an insulating layer on the semiconductor substrate and on the floating gate electrode;
Processing the insulating layer to be lower than the upper surface of the floating gate electrode;
Forming an inter-gate insulating film on the entire surface of the semiconductor substrate;
Forming a control gate electrode on the inter-gate insulating film;
Etching the control gate electrode and the inter-gate insulating film to form a pattern of the control electrode and the inter-gate insulating film. A method for manufacturing a nonvolatile semiconductor memory device, comprising:

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