JP2010073542A - Flat-surface display and spacer - Google Patents

Abstract

A flat display device having a configuration and structure capable of reducing a relative luminance change of pixels along a spacer is provided.
A flat panel display device includes an anode panel AP and a cathode panel CP joined at an outer periphery, and a spacer 40 is disposed between the anode panel AP and the cathode panel CP. A spacer base 41 having a height H ₀ having a first end face on the anode panel side and a second end face on the cathode panel side, and an antistatic film 43, the antistatic film 43 on the side surface of the spacer base 41, Region from the first end face to the distance H ₁ (where H ₁ is a distance with respect to the first end face, and is 0.6H ₀ ≦ H ₁ ≦ 0.9H ₀ , preferably 0.7H ₀ ≦ H ₁ ≦ 0.9H ₀ ).
[Selection] Figure 1

Description

  The present invention relates to a spacer used in a flat display device and a flat display device in which such a spacer is incorporated.

  As an image display device that can replace the mainstream cathode ray tube (CRT), various types of flat display devices have been studied. Examples of such a flat display device include a liquid crystal display device (LCD), an electroluminescence display device (ELD), and a plasma display device (PDP). In addition, development of a flat display device incorporating a cathode panel equipped with an electron-emitting device is also in progress. Here, as the electron-emitting device, a cold cathode field electron-emitting device, a metal / insulating film / metal-type device (also called MIM device), and a surface conduction electron-emitting device are known. A flat display device incorporating a cathode panel provided with the electron-emitting device is attracting attention from the viewpoint of high resolution, high-speed response, high-luminance color display, and low power consumption.

  A cold cathode field emission display device (hereinafter sometimes abbreviated as “display device”), which is a flat display device incorporating a cold cathode field emission device as an electron emission device, generally has a plurality of cold cathode field fields. A cathode panel provided with an electron-emitting device (hereinafter sometimes abbreviated as “field-emitting device”), and an anode panel having a phosphor region that emits light when excited by collision with electrons emitted from the field-emitting device; However, it has a configuration in which the cathode panel and the anode panel are joined to each other through a joining member at the peripheral edge portion through a space maintained at a high vacuum. Here, the cathode panel has electron emission regions corresponding to the sub-pixels arranged in a two-dimensional matrix, and each electron emission region is provided with one or a plurality of field emission elements. Examples of field emission devices include Spindt type, flat type, edge type, and planar type.

  As an example, FIG. 12 shows a schematic partial end view of a typical display device having a Spindt-type field emission device, and a part of the cathode panel CP and the anode panel AP when the cathode panel CP and the anode panel AP are disassembled. FIG. 3 shows a schematic exploded perspective view. The Spindt-type field emission device constituting this display device was formed on the cathode 10 formed on the support 10, the insulating layer 12 formed on the support 10 and the cathode 11, and the insulating layer 12. A gate electrode 13 and an opening 14 provided in the gate electrode 13 and the insulating layer 12 (a first opening 14A provided in the gate electrode 13 and a second opening 14B provided in the insulating layer 12); It is composed of a conical electron emission portion 15 formed on the cathode electrode 11 located at the bottom of the opening 14. An interlayer insulating layer 16 is formed on the insulating layer 12, and a focusing electrode 17 is formed on the interlayer insulating layer 16.

  In this display device, the cathode electrode 11 has a strip shape extending in the column direction (Y direction), and the gate electrode 13 has a strip shape extending in a row direction (X direction) different from the Y direction. In general, the cathode electrode 11 and the gate electrode 13 are formed in directions in which the projected images of both the electrodes 11 and 13 are orthogonal to each other. An overlapping region where the strip-shaped cathode electrode 11 and the strip-shaped gate electrode 13 overlap is an electron emission region EA. The electron emission area EA is an effective area EF of the cathode panel CP (a central display area that performs a display function, which is a practical function as a flat display device), and the invalid area NF corresponds to the effective area EF. They are usually arranged in a two-dimensional matrix within the outer area and surrounding the effective area EF in a frame shape.

  On the other hand, the anode panel AP has phosphor regions 22 having a predetermined pattern on the substrate 20 (specifically, a red light-emitting phosphor region 22R, a green light-emitting phosphor region 22G, and a blue light-emitting phosphor region 22B). The phosphor region 22 is formed and covered with the anode electrode 24. In addition, a space between these phosphor regions 22 is embedded with a light absorbing layer (black matrix) 23 made of a light absorbing material such as carbon to prevent the occurrence of color turbidity and optical crosstalk in the display image. ing. Further, each of the phosphor regions 22 is surrounded by the partition walls 21, and the planar shape of the partition walls 21 is a lattice shape (cross-beam shape). In the figure, reference numeral 140 represents a spacer extending in the row direction (X direction), reference numeral 25 represents a spacer holding portion, and reference numeral 26 represents a joining member. In FIG. 3, the illustration of the partition walls and the spacers is omitted.

One subpixel is constituted by an electron emission area EA on the cathode panel side and a phosphor area 22 on the anode panel side facing (facing to) the electron emission area EA. In the effective area EF, pixels (pixels) are arranged on the order of hundreds of thousands to millions, for example. In a display device for color display, one pixel (one pixel) includes a set of a red light emitting subpixel, a green light emitting subpixel, and a blue light emitting subpixel. Then, the anode panel AP and the cathode panel CP are arranged so that the electron emission region EA and the phosphor region 22 are opposed to each other, joined at the peripheral portion via the joining member 26, and then exhausted and sealed. Thus, a display device can be manufactured. A space SP surrounded by the anode panel AP, the cathode panel CP, and the bonding member 26 is in a high vacuum (for example, 1 × 10 ⁻³ Pa or less). Therefore, unless the spacer 140 is disposed between the anode panel AP and the cathode panel CP, the display device is damaged by the atmospheric pressure. The spacer 140 includes a spacer base material 141 and an antistatic film 143 formed on the side surface of the spacer base material 141.

  The spacer base material 141 constituting the conventional spacer 140 is made of ceramics such as mullite, alumina, barium titanate, or a high resistance rigid material such as glass. Both ends of the spacer 140 are in contact with the anode electrode 24 and the focusing electrode 17, respectively. Therefore, a potential difference (voltage) between the voltage applied to the anode electrode 24 and the voltage applied to the focusing electrode 17 is applied between both ends of the spacer 140. Depending on the type of the display device, the cathode panel side of the spacer 140 is in contact with the gate electrode 13. In this case, a potential difference (voltage) between the voltage applied to the anode electrode and the voltage applied to the gate electrode is applied between both ends of the spacer 140. Therefore, the spacer 140 is basically required to have a high resistance so that an excessive current does not flow through the spacer 140. Further, the potential difference (voltage) at both ends of the spacer 140 needs to be divided equally between both ends of the spacer 140. Therefore, it is preferable that the specific resistance of the high-resistance rigid material constituting the spacer base material 141 is a value within a predetermined range and is as uniform as possible. For example, JP 2003-524280 A discloses various ceramic materials as the high resistance rigid material.

13A and 13B schematically show the trajectory of the electron beam in the pixel located in the vicinity of the spacer 140. FIG. As shown in FIG. 13A, the electrons emitted from the electron emission unit 15 go to the phosphor region 22. Then, a part of the electrons that have passed through the anode electrode 24 in the anode panel AP and collided with the phosphor region 22 are scattered backward by the phosphor region 22. Hereinafter, these electrons are referred to as “backscattered electrons”. Some of the backscattered electrons collide with the side surface of the spacer 140 (see FIG. 13B). When electrons collide with the side surface of the spacer 140, secondary electrons are emitted from the surface. When there is a difference between the amount of electrons colliding with the spacer 140 and the amount of secondary electrons emitted from the spacer 140, the spacer 140 is charged and affects the trajectory of the electrons. Therefore, an antistatic film 143 made of a material having a secondary electron emission coefficient close to 1, for example, an antistatic film 143 made of CrO _x is provided on the side surface of the spacer base material 141. Other materials that make up the antistatic film 143 (materials whose secondary electron emission coefficient is close to 1) include semimetals such as graphite, oxides, borides, carbides, sulfides, and nitrides. For example, various materials are disclosed in JP-T-2004-500688.

Special table 2003-524280 gazette JP-T-2004-500688

  By the way, a part of the antistatic film 143 is scattered and scattered by heat treatment in the manufacturing process of the display device (for example, heat treatment when the anode panel AP and the cathode panel CP are joined through the joining member 26 at the peripheral portion). The material constituting the antistatic film 143 adheres to the electron emission portion 15 located in the vicinity of the spacer 140. As a result, there is a problem that the electron emission characteristics from the electron emission portion 15 change, and a relative luminance change occurs in the pixels along the spacer 140. The completed display device was disassembled, and the result of examining the amount of the material constituting the antistatic film 143 scattered on the electron emitting portion 15 located in the vicinity of the spacer 140 by ToF-SIMS is shown in FIG. 14 shows. Here, the horizontal axis of FIG. 14 indicates the position of the subpixel from the spacer 140 (that is, for example, the value “10” indicates the electron emission area EA that constitutes the tenth subpixel located from the spacer 140. The vertical axis indicates the relative value of the amount of the substance constituting the antistatic film in the electron emission portion 15. Further, in the electron emission region EA that constitutes the subpixel adjacent to the spacer 140, that is, the first subpixel located from the spacer 140, the amount of the substance constituting the antistatic film attached is “1”.

  From FIG. 14, it can be seen that a considerable amount of the material constituting the antistatic film is attached to the electron emission region EA constituting the subpixel located adjacent to or close to the spacer 140.

  Accordingly, an object of the present invention is to provide a flat panel display having a configuration and structure capable of reducing the relative luminance change of pixels along the spacer, and a spacer used in the flat panel display. .

In order to achieve the above object, a flat display device of the present invention comprises an anode panel having a phosphor region and an anode electrode provided on a substrate, and an electron emission region arranged in a two-dimensional matrix on a support. A flat panel type in which a space between the cathode panel and the anode panel is held in a vacuum, and a spacer is disposed between the anode panel and the cathode panel. It is a display device. The spacer includes a spacer substrate having a height H ₀ having a first end surface on the anode panel side and a second end surface on the cathode panel side, and an antistatic film, and the antistatic film is formed on the side surface of the spacer substrate. , A region from the first end surface to the distance H ₁ (where H ₁ is a distance with respect to the first end surface, and is 0.6H ₀ ≦ H ₁ ≦ 0.9H ₀ , preferably 0.7H ₀ ≦ H ₁ ≦ 0.9H ₀ ).

In addition, a spacer of the present invention for achieving the above object includes an anode panel in which a phosphor region and an anode electrode are provided on a substrate, and an electron emission region arranged in a two-dimensional matrix on a support. The cathode panel is joined at the outer periphery, and is used in a flat display device in which the space sandwiched between the cathode panel and the anode panel is maintained in a vacuum, and is disposed between the anode panel and the cathode panel. Spacer. The spacer base material has a height H ₀ having a first end face on the anode panel side and a second end face on the cathode panel side, and an antistatic film. A region from the end face to the distance H ₁ (where H ₁ is a distance based on the first end face, and is 0.6H ₀ ≦ H ₁ ≦ 0.9H ₀ , preferably 0.7H ₀ ≦ H ₁ ≦ 0) .9H ₀ is satisfied).

In the flat display device of the present invention or the spacer of the present invention, the spacer base material is preferably made of a ceramic material. In this case, it is more preferable that the ceramic material contains a reducing substance. Here, the reducing substance means that oxygen desorption proceeds by a reducing action in a reducing gas atmosphere such as high-temperature H ₂ gas or an inert gas atmosphere such as high-temperature N ₂ gas. It refers to a substance whose value changes, and a spacer base material containing a reducing substance can easily control the electric resistance value.

In the flat display device or spacer of the present invention including the above-described preferred structure, the antistatic film is made of silicon (Si), and silicon oxide (SiO _x ) is interposed between the antistatic film and the surface of the spacer substrate. In addition, an electron absorption layer made of silicon nitride (SiN _Y ) or silicon oxynitride (SiO _X N _Y ) may be formed. The silicon constituting the antistatic film can be composed of amorphous silicon, polycrystalline silicon, or single crystal silicon. A natural oxide film may be formed on the outermost surface of the antistatic film made of silicon (Si). Even in this case, the antistatic film is made of silicon (Si). The secondary electron emission coefficient of silicon is in the range of 1 ± 0.3 at the operating voltage of the flat panel display device (for example, when the anode voltage V _A described later is 5 kilovolts to 15 kilovolts). It is preferable to form the antistatic film from a material having a secondary electron emission coefficient in the range of 1 ± 0.3. The antistatic film itself does not have the ability to block the transmission of electrons, but by forming an electron absorption layer between the antistatic film and the surface of the spacer substrate, at least a part of the electrons that have passed through the antistatic film Can be absorbed by the electron absorption layer and the amount of electrons reaching the spacer base material can be reduced, and the change in the characteristics of the spacer base material due to the collision of electrons (specifically, the change in the electrical resistance value) Can be suppressed. In addition, silicon constituting the antistatic film has little change in electric resistance value even when electrons collide. The thickness of the electron absorption layer is desirably such that at least 50% of the electrons that have passed through the antistatic film are absorbed by the electron absorption layer. For example, when the electron absorption layer is made of SiO _x, if the thickness of the electron absorption layer is 20 nm or more, at least 50% of the electrons that have passed through the antistatic film are absorbed by the electron absorption layer. Therefore, the thickness of the electron absorption layer is preferably 20 nm or more. In general, the thickness of the antistatic film made of Si can be 1 × 10 ⁻⁹ m to 1 × 10 ⁻⁸ m, and the thickness of the electron absorption layer can be 4 × 10 ^−9. m to 2 × 10 ⁻⁷ m can be exemplified. The antistatic film and the electron absorption layer may be formed by various physical vapor deposition methods (PVD method) such as vacuum deposition method including electron beam deposition method and hot filament deposition method, sputtering method, ion plating method, laser ablation method; It can be formed (film formation) by a known method such as a chemical vapor deposition (CVD) method. Alternatively, the antistatic film can be made of germanium nitride (GeN). In this case, the secondary electron emission coefficient of the antistatic film itself is 1 ± 0 at the operating voltage of the flat display device. .3 can be satisfied, it is not necessary to form an electron absorption layer.

  The spacer in the flat display device of the present invention including the preferred configuration and configuration described above, or the spacer of the present invention including the preferable configuration and configuration described above (hereinafter, these are collectively referred to simply as “book”. In some cases, the spacer electrode may be referred to as “the spacer of the invention”), and the end electrode layer is formed on the first end surface (top surface) and the second end surface (bottom surface) of the spacer base material. Here, the end electrode layer formed on the first end surface (top surface) of the spacer base material is in contact with the anode electrode, and the end electrode layer formed on the second end surface (bottom surface) of the spacer base material is an electrode, For example, it is in contact with a focusing electrode described later. For example, the spacer may be fixed by being sandwiched between partition walls provided in the anode panel, or, for example, a spacer holding portion may be formed on the anode panel and / or the cathode panel and fixed by the spacer holding portion. do it.

  In the present invention, one row of spacers may be composed of a single spacer or a plurality of spacers. For example, as described above, the spacer base material is preferably made of ceramics. As the ceramics, aluminum silicate compounds such as mullite, aluminum oxides such as alumina, barium titanate, lead zirconate titanate, zirconia (oxidized) Zirconium), cordiolite, borosilicate barium, iron silicate, glass-ceramic materials, and metal oxides such as titanium oxide, chromium oxide, magnesium oxide, iron oxide, vanadium oxide, and nickel oxide as reducing substances. Etc., and for example, materials described in JP-T-2003-524280 can be used.

The spacer substrate is, for example,
(A) Using ceramic powder as a dispersoid, adding a binder to prepare a slurry for a green sheet,
(B) After forming (shaping) the green sheet slurry to obtain a green sheet,
(C) firing the green sheet;
Can be manufactured.

  The ceramic material constituting the spacer base material is formed by sintering the ceramic powder in the green sheet slurry. The ceramics mentioned above can be mentioned as a material which comprises the ceramic powder used as the dispersoid of the slurry for green sheets. In addition, you may add the reducing material (conductivity provision material) mentioned above to the slurry for green sheets as a dispersoid as needed. The reducing material does not necessarily have conductivity in the green sheet slurry. The reducing substance may have a chemical composition that changes when the green sheet is fired, or may have a chemical composition that does not change by firing. Specifically, by firing the green sheet, the reducing substance in the green sheet is also fired, but it is sufficient that the fired reducing substance exhibits conductivity. In addition to the materials described above, for example, noble metals such as gold and platinum; metal oxides such as molybdenum oxide, niobium oxide, tungsten oxide, and nickel oxide; Metal carbides such as carbide, tungsten carbide, nickel carbide; metal salts such as ammonium molybdate can be mentioned. Furthermore, a mixture thereof may be used. That is, the reducing substance may be in the form of a single type of material or in the form of a plurality of types of material. Examples of the material constituting the binder added to the green sheet slurry include organic binder materials (for example, acrylic emulsion, polyvinyl alcohol (PVA), polyethylene glycol) or inorganic binder materials (for example, water glass). be able to.

In a flat panel display device, a substrate that constitutes a cathode panel or a substrate that constitutes an anode panel may be any glass substrate, surface only if the surfaces of these substrates facing each other are composed of insulating members. Examples of the glass substrate, quartz substrate, quartz substrate having an insulating film formed on the surface, and semiconductor substrate having an insulating film formed on the surface include glass substrate from the viewpoint of reducing the manufacturing cost. It is preferable to use a substrate or a glass substrate having an insulating film formed on the surface. As glass substrates, high strain point glass, low alkali glass, soda glass (Na ₂ O · CaO · SiO ₂ ), borosilicate glass (Na ₂ O · B ₂ O ₃ · SiO ₂ ), forsterite (2MgO · SiO ₂₎ ), Lead glass (Na ₂ O · PbO · SiO ₂ ), and alkali-free glass.

  In the flat display device, cold cathode field emission devices (field emission devices), metal / insulating film / metal type devices (MIM devices), and surface conduction electron emission devices are listed as electron emission devices constituting the electron emission region. be able to. Further, as a flat display device, a flat display device (cold cathode field electron emission display device) provided with a cold cathode field emission device, a flat display device incorporating an MIM element, and a surface conduction electron emission device are incorporated. And a flat display device.

Here, when the flat display device is a cold cathode field emission display device including a field emission device, the field emission device is:
(A) a cathode electrode formed on a support;
(B) an insulating layer formed on the support and the cathode electrode;
(C) a gate electrode formed on the insulating layer;
(D) an opening provided in a portion of the gate electrode and the insulating layer located in an overlapping region where the cathode electrode and the gate electrode overlap, and an exposed portion of the cathode electrode at the bottom; and
(E) an electron emission portion provided on the cathode electrode exposed at the bottom of the opening, the electron emission being controlled by application of a voltage to the cathode electrode and the gate electrode;
Consists of.

  The type of the field emission device is not particularly limited, and a Spindt-type field emission device (a field emission device in which a conical electron emission portion is provided on the cathode electrode positioned at the bottom of the opening) or a flat type field emission device An element (a field emission element in which a substantially planar electron emission portion is provided on a cathode electrode positioned at the bottom of an opening) can be given. In the cathode panel, it is preferable that the projected image of the gate electrode and the projected image of the cathode electrode be orthogonal from the viewpoint of simplifying the structure of the cold cathode field emission display. Here, the gate electrode may extend in the row direction (X direction), and the cathode electrode may extend in the column direction (Y direction). In the cathode panel, an overlapping region where the gate electrode and the cathode electrode overlap constitutes an electron emission region, and the electron emission regions are arranged in a two-dimensional matrix, and each electron emission region has one or a plurality of field emission elements. An element is provided.

  In the cold cathode field emission display device, a strong electric field generated by the voltage applied to the gate electrode and the cathode electrode is applied to the electron emission portion during actual display operation. Electrons are emitted. The electrons are attracted to the anode panel by the anode electrode provided on the anode panel, and collide with the phosphor region. As a result of the collision of electrons with the phosphor region, the phosphor region emits light and can be recognized as an image.

In the cold cathode field emission display, the cathode electrode is connected to the cathode electrode control circuit, the gate electrode is connected to the gate electrode control circuit, and the anode electrode is connected to the anode electrode control circuit. Note that these control circuits can be constituted by known circuits. During actual display operation, the voltage (anode voltage) V _A applied from the anode electrode control circuit to the anode electrode is normally constant, and can be set to, for example, 5 kilovolts to 15 kilovolts. Alternatively, when the distance between the anode panel and the cathode panel is d ₀ (where 0.5 mm ≦ d ₀ ≦ 10 mm), the value of V _A / d ₀ (unit: kilovolt / mm) is 0. It is desirable to satisfy 5 or more and 20 or less, preferably 1 or more and 10 or less, and more preferably 4 or more and 8 or less. During actual display operation of the cold cathode field emission display device, for example, with respect to the voltage V _C applied to the cathode electrode and the voltage V _G applied to the gate electrode, a voltage modulation method or a pulse width modulation method is adopted as a gradation control method. can do.

A field emission device can be generally manufactured by the following method.
(1) forming a cathode electrode on a support;
(2) forming an insulating layer on the entire surface (on the support and the cathode electrode);
(3) forming a gate electrode on the insulating layer;
(4) forming an opening in a portion of the gate electrode and the insulating layer in a region where the cathode electrode and the gate electrode overlap, and exposing the cathode electrode at the bottom of the opening;
(5) A step of forming an electron emission portion on the cathode electrode located at the bottom of the opening.

Alternatively, the field emission device can be manufactured by the following method.
(1) forming a cathode electrode on a support;
(2) forming an electron emission portion on the cathode electrode;
(3) forming an insulating layer on the entire surface (on the support and the electron emission portion or on the support, the cathode electrode and the electron emission portion);
(4) forming a gate electrode on the insulating layer;
(5) A step of forming an opening in a portion of the gate electrode and the insulating layer in the overlapping region of the cathode electrode and the gate electrode, and exposing the electron emission portion at the bottom of the opening.

  When a focusing electrode (focus electrode) is provided, an interlayer insulating layer is further provided on the gate electrode and the insulating layer, and a focusing electrode is provided on the interlayer insulating layer, or above the gate electrode. The focusing electrode may be provided with a focusing electrode. Here, the focusing electrode is an electrode for converging the trajectory of emitted electrons that are emitted from the opening and directed toward the anode electrode, thereby improving the luminance and preventing optical crosstalk between adjacent pixels. It is. In a so-called high voltage type cold cathode field emission display, the potential difference between the anode electrode and the cathode electrode is on the order of several kilovolts or more and the distance between the anode electrode and the cathode electrode is relatively long. The electrode is particularly effective. A relatively negative voltage (for example, 0 volts) is applied to the focusing electrode from the focusing electrode control circuit. The focusing electrode does not necessarily have to be individually formed so as to surround each of the electron emission portion or the electron emission region provided in the overlapping region where the cathode electrode and the gate electrode overlap, for example, the electron emission portion or The electron emission regions may be extended along a predetermined arrangement direction, or the electron emission portion or the electron emission region may be surrounded by a single convergence electrode (that is, the convergence electrode may be formed in the entire effective region). In this case, a single sheet-like structure covering the plurality of electron emission portions or electron emission regions can be provided with a common convergence effect. Note that an opening (third opening) is provided in the focusing electrode and the interlayer insulating layer.

  Here, the effective area is a central display area that performs a display function that is a practical function as a flat display device, and the ineffective area is located outside the effective area, and the effective area is framed. Besieged.

As constituent materials for the gate electrode, cathode electrode, focusing electrode, and end electrode layer, chromium (Cr), aluminum (Al), tungsten (W), niobium (Nb), tantalum (Ta), molybdenum (Mo), copper ( Metals such as Cu), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), cobalt (Co), zirconium (Zr), iron (Fe), platinum (Pt), zinc (Zn) Various metals including these metals; alloys (such as MoW) or compounds (such as TiW; nitrides such as TiN and WN; silicides such as WSi ₂ , MoSi ₂ , TiSi ₂ and TaSi ₂ ); silicon (Si And the like; carbon thin films such as diamond; and conductive metal oxides such as ITO (indium oxide-tin), indium oxide, and zinc oxide. The gate electrode, the cathode electrode, the focusing electrode, and the end electrode layer can have a single layer structure or a laminated structure of these materials. In addition, as a method of forming these electrodes and end electrode layers, for example, various PVD methods including vacuum deposition methods such as an electron beam deposition method and a hot filament deposition method, a sputtering method, an ion plating method, and a laser ablation method; Various printing methods including screen printing method, ink jet printing method, metal mask printing method; plating method (electroplating method and electroless plating method); lift-off method; sol-gel method, etc. A combination of a method and an etching method can also be mentioned. Here, by appropriately selecting the formation method, it is possible to directly form a patterned strip-shaped cathode electrode, gate electrode, and focusing electrode.

  In the Spindt-type field emission device, as the material constituting the electron emission portion, molybdenum, molybdenum alloy, tungsten, tungsten alloy, titanium, titanium alloy, niobium, niobium alloy, tantalum, tantalum alloy, chromium, chromium alloy, and And at least one material selected from the group consisting of silicon (polysilicon and amorphous silicon) containing impurities. The electron emission portion of the Spindt-type field emission device can be formed by various PVD methods such as a sputtering method and a vacuum deposition method, and various CVD methods.

In the flat field emission device, it is preferable that the material constituting the electron emission portion is composed of a material having a work function Φ smaller than that of the material constituting the cathode electrode. What is necessary is just to determine based on the work function of the material which comprises a cathode electrode, the electric potential difference between a gate electrode and a cathode electrode, the magnitude | size of the emission electron current density requested | required, etc. Alternatively, the material constituting the electron emission portion may be appropriately selected from materials in which the secondary electron gain δ of the material is larger than the secondary electron gain δ of the conductive material constituting the cathode electrode. Good. In the flat type field emission device, carbon, more specifically, amorphous diamond or graphite, a carbon nanotube structure (carbon nanotube and / or graphite nanofiber), as a particularly preferable constituent material of the electron emission portion, Examples thereof include ZnO whiskers, MgO whiskers, SnO ₂ whiskers, MnO whiskers, Y ₂ O ₃ whiskers, NiO whiskers, ITO whiskers, In ₂ O ₃ whiskers, and Al ₂ O ₃ whiskers. In addition, the material which comprises an electron emission part does not necessarily need to be provided with electroconductivity.

  Planar shape of the first opening (opening formed in the gate electrode) or the second opening (opening formed in the insulating layer) (shape when the opening is cut in a virtual plane parallel to the support surface) ) Can be any shape such as a circle, an ellipse, a rectangle, a polygon, a rounded rectangle, a rounded polygon. The formation of the first opening can be performed by, for example, anisotropic etching, isotropic etching, a combination of anisotropic etching and isotropic etching, or, depending on the method of forming the gate electrode, The first opening can also be formed directly. The second opening can also be formed by, for example, anisotropic etching, isotropic etching, or a combination of anisotropic etching and isotropic etching. The formation of the third opening provided in the focusing electrode and the interlayer insulating layer can be performed in the same manner.

  In the field emission device, depending on the structure of the field emission device, one electron emission portion may exist in one opening, or a plurality of electron emission portions may exist in one opening. In addition, a plurality of first openings are provided in the gate electrode, one second opening communicating with the first opening is provided in the insulating layer, and one or more are provided in one second opening provided in the insulating layer. There may be an electron emission portion.

In the field emission device, a resistor thin film may be formed between the cathode electrode and the electron emission portion. By forming the resistor thin film, the operation of the field emission device can be stabilized, the electron emission characteristics can be made uniform, and the leakage current between the cathode electrode and the gate electrode can be suppressed. As a material constituting the resistor thin film, a carbon resistor material such as silicon carbide (SiC) or SiCN, a semiconductor resistor material such as SiN or amorphous silicon, a high melting point such as ruthenium oxide (RuO ₂ ), tantalum oxide, or tantalum nitride. Examples thereof include metal oxides and refractory metal nitrides. Examples of the method of forming the resistor thin film include various printing methods such as a sputtering method, various CVD methods, and a screen printing method. The electric resistance value per one electron emitting portion may be about 1 × 10 ⁵ to 1 × 10 ¹¹ Ω, preferably several MΩ to several tens of gigaΩ.

Insulating layer, as a constituent material of the interlayer insulating _{layer, SiO 2, BPSG, PSG,} BSG, AsSG, PbSG, SiON, SOG ( spin on glass), low-melting glass, SiO ₂ based materials such glass paste; SiN-based materials; polyimide These insulating resins can be used alone or in appropriate combination. For forming the insulating layer and the interlayer insulating layer, known processes such as various printing methods such as various CVD methods, coating methods, sputtering methods, and screen printing methods can be used.

In the flat display device, as a configuration example of the anode electrode and the phosphor region,
(1) A configuration in which an anode electrode is formed on a substrate and a phosphor region is formed on the anode electrode. (2) A configuration in which a phosphor region is formed on the substrate and an anode electrode is formed on the phosphor region. Can be mentioned. In the configuration (1), a so-called metal back film that is electrically connected to the anode electrode may be formed on the phosphor region. In the configuration (2), a metal back film may be formed on the anode electrode. The metal back film can also serve as the anode electrode.

The anode electrode may be composed of one anode electrode as a whole, or may be composed of a plurality of anode electrode units. In the latter case, it is preferable that the anode electrode unit and the anode electrode unit are electrically connected by an anode electrode resistor layer. The material constituting the anode electrode resistor layer includes carbon-based materials such as carbon, silicon carbide (SiC), and SiCN; SiN-based materials; ruthenium oxide (RuO ₂ ), tantalum oxide, tantalum nitride, chromium oxide, titanium oxide, and the like. Examples thereof include melting point metal oxides and high melting point metal nitrides; semiconductor materials such as amorphous silicon; ITO. It is also possible to realize a stable desired sheet resistance value by combining a plurality of films such as laminating a carbon thin film having a low resistance value on the SiC resistance film. Examples of the sheet resistance value of the anode electrode resistor layer include 1 × 10 ⁻¹ Ω / □ to 1 × 10 ¹⁰ Ω / □, preferably 1 × 10 ³ Ω / □ to 1 × 10 ⁸ Ω / □. it can. The number of anode electrode units [UN] may be two or more. For example, when the total number of phosphor regions arranged in a straight line is [un], [UN] = [un], or , [Un] = u · [UN] (u is an integer of 2 or more, preferably 10 ≦ u ≦ 100, more preferably 20 ≦ u ≦ 50), or spacers arranged at a constant interval. The number of pixels can be a number obtained by adding 1, or the number of pixels or the number of subpixels can be matched, or the number of pixels or the number of subpixels can be an integer. The size of each anode electrode unit may be the same regardless of the position of the anode electrode unit, or may vary depending on the position of the anode electrode unit. An anode electrode resistor layer may be formed on one anode electrode as a whole. As described above, if the anode electrode is divided into anode electrode units having a smaller area, instead of being formed over almost the entire effective area, the static electricity between the anode electrode unit and the electron emission area is formed. The electric capacity can be reduced. As a result, the occurrence of discharge can be reduced, and the occurrence of damage to the anode electrode and the electron emission region due to the discharge can be effectively reduced.

  When the anode electrode is composed of an anode electrode unit and a partition wall (described later) is formed, the anode electrode unit may be formed so as to extend from each phosphor region to the partition wall side surface. it can. The anode electrode unit may be formed from each phosphor region to the middle of the side wall of the partition wall.

The anode electrode (including the anode electrode unit) may be formed using a conductive material layer. As a method for forming the conductive material layer, for example, vacuum deposition methods such as electron beam deposition method and hot filament deposition method, various PVD methods such as sputtering method, ion plating method and laser ablation method; various CVD methods; various methods including screen printing method Examples thereof include printing method; metal mask printing method; lift-off method; sol-gel method. That is, a conductive material layer is formed, and based on lithography technology and etching technology, this conductive material layer can be patterned to form an anode electrode. Alternatively, the anode electrode can be obtained by forming a conductive material based on various PVD methods or various printing methods through a mask or screen having an anode electrode pattern. The anode electrode resistor layer can also be formed by the same or similar method as the anode electrode. That is, an anode electrode resistor layer may be formed from a resistor material, and the anode electrode resistor layer may be patterned based on a lithography technique and an etching technique, or a mask or a screen having an anode electrode resistor layer pattern. The anode electrode resistor layer can be obtained by forming the resistor material through various PVD methods and various printing methods. 3 × 10 ⁻⁸ m (30 nm) to 1 as the average thickness of the anode electrode on the substrate (or above the substrate) (when the partition is provided as described later, the average thickness of the anode electrode on the top surface of the partition) Examples include x10 ⁻⁶ m (1 μm), preferably 5 × 10 ⁻⁸ m (50 nm) to 5 × 10 ⁻⁷ m (0.5 μm).

As the constituent material of the anode electrode, aluminum (Al), molybdenum (Mo), chromium (Cr), tungsten (W), niobium (Nb), tantalum (Ta), gold (Au), silver (Ag), titanium (Ti ), Cobalt (Co), zirconium (Zr), iron (Fe), platinum (Pt), zinc (Zn), etc .; alloys or compounds containing these metal elements (for example, nitrides such as TiN, WSi ₂ , MoSi ₂ , TiSi ₂ , TaSi _2, etc.); silicon (Si), semiconductors; diamond, graphite and other carbon thin films; ITO (indium oxide-tin), indium oxide, zinc oxide, etc., conductive metal oxides Can be illustrated. When the anode electrode resistor layer is formed, the anode electrode is preferably made of a conductive material that does not change the electric resistance value of the anode electrode resistor layer. For example, the anode electrode resistor layer is made of silicon carbide (SiC). When comprised, it is preferable to comprise an anode electrode from molybdenum (Mo) or aluminum (Al).

  The phosphor region may be composed of monochromatic phosphor particles or may be composed of three primary color phosphor particles. The arrangement pattern of the phosphor regions is, for example, a dot shape. Specifically, when the flat display device is a color display, examples of the arrangement and arrangement of the phosphor regions include a delta arrangement, a stripe arrangement, a diagonal arrangement, and a rectangle arrangement. That is, one row of the phosphor regions arranged in a straight line is occupied by the row occupied by the red light emitting phosphor region, the row occupied by the green light emitting phosphor region, and the blue light emitting phosphor region. May be composed of a row in which a red light-emitting phosphor region, a green light-emitting phosphor region, and a blue light-emitting phosphor region are sequentially arranged. Here, the phosphor region is defined as a phosphor region that generates one bright spot on the anode panel. One pixel (one pixel) is composed of a set of one red light emitting phosphor region, one green light emitting phosphor region, and one blue light emitting phosphor region, and one subpixel is one phosphor. The region is composed of one red light emitting phosphor region, one green light emitting phosphor region, or one blue light emitting phosphor region. A gap between adjacent phosphor regions may be filled with a light absorption layer (black matrix) for the purpose of improving contrast.

  For the phosphor region, a luminescent crystal particle composition prepared from luminescent crystal particles is used. For example, a red photosensitive luminescent crystal particle composition (red light-emitting phosphor slurry) is applied to the entire surface and exposed. And developing to form a red light emitting phosphor region, and then applying a green photosensitive luminescent crystal particle composition (green light emitting phosphor slurry) to the entire surface, exposing and developing, and then producing a green light emitting phosphor. A region is formed, and further, a blue photosensitive luminescent crystal particle composition (blue light emitting phosphor slurry) is coated on the entire surface, exposed and developed to form a blue light emitting phosphor region. be able to. Alternatively, each phosphor region may be formed by a screen printing method, an ink jet printing method, a float coating method, a sedimentation coating method, a phosphor film transfer method, or the like. The average thickness of the phosphor region on the substrate is not limited, but is desirably 3 μm to 20 μm, preferably 5 μm to 10 μm. The phosphor material constituting the luminescent crystal particles can be appropriately selected and used from conventionally known phosphor materials. In the case of color display, a phosphor material whose color purity is close to the three primary colors specified by NTSC, white balance is achieved when the three primary colors are mixed, the afterglow time is short, and the afterglow time of the three primary colors is almost equal. It is preferable to combine them.

  It is preferable from the viewpoint of improving the contrast of the display image that the light absorption layer that absorbs light from the phosphor region is formed between adjacent phosphor regions or between a partition wall and a substrate described later. Here, the light absorption layer functions as a so-called black matrix. As a material constituting the light absorption layer, it is preferable to select a material that absorbs 90% or more of light from the phosphor region. Such materials include carbon, metal thin films (eg, chromium, nickel, aluminum, molybdenum, etc., or alloys thereof), metal oxides (eg, chromium oxide), metal nitrides (eg, chromium nitride), heat resistance Materials such as photosensitive organic resins, glass pastes, glass pastes containing conductive particles such as black pigments and silver, and specifically, photosensitive polyimide resins, chromium oxides, and chromium oxide / chromium laminated films Can be illustrated. In the chromium oxide / chromium laminated film, the chromium film is in contact with the substrate. The light absorption layer depends on the material used, for example, a combination of a vacuum deposition method, a sputtering method and an etching method, a combination of a vacuum deposition method, a sputtering method, a spin coating method and a lift-off method, various printing methods, a lithography technique, etc. Thus, it can be formed by a method selected as appropriate.

  In order to prevent an electron recoiled from the phosphor region or a secondary electron emitted from the phosphor region from entering another phosphor region, so-called optical crosstalk (color turbidity) is generated. It is preferable to provide a partition wall. Examples of the partition wall forming method include a screen printing method, a dry film method, a photosensitive method, a casting method, and a sandblast forming method. Here, in the screen printing method, an opening is formed in a portion of the screen corresponding to a portion where a partition is to be formed, and the partition forming material on the screen is passed through the opening using a squeegee, and the partition is formed on the substrate. In this method, after the formation material layer is formed, the partition wall formation material layer is fired. The dry film method is a method of laminating a photosensitive film on a substrate, removing the photosensitive film at the part where the partition wall is to be formed by exposure and development, embedding the partition wall forming material in the opening generated by the removal, and baking. . The photosensitive film is burned and removed by baking, and the partition wall-forming material embedded in the openings remains to form partition walls. The photosensitive method is a method in which a barrier rib-forming material layer having photosensitivity is formed on a substrate, the barrier rib-forming material layer is patterned by exposure and development, and then fired (cured). The casting method (embossing molding method) is a method of forming a partition wall forming material layer by extruding a partition wall forming material made of a paste-like organic material or inorganic material onto a substrate from a mold (cast), and then forming the partition wall. In this method, the forming material layer is fired. The sand blast forming method is, for example, forming a partition wall forming material layer on a substrate using a screen printing or a metal mask printing method, a roll coater, a doctor blade, a nozzle discharge type coater, and the like, and forming a partition after drying. In this method, the part of the partition wall forming material layer to be covered is covered with a mask layer, and then the exposed part of the partition wall forming material layer is removed by sandblasting. After the partition wall is formed, the partition wall may be polished to flatten the top surface of the partition wall.

  As a planar shape of the part surrounding the phosphor region in the partition wall (corresponding to the inner contour line of the projected image of the partition wall side surface and a kind of opening region), a rectangular shape, a circular shape, an elliptical shape, an oval shape, a triangular shape, Examples include pentagonal or more polygonal shapes, rounded triangular shapes, rounded rectangular shapes, rounded polygons, etc., and linear shapes extending parallel to two sides of the phosphor region (Rod-like shape). By arranging these planar shapes (planar shapes of the opening regions) in a two-dimensional matrix, a lattice-like partition is formed. This two-dimensional matrix-like arrangement may be arranged, for example, like a cross or like a zigzag.

Examples of the partition wall forming material include photosensitive polyimide resin, lead glass colored with a metal oxide such as cobalt oxide, SiO ₂ , and a low melting point glass paste. A protective layer (for example, made of SiO ₂ , SiON, or AlN) is provided on the surface (top surface and side surface) of the partition wall to prevent an electron beam from colliding with the partition wall and releasing gas from the partition wall. It may be formed.

The cathode panel and the anode panel are joined at the peripheral part, but the joining may be performed by using an adhesive layer as a joining member, or a rod-like or frame-like (frame-like) insulating rigidity such as glass or ceramics. You may carry out using the joining member which consists of the frame body comprised from material and an adhesive layer. When using a joining member consisting of a frame and an adhesive layer, the height of the frame is appropriately selected, so that the cathode panel and the anode panel are compared with the case where a joining member consisting only of the adhesive layer is used. It is possible to set the facing distance between the longer. As a constituent material of the adhesive layer, frit glass such as B ₂ O ₃ —PbO-based frit glass and SiO ₂ —B ₂ O ₃ —PbO-based frit glass is generally used, but the melting point is about 120 to 400 ° C. A so-called low melting point metal material may be used. As such low melting point metal materials, In (indium: melting point 157 ° C.); indium-gold low melting point alloy; Sn ₈₀ Ag ₂₀ (melting point 220 to 370 ° C.), Sn ₉₅ Cu ₅ (melting point 227 to 370 ° C.) Tin (Sn) high-temperature solder such as Pb _97.5 Ag _2.5 (melting point 304 ° C.), Pb _94.5 Ag _5.5 (melting point 304 to 365 ° C.), Pb _97.5 Ag _1.5 Sn _1.0 (melting point 309 ° C.) (Pb) high temperature solder; zinc (Zn) high temperature solder such as Zn ₉₅ Al ₅ (melting point 380 ° C.); Sn ₅ Pb ₉₅ (melting point 300 to 314 ° C.), Sn ₂ Pb ₉₈ (melting point 316 to 322 ° C.) Examples thereof include tin-lead based standard solder such as C); brazing material such as Au ₈₈ Ga ₁₂ (melting point 381 ° C.) (the above subscripts all represent atomic%).

  When joining the three members of the cathode panel, the anode panel, and the joining member, the three members may be joined at the same time, or in the first stage, either the cathode panel or the anode panel and the joining member are joined, In the second stage, the other of the cathode panel or the anode panel and the joining member may be joined. If the three-party simultaneous bonding or the second stage bonding is performed in a high vacuum atmosphere, the space surrounded by the cathode panel, the anode panel, and the bonding member becomes a vacuum simultaneously with the bonding. Alternatively, after the three members are joined, the space surrounded by the cathode panel, the anode panel, and the joining member can be evacuated to create a vacuum. When exhausting after joining, the atmosphere pressure during joining may be either normal pressure or reduced pressure, and the gas constituting the atmosphere may be nitrogen gas or a gas belonging to Group 0 of the periodic table (for example, Ar gas) ) Is preferable, but it can also be performed in the atmosphere.

  When exhaust is performed, the exhaust can be performed through an exhaust pipe called a tip pipe connected in advance to the cathode panel and / or the anode panel. The exhaust pipe is typically a glass pipe, or a metal or alloy having a low coefficient of thermal expansion [for example, an iron (Fe) alloy containing 42 wt% nickel (Ni), 42 wt% nickel (Ni), A hollow tube made of an iron (Fe) alloy containing 6 wt% chromium (Cr)], and the above-mentioned frit glass or After being joined using a low melting point metal material and the space has reached a predetermined degree of vacuum, it is sealed off by thermal fusion or sealed by crimping. In addition, if the whole flat display device is once heated and then cooled before sealing, it is preferable because residual gas can be released into the space, and this residual gas can be removed out of the space by exhaust. .

  In the present invention, when the number of pixels is M × N, as (M, N), specifically, VGA (640, 480), S-VGA (800, 600), XGA (1024, 768), APRC (1152,900), S-XGA (1280,1024), U-XGA (1600,1200), HD-TV (1920,1080), Q-XGA (2048,1536), (1920,1035), Some of the image display resolutions such as (720, 480) and (1280, 960) can be exemplified, but are not limited to these values.

In the present invention, the antistatic film is formed in the antistatic film / formation region on the side surface of the spacer base material. Here, the antistatic film / formation region occupies a region from the first end face to the distance H ₁ (provided that 0.6H ₀ ≦ H ₁ ≦ 0.9H ₀ ). Stated words, based on the first end surface, on the side of the spacer base material, in a region accounting for at least 0.9H ₀ to 1.0H _0, antistatic film is not formed. That is, there is an antistatic film / non-formation region on which the antistatic film is not formed on the side surface of the spacer base material, and the antistatic film / non-formation region is defined by the second end surface on the basis of the second end surface. To the distance H ₂ (where H ₂ = H ₀ −H ₁ ). The boundary between the antistatic film / formation region and the antistatic film / non-formation region is located at a distance H ₁ from the first end face, or at a distance H ₂ from the second end face. Accordingly, since the antistatic film does not exist in the spacer portion adjacent to the cathode panel in the first place, the heat treatment in the manufacturing process of the flat panel display device (for example, the anode panel and the cathode panel are joined at the peripheral portion). Even if a part of the antistatic film is scattered by the heat treatment when bonding via the material, the amount of the material constituting the scattered antistatic film can be reduced to the electron emitting portion located near the spacer. it can. Therefore, as a result of suppressing the change in the electron emission characteristics from the electron emission portion, it is possible to prevent the occurrence of a problem that a relative luminance change occurs in the pixels along the spacer.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to the flat display device of the present invention and the spacer of the present invention. In Example 1, a flat display device, specifically, a cold cathode field emission display device (hereinafter simply referred to as a display device) provided with a cold cathode field emission device (field emission device). It was. A schematic partial end view of the display device of Example 1 is shown in FIG. 1, and a schematic cross-sectional view of the spacer is shown in FIG. FIG. 3 shows a schematic exploded perspective view of a part of the cathode panel CP and the anode panel AP when the cathode panel CP and the anode panel AP are disassembled.

  That is, in the display device according to the first embodiment, the anode panel AP in which the phosphor region 22 and the anode electrode 24 are provided on the substrate 20, and the row direction (X direction) and the column direction (Y direction) on the support 10. A cathode panel CP provided with electron emission regions EA arranged in a two-dimensional matrix along the outer periphery is joined. The space SP sandwiched between the cathode panel CP and the anode panel AP is maintained in a vacuum, and the spacer 40 is disposed between the anode panel AP and the cathode panel CP.

  The spacer 40 according to the first embodiment includes an anode panel AP in which the phosphor region 22 and the anode electrode 24 are provided on the substrate 20, and an electron emission region EA arranged in a two-dimensional matrix on the support 10. The cathode panel CP is joined at the outer periphery, and is used in a flat display device in which a space SP sandwiched between the cathode panel CP and the anode panel AP is maintained in a vacuum. The anode panel AP and the cathode panel It is a spacer arrange | positioned between CP.

Here, the display device according to the first embodiment includes the effective area EF and the invalid area NF surrounding the effective area EF. The effective area EF is a display area located substantially in the center that performs a practical image display function as a display device. The effective area EF is surrounded by an ineffective area NF that surrounds the frame. The space SP sandwiched between the cathode panel CP, the anode panel AP, and the joining member 26 is maintained in a vacuum (pressure: for example, 10 ⁻³ Pa or less). The ineffective area NF of the cathode panel CP is provided with a through hole (not shown) for evacuation, and in this through hole, an exhaust pipe (not shown) called a chip tube that is sealed after evacuation. Is attached.

In the first embodiment, the field emission device forming the electron emission region is constituted by, for example, a Spindt type field emission device. Spindt-type field emission devices
(A) a strip-shaped cathode electrode 11 formed on the support 10;
(B) an insulating layer 12 formed on the support 10 and the cathode electrode 11;
(C) a strip-shaped gate electrode 13 formed on the insulating layer 12;
(D) An opening 14 (provided in the gate electrode 13) provided in a portion of the gate electrode 13 and the insulating layer 12 located in the overlapping region where the cathode electrode 11 and the gate electrode 13 overlap, with the cathode electrode 11 exposed at the bottom. 14A of 1st opening parts, 2nd opening part 14B provided in the insulating layer 12, and,
(E) an electron emitting portion 15 provided on the cathode electrode 11 exposed at the bottom of the opening 14 and whose electron emission is controlled by applying a voltage to the cathode electrode 11 and the gate electrode 13;
It is composed of Here, the shape of the electron emission portion 15 is a conical shape. An interlayer insulating layer 16 is formed on the insulating layer 12, and a focusing electrode 17 is formed on the interlayer insulating layer 16.

  In the display device according to the first exemplary embodiment, the cathode electrode 11 (for example, the data electrode) and the gate electrode 13 (for example, the scanning electrode) are arranged in directions (column direction, Y direction, and Each of the electrodes is formed in a band shape in the row direction and the X direction, and the projected images of these two electrodes overlap each other (corresponding to a region corresponding to one subpixel (subpixel), which is an electron emission region EA). A plurality of field emission elements are provided. For simplification of the drawing, FIG. 1 shows two electron emission portions 15 in each electron emission area EA. The electron emission areas EA are usually arranged in a two-dimensional matrix as described above in the effective area EF (area that functions as an actual display portion) of the cathode panel CP.

  The anode panel AP includes a substrate 20, a phosphor region 22 formed on the substrate 20 and having a predetermined pattern, and an anode electrode 24 formed thereon. One sub-pixel (one sub-pixel) includes an electron emission area EA and a phosphor area 22 on the anode panel side facing the electron emission area EA. In the effective area EF, the sub-pixels are arranged on the order of several hundred thousand to several million, for example. A light absorption layer (black matrix) 23 is formed on the substrate 20 between the phosphor region 22 and the phosphor region 22 in order to prevent color turbidity of the display image and occurrence of optical crosstalk. ing. The anode electrode 24 is made of aluminum (Al) having a thickness of about 0.3 μm, is in the form of a thin sheet that covers the effective region EF, and is provided so as to cover the phosphor region 22. In FIG. 3, illustration of the partition walls, the spacers, and the spacer holding portions is omitted. In the case of a color display device, one pixel (one pixel) is composed of a set of one red light emitting phosphor region 22R, one green light emitting phosphor region 22G, and one blue light emitting phosphor region 22B. Has been. A grid-like partition wall 21 surrounding each phosphor region 22 is formed on the substrate 20. Each phosphor region 22 is surrounded by a partition wall 21. The planar shape (corresponding to the inner contour line of the projected image of the partition wall side surface and a kind of opening region) of the portion surrounding the phosphor region 22 in the lattice-shaped partition wall 21 is a rectangular shape (rectangle), and these planes The shape (planar shape of the opening region) is arranged in a two-dimensional matrix (more specifically, a cross beam), and a lattice-like partition wall 21 is formed. A part of the partition functions as the spacer holding part 25.

  The flat spacers 40 are arranged in a plurality of columns along the row direction (X direction). In addition, several tens to several hundreds of gate electrodes 13 are sandwiched between the spacers 40 and 40. The first end surface (top surface) and the second end surface (bottom surface) of the spacer 40 are parallel to the XY plane, the side surfaces are parallel to the XZ plane, and the end surfaces are parallel to the YZ plane. The spacer 40 is held by the spacer holding part 25.

The spacer 40 includes a spacer substrate 41 having a height H ₀ having a first end face 42 A on the anode panel side and a second end face 42 B on the cathode panel side, and an antistatic film 43. Here, the spacer base material 41 includes a ceramic material, specifically, a ceramic material containing a reducing substance, and more specifically, titania (titanium oxide, TiO ₂ (IV)) as a reducing substance. Made of alumina (Al ₂ O ₃ ). In Example 1, the dimensions of the spacer 40 or spacer base material 41 are 150 mm in the longitudinal direction (X direction in FIG. 1), 100 μm in the thickness direction (Y direction in FIG. 1), and the height direction (Z direction in FIG. 1). ) Is 2.0 mm (= H ₀ ), but is not limited thereto. The resistance value between the first end face and the second end face of the spacer 40 is about 1 × 10 ⁸ Ω to about 1 × 10 ⁸ Ω at the operating voltage of the display device (for example, when the anode voltage V _A is 5 to 15 kilovolts). About 1 × 10 ¹¹ Ω.

The antistatic film 43 is a region on the side surface of the spacer base material 41 from the first end face 42A to the distance H ₁ (where H ₁ is a distance based on the first end face 42A and is 0.6H _0. ≦ H ₁ ≦ 0.9H ₀ (antistatic film / formation region). On the other hand, based on the first end surface 42A, on the side of the spacer base material 41, in a region accounting for at least 0.9H ₀ to 1.0H _0, antistatic film 43 is not formed. That is, there is an antistatic film / non-formation region where the antistatic film 43 is not formed on the side surface of the spacer base material 41, and this antistatic film / non-formation region is based on the second end face 42B. It occupies a region from the second end face 42B to the distance H ₂ (where H ₂ = H ₀ −H ₁ ).
In particular,
H ₁ = 1.6mm
H ₂ = 0.4 mm (= H ₀ −H ₁ )
It was.
The antistatic film 43 is made of silicon (Si) having a thickness of 4 nm, more specifically, amorphous silicon. Further, between the surface of the antistatic film 43 and the spacer base material 41, an electron absorption layer 44 having a thickness of 0.1 μm made of silicon oxide (SiO _x , more specifically SiO ₂₎ is formed. .

  Furthermore, end electrode layers 45A and 45B made of platinum (Pt) are formed on the first end face 42A and the second end face 42B of the spacer base material 41. Alternatively, a nickel-vanadium alloy can be used as the material constituting the end electrode layers 45A and 45B. The end electrode layer 45A formed on the first end face 42A of the spacer base material 41 is in contact with the anode electrode 24, and the end electrode layer 45B formed on the second end face 42B of the spacer base material 41 is in contact with the focusing electrode 17.

  FIG. 4 shows the result of a simulation of how far the material constituting the scattered antistatic film 43 adheres to the electron emission portion 15 constituting the subpixel, which is away from the spacer 40. The subpixel pitch was 0.30 mm. The atoms of the material constituting the 500 antistatic films 43 are isotropic (angle: −π / 2 to + π / 2) from each of the regions (finite elements) obtained by dividing the spacer 40 into 100 in the height direction. A simulation was performed assuming that it was scattered with equal probability. The horizontal axis in FIG. 4 indicates the position of the subpixel from the spacer 40, and the vertical axis in FIG. 4 indicates the total number of atoms that have reached the electron emission region EA that constitutes each subpixel of the cathode panel CP (100 × 500 = The ratio to 50000) is shown. In the calculation in the region where the antistatic film 43 is not formed (antistatic film / non-formed region), it is assumed that atoms do not scatter and reach nowhere.

The case where the antistatic film is formed on the entire side surface of the spacer base material is shown as Comparative Example 1 with diamonds filled with black, and H = 0.9H ₀ , H = 0.8H ₀ , H = 0.7H _0. , H = 0.6H ₀ are indicated by white rhombus marks, white triangle marks, x marks, and circles filled with black, respectively.

4, in comparison with Comparative Example 1, even _{H 1 = 0.9H 0, H 1} = 0.8H 0, H 1 = 0.7H 0, in either case of H ₁ = 0.6H _0, scattered The amount of the substance constituting the antistatic film 43 is reduced on the electron emitting portion 15 constituting the subpixel. Further, as the value of H ₁ becomes smaller, the amount attached to the electron emission portion 15 is further reduced. As compared with Comparative Example 1, when H ₁ = 0.8H ₀ , the amount adhering to the electron emission portion 15 constituting the subpixel located in the vicinity of the spacer is about ½ times, and H ₁ When = 0.6H ₀ , the amount adhering to the electron emission portion 15 constituting the subpixel located in the vicinity of the spacer is about 1/3 times.

On the other hand, if the value of H ₁ becomes too small, the antistatic effect is reduced. When a voltage of 9 kilovolts is applied to the anode electrode 24 and the same drive signal is applied to all the electron emission areas EA (that is, the same potential is applied to the cathode electrode 11 and the gate electrode 13 in all the electron emission areas EA). The electron beam trajectory from the electron emission area EA in the vicinity of the spacer 40 was measured. The results are shown in FIGS. 5A and 5B, FIGS. 6A and 6B, and FIG. 5A shows the result of Comparative Example 1, FIG. 5B shows the result of H ₁ = 0.9H ₀ , and FIG. 6A shows H ₁ = 0. The result of .8H ₀ is shown, and FIG. 6B shows the result of H ₁ = 0.6H ₀ . Further, FIG. 7 shows a case where an antistatic film is not formed for comparison. In the graphs in these drawings, the horizontal axis is the anode current (unit: milliamperes), and the higher the anode current value, the more backscattered electrons from the anode panel AP increase, and the more the electrons collide with the spacer 40. . On the other hand, the vertical axis represents the amount of deviation of the electron beam trajectory from the normal trajectory (unit: μm). When the value is negative, it indicates that the trajectory is shifted away from the spacer, and the value is positive. In this case, the track is shifted in the direction approaching the spacer.

As shown in FIG. 7, when the antistatic film is not formed, the secondary electron emission coefficient of the material constituting the spacer base material (main component is alumina) is larger than 1 and is easily positively charged, so that the anode current is large. The spacer becomes easier to attract electrons, and the numerical value on the vertical axis is greatly changed to plus. As shown in FIG. 5A, FIG. 5B, and FIG. 6A, in Comparative Example 1, H ₁ = 0.9H ₀ , H ₁ = 0.8H ₀ , the anode current was Even if it is increased, there is not much change in the deviation of the electron beam trajectory. Further, as shown in FIG. 6B, it can be seen that when H ₁ = 0.6H ₀ , the deviation of the electron beam trajectory changes in the positive direction as the anode current increases. From the above results, it can be said that the antistatic effect of the antistatic film begins to be impaired when H ₁ = 0.6H ₀ or less. Depending on the current used by the display device, the spacer may be visually recognized, so it is not a good idea to fall below H ₁ = 0.6H ₀ . Therefore,
0.6H ₀ ≦ H ₁ ≦ 0.9H ₀
Preferably, 0.7H ₀ ≦ H ₁ ≦ 0.9H ₀
It is desirable to satisfy

In the display device according to the first embodiment, when the cathode electrode 11 is connected to the cathode electrode control circuit 31, the gate electrode 13 is connected to the gate electrode control circuit 32, and the focusing electrode is provided, the focusing electrode is the focusing electrode. Connected to a control circuit (not shown), the anode electrode 24 is connected to an anode electrode control circuit 33. At the time of actual display operation of the display device, the anode voltage V _A applied from the anode electrode control circuit 33 to the anode electrode 24 is normally constant, for example, 5 kilovolts to 15 kilovolts, specifically, for example, 9 kilovolts. (For example, d ₀ = 2.0 mm). On the other hand, regarding the voltage V _C applied to the cathode electrode 11 and the voltage V _G applied to the gate electrode 13 during the actual display operation of the display device,
(1) A method in which the voltage V _C applied to the cathode electrode 11 is constant and the voltage V _G applied to the gate electrode 13 is changed. (2) The voltage V _C applied to the cathode electrode 11 is changed and applied to the gate electrode 13. changing the voltage V _C is applied the voltage V _G to the method (3) a cathode electrode 11, fixed to, and, any method to change the voltage V _G applied to the gate electrode 13 may be employed but, In the display device according to the first embodiment, the above-described method (2) is adopted.

That is, during the actual display operation of the display device, a relatively negative voltage (V _C ) is applied to the cathode electrode 11 from the cathode electrode control circuit 31, and a relatively positive voltage (V _G ) is applied to the gate electrode 13. When a focusing electrode is applied from the electrode control circuit 32, 0 V, for example, is applied to the focusing electrode from the focusing electrode control circuit, and a positive voltage (a voltage higher than that of the gate electrode 13) is applied to the anode electrode 24. An anode voltage V _A ) is applied from the anode electrode control circuit 33. In such a display device, when an image is displayed by a line sequential driving method, for example, a video signal is input from the cathode electrode control circuit 31 to the cathode electrode 11 and a scanning signal is input from the gate electrode control circuit 32 to the gate electrode 13. . When the cathode electrode 11 is a scan electrode and the gate electrode 13 is a data electrode, a scan signal is input from the cathode electrode control circuit 31 to the cathode electrode 11 and a video signal is input from the gate electrode control circuit 32 to the gate electrode 13. You can enter. Electrons are emitted from the electron emitter 15 based on the quantum tunnel effect due to an electric field generated when a voltage is applied between the cathode electrode 11 and the gate electrode 13, and the electrons are attracted to the anode electrode 24. It passes through and collides with the phosphor region 22. As a result, the phosphor region 22 is excited to emit light, and a desired image can be obtained. That is, the operation of this display device is basically controlled by the voltage V _G applied to the gate electrode 13 and the voltage V _C applied to the cathode electrode 11. The cathode electrode 11 is driven by a cathode electrode drive driver, and the gate electrode 13 is driven by a gate electrode drive driver. The cathode electrode control circuit 31, the gate electrode control circuit 32, the anode electrode control circuit 33, and the drive driver can be composed of known circuits.

  Hereinafter, the manufacturing method of the display device of Example 1 will be described with reference to FIGS. 8A to 8E which are schematic end views and cross-sectional views of the spacer base material and the like. 8A to 8E are schematic cross-sectional views along the XY plane.

[Step-100]
First, a green sheet slurry is prepared. Alumina powder (Alcoa Incorporated) and titania powder (Kanto Chemical Co., Ltd.) pulverized and classified to have an average particle size of 1 to 2 μm and mixed so that the volume ratio is 98: 2, polyvinyl butyral A binder for a resin and a surfactant are added, dispersed in a mixed solvent of toluene and ethanol, and stirred by a ball mill to obtain a slurry for a green sheet.

[Step-110]
Next, a green sheet is obtained from the slurry for the green sheet. In Example 1, the prepared green sheet slurry was formed into a sheet having a thickness of about 100 μm by a blade coating method and sufficiently dried at 100 ° C. to obtain a green sheet, but the present invention is not limited to this.

[Step-120]
Thereafter, the green sheet is fired to obtain a ceramic material. A ceramic material was obtained by placing the above sheet on a molybdenum setter and firing it for about 1 hour in an atmosphere of 1650 ° C. and nitrogen: hydrogen = 1: 3. Absent.

[Step-130]
Next, the spacer base material 41 is obtained by cutting the ceramic material. In Example 1, as described above, the dimension of the spacer base material 41 is 150 mm in the longitudinal direction (X direction in FIG. 1), 100 μm in the thickness direction (Y direction in FIG. 1), and the height direction (Z in FIG. 1). (Direction) is 2.0 mm, but is not limited thereto.

[Step-140]
Next, the electron absorption layer 44 and the antistatic film 43 are sequentially formed (film formation) on a part (antistatic film / formation region) of both side surfaces of the spacer base material 41. Specifically, the spacer base material 41 in which the end electrode layers 45A and 45B are formed on the first end surface 42A and the second end surface 42B based on the lift-off method and the sputtering method is placed on the base 100 ((( A)). Then, a resist layer 101 covering the antistatic film / non-formation region is formed based on a well-known lithography technique (see FIG. 8B), and the electron absorption layer 44 made of SiO _{2 is} sputtered as exemplified below. Then, an antistatic film 43 made of Si is formed based on the sputtering method exemplified below (see FIG. 8C). Next, after removing the resist layer 101 (see FIG. 8D), a spacer in which the electron absorbing layer 44 and the antistatic film 43 are formed on a part of one side surface (antistatic film / formation region). The base material 41 is removed from the base 100 (see (E) of FIG. 8). Thereafter, the electron absorbing layer 44 and the antistatic film 43 are formed on a part of the other side surface (antistatic film / formation region) of the spacer base material 41 by the same method. 8 to 11, the stacked body of the electron absorption layer 44 and the antistatic film 43 is shown as one layer, and the end electrode layers 45A and 45B are not shown.

[Sputtering conditions for electron absorbing layer 44]
Spacer base material temperature: No particular heating Deposition rate: 0.01 to 0.03 nm / second Pressure: 5 × 10 ⁻¹ Pa
Process gas: Ar
Sputtering method: RF sputtering [Sputtering conditions for antistatic film 43]
Spacer base material temperature: not particularly heated Deposition rate: 0.002 to 0.02 nm / sec Pressure: 5 × 10 ⁻¹ Pa
Process gas: Ar
Sputtering method: RF sputtering

[Step-150]
Next, the display device shown in FIG. 1 is assembled. Specifically, the anode panel AP and the cathode panel CP are arranged so that the phosphor region 22 and the electron emission region EA face each other with the spacer 40 interposed therebetween. The anode panel AP and the cathode panel CP (more specifically, the support body 10 and the substrate 20) are joined together at the peripheral edge via a joining member (including a frame body) 26, for example. At the time of joining, frit glass is applied to the joining portion between the joining member 26 and the anode panel AP and the joining portion between the joining member 26 and the cathode panel CP, and the frit glass is dried by pre-baking, and then the anode panel AP. Then, the cathode panel CP and the bonding member 26 are bonded together, and main baking is performed at about 450 ° C. for 10 to 30 minutes. Thereafter, the space SP surrounded by the anode panel AP, the cathode panel CP, the joining member 26 and the frit glass is exhausted through a through hole (not shown) and a tip tube (not shown), and the pressure of the space SP is 10 ^{When the} pressure reaches about ^-4 Pa, the tip tube is sealed by heat melting or pressure welding. In this manner, the space SP surrounded by the anode panel AP, the cathode panel CP, and the bonding member 26 can be evacuated. Thereafter, wiring with necessary external circuits is performed, and the display device of Example 1 can be completed.

In Example 1, the antistatic film 43 is formed in the antistatic film / formation region on the side surface of the spacer base material 41. Further, on the side of the spacer base material 41, the area occupied by at least 0.9H ₀ to 1.0H ₀ is antistatic film-non-forming region. Accordingly, since the antistatic film 43 does not exist in the portion of the spacer 40 adjacent to the cathode panel CP, the heat treatment in the manufacturing process of the display device (for example, the anode panel AP and the cathode panel CP in [Step-150]) Even if a part of the antistatic film 43 is scattered by the heat treatment when bonding the peripheral edge portion via the bonding member 26, the material constituting the scattered antistatic film 43 is not located in the vicinity of the spacer 40. A large amount does not adhere to the discharge part 15. Therefore, the change in the electron emission characteristics from the electron emission portion 15 can be kept small, and the occurrence of a problem that a relative luminance change occurs in the pixels along the spacer 40 can be prevented or suppressed. .

In addition, the applicant of the present invention has disclosed an invention of a spacer having an antistatic film / formation region and an antistatic film / non-formation region in Japanese Patent Application No. 2005-298543 (Japanese Patent Laid-Open No. 2007-109498) filed on Oct. 13, 2005. Has been filed. Here, in the spacer in this patent application, an antistatic film / non-formation region is provided on the anode panel side. On the other hand, in the spacer of Example 1, an antistatic film / non-formation region is provided on the cathode panel side. When a metal oxide film made of CrO _x is provided as an antistatic film on the side surface of the spacer base material, this metal oxide film is reduced by collision of electrons, and its electric resistance value changes. As a result, the electric field in the vicinity of the spacer changes and the electron beam trajectory is curved, so that the luminance characteristics in the pixels in the vicinity of the spacer of the display device also change. Therefore, in this patent application, the occurrence of such a problem is avoided by providing an antistatic film / non-formation region on the anode panel side. On the other hand, in the first embodiment, for example, by forming the antistatic film 43 from Si, the change in the electric resistance value of the antistatic film 43 is small even by the collision of electrons. Does not change and the electron beam trajectory is not curved. However, as described above, even if a part of the antistatic film 43 is scattered by the heat treatment in the manufacturing process of the display device, the material constituting the scattered antistatic film remains in the electron emitting portion 15 located in the vicinity of the spacer 40. In order to prevent a large amount of adhesion, an antistatic film / non-formation region is provided on the cathode panel side.

  The second embodiment is a modification of the first embodiment. Example 2 or Example 3 to Example 4 described later is different from Example 1 in that [Step-140] for producing a spacer is different. Since other configurations, configurations and structures of the display device and the spacer are the same as the configurations and structures of the display device and the spacer described in the first embodiment, detailed description is omitted.

  In Example 2, end electrode layers 45A and 45B are formed on the first end face 42A and the second end face 42B based on the lift-off method and the sputtering method in the same process as [Step-140] in Example 1. The spacer base material 41 is placed on the pedestal 110 (see FIG. 9A). Next, the antistatic film / non-formation region is covered with a shielding mask 111 (see FIG. 9B). Then, the electron absorption layer 44 and the antistatic film 43 are formed in the same manner as in [Step-140] of Example 1 (see FIG. 9C). Thereafter, the shielding mask 111 is removed (see FIG. 9D), and the spacer base material in which the electron absorption layer 44 and the antistatic film 43 are formed on a part of one side surface (antistatic film / formation region). 41 is removed from the pedestal 110 (see FIG. 9E). Thereafter, the electron absorbing layer 44 and the antistatic film 43 are formed on a part of the other side surface (antistatic film / formation region) of the spacer base material 41 by the same method.

  The third embodiment is also a modification of the first embodiment. In Example 3, end electrode layers 45A and 45B are formed on the first end surface 42A and the second end surface 42B based on the lift-off method and the sputtering method in the same process as [Step-140] of Example 1. The spacer base material 41 is placed on the pedestal 120 (see FIG. 10A). Unlike Example 2, the surface of the pedestal 120 on which the spacer base material 41 is placed is inclined such that the first end surface 42A is higher than the second end surface 42B. Further, a stopper (holding portion) 122 is provided on the surface of the pedestal 120 on which the spacer base material 41 is placed, so that when the spacer base material 41 is placed on the inclined pedestal 120, it does not slide down. Yes. Then, the antistatic film / non-formation region is covered with a shielding mask 121 (see FIG. 10B). Next, an electron absorption layer 44 and an antistatic film 43 are formed in the same manner as in [Step-140] of Example 1 (see FIG. 10C). Thereafter, the shielding mask 121 is removed (see FIG. 10D), and the spacer base material in which the electron absorption layer 44 and the antistatic film 43 are formed on a part of one side surface (antistatic film / formation region). 41 is removed from the pedestal 120 (see FIG. 10E). Thereafter, the electron absorbing layer 44 and the antistatic film 43 are formed on a part of the other side surface (antistatic film / formation region) of the spacer base material 41 by the same method.

  The fourth embodiment is also a modification of the first embodiment. In Example 4, end electrode layers 45A and 45B are formed on the first end face 42A and the second end face 42B based on the lift-off method and the sputtering method in the same process as [Step-140] in Example 1. The antistatic film / non-formation region of the spacer base material 41 is inserted into a hole provided in the pedestal 130 (see FIG. 11A). Then, the electron absorbing layer 44 and the antistatic film 43 are formed in the same manner as in [Step-140] of Example 1 (see FIG. 11B). Next, the spacer base material 41 on which the electron absorption layer 44 and the antistatic film 43 are formed on part of both side surfaces (antistatic film / formation region) is removed from the pedestal 120 (see FIG. 11C). .

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The configurations and structures of the flat display device, cathode panel and anode panel, cold cathode field emission display device and cold cathode field emission device described in the embodiments are examples, and can be changed as appropriate. A method for manufacturing a panel, a cathode panel, a cold cathode field emission display, or a cold cathode field emission device is also an example, and can be changed as appropriate. Furthermore, various materials used in the manufacture of the anode panel and the cathode panel are also examples, and can be changed as appropriate. The display device has been described by taking color display as an example, but it may also be a single color display.

  In the field emission device, a mode in which one electron emission portion corresponds to one opening has been described. However, depending on the structure of the field emission device, a mode in which a plurality of electron emission portions correspond to one opening. Alternatively, one electron emission portion may correspond to a plurality of openings. Alternatively, a plurality of first openings may be provided in the gate electrode, a second opening connected to the plurality of first openings related to the insulating layer may be provided, and one or a plurality of electron emission portions may be provided. .

The electron emission region can also be constituted by an electron emission element commonly called a surface conduction electron emission element. This surface conduction electron-emitting device is formed on a support made of glass, for example, tin oxide (SnO ₂ ), gold (Au), indium oxide (In ₂ O ₃ ) / tin oxide (SnO ₂ ), carbon, palladium oxide ( A pair of electrodes made of a conductive material such as (PdO), having a very small area and arranged with a predetermined gap (gap) are formed in a matrix. A carbon thin film is formed on each electrode. The row direction wiring is connected to one electrode of the pair of electrodes, and the column direction wiring is connected to the other electrode of the pair of electrodes. By applying a voltage to the pair of electrodes, an electric field is applied to the carbon thin films facing each other across the gap, and electrons are emitted from the carbon thin film. By causing the electrons to collide with the phosphor region on the anode panel, the phosphor region is excited to emit light, and a desired image can be obtained. Alternatively, the electron emission region can be formed from a metal / insulating film / metal type element.

FIG. 1 is a schematic partial end view of a flat panel display device of Example 1, specifically, a cold cathode field emission display device provided with a cold cathode field emission device. FIG. 2 is a schematic cross-sectional view of the spacer according to the first embodiment. FIG. 3 is a schematic exploded perspective view of a part of the cathode panel and the anode panel when the cathode panel and the anode panel are disassembled. FIG. 4 is a graph showing a result of simulating how far the material constituting the scattered antistatic film adheres to the electron emission portion constituting the subpixel, which is away from the spacer. 5A and 5B are graphs showing the results of actual measurement of the electron beam trajectory from the electron emission region near the spacer, and FIG. 5A is a graph showing the results of Comparative Example 1. FIG. 5B is a graph showing the results of Example 1 (where H ₁ = 0.9H ₀ ). 6A and 6B are also graphs showing the results of actual measurement of the electron beam trajectory from the electron emission region in the vicinity of the spacer, and FIG. 6A shows Example 1 (where H ₁ = 0). .8H ₀ ), and FIG. 6B is a graph showing the results of Example 1 (where H ₁ = 0.6H ₀ ). FIG. 7 is also a graph showing the result of actually measuring the electron beam trajectory from the electron emission region in the vicinity of the spacer, but is a graph showing the result when the antistatic film is not provided. 8A to 8E are schematic cross-sectional views of a spacer base material and the like for explaining the manufacturing process of the spacer of Example 1. FIG. 9A to 9E are schematic cross-sectional views of a spacer base material and the like for explaining the spacer manufacturing process of Example 2. FIG. FIGS. 10A to 10E are schematic cross-sectional views of a spacer base material and the like for explaining a spacer manufacturing process of Example 3. FIG. 11A to 11C are schematic cross-sectional views of a spacer base material and the like for explaining the spacer manufacturing process of Example 4. FIG. FIG. 12 is a schematic partial end view of a conventional cold cathode field emission display. FIGS. 13A and 13B are diagrams schematically showing an electron beam trajectory in a pixel located in the vicinity of a spacer in a cold cathode field emission display. FIG. 14 is a graph showing the results of investigation by ToF-SIMS on how much the material constituting the scattered antistatic film is attached to the electron emission portion located in the vicinity of the spacer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Support body, 11 ... Cathode electrode, 12 ... Insulating layer, 13 ... Gate electrode, 14, 14A, 14B ... Opening part, 15 ... Electron emission part, 16 ... Interlayer insulating layer, 17 ... convergence electrode, 20 ... substrate, 21 ... partition, 22, 22R, 22G, 22B ... phosphor region, 23 ... light absorption layer (black matrix), 24 ... Anode electrode, 25 ... Spacer holding part, 26 ... Joint member, 31 ... Cathode electrode control circuit, 32 ... Gate electrode control circuit, 33 ... Anode electrode control circuit, 40 ... Spacer, 41 ... Spacer base, 42A ... First end face of spacer base, 42B ... Second end face of spacer base, 43 ... Antistatic film, 44 ... Electronic Absorption layer, 45A, 45B ... end electrode layer, 100, 10, 120, 130 ... pedestal, 101 ... resist layer, 111, 121 ... shielding jig, 122 ... stopper, EA ... electron emission region, EF ... effective region, NF. ..Invalid area, SP ... space

Claims (8)

An anode panel in which a phosphor region and an anode electrode are provided on a substrate, and a cathode panel having electron emission regions arranged in a two-dimensional matrix on a support are joined at the outer periphery, and the cathode panel A space between the anode panel and the anode panel is maintained in a vacuum, and a spacer is a flat display device disposed between the anode panel and the cathode panel,
The spacer comprises a spacer substrate having a height H ₀ having a first end face on the anode panel side and a second end face on the cathode panel side, and an antistatic film,
The antistatic film is a region on the side surface of the spacer base material from the first end surface to the distance H ₁ (where H ₁ is a distance with respect to the first end surface, and 0.6H ₀ ≦ H ₁ ≦ 0. 9H ₀ is satisfied).   The flat display device according to claim 1, wherein the spacer base material is made of a ceramic material.   The flat display device according to claim 2, wherein the ceramic material contains a reducing substance. The antistatic film is made of silicon,
2. The flat display device according to claim 1, wherein an electron absorption layer made of silicon oxide, silicon nitride, or silicon oxynitride is formed between the antistatic film and the surface of the spacer base material. An anode panel in which a phosphor region and an anode electrode are provided on a substrate, and a cathode panel having electron emission regions arranged in a two-dimensional matrix on a support are joined at the outer periphery, and the cathode panel Used in a flat display device in which a space sandwiched between the anode panel and the anode panel is maintained in a vacuum, and is a spacer disposed between the anode panel and the cathode panel,
A spacer substrate having a height H ₀ having a first end face on the anode panel side and a second end face on the cathode panel side, and an antistatic film,
The antistatic film is a region on the side surface of the spacer base material from the first end surface to the distance H ₁ (where H ₁ is a distance with respect to the first end surface, and 0.6H ₀ ≦ H ₁ ≦ 0. 9H ₀ ).   The spacer according to claim 5, wherein the spacer substrate is made of a ceramic material.   The spacer according to claim 6, wherein the ceramic material contains a reducing substance. The antistatic film is made of silicon,
The spacer according to claim 5, wherein an underlayer made of silicon oxide, silicon nitride, or silicon oxynitride is formed between the antistatic film and the surface of the spacer base material.

Images