JP2010071697A - Testing apparatus and testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption of a testing apparatus for electronic devices, such as LSI. <P>SOLUTION: The testing apparatus for testing a device under testing by providing the device under testing with a testing signal includes: a periodic signal generation section for generating a periodic signal providing a testing period; a pattern generation section for generating a testing pattern indicating the pattern of the testing signal and an output allowance pattern, indicating allowance for outputting the testing signal on the basis of the periodic signal; an output waveform generation section for generating an output waveform, in accordance with the testing pattern when the output allowance pattern in at least the present period of the periodic signal is in the allowed state; an allowed waveform generating section for generating an allowed waveform, in accordance with the output allowance pattern; and a signal output section for outputting the testing signal, in accordance with the output waveform, when the allowed waveform is in the allowed state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a test apparatus and a test method for an electronic device such as an LSI.

  As the semiconductor device that becomes the device under test of the test apparatus becomes highly functional, the number of terminals of the device under test to which the test signal is to be applied tends to increase. Even if the power consumption in the driver, which is the output stage of the pin that outputs the test signal, corresponding to each terminal is insignificant for each pin, the power consumption in the total number of pins is considerable as the number of terminals increases. Reach the correct value. Since an increase in power consumption results in an increase in heat generation, there is a strong demand for reducing power consumption from the problem of exhaust heat treatment.

For example, Patent Document 1 discloses an LSI test apparatus and a test method that reduce power consumption in accordance with an LSI to be tested and reduce running costs in a factory test. The LSI test apparatus has a plurality of pins P1, P2,... PN, and a function of supplying a signal for LSI test to each pin and performing a test determination. A function unit provided for each pin and each function And a clock mask function unit provided on the input side of the unit. Then, pins and functions that are not used at the time of testing are detected, and clock function units corresponding to the pins and functions are masked to reduce power consumption in units of pins and functions.
Japanese Patent Laid-Open No. 2002-22808

  According to the technique described in Patent Document 1, power consumption can be reduced by using a gated clock technique in which a clock is masked in units of pins or functions. However, when the operation differs between data writing and reading, such as a DQ (data) terminal group or DQS (data strobe) terminal group of a DRAM (Dynamic Random Access Memory), for example, the gated clock is simply used. The technique cannot be applied to mask the clock of pins or functions corresponding to DQ or DQS terminal groups.

  That is, in a cycle in which a pin corresponding to DQ or DQS is executing a write operation, it is useless to consume power by supplying a clock to the signal comparison function of the pin. On the other hand, in the cycle in which the read operation is executed, it is useless to supply the clock to the signal application function to consume power. However, as long as the pin corresponding to DQ or DQS is performing a read or write operation, the clock related to the function cannot be masked. It cannot be excluded. Therefore, a technique for dynamically controlling the clock signal is desired in order to reduce power consumption in the signal output system or signal comparison system of the test apparatus.

  In order to solve the above-described problem, in a first aspect of the present invention, a test apparatus for testing a device under test by giving a test signal to the device under test, the cycle generating a cycle signal for giving a test cycle A signal generation unit, a pattern generation unit that generates a test pattern indicating a test signal pattern and an output permission pattern indicating permission to output the test signal based on the periodic signal, and output permission of the periodic signal at least in the current cycle An output waveform generator that generates an output waveform according to the test pattern when the pattern is in a permitted state, a permission waveform generator that generates a permitted waveform according to the output permission pattern, and an output when the permitted waveform is in a permitted state Provided is a test apparatus including a signal output unit that outputs a test signal according to a waveform. When the pin connected to the device under test is a bidirectional pin, the output waveform generator described above outputs an output waveform according to the test pattern when the output permission pattern of at least the current cycle is in the permitted state. May be generated.

  The permission waveform generation unit has a pattern holding unit that holds each output permission pattern in the current cycle of the periodic signal and its preceding and following cycles, and the output waveform generation unit has each output permission pattern held by the pattern holding unit in a permitted state. At some point, an output waveform that follows the test pattern may be generated. The output waveform generation unit includes an initial cycle detection unit that detects that the periodic signal is the first cycle, and the output permission pattern is in a permitted state when the first cycle detection unit detects that it is the first cycle. Regardless of whether or not, an output waveform according to the test pattern may be generated.

  According to a second aspect of the present invention, there is provided a test method in a test apparatus for testing a device under test by supplying a test signal to the device under test, the periodic signal generating step for generating a periodic signal for giving a test cycle; A pattern generation stage for generating a test pattern indicating a test signal pattern and an output permission pattern indicating permission to output the test signal based on the periodic signal, and an output permission pattern at least in the current period of the periodic signal in the permitted state. In some cases, an output waveform generation stage for generating an output waveform according to the test pattern, a permission waveform generation stage for generating a permission waveform according to the output permission pattern, and a test signal according to the output waveform when the permission waveform is in a permission state. And a signal output stage for outputting a test method.

  In the permission waveform generation stage, the output permission pattern for three periods in the current period of the periodic signal and the preceding and succeeding periods is held, and in the output waveform generation stage, any of the output permission patterns for the three periods is in the permission state. An output waveform according to the test pattern may be generated. In the output waveform generation stage, when it is detected that the periodic signal is the first period, an output waveform according to the test pattern may be generated regardless of whether the output permission pattern is in the permitted state.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows an outline of a test apparatus 100 of this embodiment together with a device under test (DUT) 200. The test apparatus 100 tests the device under test 200 by giving a test signal to the device under test 200. The test apparatus 100 includes a periodic signal generator 102, a pattern generator 104, an output waveform generator 106, a permission waveform generator 108, an OR circuit 109, a signal output unit 110, a signal comparator 112, a timing comparator 114, and a strobe waveform shaping. Unit 116, phase delay unit 118, logic comparison unit 120, and test result storage unit 122.

  The periodic signal generator 102 generates a periodic signal RATE that gives a test period. The periodic signal RATE generated by the periodic signal generator 102 may be supplied to each unit of the test apparatus 100 and supplied to the device under test 200 as an operation clock.

  The pattern generation unit 104 generates a test pattern PAT and an output permission pattern DRE based on the periodic signal RATE. The test pattern PAT indicates a test signal pattern, and the output permission pattern DRE indicates permission to output a test signal. The pattern generation unit 104 has, for example, a pattern memory, and reads a pattern string recorded in the pattern memory according to a programmed sequence. The pattern generation unit 104 can output the read pattern sequence as the test pattern PAT.

  The output permission pattern DRE outputs, for example, logic H when the output of the test pattern PAT is permitted, and outputs logic L, for example, when the output of the test pattern PAT is not permitted. When outputting logic H as the output permission pattern DRE, the signal output unit 110 that receives the permission signal is enabled and outputs a test signal. On the other hand, when the logic L is output as the output permission pattern DRE, the signal output unit 110 is disabled and the test signal is not output. While the signal output unit 110 is disabled, the signal comparison unit 112 can legitimately measure the signal from the device under test 200.

  Further, the pattern generation unit 104 generates an expected value pattern EXP and a comparison permission signal CPE. The expected value pattern EXP indicates an expected value for the test pattern PAT. That is, the test pattern PAT is input to the device under test 200, and a value that would be output if the device under test 200 is normal is output as the expected value pattern EXP. The comparison permission signal CPE controls whether or not to enable a comparison operation for comparing a signal output from the device under test 200 with an expected value in response to an input of the test signal to the device under test 200.

  The output waveform generation unit 106 generates an output waveform according to the test pattern PAT when the output permission pattern DRE in at least the current cycle of the periodic signal RATE is in the permitted state. As an output waveform output by the output waveform generation unit 106, for example, an NRZ waveform can be exemplified. The output waveform generation unit 106 includes an output waveform shaping unit 124, phase delay circuits 126 and 128, and an SR latch 130.

  The output waveform shaping unit 124 generates a set signal S1 and a reset signal S2 for use in generating an output waveform. The set signal S1 and the reset signal S2 are generated based on the periodic signal RATE and the test pattern PAT. The phase delay circuit 126 delays the phase of the set signal S1, and the phase delay circuit 128 delays the phase of the reset signal S2. The SR latch 130 generates an output waveform according to the set signal S1 and the reset signal S2.

  The permission waveform generation unit 108 generates a permission waveform according to the output permission pattern DRE. The permission waveform generation unit 108 includes a permission waveform shaping unit 132, phase delay circuits 134 and 136, and an SR latch 138. The output of the permission waveform generation unit 108 is input to the OR circuit 109.

  The permission waveform shaping unit 132 generates a set signal S3 and a reset signal S4 for use in generating a permission waveform. The set signal S3 and the reset signal S4 are generated based on the periodic signal RATE and the output permission pattern DRE. The phase delay circuit 134 delays the phase of the set signal S3, and the phase delay circuit 136 delays the phase of the reset signal S4. The SR latch 138 generates an output waveform according to the set signal S3 and the reset signal S4.

  The OR circuit 109 outputs an OR operation result between the output of the SR latch 138 which is the output of the permission waveform generation unit 108 and the DrPinMode signal. The DrPinMode signal is a control signal that designates the mode of the signal output unit 110. For example, the logic is H for a unidirectional signal pin that only outputs a signal, and L for an input and output bidirectional signal. Logic can be assigned. That is, “1” is output regardless of the output of the SR latch 138 when DrPinMode is “1”, and the output signal of the SR latch 138 is output to the signal output unit 110 when DrPinMode is “0”.

  The signal output unit 110 outputs a test signal according to the output waveform generated by the output waveform shaping unit 124 when the permission waveform generated by the permission waveform shaping unit 132 is in the permitted state. However, it is necessary that the DrPinMode signal = “0” is input to the OR circuit 109 and the bidirectional signal mode is selected. When the DrPinMode signal is a one-way signal mode of “1”, the test signal is output according to the output waveform generated by the output waveform shaping unit 124 without depending on the permission state of the permission waveform shaping unit 132. . The test signal is supplied to the device under test 200 and used for the test.

  The signal comparison unit 112 measures a signal from the device under test 200 that responds to the test signal. The signal comparison unit 112 can compare a predetermined threshold value with a signal from the device under test 200 and output a comparison result. The timing comparison unit 114 acquires the value output by the signal comparison unit 112 at the timing indicated by the strobe signal, and outputs the acquired result as a logical value. The strobe waveform shaping unit 116 generates a strobe signal based on the periodic signal RATE. The phase delay unit 118 delays the phase of the strobe signal.

  The logical comparison unit 120 compares the logical value output from the timing comparison unit 114 with the expected value pattern EXP. The comparison result is stored in the test result storage unit 122. The test result storage unit 122 can appropriately output the stored information to the outside.

  FIG. 2 shows details of the output waveform shaping unit 124 and the allowed waveform shaping unit 132. The circuit shown in FIG. 2 includes flip-flop circuits 140, 142, 144, 146, 148, 160, 162, and 164, AND circuits 150, 156, 158, 166, and 168, and OR circuits 152 and 154. The flip-flop circuits 140 and 144 are circuits intended to delay the periodic signal RATE and the test pattern PAT by one period, and the output of the flip-flop circuit 140 is the current period.

  Since the output waveform shaping unit 124 includes AND circuits 156 and 158 that receive the periodic signal RATE, the test pattern PAT, the output permission pattern DRE, and the NRZ, the output permission is obtained in the case of a simple NRZ. When the pattern DRE is H logic in the permitted state, a set signal S1 and a reset signal S2 according to the test pattern PAT are output. Further, since the permission waveform shaping unit 132 includes AND circuits 166 and 168 that receive the periodic signal RATE, the output permission pattern DRE, and the driver pin mode signal DrPinMode, when the DrPinMode = 0, the periodic signal A set signal S3 and a reset signal S4 are output in accordance with RATE and the output permission pattern DRE. When DrPinMode = 1, the output of the set signal S3 and the reset signal S4 in this clock cycle is prohibited. When DrPinMode = 1, the OR circuit 109 shown in FIG. 1 makes the output in the signal output unit 110 unconditionally, that is, does not depend on the DER signal.

  The permission waveform generation unit 108 includes a pattern holding unit that holds each output permission pattern DRE in the current cycle of the periodic signal RATE and the preceding and succeeding cycles. The pattern holding unit can be constituted by three flip-flop circuits 160, 162, 164, for example. That is, the flip-flop circuit 160 holds the output permission pattern DRE of the previous cycle, the flip-flop circuit 162 holds the output permission pattern DRE of the current cycle, and the flip-flop circuit 164 holds the output permission pattern DRE of the subsequent cycle. it can. Since the outputs of the flip-flop circuits 160, 162, and 164 are input to the 3-input OR circuit 152, and the output of the OR circuit 152 is input to the AND circuits 156 and 158, the output waveform generation unit 106 is held by the pattern holding unit. When each output permission pattern DRE is in the permission state, an output waveform according to the test pattern PAT is generated.

  The output waveform generation unit 106 includes a first cycle detection unit that detects that the cycle signal RATE is the first cycle. The initial period detection unit can be constituted by a flip-flop circuit 148 and an AND circuit 150, for example. That is, since the logic H is always input to the input of the flip-flop circuit 148, the logic L, which is the input NOT value, is output. However, if the cycle is the first, the output is H logic that is the NOT value of the reset value, and the first cycle can be detected. As described above, when the first cycle detection unit detects that the cycle is the first cycle, the output of the AND circuit 150 and the output of the OR circuit 152 are input to the OR circuit 154. When DrPinMode = 0, the OR circuit 154 is output. Are input to inputs of AND circuits 156 and 158. Therefore, an output waveform according to the test pattern PAT is generated regardless of whether or not the output permission pattern DRE is in the permitted state. When DrPinMode = 1, the OR circuit 154 outputs the set signal S1 and the reset signal S2 regardless of the results of the AND circuit 150 and the OR circuit 152.

  With the above configuration, the output permission pattern DRE for three cycles in the current cycle of the periodic signal RATE and the preceding and succeeding cycles is held, and when any of the output permission patterns DRE for three cycles is in the permitted state, the test pattern PAT An output waveform that conforms to can be generated. When it is detected that the period signal RATE is the first period, an output waveform according to the test pattern PAT is generated regardless of whether or not the output permission pattern DRE is in the permitted state.

  Depending on the AC characteristics of the signal output unit 110 or the setting of the user program, the output waveform of the SR latch 130 or SR latch of the cycle to be controlled may be slightly shifted. In such a case, it is expected that an unexpected output waveform is observed in the signal output unit 110. However, as described above, not only the current period of the cycle but also the signal output for one period before and after can be validated to cope with such a slight deviation. A similar shift is predicted in the case of the initial operation, but such a shift can be dealt with by enabling the signal output in the first cycle regardless of the permission state of the output permission pattern.

  According to the test apparatus 100 of the above-described embodiment, the signal output unit 110 is dynamically controlled to operate when the output permission pattern DRE is in the permitted state. As a result, the power consumption can be reduced even when the operation differs between data writing and reading, as in DQ or DQS of a DRAM. Further, in addition to the current cycle of the output permission pattern DRE, by controlling the signal output unit 110 to operate in the preceding and following cycles or the first cycle, a stable test with a margin can be performed.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

An outline of the test apparatus 100 of this embodiment is shown together with a device under test (DUT) 200. The details of the output waveform shaping unit 124 and the permitted waveform shaping unit 132 are shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Test apparatus 102 Periodic signal generation part 104 Pattern generation part 106 Output waveform generation part 108 Allowed waveform generation part 109 OR circuit 110 Signal output part 112 Signal comparison part 114 Timing comparison part 116 Strobe waveform shaping part 118 Phase delay part 120 Logic comparison part 122 test result storage unit 124 output waveform shaping unit 126 phase delay circuit 128 phase delay circuit 130 SR latch 132 permission waveform shaping unit 134 phase delay circuit 136 phase delay circuit 138 SR latch 140, 142, 144, 146, 148, 160, 162 , 164 flip-flop circuit 150, 156, 158, 166, 168 AND circuit 152, 154 OR circuit 200 device under test CPE comparison enable signal DRE output enable pattern DrPinMode driver pin mode Signal EXP Expected value pattern PAT Test pattern RATE Periodic signal

Claims (6)

A test apparatus for testing a device under test by supplying a test signal to the device under test,
A periodic signal generator for generating a periodic signal for giving a test period;
A pattern generation unit that generates a test pattern indicating the pattern of the test signal and an output permission pattern indicating permission to output the test signal based on the periodic signal;
An output waveform generator for generating an output waveform according to the test pattern when the output permission pattern in at least the current cycle of the periodic signal is in a permitted state;
According to the output permission pattern, a permission waveform generation unit that generates a permission waveform;
When the permission waveform is in a permission state, a signal output unit that outputs the test signal according to the output waveform;
Test equipment with The permission waveform generation unit includes a pattern holding unit that holds each output permission pattern in the current period of the periodic signal and the period before and after the period.
The output waveform generation unit generates an output waveform according to the test pattern when each output permission pattern held by the pattern holding unit is in a permitted state.
The test apparatus according to claim 1. The output waveform generation unit includes an initial cycle detection unit that detects that the periodic signal is an initial cycle, and when the first cycle detection unit detects the initial cycle, the output permission pattern is Generate an output waveform according to the test pattern regardless of whether or not it is in a permitted state;
The test apparatus according to claim 2. A test method in a test apparatus for testing a device under test by giving a test signal to the device under test,
A periodic signal generation stage for generating a periodic signal for giving a test period;
Based on the periodic signal, a pattern generation step of generating a test pattern indicating a pattern of the test signal and an output permission pattern indicating permission to output the test signal;
An output waveform generation step of generating an output waveform according to the test pattern when the output permission pattern in at least the current cycle of the periodic signal is in a permitted state;
A permission waveform generation stage for generating a permission waveform according to the output permission pattern;
A signal output step of outputting the test signal according to the output waveform when the permission waveform is in a permission state;
A test method comprising: In the permission waveform generation stage, an output permission pattern for three periods in the current period and the period before and after the period signal is held,
In the output waveform generation step, when any of the output permission patterns for the three cycles is in a permission state, an output waveform according to the test pattern is generated.
The test method according to claim 4. In the output waveform generation step, when it is detected that the periodic signal is the first period, an output waveform according to the test pattern is generated regardless of whether or not the output permission pattern is in a permitted state.
The test method according to claim 5.

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