JP2010067677A - Semiconductor storage apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory cell capable of improving the performance of an SRAM by shortening a bit line length. <P>SOLUTION: A semiconductor storage apparatus has: first and second inverters; an NMOS transfer transistor 102a having a source 20a electrically connected to an output terminal of the first inverter, a polysilicon layer 30 as a gate electrode electrically connected to a word line 11, and a drain 20b electrically connected to a bit line 10a; and an NMOS transfer transistor 102b having a source 20a connected to an output terminal of the second inverter, a polysilicon layer 30 as a gate electrode electrically connected to a word line 11, and a drain electrically connected to a bit line 10b. A height L of a memory cell 1 is the sum of a height La of one transistor and a distance Lb from the center of the contact on the source or drain of the transistor to a borderline 40 with an adjacent cell. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a layout of an SRAM memory cell.

  A large-scale logic LSI is equipped with a static storage device (SRAM) for temporary storage of data. In recent years, due to demands for improving system performance and advances in microfabrication technology, mounted SRAMs are required to operate on a large scale and at high speed.

  In Patent Document 1, the layout of the SRAM memory cell is such that all transistors are arranged in the same direction, and the source, drain, and polycrystalline silicon layers constituting the gate electrode are each formed in a straight line.

  In general, the performance of SRAM is dominated by the time for reading data from a memory cell via a bit line (hereinafter referred to as bit line delay). This bit line delay is determined by the bit line current amount of the memory cell and the capacity load of the bit line.

  Since the amount of the bit line current is determined by the performance of the transistor of the memory cell, to improve the bit line current, it is necessary to improve the performance of the transistor or the driving power of the transistor. From the viewpoint of memory cell size, improvement is not easy.

  On the other hand, the bit line load capacitance is composed of the capacitance of the bit line terminal of the memory cell and the wiring capacitance of the bit line. In order to reduce the bit line wiring capacity in the same cell array configuration, it is effective to reduce the size (height L) of the memory cells in the bit line direction, that is, to shorten the bit line length.

  In the conventional example shown in FIG. 2 of Patent Document 1, the height L of the cell is determined by the height of two transistors including N-channel MOS transistors N3 and N5 arranged on the same straight line. Two heights are required, which may cause bit line delay.

In addition, the data retention characteristics of the SRAM cell are determined by the size ratio of the driver transistor and the transfer transistor. However, in the conventional example, when the width of each transistor is different, the diffusion layer does not have to be rectangular, and it is necessary to provide unevenness. there were. For this reason, from the viewpoint of lithography, there has been a possibility that the variation in the size of the transistor becomes large and miniaturization becomes difficult.
JP 2002-43441 (FIG. 2)

  An object of the present invention is to provide a memory cell capable of improving the performance of an SRAM by shortening the bit line length.

  In order to achieve the above object, a semiconductor memory device according to one embodiment of the present invention includes a first N-channel MOSFET, a first inverter including a first P-channel MOSFET, and a second N-channel MOSFET. And a second P-channel MOSFET having an input terminal electrically connected to the output terminal of the first inverter and an output terminal electrically connected to the input terminal of the first inverter. An inverter, a third N-channel MOSFET in which the output terminal of the first inverter is electrically connected to the source, the word line is electrically connected to the gate, and the first bit line is electrically connected to the drain; and the second inverter A first memory cell comprising a fourth N-channel MOSFET having an output terminal electrically connected to the source, a word line electrically connected to the gate, and a second bit line electrically connected to the drain; And wiring layers used for the gate electrodes of the first N-channel MOSFET, the first P-channel MOSFET, and the third N-channel MOSFET are on the same straight line, Wiring layers used for the gate electrodes of the two N-channel MOSFETs, the second P-channel MOSFET, and the fourth N-channel MOSFET are on the same straight line, and the first bit line And the wiring length of the second bit line is the height La from the center of the contact on the source of the third or fourth N-channel MOSFET of the first memory cell to the center of the contact on the drain. And a boundary line between the first memory cell and the second memory cell connected in the height direction, and the third or fourth N-channel MOSFET. The distance between the center of contacts on the scan is characterized in that it is a sum of Lb.

  According to the present invention, it is possible to provide a memory cell capable of improving the performance of the SRAM by shortening the bit line length.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
1A and 1B are plan views of the layout configuration in all layers of the memory cell of the semiconductor memory device according to the first embodiment of the present invention. FIG. 1C is an equivalent circuit diagram of an SRAM memory cell including the six transistors shown in FIG. 2 is a plan view mainly showing a layout configuration below the metal wiring layer in FIG. 1, and FIG. 3 is a plan view mainly showing a layout configuration on the metal wiring layer in FIG. That is, FIGS. 2 and 3 are supplementary diagrams of FIG. 1 that are shown separately for each wiring layer in order to facilitate understanding of the layout configuration shown in FIG.

  First, the overall layout configuration of the memory cell 1 of the present embodiment will be described with reference to FIGS.

  The memory cell 1 of the present embodiment is formed in a region where an N well is formed in the center and P wells are formed on both sides thereof. PMOS load transistors 100a and 100b, which are first P-channel MOSFETs, are formed in the central N well. Of the P wells formed on both sides of the N well, the P well formed on the PMOS load transistor 100a side. The NMOS driver transistor 101a, which is the first N-channel MOSFET, and the NMOS transfer transistor 102a, which is the third N-channel MOSFET, are formed. The P-well formed on the PMOS load transistor 100b side includes the first N-channel MOSFET 101a. An NMOS driver transistor 101b, which is a second N-channel MOSFET, and an NMOS transfer transistor 102b, which is a fourth N-channel MOSFET, are formed.

  The PMOS load transistor 100a and the NMOS driver transistor 101a form a first inverter, and the PMOS load transistor 100b and the NMOS driver transistor 101b form a second inverter.

  Next, a layout configuration under the metal wiring layer 31 will be described with reference to FIG.

  The arrangement direction of the source 20a and the drain 20b of all of the PMOS load transistors 100a and 100b, the NMOS driver transistors 101a and 101b, and the NMOS transfer transistors 102a and 102b is parallel to the boundary line between the P well and the N well. The drain 20b of the PMOS load transistor 100a, the drain 20b of the NMOS driver transistor 101a, and the source 20a of the NMOS transfer transistor 102a are electrically connected to the same linear metal wiring layer 31 through the vias 21, respectively. Connected. Similarly, the drain 20b of the PMOS load transistor 100b, the drain 20b of the NMOS driver transistor 101b, and the source 20a of the NMOS transfer transistor 102b are electrically connected to the metal wiring layer 31 on the same straight line via the vias 21, respectively.

  Furthermore, the polycrystalline silicon layers 30 which are the gate electrodes of the PMOS load transistor 100a, the NMOS driver transistor 101a, and the NMOS transfer transistor 102a are formed on the same straight line. Similarly, the polycrystalline silicon layers 30 which are the gate electrodes of the PMOS load transistor 100b, the NMOS driver transistor 101b, and the NMOS transfer transistor 102b are formed on the same straight line. Note that the gate electrodes of the PMOS load transistor 100a and the NMOS driver transistor 101a that form the first inverter are electrically connected to each other, and similarly, the PMOS load transistor 100b and the NMOS driver transistor 101b that form the second inverter. The gate electrodes are electrically connected to each other.

  Further, the power supply line VDD is electrically connected to the sources 20a of the PMOS load transistors 100a and 100b via the vias 21, and the ground line GND is electrically connected to the NMOS driver transistors 101a and 101b via the vias 21. Is done. The NMOS transfer transistor 102a is electrically connected to the bit line (BL) 10a via the via 21, and the NMOS transfer transistor 102b is electrically connected to the bit line (/ BL) 10b via the via 21. Further, the word lines 11 are electrically connected to the gate electrodes of the NMOS transfer transistors 102 a and 102 b through the vias 21, respectively.

  Next, a layout configuration on the metal wiring layer 30 will be described with reference to FIG.

  In this layout, a power supply line VDD, a ground line GND, a bit line (BL) 10a, a bit line (/ BL) 10b, and a word line 11 are arranged. These lines are electrically connected through the vias 21 described above. Among these, the power supply line VDD, the ground line GND, the bit line (BL) 10a, and the bit line (/ BL) 10b are formed by linear metal wiring parallel to the boundary line between the N well and the P well. These power supply line VDD, ground line GND, bit line (BL) 10a, and bit line (/ BL) 10b are connected to the power supply line VDD and ground line of each memory cell 1 connected vertically as shown in FIG. They are electrically connected to the GND, the bit line (BL) 10a, and the bit line (/ BL) 10b, respectively.

  On the other hand, the word line 11 is a linear metal wiring on the power supply line VDD, the ground line GND, the bit line (BL) 10a, and the bit line (/ BL) orthogonal to the boundary line between the N well and the P well. Thus, the via 21 electrically connected to the gate electrode of the NMOS transfer transistor 102a is connected to the via 21 electrically connected to the gate electrode of the NMOS transfer transistor 102b.

  Usually, the SRAM is constituted by a memory macro in which a plurality of memory cells 1 are arranged. As described above, in this memory macro, a plurality of memory cells 1 are arranged symmetrically with respect to the boundary line 40 so as to be connected in the height direction of the memory cells, as shown in FIG.

  At this time, the height L of the cell is the sum of the height La of one transistor and the distance Lb from the center of the contact on the source or drain of the transistor to the boundary line 40 with the connected cell. Here, the height of one transistor means the height from the center of the contact on the source of the transistor to the center of the contact on the drain. Specifically, in FIG. 4, the height from the center of the contact on the source 20a of the NMOS transfer transistor 102b to the center of the contact on the drain 20b is La, and the other is connected in the height direction of the memory cell 1. The distance between the boundary line with the memory cell 1 and the center of the contact on the source 20a of the NMOS transfer transistor 102b is Lb.

  Since this Lb is smaller than the height La of one transistor, the memory cell of the present invention is smaller than the height of two transistors, and the height can be reduced in the bit line direction as compared with the conventional example. It is.

  The reduction in the bit line direction reduces the bit line capacitance load and the bit line delay. Specifically, the cell height L is changed from 2La for two transistors to La + Lb obtained by adding Lb to the height for one transistor, which is reduced by about 25% from the height of the conventional cell. In general, since the wiring occupies about 50% of the bit line capacity, the bit line capacity is reduced by about 12.5% by using the memory cell of the present invention.

  On the other hand, the increase in the word line direction increases the word line load, which may reduce the operation speed of the encoding circuit. In response to this, the driving force of the word line buffer for driving the word line is increased. It is easily possible to prevent this.

  According to the present embodiment, the PMOS load transistor, NMOS driver transistor, and NMOS transfer transistor are all arranged on the same straight line, and the transistors are aligned in the same direction, and the polysilicon layer of the gate electrode of each transistor By arranging the lines in a straight line, the bit line capacitance is reduced by reducing the cell height. This reduces bit line delay and speeds up data access.

  In the memory cell of the present invention, the driver transistor and the transfer transistor are each composed of independent diffusion layers, and each diffusion layer has no irregularities and is formed in a rectangular shape. It can be adjusted easily and is suitable for fine processing. Thereby, since the size of each transistor can be set freely, the degree of freedom in designing the memory cell is increased.

(Second Embodiment)
FIG. 5 is a plan view of the layout configuration of the memory macro in the semiconductor memory device according to the second embodiment of the present invention. The present embodiment is a memory macro in which the memory cells of the first embodiment are laid out in an array.

  In this embodiment, a memory array 200 in which memory cells of 64 rows × 128 columns are arranged, an address decoder 201 that specifies the address of each word line, and a read / write circuit 202 that reads and writes data specified by the address decoder 201. It consists of and. The Read / Write circuit 202 includes a sense amplifier 203 that amplifies the read data. Further, as described above, each memory cell 1 is arranged symmetrically with respect to the upper and lower boundary lines of each memory cell, as shown in FIG.

  In the memory cell, the power supply line VDD and the ground line GND are formed in parallel to the bit line 10a.

  According to the present embodiment, since the memory cell having a cell height lower than that of the conventional memory cell is used, even when 64 row memory cells are arranged, the length of the bit line becomes shorter than the conventional memory cell. Data access is speeded up and memory macro performance can be improved.

  In addition, since the memory macro according to the present embodiment has a wide width in the word line direction, the layout of the sense amplifier is facilitated.

  In this embodiment, the horizontal width of the memory array is large, but generally the peripheral width of peripheral circuits such as data latches and output buffers is larger than the horizontal width of the memory array. It does not contribute to the overall size.

  The number of memory cells arranged is not limited to this.

(Third embodiment)
FIG. 6 is a layout of a static semiconductor memory device according to the third embodiment of the present invention. In the present embodiment, the number of rows is doubled compared to the second embodiment.

  Conventionally, for example, when arranging 128 row × 128 column memory cells, if the 128 row memory cells are arranged in one column on one bit line 100a, the height dimension becomes large, so that two column memory cells are arranged. Are combined into one using Mux (Multiplexer), and the two-column memory cells are arranged in 64 rows, but in this embodiment, a memory cell having a lower cell height than a conventional memory cell is used. , 128 rows of memory cells can be arranged.

  According to the present embodiment, since the number of memory cells electrically connected to one bit line can be increased, a memory macro having the same configuration as the conventional one can be formed without using Mux. .

  Note that although the number of memory cells electrically connected to the bit line increases, the wiring length is not so large, so that an increase in bit line capacitance can be suppressed.

  Further, since the Mux is unnecessary, the read data delay is further reduced, the data access is speeded up, and the performance of the memory macro can be improved.

  Conventionally, since a 2-column memory cell is electrically connected to one word line, even when only one memory cell from which data is read is activated, it is necessary to read the other data. Although the bit lines that do not need to be activated are also activated, in the present embodiment, only the necessary bit lines are activated, so that power consumption can be reduced.

  In this embodiment, the horizontal width of the memory array is large, but generally the peripheral width of peripheral circuits such as data latches and output buffers is larger than the horizontal width of the memory array. It does not contribute to the overall size.

  The number of memory cells arranged is not limited to this.

1 is a plan view of a semiconductor memory device according to a first embodiment. 1 is a plan view showing a base layout of a semiconductor memory device according to a first embodiment; 1 is a plan view showing an upper layout of a semiconductor memory device according to a first embodiment. 1 is a plan view of a case where semiconductor memory devices according to a first embodiment are connected. FIG. 6 is a plan view of a semiconductor memory device according to a second embodiment. It is a circuit diagram of a third embodiment and a conventional semiconductor memory device.

Explanation of symbols

1: Memory cell 10a: Bit line (BL)
10b: Bit line (/ BL)
11: Word line (WL)
20: diffusion layer 20a: source 20b: drain 21: via 22: contact 30: polycrystalline silicon layer 31: metal wiring layer 40: boundary lines 100a, 100b: load transistors 101a, 101b: driver transistors 102a, 102b: transfer transistor 200 : Cell array 201: Address decoder 202: Read / Write circuit 203: Sense amplifier 204: Mux

Claims (5)

A first inverter composed of a first N-channel MOSFET and a first P-channel MOSFET;
The input terminal is electrically connected to the output terminal of the first inverter, and the output terminal is electrically connected to the input terminal of the first inverter. A connected second inverter;
A third N-channel MOSFET in which the output terminal of the first inverter is electrically connected to the source, the word line is electrically connected to the gate, and the first bit line is electrically connected to the drain;
A first memory cell comprising a fourth N-channel MOSFET having an output terminal of the second inverter electrically connected to the source, a word line connected to the gate, and a second bit line electrically connected to the drain; ,
The wiring layers used for the gate electrodes of the first N-channel MOSFET, the first P-channel MOSFET, and the third N-channel MOSFET are on the same straight line,
The wiring layers used for the gate electrodes of the second N-channel MOSFET, the second P-channel MOSFET, and the fourth N-channel MOSFET are on the same straight line,
The wiring lengths of the first bit line and the second bit line are:
A height La from the center of the contact on the source of the third or fourth N-channel MOSFET of the first memory cell to the center of the contact on the drain;
The distance between the boundary line between the first memory cell and the second memory cell connected in the height direction and the center of the contact on the source of the third or fourth N-channel MOSFET is Lb. A semiconductor memory device characterized by the sum of The first and second P-channel MOSFETs are formed in an N well,
The first and third N-channel MOSFETs and the second and fourth N-channel MOSFETs are formed in P wells formed on both sides of the N well, respectively.
The source and drain of each of the first to fourth N-channel MOSFETs and the first and second P-channel MOSFETs are formed in a rectangular shape, and the arrangement direction thereof is the first to fourth N-channel MOSFETs. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is parallel to a boundary line between the formed P-well and the N-well in which the first and second P-channel MOSFETs are formed. The first bit line, the second bit line, the first power supply line, the second power supply line, the first ground line, and the second ground line are respectively connected to the third N-channel MOSFET. The drain of the fourth N-channel MOSFET, the source of the first P-channel MOSFET, the source of the second P-channel MOSFET, the source of the first N-channel MOSFET And electrically connected to the open ends of the vias electrically connected to the source of the second N-channel MOSFET,
The first bit line, the second bit line, the first power supply line, the second power supply line, the first ground line, and the second ground line are boundaries between the N well and the P well. Formed in parallel with the line and in a straight line,
The word line is perpendicular to a boundary line between the N well and the P well on the first and second power supply lines, the first and second ground lines, and the first and second bit lines. And an open end of a via electrically connected to the gate electrode of the first N-channel MOSFET and a gate electrode of the second N-channel MOSFET in a straight line. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is formed to connect to an open end of the via. With respect to the boundary line in the long side direction of the memory cell composed of the first inverter, the second inverter, the third N-channel MOSFET, and the fourth N-channel MOSFET A memory array in which a plurality of the memory cells are arranged in line symmetry,
An address decoder for designating an address of each word line of the memory array;
A read / write circuit for reading and writing data stored at the address designated by the address decoder;
The semiconductor memory device according to claim 1, further comprising:   5. The semiconductor memory device according to claim 4, wherein the read / write circuit includes a sense amplifier that amplifies read data.

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