JP2010066593A - Driver ic and electrooptical apparatus using it - Google Patents

Abstract

Data of a specified gradation bit number that is less than the maximum gradation bit number can be stored as it is in a display data RAM with variable gradation bit number / pixel, read from the RAM, and input to an analog-digital conversion circuit The converted data is converted into the number of gradation bits / pixel.
A driver IC that drives a display panel by supplying a data signal corresponding to the number of gradation bits / pixel of the display panel to the display panel includes a RAM and a line address circuit that specifies a line address of the RAM. The RAM is 2k (2) satisfying k = log ₂ (n1 / n2) where n1 is the maximum gradation bit number (n1 is an integer of 2 or more) and n2 (1 ≦ n2 ≦ n1) is the designated gradation bit number. k is 0 or a natural number) n2 display data is stored divided into frames. The line address circuit generates an M-bit line address corresponding to n1 (M is an integer of 2 or more), and outputs an M-bit line read address offset according to a k-bit frame address that is an offset value.
[Selection] Figure 11

Description

  The present invention relates to a driver IC for driving a display panel having an electro-optical element, an electro-optical device using the driver IC, and the like.

  For example, as a liquid crystal driver IC, a display data RAM, a latch circuit that latches the RAM output, a digital-analog conversion circuit that converts the latched display data (digital value) into an analog gradation voltage, and a gradation voltage And a driver unit for driving data signal lines of the liquid crystal panel.

  Some liquid crystal driver ICs of this type can change the number of gradation bits per pixel (Bit Per Pixel). However, the number of gradation bits input to the digital-analog conversion circuit is fixed at the maximum number of gradation bits. Therefore, when data having a gradation bit number less than the maximum gradation bit number is input, it is necessary to replace the data with the maximum gradation bit number upstream of the digital-analog conversion circuit in the driver IC.

  2. Description of the Related Art Conventionally, two methods are broadly known as methods of replacing data with a gradation bit number less than the maximum gradation bit number with the maximum gradation bit number. One is a method of increasing the bit number by adding the MSB of the data to the LSB of the data when data having a gradation bit number less than the maximum gradation bit number is input.

The other one, as described in Patent Document 1, is to convert data having a gradation bit number less than the maximum gradation bit number into a maximum gradation bit number using a lookup table.
JP 2003-241733 A

  In the two methods described above, a circuit that allocates the MSB of input data to the LSB and a lookup table are required, and the circuit scale in the driver IC increases.

  Furthermore, since these additional circuits are provided upstream of the display data RAM and the number of bits is increased, even if the number of gradation bits of the input multiple data is less than the maximum gradation bit number, The occupied storage area is the same as the data of the maximum number of gradation bits. Therefore, the number of frames of display data that can be stored in the display data RAM cannot be increased in inverse proportion to the reduction in the number of gradation bits per pixel.

  Therefore, an object of the present invention is to make the number of gradation bits per pixel variable and to store each data of the maximum gradation bit number and the gradation bit number less than that in the display data RAM without changing the gradation bit number. Provided is a driver IC that can store and read data of a gradation bit number less than the maximum gradation bit number by using a line address used for data of the maximum gradation bit number, and an electro-optical device using the driver IC It is in.

  Another object of the present invention is that the number of gradation bits per pixel is variable, and data of a specified gradation bit number that is equal to or less than the maximum gradation bit number can be stored in the display data RAM as it is and read out from the RAM. Another object of the present invention is to provide a driver IC capable of converting data input to an analog-digital conversion circuit into the maximum number of gradation bits per pixel and an electro-optical device using the driver IC.

One aspect of the present invention is a driver IC that supplies and drives a data signal corresponding to the number of gradation bits per pixel (Bit Per Pixel) to a plurality of data signal lines of the display panel.
A RAM having a capacity for storing display data of the maximum number of gradation bits for at least one frame;
A line address circuit for designating a line read address of the RAM;
A drive circuit for driving the plurality of data signal lines based on an output from the RAM;
Have
In the RAM, when the maximum gradation bit number is n1 (n1 is an integer of 2 or more) and the designated gradation bit number is n2 (1 ≦ n2 ≦ n1), k = log ₂ (n1 / n2) is set. The display data of the designated gradation bit number n2 is stored divided into 2 ^k (k is 0 or a natural number) frames to satisfy,
The line address circuit generates a line address of M (M is an integer of 2 or more) bits corresponding to the maximum gradation bit number n1, and is offset according to a k-bit frame address which is an offset value. The present invention relates to a driver IC characterized by outputting a line read address.

According to one aspect of the present invention, the number of gradation bits per pixel is variable, and each data of the maximum gradation bit number n1 and a gradation bit number less than that is stored in the RAM. The number of gradation bits can be stored in the display data RAM, and data having a gradation bit number less than the maximum gradation bit number can be read using an M-bit line address used for data having the maximum gradation bit number. For example, when there is an M-bit display line counter (corresponding to a scanning line row number), k = 0 when the maximum number of gradation bits is 4 (4 BPP: Bit Per Pixel), and 2 ^k = 1 frame is stored. The displayed display data is read out with an Mk = M bit line read address without offset (display line counter line address = line read address). In the specified gradation bit number 2 (2BPP), k = 1, and 2 ^k = 2 frames are stored in 2 ^k = 2 frames, and the upper (M−k) bits of the M-bit display line counter are stored in the upper (M−k) bits. Display data is read by designating an M-bit line read address obtained by being offset (added) by a value corresponding to a k-bit frame address. When the specified gradation bit number is 1 (1 BPP), k = 2 and 2 ^k = 4 frames are divided into 1-bit 1-bit data and stored in the upper (Mk) bits of the M-bit display line counter. The display data is read by designating an M-bit line read address obtained by being offset (added) by a value corresponding to the bit frame address. In any case, an M-bit line read address can be generated by adding the k-bit frame address to the upper (Mk) bits of the display line counter. Note that the lower k bits of the M-bit line address can be used as a timing switching signal after output from the RAM, as will be described later.

  In one aspect of the present invention, the line address circuit generates a frame address that generates a frame address of k bits that is an offset value based on the counter that generates the line address of M bits and the number n2 of designated gradation bits. The k-bit frame address is added to the high-order side of the high-order (Mk) bits of the M-bit line address that is the output of the generation circuit and the counter, and the offset M-bit line read address is added to the RAM. And an adder that outputs to the output.

  Thus, when n1 = n2, the counter output line address is used as the line read address as it is, and when n1 <n2, the line address from the first line to the end line of the first frame is set by the offset M-bit line read address. After the designation, the first line address of the second frame can be addressed by another M-bit line read address.

In one aspect of the present invention, the drive circuit includes:
The plurality of digital-analog conversion circuits;
A power supply circuit for supplying an analog gradation voltage to the plurality of digital-analog conversion circuits;
A plurality of data selectors provided between the plurality of digital-analog conversion circuits and the RAM;
Each of the plurality of digital-analog conversion circuits includes 2 ⁿ¹ 1-bit coincidence detection circuits,
The data selector selects n1 bits, which are the RAM outputs, n2 bits at a time based on a select signal, and selects a higher order of n2 bits selected based on a mode signal for selecting the designated gradation bit number n2. By adding 0 to n0 (n0 = n1-n2) bits, the data length per pixel input to the 1-bit coincidence detection circuit can be set to n1 bits regardless of the number of designated gradation bits.

  As described above, the RAM can be stored in the display data RAM as it is with the designated gradation bit number, and data of the maximum gradation bit number n1 is input to the plurality of analog-digital conversion circuits regardless of the designated gradation bit number. be able to.

  In one aspect of the present invention, the data selector can input a lower k-bit address of the M-bit line address as the select signal switching timing signal. For example, when the maximum number of gradation bits is 4 (4 BPP), k = 0, and selection signal switching is not necessary. When the designated gradation bit number is 2 (2 BPP), k = 1, and the selector signal is switched by k = 1 bit, and the display data can be output in two steps. When the designated gradation bit number is 1 (1 BPP), k = 2, and the selector signal is switched by k = 2 bits, so that the display data can be output in four steps.

In one aspect of the present invention, when the maximum gradation bit number n1 is set, the power supply circuit is subjected to 2 ⁿ¹ gamma correction from S (S> 2 ⁿ¹ ) analog voltages based on the setting data. Including multiple analog switches to select different gradation voltages,
The setting data includes BPP switching data, said plurality of analog switches can be a 2 ⁿ² pieces of gradation voltages selected based on the specified gradation bit number n2.

As described above, 2 ⁿ² gradation voltages corresponding to the designated gradation bit number n2 can be selected using the power supply circuit used as the gamma correction circuit.

In one aspect of the present invention, the plurality of analog switches are input to the 1-bit coincidence detection circuit for each specified gradation bit number except for one of the maximum and minimum voltages of the 2 ⁿ¹ gradation voltages. Different gradation voltages can be selected for the same n1 bit data.

For example n1 = 4 with the exception of one of the maximum and minimum voltage of ² n1 = 16 pieces of gradation voltages (V0-V15) when the (4 BPP) (e.g. V0), for each specified gradation bits number n2, 1 bit Different gradation voltages (for example, V1, V5, V15) can be selected for the same n1 bit data (for example, 0001) input to the coincidence detection circuit.

Another aspect of the present invention is a driver IC that supplies and drives a data signal corresponding to the number of gradation bits per pixel (Bit Per Pixel) to a plurality of data signal lines of the display panel.
A RAM having a capacity for storing display data of the maximum number of gradation bits for at least one frame;
A drive circuit for driving the plurality of data signal lines based on an output from the RAM;
Have
In the RAM, when the maximum gradation bit number is n1 (n1 is an integer of 2 or more) and the designated gradation bit number is n2 (1 ≦ n2 ≦ n1), display data of the designated gradation bit number n2 is displayed. Store and
The drive circuit is
The plurality of digital-analog conversion circuits;
A power supply circuit for supplying an analog gradation voltage to the plurality of digital-analog conversion circuits;
A plurality of data selectors provided between the plurality of digital-analog conversion circuits and the RAM;
Wherein the plurality of digital - each of the analog conversion circuit includes a 2 ⁿ¹ pieces of 1-bit coincidence detector circuit,
The data selector selects n1 bits, which are the RAM outputs, n2 bits at a time based on a select signal, and selects a higher order of n2 bits selected based on a mode signal for selecting the designated gradation bit number n2. The present invention relates to a driver IC characterized in that 0 is added to n0 (n0 = n1-n2) bits so that the data length per pixel input to the 1-bit coincidence detection circuit is n1 bits.

  According to another aspect of the present invention, the number of gradation bits per pixel can be made variable, and data with a designated gradation bit number n2 equal to or less than the maximum gradation bit number can be stored in the display data RAM as it is. Can be converted into the maximum number of gradation bits n1 per pixel.

At this time, as described above, the counter further generates a line address of M (M is an integer of 2 or more) bits corresponding to the maximum number of gradation bits n1, and the data selector switches the select signal. As a timing signal, a low-order k-bit address satisfying k = log ₂ (n1 / n2) among the M-bit line addresses can be supplied.

  In another aspect of the present invention, a polarity inversion circuit that digitally inverts the output of the data selector in a predetermined cycle is provided between each of the plurality of digital-analog conversion circuits and each of the data selectors. Can have. At this time, the polarity inversion circuit does not invert the upper n0 data among the outputs of the data selector. Thereby, the polarity of the output of the data selector can be digitally inverted, and the voltage applied to the electro-optical element can be inverted at a predetermined cycle. Note that the polarity inversion drive may invert analog gradation voltages supplied to a plurality of digital-analog conversion circuits.

Still another aspect of the present invention provides:
An electro-optical device is defined that includes a display panel including an electro-optical element driven by a plurality of scanning lines and a plurality of data signal lines, and a driver IC according to any one of the above-described embodiments. .

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

(Display unit)
FIG. 1 is a plan view of a vehicle-mounted display unit (electro-optical device in a broad sense) according to this embodiment. The in-vehicle display unit 10 includes a display panel 20, an MPU (microprocessor unit) 30, and a driver IC 100.

  The display panel 20 is an amorphous Si-TFT liquid crystal panel having 320 × 320 pixels, for example, the number of pixels in the X direction X1 = 320 and the number of pixels in the Y direction Y1 = 320. Each pixel of the display panel 20 includes a thin film transistor (TFT) T having a gate connected to a scanning line (gate line) G and a source connected to a data signal line (source line) S, as shown in FIG. The storage capacitor C, the pixel electrode P, and the like are included. The display panel 20 has Y1 scanning lines G extending along the X direction and arranged at equal intervals in the Y direction, and X1 lines extending along the Y direction and arranged at equal intervals in the X direction. Data signal line S. The liquid crystal panel 20 includes an active matrix substrate on which scanning lines G, data signal lines S, thin film transistors T, pixel electrodes P and the like are formed, and a counter substrate on which counter electrodes facing all the pixel electrodes P are formed. The liquid crystal is an electro-optic element.

  The driver IC 100 shown in FIG. 1 sets each pixel of the liquid crystal panel 20 based on a command from the MPU 30, parameters or data following the command, for example, a BPP (Bit Peripheral) of any one of 2 gradations, 4 gradations, and 16 gradations. This is a one-chip driver IC that can be driven in the (Pixel) mode. The driver IC 100 can have, for example, bumps compatible with COG (Chip on Glass) that can be directly mounted on a wiring region on an active matrix substrate (glass substrate). Thus, a display module (which is also an electro-optical device) can be configured by the display panel 20 and the driver IC 100.

  The peripheral edge of the liquid crystal panel 20 according to the present embodiment is covered with the outer frame 40, and the exposed area inside the opening 42 of the outer frame 40 has, for example, the number of pixels in the X direction X2 = 200 and the number of pixels in the Y direction. It is a rectangular area composed of Y2 = 200.

  The effective display area 20A of 200 × 200 pixels exposed inside the opening 42 has a center image area 20B and a border area 20C at the periphery thereof. The number of pixels X3 and X4 in the X direction and the number of pixels Y3 and Y4 in the Y direction, which are the width of the border area 20C, are about several pixels, respectively. In this embodiment, X3 = X4 = Y3 = Y4 = 2 pixels.

  The border area 20C is a connecting portion between the outer frame 40 and the center image area 20B. The material of the outer frame 40 that covers the periphery of the display unit 10 is plastic, for example, and the outermost surface of the central region 20B of the display panel 20 is glass, and the connecting portion between the outer frame 40 and the central image region 20B of different materials is used. For the purpose of making it look neat or making the connecting portion inconspicuous, only the width of, for example, two pixels at the periphery of the effective display area 20A is driven as a border area 20C with a specific gradation value. In the present embodiment, for example, black is displayed in order to make the border area 20 </ b> C the same color as the color of the outer frame 40.

(Driver IC)
FIG. 3 is a block diagram of the driver IC 100. In FIG. 3, a system interface 102 is an interface for inputting and outputting signals to and from the MPU 30 shown in FIG. The system interface 102 has the following terminals as control terminals. When LOW is input to the chip select terminal XCS, data / commands can be input / output. Data bus terminals D0 to D7 receive and input 8-bit data or commands in parallel. In the identification terminal AO, when HIGH is input, data (or a parameter following the command) is input to the data bus terminals D0 to D7, and when LOW is input, a command is input to the data bus terminals D0 to D7. . The read terminal XRD sets the data bus terminals D0 to D7 to an output state over a period during which LOW is input. A write signal from the MPU 30 is input to the write terminal XWR, and a signal to the data bus terminals D0 to D7 is latched at the rising edge of the write signal. A serial clock is input to the serial clock terminal SCL, serial data is input to the serial data input terminal SD, and a serial / parallel identification signal is input to the MPU interface selection terminal IF.

The control logic circuit 104 formed of a gate array includes a decoder / register for a command / parameter from the data bus terminals D0 to D7 or the serial data input terminal SD, and the like. The multi-time PROM 106, which is a non-volatile memory, is used to adjust the offset of the electronic volume for the voltage value VcomH applied to the counter electrode, for example, as control data specific to the display panel 10 to which the driver IC 100 is connected, for example, image quality adjustment data. Control data and the like are stored. Thus, by storing the control data specific to the display panel 20 in the driver IC used as a set with the display panel 20, image quality adjustment can be performed for each display module composed of the display panel 20 and the driver IC 100. It becomes possible. The driver IC 100 or MPU 30 is connected to a non-volatile memory having a larger capacity than the multi-time PROM 106, for example, E ² PROM, and can store control data other than control data unique to the display panel 20. The multi-time PROM 106 can be electrically rewritten up to about 5 times, and can store user ID data and the like in addition to the image quality adjustment data described above. The oscillation circuit 108 generates a reference clock inside the driver IC 100.

  The driver IC 100 includes a display data RAM 110 that stores display data. In the present embodiment, in order to display each pixel of 320 × 320 with the maximum number of gradations 16 (4 BPP), the storage capacity is 320 × 320 × 4 bits. That is, the display data RAM 110 can store display data for at least one frame in the 4BPP mode. If the number of gradations per pixel decreases, the display data for one frame decreases, and the number of frames of display data that can be stored in the RAM 110 increases in inverse proportion to the number of bits of BPP (Bit Per Pixel). That is, in 2 BPP (4 gradations), one frame data is 320 × 320 × 2 bits, so that the display data RAM 110 can store display data for two frames. Similarly, in 1 BPP (2 gradations), one frame data is 320 × 320 × 1 bit, and therefore display data for four frames can be stored in the display data RAM 110.

  As peripheral circuits of the display data RAM 110, an I / O buffer 112, a display timing generation circuit 114, a page address circuit 116, a column address circuit 118, and a line address circuit 120 are provided. Data is input / output between the MPU 30 and the display data RAM 110 via the system interface 102, the control logic 104, and the I / O buffer 112. The control logic 104 can include a write bus holder, a read bus holder, and the like in addition to various decoders and registers.

  For the display data RAM 110, the page address circuit 116 and the column address circuit 118 are used when inputting / outputting display data to / from the MPU 30, and the line address circuit 120 is used when driving the display panel 20. Timing signals from the display timing generation circuit 114 are input to these address circuits 116-120.

  In order to drive the display panel 20 based on the display data of the display data RAM 110, a display data latch circuit 122 and a source driver (driver circuit in a broad sense) 130 for driving 320 source lines S are provided.

  A power supply circuit 140 that supplies a voltage to each part of the driver IC 100 is provided. The power supply circuit 140 generates and supplies a necessary voltage to each part of the driver IC 100 based on a voltage supplied from the outside. The power supply circuit 140 includes a gamma correction circuit for supplying a gradation voltage to a digital-analog conversion circuit (DAC) provided in the source driver 130.

  The driver IC 100 includes gate drivers 142A and 142B that drive 320 gate lines G. As shown in FIG. 1, since it is not necessary to drive the gate lines in the region (non-display region) covered by the outer frame 40, in the present embodiment, if the 320 gate lines are G0 to G319, FIG. The gate lines G0 to G59 and the gate lines G260 to G319 corresponding to 60 both ends in the Y direction of 1 may not be connected to the driver IC 100. Alternatively, when all the gate lines are connected to the driver IC 100, the non-display area may be set by the partial drive described above.

(Relationship between memory space of display data RAM and display space in each BPP mode)
FIG. 4 shows a memory space of the display data RAM 110, and FIGS. 5 to 7 show a bit arrangement for each pixel of the display data RAM 110 in each mode of 4BPP, 2BPP, and 1BPP on the display space. As shown in FIG. 4, in the display data RAM 110, in the maximum gradation number 16 (4 BPP) mode, 8-bit data D0 to D7 for two pixels are displayed in the memory space (FIG. 4) and the display space (FIG. 5). It is stored in 4 bits × 2 lines per pixel so that there are also 2 lines on the top. That is, 8-bit data D0-D7, which is an internal data bus unit, corresponds to the first line data (D0-D3) and the second line data (D4-D7).

  Since 8-bit data D0-D7, which is an internal data bus unit, is stored in 4 bits × 2 lines per pixel, the display data RAM 110 is address-managed with page addresses having 2 lines per page as shown in FIG. The Since there are 320 lines in the present embodiment, the display data RAM 110 has 160 pages (page addresses 0 to 159) as shown in FIG. Note that 4-bit display data (corresponding to the maximum number of gradation bits) read from two lines of the display data RAM 110 is latched by the display data latch circuit 122 shown in FIG. However, as will be described later, the display data latch circuit 122 may be omitted.

  When the MPU 30 stores display data in the display data RAM 110, the line direction is specified by a page address. In the page address method, display data is stored in a rectangular memory space specified by a start page address, an end page address, a start column address, and an end column address. Therefore, all the 320 × 320 pixel areas, the 200 × 200 effective display area 20A shown in FIG. 1, or the specific rewrite rectangular area can be collectively addressed by the page address method.

  On the other hand, in the 4-tone (2BPP) mode shown in FIG. 6, the display data stored in the memory space shown in FIG. 4 corresponds to the bit arrangement of the display space shown in FIG. That is, 8-bit data D0-D7, which is an internal data bus unit, corresponds to 2 bits × 4 lines per pixel, the first line data (D0, D1), the second line data (D2, D3), the third line It corresponds to the data (D4, D5) and the fourth line data (D6, D7).

  Further, in the two gradation (1 BPP) mode shown in FIG. 7, the display data stored in the memory space shown in FIG. 4 corresponds to the bit arrangement of the display space shown in FIG. That is, 8-bit data D0-D7, which is an internal data bus unit, corresponds to 1 pixel 1 bit × 8 lines, and the first line data (D0), the second line data (D1), and the third line data (D2). This corresponds to the fourth line data (D3), the fifth line data (D4), the sixth line data (D5), the seventh line data (D6), and the eighth line data (D7).

(Relationship between the number N of lines on the display space corresponding to one page in the memory space and the number n of pixels in the border area)
In the present embodiment, the display data (first image data) for one frame supplied from the MPU 30 corresponds to N (N ≧ 2) lines in the Y direction on the display space of the display memory 20 shown in FIG. Each page is written on a plurality of pages in the memory space of the display data RAM 110. Here, in 2 gradations (1 BPP), N = 8 as shown in FIG. 7, in 4 gradations (2 BPP), N = 4 as shown in FIG. 6, and in 16 gradations (4 BPP), FIG. N = 2 as shown in FIG.

  Here, in the border region 20C shown in FIG. 1, the number of pixels corresponding to the width of the border region 20C at both ends in the Y direction is n. In FIG. 8, N> n is established. In fact, N = 8 for 2 gradations (1BPP) and N = 4 for 4 gradations (2BPP), so that N> n holds in this embodiment where n = 2 in FIG. On the other hand, N = n = 2 for 16 gradations (4 BPP).

  In the case of 16 gradations (4 BPP) where N = n = 2, it is relatively easy to display N = 2 lines on the display space shown in FIG. This is because “black” data having the same color as the border data is once written in a pixel area of 200 lines (for 100 pages) × 200 columns in the display data RAM 110 corresponding to the effective display area 20A (20B + 20C) in FIG. This is because desired image data may be overwritten on a pixel area of 196 lines (for 98 pages) × 196 columns corresponding to one central display area 20B. Further, even when the border areas 20C are set at both ends in the X direction in FIG. 8, since there is no page concept in the X direction and can be specified for each column address, "black" data having the same color as the border data is displayed in all areas. Once writing is performed, the column address corresponding to the center display area 20B in FIG. 1 may be designated to overwrite desired image data.

  However, when N = 8 in the two-gradation (1BPP) mode or N = 4 in the four-gradation (2BPP) mode, N> n = 2, and the method described above supports only the border area 20C. Cannot write "black" data in the memory area. This is because, for example, when N = 8 in the two gradation (1BPP) mode, data can be rewritten only every 8 lines (for each partition line in FIG. 7) on the display space corresponding to one page of the page address. It is. This is because, when N = 4 in the 4-gradation (2BPP) mode, data can be rewritten only for every four lines (each partition line in FIG. 6) on the display space corresponding to one page of the page address. Therefore, “black” data cannot be written only in two lines on the display space corresponding to less than one page of the page address.

  Therefore, in such a case, the MPU 30 must supply “black” data only for two specific lines in eight lines on the display space corresponding to one page of the page address, and the burden on the MPU 30 is large. turn into. Even in the 16 gray scale (4BPP) mode, N> n, and the same problem arises depending on the setting of N and n.

(Bit operation circuit provided in the input stage of the display data RAM)
FIG. 9 shows display data (first data) supplied from the MPU 30 over n (1 ≦ n <N) lines continuous in the Y direction of the display space of the display panel 20 even when N> n. Border data (second image data) other than (image data) can be output from the driver IC 100.

  In this embodiment, a predetermined bit operation pattern is written before writing a part of display data (first image data) supplied from the MPU 30 to a specified page (for example, the first and / or last page) in the display data RAM 110. And a part of the first image data are bit-calculated, and a bit arithmetic circuit 200 is provided that generates border data (second image data) over n lines.

  The principle that the edge data (second image data) can be generated by the bit arithmetic circuit 200 is as shown in FIGS. 10 (A) to 10 (C). In FIG. 10A, in order to simplify the description, a two gradation (1 BPP) mode (N = 8) is taken as an example, and black display is performed when 1-bit pixel data is “0”, and “1”. If so, white display is performed, and a border area 20C of n = 2 lines in the display space is set as black display data.

  In FIG. 10A, display data D0 to D7 are display data (first image data) supplied from the MPU 3, and each of eight lines on the display space of the display memory 20 in the two gradation (1 BPP) mode. It corresponds to pixel data. In the 8-bit operation pattern BP1 shown in FIG. 10A, the lower 2 bits on the LSB side are fixed to “0” and the upper 6 bits on the MSB side are fixed to “1”.

  The bit operation circuit 200 shown in FIG. 9 receives display data D0-D7 and an 8-bit operation pattern BP1 shown in FIG. 10A, and performs an AND operation on the same bit digits, for example. Then, the output of the bit operation circuit 200 is forcibly fixed to “0”, which is the same as the bit digit of the corresponding bit operation pattern BP1, and the upper 6 bits are the display data D2-D7, as shown in FIG. Is obtained as it is. The lower 2 bits of the bit operation result correspond to 2 pixels in the border area 20C shown in FIG. Therefore, even in the case of the two gradation (1 BPP) mode of 8 = N> n = 2, the n (1 ≦ n <N) lines that are continuous in the Y direction of the display space of the display panel 20 are Border data (second image data) other than the display data (first image data) supplied from the MPU 30 can be stored in the data display RAM 30.

  FIG. 10B shows a four gradation (2BPP) mode (N = 4). When the 2-bit pixel data is “00”, black display is performed, and when “11” is performed, white display is performed. In this example, the border area 20C of n = 2 lines is used as black display data. In this case, in the bit operation pattern BP2, the lower 4 bits corresponding to n = 2 lines in the display space may be “0” and the upper 4 bits may be “1”.

  FIG. 10C shows an example in which the number of lines in the border region 20C is n = 1 in the 16 gradation (4BPP) mode (N = 2) in the display space of the display panel 20 shown in FIG. ing. At this time, N> n is established. In this case, if the 4-bit pixel data is “0000”, the display is black, and if “1111”, the display is white. To make the border area 20C of n = 1 line on the display space black display data, the bit calculation pattern BP3 sets the lower 4 bits corresponding to the n = 1 line on the display space to “0” and the upper 4 bits. Should be set to “1”.

  Here, the bit operation circuit 200 is not limited to an AND gate that performs an AND operation for each corresponding bit, and may be a NAND gate. For example, in order to display the border area 20 </ b> C in white, an OR gate or a NOR gate that performs a logical ring operation that fixes the output to “1” of the bit operation pattern may be used. Alternatively, in order to fix the output of the bit arithmetic circuit 200 to a specific gradation value, one of an AND gate and an OR gate may be provided for each bit digit. Alternatively, exclusive OR operation may be performed by exclusive OR gate for bit operation.

  Next, a circuit configuration for causing the bit arithmetic circuit 200 shown in FIG. In FIG. 9, various registers 202 to 212 are provided in the control logic circuit 104 shown in FIG. 3 in addition to the bit arithmetic circuit 200 described above.

  First, in order to set the border areas 20C at both ends in the Y direction shown in FIG. 8, a first page bit calculation pattern register (first bit calculation pattern register) 202 and an end page bit calculation pattern register (second Bit operation pattern register) 204.

  Next, the four registers 206 to 212 for the MPU 30 to specify the write address for the rectangular area of the display data RAM 110 using the page address method will be described. The rectangular area shown in FIG. 8 is designated by a start column address C1, an end column address Cm, a start page address P1, and an end page address PM. 9, the first column register 206 stores the first column address C1, the end column register 208 stores the end column address Cm, the first page register 210 stores the first page address P1, and the end page register 212 stores the end page address PM. is doing. Each of these head / end addresses is designated by the MPU 30.

  As shown in FIG. 9, the column address circuit 118 shown in FIG. 3 includes a column address register 220, a final column match detection circuit 222, and a column address update circuit 224. The column address register 220 repeatedly updates the column address between the start column address C1 from the start column register 206 and the end column address Cm from the end column register 208 and outputs the updated column address to the RAM 110. After the first column address C1 is designated, the column address update circuit 224 increments by one unless the final column match detection circuit 222 matches, and the column address from the column address register 220 is updated. . When the final column match detection circuit 222 detects the final column address Cm, a carry-over signal is output, and the column address update circuit 224 loads the head address C1 and repeats this thereafter.

  As shown in FIG. 9, the page address circuit 116 shown in FIG. 3 includes a page address register 230, a final page match detection circuit 232, a page address update circuit 234, and a head page match detection circuit 236. The page address register 230 repeatedly updates the page address between the first page address P1 from the first page register 210 and the end page address PM from the end page register 212 and outputs the updated page address to the RAM 110. After the first page address P1 is designated, the page address update circuit 234 increments by one each time a carryover is input from the last column match detection circuit 222 unless the last page match detection circuit 232 matches. Then, the page address from the page address register 230 is updated. Then, when the final page address PM is detected by the final page coincidence detection circuit 232 and the carryover from the final column coincidence detection circuit 222 is input, the page address update circuit 234 loads the head address P1, and thereafter repeat.

  Here, the bit operation patterns BP1 to BP3 shown in FIGS. 10A to 10C are stored in the first page bit operation pattern register 202 or the end page bit operation pattern register 204 in association with the first page and the end page. Stored and supplied to the bit arithmetic circuit 200. When the same bit operation pattern is used for both the top and end pages, only one register 202, 204 is required.

  In addition, the bit operations shown in FIGS. 10A to 10C need only be performed for the first page and the end page in the example shown in FIG. 8, and the bits in the bit operation circuit 200 are used for other pages. No calculation is required, and the display data can be passed through as it is. Therefore, the bit calculation circuit 200 receives the match detection signals from the first page match detection circuit 236 and the end page match detection circuit 232, and performs bit calculation only on the first and last pages.

(Driver circuit and line address circuit)
FIG. 11 shows a source driver 130, a power supply circuit 140, and a line address circuit 120 which are driver circuits. Note that FIG. 11 shows only the configuration corresponding to the four source lines S1 to S4 for convenience of explanation.

  In FIG. 11, the source driver 130 includes a data selector 240, an analog-digital conversion circuit (DAC) 250, and a buffer 260 corresponding to each of four source lines S1-S4. The data selector 240 receives 4-bit data (matching the maximum number of gradation bits) output from the RAM 110 and latched by the display data latch circuit 122. The data selector 240 selects n1 bits of the data display RAM output n2 bits at a time, where n1 is the maximum gradation bit number and n2 is the current designated gradation bit number, and the upper n0 of the selected n2 bits. 0 is added to (n0 = n1-n2) bits to make n1 bits.

  In the present embodiment, the maximum number of gradations, 16 gradations, is 4 bits, so n1 = 4. Further, in this embodiment, since the number of gradation bits per pixel can be selected from three modes of 4, 2, and 1, n2 = 4 (4 BPP), n2 = 2 (2 BPP), or n2 = 1 (1 BPP). is there.

  Here, the 4-bit data input to one data selector 240 is D0-D3. In the 16 gradation (4 BPP) mode, the output of the data selector 240 is the same as the input and becomes D0-D3. In the 4 gradation (2BPP) mode, the output of the data selector 240 is D0, D1, 0, 0 (the upper 2 bits are 0) sequentially from the LSB, and the second output is D2, D3, sequentially from the LSB. 0, 0 (the upper 2 bits are 0). In the two gradation (1BPP) mode, the output of the data selector 240 is D0,0,0,0 (the upper 3 bits are 0) in order from the LSB, and the second output is D1,0,0 in order from the LSB. , 0 (the upper 3 bits are 0), the third output is D2, 0, 0, 0 (the upper 3 bits are 0) in order from the LSB, and the fourth output is D3, 0, 0, 0 (the upper 3 bits are in order from the LSB) 0).

  An example of such a data selector 240 is shown in FIG. 12, and the contents of the control signal shown in FIG. 12 are shown in FIG. In FIG. 12, a 2BPP mode signal and a 4BPP mode signal (BPP mode signal in a broad sense) are used to replace the upper bits in each mode with 0. In the 2BPP and 1BPP modes, the 4BPP mode signal is LOW as shown in FIG. 13, the outputs of the AND gates AND1 and AND2 in FIG. 12 are both LOW, and the upper 2 bits are both 0. Furthermore, since the 2BPP mode signal and the 4BPP mode signal are both LOW only in the 1BPP mode as shown in FIG. 13, the output of the OR gate OR1 in FIG. 12 becomes LOW, and the output of the AND3 eventually becomes LOW. Since the outputs of the AND gates AND1 and AND2 are LOW as described above, the upper 3 bits are both 0. On the other hand, in the 4BPP mode, the AND gates AND1 to AND3 do not become LOW by the 2BPP and 4BPP mode signals, so that the upper bits are not forcibly fixed LOW.

  Next, 4-bit output and output timing in each mode will be described. In the 4BPP mode, since the select signals SEL_1 and SEL_2 are both LOW, the data D0 is output through the AND gate AND9, the OR gate OR3, the AND gate AND5, or the OR gate OR2. Similarly, the data D1 is output through the AND gate AND7, the OR gate OR2, and the AND gate AND3 (the output of the OR gate OR1 is fixed to HIGH). Data D2 and D3 are output through AND gates AND2 and AND1, respectively. After all, in the 4BPP mode, the input data is directly passed through the data selector 240 and output.

  In the 2BPP mode, the upper 2 bits are fixed to 0 as described above. Here, if the select signals SEL_1 and SEL_2 are both LOW, the data D0 and D1 are passed through and output in the same manner as in the 4BPP mode. As a result, the 4-bit first of D0, D1, 0, 0 in order from the LSB. Output is obtained. Thereafter, as shown in FIG. 13, when only the select signal SEL_1 changes to HIGH, the data D2 is output through the AND gate AND8, the OR gate OR3, the AND gate AND5, or the OR gate OR2. Similarly, the data D3 is output through the AND gate AND6, the OR gate OR2, and the AND gate AND3 (the output of the OR gate OR1 is fixed to HIGH). Eventually, a 4-bit second output of D2, D3, 0, 0 is obtained in order from the LSB.

  In the 1BPP mode, the upper 3 bits are fixed to 0 as described above. When the select signals SEL_1 and SEL_2 are both LOW, the data D0 is output through the AND gate AND9, the OR gate OR3, the AND gate AND5, and the OR gate OR2. Eventually, a 4-bit first output of D0, 0, 0, 0 in order from the LSB is obtained. Next, as shown in FIG. 13, when only the select signal SEL_2 changes to HIGH, the data D1 passes through the AND gate AND7, the OR gate OR2, the AND gate AND4, and the OR gate OR2. Eventually, a 4-bit second output of D1, 0, 0, 0 in order from the LSB is obtained. Next, as shown in FIG. 13, when the select signal SEL_1 changes to HIGH and the select signal SEL_2 changes to LOW, the data D3 passes through the AND gate AND8, OR gate OR3, AND gate AND5, or OR gate OR2. Eventually, a 4-bit third output of D2, 0, 0, 0 in order from the LSB is obtained. Finally, as shown in FIG. 13, when both the select signals SEL_1 and SEL_2 are HIGH, the data D3 passes through the AND gate AND6, the OR gate OR2, the AND gate AND4, and the OR gate OR2. Eventually, a 4-bit fourth output of D3, 0, 0, 0 in order from the LSB is obtained.

Next, a line address for reading display data from the display data RAM in each mode of 4BPP, 2BPP, and 1BPP will be described. Since the display data RAM has 320 lines in the Y direction, the number of bits M of the line address is M = 9 bits because it is necessary to satisfy 2 ^M ≧ 320.

  Here, the maximum number of gradation bits of BPP is n1 (n1 is an integer equal to or larger than 2 and n1 = 4 in the present embodiment), and the designated gradation bit number is n2 (1 ≦ n2 ≦ n1). In the 4BPP mode, n2 = 4, in the 2BPP mode, n2 = 2, and in the 1BPP mode, n2 = 1.

  14A to 14C show the relationship between the frame address and line address of the display data RAM 110 in the three BPP modes. In the 4BPP mode, as shown in FIG. 14A, only one frame of display data can be stored in the display data RAM 110, so that no frame address is required. In the 2BPP mode, as shown in FIG. 14B, display data for two frames can be stored in the display data RAM 110. Therefore, it is necessary to assign 0 and 1 of 1 bit as a frame address. In the 1BPP mode, as shown in FIG. 14C, display data for four frames can be stored in the display data RAM 110, so it is necessary to assign 00, 01, 10, and 11 of 2 bits as frame addresses.

  Details of the line address circuit 120 shown in FIG. 11 will be described with reference to FIGS. FIG. 15 shows an example of the line address generation circuit 120 shown in FIGS. In FIG. 15, a BPP setting register 120A for setting the designated gradation bit number n2 and a 9-bit display line counter 120B for counting the line number 320 of the RAM 110 are provided. A display line address converter 120C to which outputs of the BPP setting register 120A and the display line counter 120B are input is provided.

  The display address converter 120C includes a frame address generation circuit 120C1 that generates a k-bit frame address based on the designated gradation bit number n2 from the BPP setting register 120A, and an M = 9-bit line address that is an output of the counter 120b. An adder 120 </ b> C <b> 2 that adds a k-bit frame address, which is an offset value, to the upper side of the upper (M−k) bits, and outputs the offset M-bit line read address to the RAM 110. The frame address generation circuit 120C1 generates a frame address corresponding to the designated gradation bit number n2, that is, 4BPP, 2BPP, or 1BPP.

Here, when an integer k = log ₂ (n1 / n2) is defined, k = log ₂ (4/4) = 0 in the 4BPP mode, k = log ₂ (4/2) = 1 in the 2BPP mode, and 1BPP mode Then, k = log ₂ (4/1) = 2. 14A to 14C have 2 ^k = 2 ⁰ = 1 frame in the 4BPP mode, 2 ^k = 2 ¹ = 2 frames in the 2BPP, and 2 ^k = 2 ² = 4 frames in the 1BPP. Means. Therefore, if the frame address generation circuit 120C1 generates a k-bit frame address in the 4BPP, 2BPP, or 1BPP mode, the frame address generation circuit 120C1 corresponds to 2 ^k frames in each mode shown in FIGS. It can be seen that the frame address can be generated.

  FIG. 16 shows a display data RAM 110. The RAM 110 includes a CPU / IF 110B and a line read I / F 110C in addition to the memory cell array 110A. The CPU / IF 110B is an interface between the control logic 104 and the memory cell array 110A shown in FIG. 3, and 8-bit data is input / output according to the write / read enable signal and the CPUIF clock. A line read address and a line read clock from the line address circuit 120 are input to the line read I / F 110C.

  17 to 19 are diagrams for explaining the operation in each mode of 4BPP, 2BPP, and 1BPP. As shown in each drawing, in each mode, the display line counter 120B counts 320 lines within one frame. However, since the M-bit line read address generated in one frame is offset based on the frame address, it differs in each mode. By specifying the line read address shown in FIGS. 17 to 19, it is possible to specify an intra-frame line address in each mode shown in FIGS. 14 (A) to 14 (C).

  Next, as shown in FIG. 13, the lower k bits of the line address of all M bits are selected in the 1BPP mode as the switching timing signal of k = 2 bits for switching the select signal SEL_1 between LOW and HIGH in the 2BPP mode. The signals SEL_1 and SEL_2 are used as a switching timing signal of k = 2 bits for switching between LOW and HIGH. Since k = 0 in the 4BPP mode, it is not necessary to switch the select signals SEL_1 and SEL_2.

  That is, the line address counter 120A shown in FIG. 11 counts all M-bit line addresses in the 4BPP mode, and the lower k bits are not used as the line address of the display data RAM 110 but are input to the data selector 240. It is sent as a switching timing signal for the select signals SEL_1 and SEL2 (see FIG. 13).

  For this purpose, as shown in FIG. 15, a data selector control signal generator 120D to which the lower K bits of the M bits from the display line counter 120B are input is provided, and the k-bit data selector control signal is supplied to the data selector 240. (See also FIGS. 17 to 19).

As the line address within one frame of the display data RAM 110, it is only necessary to have the upper (M−k) bits excluding the lower k bits out of all line addresses of M = 9 bits. Since k = 0 in the 4BPP mode, all M = 9 bits are used as line addresses. Since k = 1 bit in the 2BPP mode, the upper (Mk) = 9-1 = 8 bits are used as the line address within one frame. In the 2BPP mode, since the number of lines in one frame is 160, 160 <2 ⁸ = 256 is satisfied. In the 1BPP mode, k = 2 bits, and upper (Mk) = 9-2 = 7 bits are used as the line address within one frame. In the 1BPP mode, since the number of lines in one frame is 80, 80 <2 ⁷ = 128 is satisfied. In any case, as described above, of all line addresses of M = 9 bits, the upper (M−k) bits excluding the lower k bits are offset by the k-bit frame address which is an offset value, It is converted into an M-bit line read address.

  As described above, among the bit number M of all line addresses necessary for the 4BPP mode which is the maximum gradation bit, the lower k bits are used as the switching timing signal of the select signal input to the data selector 240, and the upper (M−k ) By using a bit as a line address within one frame and adding k bits as a frame address, reading from the display data RAM 110 can be efficiently performed without changing any M = 9 bit address in the 4BPP mode. . That is, the line address at the time of driving at the maximum gradation (4 BPP) can be shared regardless of the number of bits set in BPP.

(Driver circuit and power supply circuit)
The source driver (driver circuit) 130 and the power supply circuit 140 shown in FIG. 3 will be described with reference to FIG. The power supply circuit 140 includes a ladder resistor circuit 270 that is a voltage generation circuit. Ladder resistor circuit 270, the first potential VGH and the second potential VCL and resistance division to generate a large ^{S (S> 16 = 2 n1} ) of voltages than the maximum gray-scale level of 16. The 16 analog switches 280 select and output 16 types of voltages from among the S types based on the signal from the switch switching data register 290 in the 4BPP mode. The switch switching data register 290 stores gamma characteristic setting data and corrects the gamma characteristic which is the applied voltage-transmittance characteristic of the display panel 20 to generate 16 gradation voltages.

  Here, in this embodiment, corresponding to the three BPP modes, the control data from the switch switching data register 290 is switched based on the mode signal, and the voltage values output from the 16 analog switches 280 at the maximum are changed. is doing. FIG. 20 is a diagram showing the relationship between gradation data and gradation voltages corresponding to the three BPP modes. In the 4BPP mode, 16 types of gradation voltages ranging from a high potential V0 to a low potential V15 (normally white) are prepared by the analog switch 290 corresponding to 16 gradation data (0000 to 1111). In the 2BPP mode, four types of gradation voltages of potentials V0, V1, V2, and V3 are prepared by the analog switch 290 corresponding to the four gradation data (0000 to 0011). In the 1BPP mode, two kinds of gradation voltages of high potential V0 and low potential V1 are prepared by the analog switch 290 corresponding to the two gradation data (0000 to 0001).

Next, the DAC 250 will be described. FIG. 21 shows one DAC 250 in FIG. 11 that selects the above-described gradation voltage based on a 4-bit output. The data selector 240 shown in FIG. 11 outputs 4-bit data in any BPP mode. Therefore, 2 ⁴ = 16 1-bit coincidence detection circuits 300 to which the 4-bit data is input in common are provided. In any BPP mode, any one of the 16 match detection circuits 300 always matches.

  Sixteen gradation voltage supply lines 310 that supply 16 kinds of gradation voltages V0 to V15 from the analog switch 280 and 16 analog voltage output lines 312 that are short-circuited at one end are arranged orthogonally. . Each one of the 16 voltage supply lines 310 and one different one of the 16 analog voltage output lines 312 can be switched between connection and non-connection via the switches ST1 to ST16. Then, any one of the switches ST1 to ST16 is turned on by the signal output line 314 of any one of the 16 coincidence detection circuits 300 that have detected a coincidence.

  Here, as shown in FIG. 20, in the three BPP modes, 4-bit gradation data and gradation voltage numbers (V0, V1, V2, etc.) have a one-to-one relationship. Accordingly, the 16 coincidence detection circuits 300 output a signal for selecting the gradation voltage number V0 when 4-bit data (0000) is input, and the gradation voltage when 4-bit data (0001) is input. A signal for selecting the number V1 is output, and so on.

  However, in the three BPP modes, except that the voltage of gradation voltage number V0 corresponding to 4-bit data (0000) is the highest voltage, other gradation voltage numbers V1, V2,... Corresponding gradation voltage values Are inconsistent in the three modes. For example, the gradation voltage value corresponding to the gradation voltage number V1 in the 2BPP mode substantially matches the gradation voltage value corresponding to the gradation voltage number V5 in the 4BPP mode, and the gradation voltage number in the 1BPP mode mode The gradation voltage value corresponding to V1 substantially matches the gradation voltage value corresponding to the gradation voltage number V15 in the 4BPP mode. The other gradation voltage numbers V2-V3 in the 2BPP mode have the same relationship as the gradation voltage numbers V5, V10, V15 in the 4BPP mode. This phenomenon occurs because 0 is forcibly added to the upper bits in the 2BPP mode and the 1BPP mode.

Therefore, according to each BPP mode, the analog switch 280 is switched as described above based on the control data from the switch switching data register 290. That is, the plurality of analog switches 290 are input to the 1-bit coincidence detection circuit 300 for every designated gradation bit number n2 except for one of the maximum and minimum voltages (for example, V0) of the 2 ⁿ¹ gradation voltages. Different gradation voltages (gradation voltage values corresponding to gradation voltage numbers V1, V5, and V15 in the 4BPP mode) are selected for the same n1 bit data (for example, 0001). Thereby, in any BPP mode, an analog voltage corresponding to the gradation value can be output.

  In the display panel 20 having an electro-optical element such as a liquid crystal, the life of the element is shortened when a voltage having the same polarity is continuously applied to the electro-optical element such as a liquid crystal. Therefore, the display panel 20 has a predetermined cycle (dot, line or frame). Polarity inversion drive. In the present embodiment, polarity inversion driving can be performed by one of the following methods.

  The first is a method of adding a polarity inverting circuit such as an exclusive OR circuit (EXOR circuit) between the data selector 120 and the DAC 250 in FIG. 11 and digitally normalizing or inverting the display data by the polarity signal. is there. In the 2BPP and 1BPP modes, however, the polarity of the 0 added to the upper side is not inverted. The second is a method of inverting the polarity of the analog output voltage by the analog switch (gamma circuit) 280 shown in FIG. As described above, when the gradation voltage number V0 is the highest voltage, the positive polarity mode is set, and in the negative polarity mode, switching is performed so that the gradation voltage number V0 becomes the lowest voltage.

(Bit operation circuit provided at the output stage of the display data RAM)
22A and 22B are diagrams showing a source driver (driver circuit) 130 including bit conversion circuits 320 and 330 according to another embodiment provided in the output stage of the display data RAM 110. In the embodiment shown in FIG. 9, the bit arithmetic circuit 200 is provided in the input stage of the display data RAM 110, but it may be provided in the output stage of the display data RAM 110. This is because, regardless of whether it is an input stage or an output stage of the display data RAM 110, the bit operation pattern and the display data subjected to the bit operation are not changed to digital data.

  Therefore, as shown in FIGS. 22A and 22B, the bit arithmetic circuits 320 and 330 can be provided in the source driver (driver circuit) 130. In FIG. 22A, a bit operation circuit 320 is provided at the input stage of the data selector 240, whereas in FIG. 22B, a bit operation circuit 330 is provided at the output stage of the data selector 240.

  Although the bit arithmetic circuit 320 shown in FIG. 22A receives 4-bit gradation data regardless of the type of the BPP mode, the meaning varies depending on the BPP mode. In the 4BPP mode, 4 bit data corresponds to 1 pixel (1 line), in the 2BPP mode, 4 bit data corresponds to 2 pixels (2 lines), and in the 1BPP mode, 4 bit data corresponds to 4 pixels (4 lines). . Therefore, according to the number of lines n in the border area 20C in FIG. 8, which bit digit of the 4-bit data is bit-converted and converted into border data (second image data) for each BPP mode.

  In the case of n = 2 lines, in the 4BPP mode and the 2BPP mode, as shown in FIG. 23A, a bit operation pattern BP4 in which all 4 bits are 0 is prepared, and the bit operation circuit 320 applies the display data of the corresponding line. It is only necessary to calculate the logical product. In the 1BPP mode, as shown in FIG. 23B, a bit operation pattern BP5 in which the lower 2 bits on the LSB side are 0 is prepared, and the bit operation circuit 320 calculates a logical product only for the display data of the corresponding line. It ’s fine.

  In order to perform an AND operation only on the corresponding line, the line address circuit 120 of FIG. 3 can include a line address register 120C storing the corresponding line in addition to the line address counter 120A. Thus, the line address counter 120A counts the line address value set in the line address register 120C, and the logical product of the display data corresponding to the line address and the bit operation pattern is performed.

  As shown in FIG. 22B, when the bit arithmetic circuit 330 is provided at the output stage of the data selector 240 and the number of lines n = 2 in the border area 20C in FIG. The calculation pattern is as follows.

  In the 4BPP mode, the input and output of the data selector 240 match, so the bit operation pattern BP5 shown in FIG. In the 2BPP mode, the upper 2 bits of the output of the data selector 240 are fixed to 0. Therefore, as shown in FIG. 24A, a bit operation pattern BP6 in which the lower 2 bits are 0 and the upper 2 bits are either 0 or 1 can be used. In the 1BPP mode, the upper 3 bits of the output of the data selector 240 are fixed to 0. Therefore, as shown in FIG. 24B, a bit operation pattern BP7 in which only the lower 1 bit is 0 and the upper 3 bits are either 0 or 1 can be used.

  In the case of FIG. 22B as well, since it is necessary to perform bit operation only on the data of the corresponding line, the line address counter 120B and the line address register 120E are used as in FIG.

(Conversion to border data in DAC)
FIG. 20 shows the gradation voltage selected by the analog switch 280 in accordance with the BPP mode. On the other hand, in order to display the border area 20C in FIG. 8 in black, for example, the gradation voltage output from the source driver 130 may be the gradation voltage V0 corresponding to black display. In the embodiment described above (the bit operation circuit according to FIGS. 9 and 22A and 22B), the gradation voltage V0 is realized by bit operation of a digital value. However, the correction is not limited to the digital value, and the result is the same even if the correction is performed with the analog value.

  Therefore, in still another embodiment of the present invention, without using the bit arithmetic circuit according to FIGS. 9 and 22A and 22B, the gradation voltage dedicated to the bordering region 20C shown in FIG. The gradation voltage shown is prepared. As the gradation voltage shown in FIG. 25, the gradation display voltage V0 (second image data) is prepared with the same gradation voltage for any gradation data in the BPP mode. Such a gradation voltage can be selected by setting the switch switching data register 290 shown in FIG. 11 based on the BPP mode and the line address.

  In this embodiment, it is not necessary to change the hardware, and it is sufficient to change the control data of the switch switching data register 290 by software based on the BPP mode and the line address.

  Although the present embodiment has been described in detail as described above, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described together with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term anywhere in the specification or the drawings.

  The present invention is not necessarily limited to the Si-TFT liquid crystal, but can be widely applied to panel driver ICs using electro-optical elements including other various liquid crystals. Applicable to molds.

It is a figure which shows the display panel driven with the driver IC which concerns on one Embodiment of this invention. It is a figure which shows one pixel of a display panel. 1 is a block diagram of a driver IC according to an embodiment of the present invention. It is a figure which shows the memory space of display data RAM. It is the figure which represented display data RAM at the time of 16 gradation (4 BPP) mode with display space. It is the figure which represented display data RAM at the time of 4 gradation (2 BPP) mode with display space. It is the figure which represented the display data RAM at the time of 2 gradation (1BPP) mode in display space. It is a figure which shows the relationship between the line number N on the display space corresponding to 1 page in memory space, and the pixel number n of a border area. It is a block diagram of a logic control circuit including a bit conversion circuit according to an embodiment provided in an input stage of a display data RAM. FIG. 10A to FIG. 10C are diagrams showing the principle that the edge data (second image data) can be generated by the bit operation circuit shown in FIG. FIG. 4 is a diagram illustrating an example of a source driver, a power supply circuit, and a line address circuit shown in FIG. 3. It is a figure which shows an example of the data selector shown in FIG. It is a figure which shows the content of the control signal of the data selector shown in FIG. FIGS. 14A to 14C are diagrams showing the relationship between the frame address and the line address of the display data RAM in the three BPP modes. It is a figure which shows an example of a line address circuit. It is a figure which shows an example of display data RAM. It is a figure for demonstrating the operation | movement at the time of 4BPP mode. It is a figure for demonstrating the operation | movement at the time of 2BPP mode. It is a figure for demonstrating the operation | movement at the time of 1BPP mode. It is a figure which shows the relationship between the gradation data and gradation voltage corresponding to three BPP modes. It is a figure which shows one DAC in FIG. 11 which selects a gradation voltage based on 4-bit output. FIGS. 22A and 22B are diagrams showing a bit operation circuit according to another embodiment provided in the output stage of the display data RAM. 23A and 23B are diagrams showing bit operation patterns applied to the bit operation circuit shown in FIG. 24A and 24B are diagrams showing bit operation patterns applied to the bit operation circuit shown in FIG. It is a figure which shows the example of 2nd image data (gradation voltage) at the time of converting 1st image data input into a digital-analog converting circuit into 2nd image data with a gradation voltage for every BPP mode.

Explanation of symbols

  10 display unit, 20 display panel, 20A effective display area, 20B center display area, 20C border area, 30 MPU, 40 outer frame, 42 opening, 100 driver IC, 102 system interface, 104 control logic, 106 multi-time PROM, 108 Oscillator circuit, 110 display data RAM, 112 I / O buffer, 114 display timing generation circuit, 116 page address circuit, 118 column address circuit, 120 line address circuit, 120A BPP setting register, 120B display line counter, 120C display line address converter 120C1 frame address generation circuit, 120C2 adder, 120D data selector control signal generator, 122 display data latch circuit, 130 source driver Bar (driver circuit), 140 power supply circuit (including gamma correction circuit), 142A, 142B gate driver, 200-bit arithmetic circuit, 202 first page bit arithmetic pattern register, 204 end page bit arithmetic pattern register, 206 first column register, 208 end Column register, 210 First page register, 212 End page register, 220 Column address register, 222 Last column match detection circuit, 224 Column address update circuit, 230 page address register, 232 Last page match detection circuit, 234 Page address update circuit, 236 First page coincidence detection circuit, 240 data selector, 250 digital-analog conversion circuit (DAC), 260 output buffer, 270 ladder resistance circuit, 280 analog Switch, 290 switch switching data register, 300 coincidence detection circuit, 310 gradation voltage supply line, 312 analog voltage output line, 314 coincidence detection signal line, 320, 330 bit arithmetic circuit, BP1 to BP7 bit arithmetic pattern, G gate line, S source line, T thin film transistor, C storage capacitor, P pixel electrode

Claims (10)

In a driver IC that drives by supplying a data signal corresponding to the number of gradation bits per pixel (Bit Per Pixel) to a plurality of data signal lines of the display panel,
A RAM having a capacity for storing display data of the maximum number of gradation bits for at least one frame;
A line address circuit for designating a line read address of the RAM;
A drive circuit for driving the plurality of data signal lines based on an output from the RAM;
Have
In the RAM, when the maximum gradation bit number is n1 (n1 is an integer of 2 or more) and the designated gradation bit number is n2 (1 ≦ n2 ≦ n1), k = log ₂ (n1 / n2) is set. The display data of the designated gradation bit number n2 is stored divided into 2 ^k (k is 0 or a natural number) frames to satisfy,
The line address circuit generates a line address of M (M is an integer of 2 or more) bits corresponding to the maximum gradation bit number n1, and is offset according to a k-bit frame address which is an offset value. A driver IC characterized by outputting a line read address. In claim 1,
The line address circuit
A counter for generating the M-bit line address;
A frame address generating circuit for generating a k-bit frame address based on the designated gradation bit number n2;
The k-bit frame address that is an offset value is added to the upper side of the upper (M−k) bits of the M-bit line address that is the output of the counter, and the offset M-bit line read address is added to the RAM. An adder that outputs to
A driver IC comprising: In claim 2,
The drive circuit is
The plurality of digital-analog conversion circuits;
A power supply circuit for supplying an analog gradation voltage to the plurality of digital-analog conversion circuits;
A plurality of data selectors provided between the plurality of digital-analog conversion circuits and the RAM;
Each of the plurality of digital-analog conversion circuits includes 2 ⁿ¹ 1-bit coincidence detection circuits,
The data selector selects n1 bits, which are the RAM outputs, n2 bits at a time based on a select signal, and selects a higher order of n2 bits selected based on a mode signal for selecting the designated gradation bit number n2. The present invention is characterized in that 0 is added to n0 (n0 = n1-n2) bits, and the data length per pixel input to the 1-bit coincidence detection circuit is n1 bits regardless of the number of designated gradation bits. Driver IC to do. In claim 3,
The driver IC, wherein the data selector receives a lower k-bit address of the M-bit line address as the select signal switching timing signal. In claim 4,
The power supply circuit selects 2 ⁿ¹ gamma-corrected gradation voltages from S (S> 2 ⁿ¹ ) analog voltages based on the setting data when the maximum gradation bit number n1 is set. Including multiple analog switches,
The setting data includes BPP switching data, and the plurality of analog switches select 2 ⁿ² gradation voltages based on the designated gradation bit number n2. In claim 5,
The plurality of analog switches have the same n1 bit data input to the 1-bit coincidence detection circuit for each of the designated gradation bits except for one of the maximum and minimum voltages of the 2 ⁿ¹ gradation voltages. A driver IC, wherein different gradation voltages are selected for the driver IC. In a driver IC that drives by supplying a data signal corresponding to the number of gradation bits per pixel (Bit Per Pixel) to a plurality of data signal lines of the display panel,
A RAM having a capacity for storing display data of the maximum number of gradation bits for at least one frame;
A drive circuit for driving the plurality of data signal lines based on an output from the RAM;
Have
In the RAM, when the maximum gradation bit number is n1 (n1 is an integer of 2 or more) and the designated gradation bit number is n2 (1 ≦ n2 ≦ n1), display data of the designated gradation bit number n2 is displayed. Store and
The drive circuit is
The plurality of digital-analog conversion circuits;
A power supply circuit for supplying an analog gradation voltage to the plurality of digital-analog conversion circuits;
A plurality of data selectors provided between the plurality of digital-analog conversion circuits and the RAM;
Wherein the plurality of digital - each of the analog conversion circuit includes a 2 ⁿ¹ pieces of 1-bit coincidence detector circuit,
The data selector selects n1 bits, which are the RAM outputs, n2 bits at a time based on a select signal, and selects a higher order of n2 bits selected based on a mode signal for selecting the designated gradation bit number n2. A driver IC characterized in that 0 is added to n0 (n0 = n1-n2) bits so that the data length per pixel input to the 1-bit match detection circuit is n1 bits. In claim 7,
A counter for generating a line address of M (M is an integer of 2 or more) bits corresponding to the maximum number of gradation bits n1;
Each of the plurality of data selectors is inputted with a lower k-bit address satisfying k = log ₂ (n1 / n2) among the M-bit line address as the select signal switching timing signal. Driver IC. In claim 7 or 8,
A polarity inversion circuit that digitally inverts the output of the data selector at a predetermined period between each of the plurality of digital-analog conversion circuits and each of the data selectors;
2. The driver IC according to claim 1, wherein the polarity inversion circuit does not invert the upper n0 data out of the output of the data selector. A display panel including an electro-optic element driven by a plurality of scanning lines and a plurality of data signal lines;
A driver IC according to any one of claims 1 to 9;
An electro-optical device comprising:

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