JP2010062679A - Image processing controller, and image processor - Google Patents

Abstract

When performing a plurality of image processing on image data, the amount of communication with a storage unit for storing the image data is reduced.
An image processing controller for processing input image data using each circuit mounted therein, a storage unit for storing the image data, and a predetermined processing for the image data A plurality of image processing circuits for performing the above processing, and communication means for branching a communication path and transmitting the stored same image data to the plurality of image processing circuits. Performs parallel processing on the same transmitted image data.
[Selection] Figure 2

Description

  The present invention relates to an image processing controller that performs specific processing on image data, and in particular, an image processing controller that reduces the amount of communication with a storage unit that stores image data, and an image using the image processing controller. The present invention relates to a processing apparatus.

Conventionally, an image processing apparatus that performs a plurality of processes on image data is known (see, for example, Patent Document 1).
In this apparatus, a plurality of image processing circuits for executing the respective processes are arranged therein so that a plurality of processes can be sequentially executed on the image data.

FIG. 8 is a block diagram showing a main part of a conventional image processing controller. When a plurality of processes are executed using hardware, the image data is stored in the storage unit and then read out from the storage unit in accordance with the processing order of each image processing circuit. Specifically, the image data stored in the storage unit is read for receiving the processing of the image processing circuit A, and after receiving the processing of the image processing circuit A, it is stored in the storage unit again. When the image processing circuit B is arranged at the subsequent stage of the image processing circuit A, the image data is read out from the storage unit to the image processing circuit B again.
JP 2000-354168 A

  In the conventional apparatus, image data is transferred between the storage unit and the image processing controller for each processing of each image processing circuit. Therefore, if the number of internal image processing circuits increases, the storage unit and the image processing controller are The amount of communication will increase. Therefore, it is necessary to increase the communication speed between the storage unit and the image processing controller in order to complete all the processing on the image data within the set time. As a result, it is necessary to increase the frequency and bus width in communication, resulting in an increase in circuit scale and cost.

  The present invention has been made in view of the above problems, and an image processing controller capable of reducing the amount of communication with a storage unit that stores image data when performing a plurality of processes on the image data. An image processing apparatus using the image processing controller is provided.

  In order to solve the above-described problem, in the present invention, an image processing controller that performs processing on input image data using each circuit mounted therein, a storage unit that stores the image data; A plurality of image processing circuits that perform predetermined processing on the image data, and the storage unit and the plurality of image processing circuits are connected, and a plurality of communication paths on the plurality of image processing circuits are branched. Communication means for transmitting the stored same image data to the image processing circuit, wherein the plurality of image processing circuits perform parallel processing on the transmitted same image data. is there.

In the invention configured as described above, the plurality of image processing circuits execute each process using the image data stored in the storage unit. At this time, the communication unit branches the communication path and transmits the same image data read from the storage unit to the plurality of image processing circuits. The plurality of image processing circuits perform parallel processing on the same transmitted image data.
Therefore, the communication means does not perform image data for each number of image processing circuits to the storage unit, but transmits the same image data read in one process to each image processing circuit. The amount of communication with the communication means can be reduced. As a result, the communication speed can be increased without increasing the frequency in communication and the bus width with the recording unit, and the increase in circuit scale and cost can be suppressed.
Here, performing parallel processing on image data means, for example, that the subsequent image processing circuit does not have a relationship to perform processing using the processing result of the previous image processing circuit.

Preferably, the communication unit is connected to the plurality of image processing circuits by branching wiring connected to one output terminal for outputting the image data.
In the invention configured as described above, since the output terminal of the communication unit and the image processing circuit are wired so as to branch on the image processing circuit side, the communication unit outputs the same image data to a plurality of image processing circuits. Therefore, it is not necessary to individually specify a transmission destination address for transmission to the image processing apparatus, and the same data can be transmitted to each image processing circuit with a simple configuration.

Preferably, the plurality of image processing circuits perform proximity processing on the target pixel using a plurality of line data indicating a plurality of pixel groups arranged in the main scanning direction in the image for each processing.
When neighborhood processing is performed using a plurality of line data, the plurality of line data is read in one process, and the relationship between the pixel of interest and the neighboring pixels of the pixel of interest is calculated. For this reason, it is necessary to read a plurality of line data in one process, and the amount of communication with the storage unit increases. Therefore, in the invention configured as described above, the amount of communication can be reduced even for the image processing circuit that performs the proximity processing.
The main scanning direction means a direction in which the original image is read by the data reading unit.

Here, as an example of an image processing circuit that performs parallel processing, preferably, the plurality of image processing circuits include an image processing circuit that performs image recognition processing for recognizing features in an image, It is an image processing circuit that performs correction processing for correcting features.
In the invention configured as described above, the image processing circuit can perform parallel processing in particular by combining image recognition processing and correction processing among the neighborhood processing.

As an example of parallel processing performed by a plurality of image processing circuits, the plurality of image processing circuits are preferably an image processing circuit that performs pixel number conversion processing on image data, and an image processing circuit that performs image processing on image data. It is an image processing circuit that performs correction processing for correcting features.
In the invention configured as described above, the image processing circuit can perform parallel processing by combining pixel number conversion processing and correction processing, among other neighborhood processing.

Preferably, the communication unit includes a line buffer memory on a communication path from the communication unit to the plurality of image processing circuits, and delays the plurality of line data by the line buffer memory to the plurality of image processing circuits. Send.
In the invention configured as described above, the line data transmitted from the communication means is output to the image processing circuit after the output timing is delayed by the line buffer memory, so the number of communication paths of the communication means is reduced. can do.

  The present invention can also be applied to an image processing apparatus including an image processing controller.

Embodiments of the present invention will be described below in the following order with reference to the drawings.
1. First embodiment:
2. Second embodiment:
3. Other embodiments:

1. First embodiment:
FIG. 1 is a block diagram illustrating a main part of the image processing apparatus according to the first embodiment. In FIG. 1, the present invention will be described by showing a multifunction peripheral as an image processing apparatus.
The main parts of the MFP 100 are a scanner engine (data reading unit) 90 that converts a document image (original image) into image data, a printer engine 91 that performs print processing on a print medium using the image data, and a user's request. An operation panel 92 that receives operation inputs, a display unit 93, and a main controller (image processing controller) 80 are configured. Further, I / Os 94 and 95 are interposed between the main controller 80, the operation panel 92, and the display unit 93, and can communicate with each other. The scanner engine will be described using a flatbed scanner as an example, but the configuration of the scanner engine is not limited to this.

  Hereinafter, the processing of the multifunction peripheral 100 will be described. When the user sets an original image on the image reading surface of the scanner engine 90 and starts reading the image, the scanner engine 90 takes in the original image as analog data using a line sensor such as a CCD (Charge Coupled Device). . The scanner engine 90 converts analog data into digital data (hereinafter referred to as image data) by an A / D converter, and outputs the image data to the main controller 80. At this time, the image data is constituted by line data indicating a plurality of pixel groups arranged in the main scanning direction in the original image, and data corresponding to the original image is constituted by arranging the line data in the sub scanning direction. The

  The main parts of the main controller 80 are a CPU 70, a ROM 60, a RAM (storage unit) 50 for storing input image data, and an ASIC (Application Specific Integrated Circuit) 40 for performing predetermined image processing on the image data. It consists of This image data is stored in the RAM 50 and then subjected to predetermined image processing by the ASIC 40. Then, the main controller 80 outputs the image data subjected to each process to the printer engine 91.

  The printer engine 91 performs print processing on the print medium using the input image data. When the user inputs a command to display a thumbnail image or the like on the display unit 93 using the operation panel 92, the CPU 70 causes the ASIC 40 to convert the number of pixels so as to decrease the number of pixels of the image data stored in the RAM 50, The display unit 93 outputs image data. The display unit 93 displays a thumbnail image on the screen using the image data with the reduced number of pixels. In the present embodiment, a laser printer is described as an example of the printer engine 91, but the configuration of the printer engine 91 may be an ink jet printer or an LED (light emitting diode) printer.

  Further, in the main controller 80 according to the present invention, different image processes are performed in parallel based on the same image data stored in the RAM 50 in order to reduce the communication amount between the RAM 50 and the ASIC 40. Among the image processing executed by the ASIC 40, there is an image processing that can execute individual processing on image data without being affected by the processing results of each other. Therefore, the main controller 80 reduces the amount of communication between the RAM 50 and the ASIC 40 by performing such image processing in parallel using image data read from the RAM 50 by one access. Hereinafter, functions of the respective units of the main controller 80 will be described in more detail.

FIG. 2 is a block diagram showing the configuration of the ASIC.
The main part of the ASIC 40 controls the access between the first to fifth image processing circuits 42 to 46 for performing specific processing on the image data, and the RAM 50 and the first to fifth image processing circuits 42 to 46. A RAM I / F (communication means) 41 and an output I / F 47 are included. The RAM I / F 41 and the RAM 40 are connected via the bus 30, and the RAM I / F 41 can transmit the image data stored in the RAM 50 to the first to fifth image processing circuits 42 to 46.

  Here, functions of the first to fifth image processing circuits 42 to 46 will be described. The first to fifth image processing circuits 42 to 46 are configured by hardware such as FPGA (Field Programmable Gate Array), and after performing predetermined processing on the image data transmitted through the RAM I / F 41, The image data is again stored in the RAM 50 through the RAM I / F 41. The first to fifth image processing circuits 42 to 46 differ in the method of reading the line data N depending on the processing to be executed. Specifically, the first, fourth, and fifth image processing circuits 42, 45, and 46 read one line data N for each processing. On the other hand, the second and third image processing circuits 43 and 44 read a plurality of line data N for each processing.

  The first image processing circuit 42 sequentially reads line data N from the RAM 50 and performs shading correction, gamma correction, and interline correction on the line data N. The shading correction is to correct variations in image data caused by the sensitivity of the line sensor of the scanner engine 90. The gamma correction is for correcting variations in image data caused by nonlinearity of the output value of the line sensor and color balance. The line-to-line correction is for correcting variations in image data caused by reading positions in the scanning direction of the R, G, and B line sensors. Since shading correction, gamma correction, and interline correction are conventional techniques, descriptions thereof are omitted.

  The fourth image processing circuit 45 sequentially reads the line data N from the RAM 50, and performs moire removal processing and image area separation processing on the line data. The moire removal process is a kind of smoothing process, and is a process of removing noise in an image or weakening the contour (edge) of a region. In the image area separation process, an image is separated into areas composed of characters or photographs, and appropriate image processing is performed on each area. In this image area separation process, the position of each area is specified based on a processing value (described later) output by the process of the second image processing circuit 43. Note that moire removal processing and image area separation processing are conventional techniques, and thus description thereof is omitted.

  The fifth image processing circuit 46 performs binarization processing on the image data. In the binarization process, the value of image data is converted into a binary value of 1 or 0 in order to reduce the amount of information of the image data. As the binarization processing, there are dither processing and simple binarization processing. Since the binarization process is a conventional technique, the description thereof is omitted.

  The second image processing circuit (a plurality of image processing circuits) 43 specifies the relationship with the neighboring pixels in the target pixel data from the read plurality of line data N by histogram extraction or edge pixel extraction, and each region indicated by the image is displayed. Identify areas such as background area, text area, print area, and photo. Here, the neighborhood processing is to determine a calculation value for the pixel-of-interest data based on the relationship between the gradation value or the luminance value with the pixel in the pixel-of-interest data. The neighborhood process will be described in detail below.

  FIG. 3 is an image diagram for explaining the proximity processing executed by the second image processing circuit 43. Here, 3 × 3 neighborhood processing will be described as an example of neighborhood processing. The second image processing circuit 43 uses the buffer memory to store the line data n including the target pixel data P5 and the preceding and following line data n−1 and n + 1 in order to determine the calculation value for the target pixel data P5 in the drawing. 43a. Then, the second image processing circuit 43 determines the calculation value of the target pixel data P5 based on the values of the pixel data P1 to P4 and P6 to P9 in the vicinity of the target pixel data P5.

  Further, the third image processing circuit (a plurality of image processing circuits) 44 calculates a relationship with the neighboring pixel in the target pixel data from the plurality of read line data N using the neighboring process, and corrects the target pixel. Filter processing and color conversion processing for removing noise as processing are performed. Here, the proximity processing executed by the second image processing circuit 43 and the third image processing circuit 44 can be performed independently without the influence of one processing result on the other processing.

  The RAM I / F 41 exchanges data including image data between the RAM 50 and the first to fifth image processing circuits 42 to 46. The RAM I / F 41 reads the image data stored in the RAM 50 for each line data N, and outputs the line data N to each image processing circuit in the order of the first to fifth image processing circuits. The first to fifth image processing circuits 42 to 46 have different connection configurations with the RAM I / F 41 depending on the line data N capturing method. In this embodiment, the RAM I / F 41 is described as directly accessing data to the RAM 50, but the function of the RAM I / F 41 is not limited to this. Specifically, the RAM I / F 41 may have only a function as a data communication path between each image processing circuit and the RAM 50.

  The first, fourth, and fifth image processing circuits 42, 45, and 46 sequentially fetch one line data N from the RAM 50 and perform processing. Therefore, input / output between the output terminal 41 a and the input terminal 41 b of the RAM I / F 41 is performed. Each output is connected by one communication path 48a to 48e.

The second and third image processing circuits 43 and 44 read the three line data n-1 to n + 1 from the RAM 50 for each processing and perform the processing. Therefore, the three communication circuits for input and the output terminal 41c of the RAM I / F 41 are used. Connected by paths 48f to 48h, and connected to the input terminal 41d by one communication path 48i, 48j for output.
Further, communication paths 48f to 48h connecting the RAM I / F 41 and the second and third image processing circuits 43 and 44 are branched on the image processing circuit side. Therefore, the same line data n-1 to n + 1 is transmitted from the RAM I / F 41 to the second image processing circuit 43 and the third image processing circuit 44 through the communication paths 48f to 48h. Since the parallel circuit is configured by branching the communication paths 48f to 48h on the image processing circuit side, the RAM I / F 41 individually transmits the destination address to transmit the same image data to the image processing circuits 43 and 44. The same data can be transmitted to each image processing circuit with a simple configuration.

  FIG. 4 is a flowchart for explaining processing executed by the ASIC 40 as an example. FIG. 5 is a sequence chart for explaining a communication state among the first to fifth image processing circuits 42 to 46, the RAM I / F 41, and the RAM 50 in time series. In the flowchart shown in FIG. 4, access to the RAM 50 by the RAM I / F 41 is displayed by one flow for reading and writing data.

  When image data composed of line data N is input to the ASIC 40, the first image processing circuit 42 performs shading correction, gamma correction, and interline correction for each line data N, and then outputs the image data. The data is output to the RAM I / F 41 (step S110).

  The RAM I / F 41 sequentially receives line data N, and image data constituted by the line data N is referred to as first intermediate image data (hereinafter, each line data constituting the first intermediate image data is described as line data N1. .) Is stored in the RAM 50. Further, the RAM I / F 41 reads line data N <b> 1-1 to N <b> 1 +1 constituting the image data from the RAM 50 and transmits it to the second image processing circuit 43. At this time, the line data N1-1 to N1 + 1 are also transmitted to the third image processing circuit 44 through the communication paths 48f to 48h of the RAM I / F 41 (step S120).

  For this reason, the RAM I / F 41 merges the access to the RAM 50 for transmitting the line data N to the third image processing circuit 44 with the access for transmitting the line data N to the second image processing circuit 43. (FIG. 5). Further, since the second image processing circuit 43 and the third image processing circuit 44 perform neighborhood processing using the three line data n1-1 to n1 + 1, the second and third image processing circuits are changed from the RAM I / F 41. A total of six line data N1 is transmitted to 43 and 44. However, since the number of line data transmitted from the RAM 50 to the RAM I / F 41 is half, three, the amount of communication between the RAM I / F 41 and the RAM 50 can be greatly reduced.

  The second image processing circuit 43 performs neighborhood processing on the target pixel data using the line data n1-1 to n1 + 1, and executes image recognition processing based on the result of the neighborhood processing. Further, the second image processing circuit 43 outputs the recognition result output by the image recognition processing to the RAM I / F 41 (step S130). The second image processing circuit 43 performs proximity processing on all pixel data constituting the image data.

  The third image processing circuit 44 performs neighborhood processing on the target pixel data using the line data n1-1 to n1 + 1, and executes filter processing, color conversion processing, and the like based on the result of the neighborhood processing. Further, the third image processing circuit 44 outputs the processed line data N to the RAM I / F 41 (step S140). The third image processing circuit 44 executes proximity processing on all the pixel data constituting the image data.

  The RAM I / F 41 uses the image data received from the third image processing circuit 44 as second intermediate image data (hereinafter, each line data constituting the second intermediate image data is described as line data N2). Are stored in a predetermined storage area of the RAM 50 together with the recognition result received from the image processing circuit 43. Further, the RAM I / F 41 reads the second intermediate image data and the recognition result from the RAM 50, and transmits them to the fourth image processing circuit 45 (step S150).

  The fourth image processing circuit 45 performs moire removal and image area separation processing on the second intermediate image data based on the received recognition result (step S160). At this time, the RAM I / F 41 reads the line data N2 constituting the second intermediate image data for each line and transmits it to the fourth image processing circuit 45. Then, the fourth image processing circuit 45 processes the line data N2 for each line, and then outputs the processed line data N2 to the RAM I / F 41.

  The RAM I / F 41 describes image data constituted by the line data N2 received from the fourth image processing circuit 45 as third intermediate image data (hereinafter, each line data constituting the third intermediate image data is described as line data N3). Stored in the RAM 50. Further, the RAM I / F 41 reads out the third intermediate image data and transmits it to the fifth image processing circuit 46 (step S170).

  The fifth image processing circuit 46 performs binarization processing on the received third intermediate image data (step S180). At this time, the RAM I / F 41 reads the line data N3 constituting the third image data for each line and transmits it to the fifth image processing circuit 46. Then, the fifth image processing circuit 46 processes the line data N3 for each line, and then outputs the processed line data NN3 to the RAM I / F 41.

  The RAM I / F 41 records the processed image data in the RAM 50 as final image data. The RAM I / F 41 outputs the final image data to the output I / F (step S190). The output IF 47 outputs the final image data to the printer engine 91. Thereafter, the printer engine 91 executes print processing on the print medium using the final image data.

  As described above, the same line data N is transmitted from the RAM I / F to the second and third image processing circuits 43 and 44 that execute image processing using a plurality of line data N. The amount of communication between the ASICs 40 can be reduced. Therefore, the communication speed between the RAM 50 and the ASIC 40 can be increased without increasing the frequency in communication and the bus width between the RAM 50 and the ASIC 40, and the increase in circuit scale and cost increase can be suppressed. .

Second embodiment:
FIG. 6 is a block diagram showing an ASIC 40 according to the second embodiment. In the second embodiment, line buffer memories 49 and 49 are provided between the RAM I / F 41 and the second and third image processing circuits 43 and 44. The line buffer memories 49, 49 are interposed between the communication path 48 connecting the RAM I / F 41 and the second and third image processing circuits 43, 44, and store line data N transmitted through the communication path 48. By temporarily storing, the input of the same line data N to the second and third image processing circuits 43 and 44 is delayed.

  The functions of the multifunction peripheral 100 according to the second embodiment will be described below. The line data n−1 input from the RAM 50 through the RAM I / F 41 is transmitted to the second and third image processing circuits 43 and 44. The line data n and n + 1 are temporarily stored in the line buffer memories 49 and 49 through the RAM I / F 41, respectively, and then sequentially input to the second and third image processing circuits 44 and 44. Therefore, when the second and third image processing circuits 43 and 44 perform one process using three line data, the RAM I / F 41 and the second and third image processing circuits 43 and 44 include the two line buffer memories 49 and 49, respectively. The communication path between the third image processing circuits 43 and 44 can be a serial wiring. In addition to the above, since the line buffer memories 49 and 49 are shared by the second and third image processing circuits 43 and 44, the circuit configuration of the ASIC 40 can be simplified.

3. Other embodiments:
There are various modifications of the present invention. The combination of the second and third image processing circuits 43 and 44 is not limited to that described above. For example, when the multifunction peripheral 100 has a function of displaying thumbnail data on the display unit 93, the third image processing circuit 44 performs a pixel number conversion process for generating a thumbnail image by reducing the number of pixels of the image data. There may be. The third image processing circuit 44 may perform background removal processing. Here, the background removal processing is intended to improve the legibility and image quality of an image by correcting the background value when the background of the document image is colored.

  The number of image processing circuits to which the same image data is supplied is not limited to two. That is, if there are two or more processes that can be executed in parallel on the same image data, an image processing circuit that performs each process may be connected in parallel to the RAM I / F 41.

  The number of line data N input to the image processing circuit may not be the same. FIG. 7 is a block diagram illustrating an image processing controller as a modification. As shown in FIG. 7, the input line data of the second image processing circuit 43 and the third image processing circuit 44 is connected to the second image processing circuit 43 without branching one of the communication paths. The number of N can be varied. Therefore, the circuit can be configured flexibly without being limited by the number of input line data N.

  As a configuration of the image processing apparatus, it is only necessary to include the image processing controller according to the present invention, and it is not necessary to include a data reading apparatus such as a scanner engine.

Needless to say, the present invention is not limited to the above embodiments. In other words, the mutually replaceable members and configurations disclosed in the examples are applied by appropriately changing the combinations thereof, and are not disclosed in the examples. Substantially replace members and configurations that are mutually interchangeable with the members and configurations disclosed in the above, and change and apply combinations thereof, although not disclosed in the examples, but based on known techniques It is an example of the present invention that a person skilled in the art appropriately replaces the members and structures that can be assumed as substitutes for the members and structures disclosed in the above-described embodiments, and modifies and applies combinations thereof. It is disclosed.

It is a block diagram which shows the principal part of the image processing apparatus which concerns on 1st Embodiment. It is a block diagram which shows the structure of ASIC. FIG. 6 is an image diagram for explaining proximity processing executed by a second image processing circuit 43. It is a flowchart for demonstrating the process performed by ASIC40 as an example. It is a sequence chart for explaining the communication state among the 1st-5th image processing circuits 42-46, RAM I / F41, and RAM50 in time series. It is a block diagram which shows ASIC40 which concerns on 2nd Embodiment. It is a block diagram which shows the image processing controller as a modification. It is a block diagram which shows the principal part of the conventional image processing controller.

Explanation of symbols

DESCRIPTION OF SYMBOLS 30 ... Bus, 40 ... ASIC, 41 ... RAM I / F, 42 ... First image processing circuit, 43 ... Second image processing circuit, 43a ... Buffer memory, 44 ... Third image processing circuit, 45 ... Fourth Image processing circuit, 46 ... fifth image processing circuit, 47 ... output I / F, 48i to j ... communication path, 49 ... line buffer memory, 50 ... RAM, 70 ... CPU, 80 ... main controller, 90 ... scanner Engine 91 91 Printer engine 92 Operation panel 93 Display unit 94 95 I / O 100 Multifunction machine

Claims (7)

An image processing controller that performs processing on input image data using each circuit mounted therein,
A storage unit for storing the image data;
A plurality of image processing circuits for performing predetermined processing on the image data;
Communication for connecting the storage unit and the plurality of image processing circuits and branching a communication path on the plurality of image processing circuits side and transmitting the stored same image data to the plurality of image processing circuits Means,
The image processing controller, wherein the plurality of image processing circuits perform parallel processing on the transmitted same image data.   2. The communication unit according to claim 1, wherein the communication unit is wired so as to branch between one output terminal that outputs the image data and the plurality of image processing circuits on the image processing circuit side. Image processing controller.   The plurality of image processing circuits perform neighborhood processing on a target pixel by using a plurality of line data indicating pixel groups arranged in the main scanning direction in the image for each processing. The image processing controller according to any one of 2.   The plurality of image processing circuits are an image processing circuit that performs image recognition processing for recognizing features in an image, and an image processing circuit that performs correction processing for correcting image features for image data. The image processing controller according to claim 3.   The plurality of image processing circuits are an image processing circuit that performs pixel number conversion processing on image data, and an image processing circuit that performs correction processing for correcting image characteristics on the image data. The image processing controller according to claim 3.   The communication unit includes a line buffer memory in a communication path between the plurality of image processing circuits from the communication unit, and delays the plurality of line data by the line buffer memory and transmits the line data to the plurality of image processing circuits. The image processing controller according to claim 3. An image processing apparatus that performs a plurality of image processing on input image data,
A storage unit for storing the image data;
A plurality of image processing circuits for performing predetermined processing on the image data;
A communication unit that connects the storage unit and the plurality of image processing circuits, and branches the communication paths on the plurality of image processing sides to transmit the stored same image data to the plurality of image processing circuits. And
The plurality of image processing circuits perform parallel processing on the same transmitted image data.

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