JP2010061765A - Laser driving device, optical unit, and optical apparatus - Google Patents

Abstract

Even when a write strategy technique is applied, an APC control signal is not affected by a transmission band reduction caused by a transmission member.
An optical member such as a semiconductor laser 41, a laser drive unit, a beam splitter 42, a light emission waveform generation unit 203, a photoelectric conversion unit (a light receiving element 310, a current-voltage conversion unit 312), a sample hold unit 330, a sampling pulse generation unit. 400 is arranged on the optical pickup 14. The APC control unit 58 and the write strategy circuit 290 are arranged on the drive board. The drive substrate and the optical pickup 14 are connected by the flexible substrate 51. Neither the sampling pulse for APC control nor the feedback signal is affected by the transmission band reduction caused by the flexible substrate 51.
[Selection] Figure 3

Description

  The present invention relates to an optical device such as a laser driving device (laser driving circuit), an optical unit, an optical disk device using a laser driving device or an optical unit (recording / reproducing device using an optical disk).

  Recording / reproducing apparatuses using a laser as a light source are used in various fields. For example, an optical disk recording / reproducing apparatus (hereinafter also simply referred to as an optical disk apparatus) that uses an optical disk as a recording or reproducing medium has attracted attention.

  An optical pickup of an optical disc apparatus usually includes a laser driving unit that drives a laser, a light detection unit for detecting a reproduction signal, and a light detection unit for monitoring the amount of laser light (Patent Document 1, Non-Patent Document). 1).

Japanese Patent No. 4019280 “Industry-leading low noise and high-speed response Blu-ray 8x speed recording and playback technology barrier”, CX-PAL74, [online], Sony Corporation, [searched on August 18, 2008] , Internet <URL: http://www.sony.co.jp/Products/SC-HP/cx_pal/vol74/pdf/featuring2_bd.pdf>

  The light detection unit for detecting a reproduction signal converts reflected light from the optical disk into an electrical signal, and has a role of detecting a control signal such as a focus signal and a tracking signal and a data signal recorded on the optical disk from the reflected light. . The light detection unit for monitoring the amount of light detects a signal that is a rule of the laser APC (Auto Power Control) system, and monitors the laser emission and monitors the laser power during reading and writing.

  An optical disc apparatus is composed of a pickup that is a movable part and a signal processing system that is a fixed part. Generally, the laser drive unit and each light detection unit are arranged in the vicinity of a laser mounted on a pickup, and a flexible printed circuit board (from a signal processing system to a pickup (laser drive / light detection system)) (Refer to FIGS. 9 and 10 of Non-Patent Document 1).

  In the light quantity monitoring method in FIG. 9 of Non-Patent Document 1, a light quantity signal (power monitor signal) is detected and amplified by a light detection unit on the optical pickup side. Then, the signal is transmitted to the APC control unit of the signal processing system via the flexible substrate, and sampled and held by the sample hold unit of the APC control unit, and a laser power monitor voltage (approximately DC level) for APC control is acquired. The pulse signal for sample and hold is supplied from a timing strategy generator (Timing Gen.) that is provided along with a write strategy section for recording (details will be described later).

  On the other hand, in the light amount monitoring method in FIG. 10 of Non-Patent Document 1, as in paragraphs 6 and 7 of Patent Document 1, a sample hold unit is arranged in the light detection unit on the optical pickup side to sample and hold the photoelectric conversion signal. As a result, the laser power monitor voltage is acquired. The recording write strategy unit arranged in the laser driving unit generates a pulse signal for sample hold and supplies it to the sample hold unit.

  In the configuration of FIG. 9 of Non-Patent Document 1, the power monitor signal PM for APC is transmitted through a flexible substrate, so that signal degradation becomes a problem. That is, the pattern of the power monitor signal for APC transmitted through the flexible board at the time of signal writing is the same as the laser emission pattern at the time of signal writing, and its frequency is increased. There is a problem associated with transmitting a high-frequency power monitor signal through the flexible board, such as the transmission band being limited by the flexible board and the power monitor signal being unable to be accurately transmitted to the APC control unit.

  In the configuration of FIG. 10 of Non-Patent Document 1, the laser power monitor voltage is almost a direct current level, and high-speed signal transmission through the flexible board is not necessary, so that the power monitor signal PM is transmitted through the flexible board. The problem as shown in FIG. 9 is solved. However, since the write strategy part is accommodated in the laser drive IC, the laser drive IC becomes large (chip area and package area is large), power consumption increases, heat generation occurs, and costs increase. There are difficulties.

  Non-Patent Document 1 describes that an increase in power consumption due to the incorporation of a write strategy section is suppressed to a practical level by reviewing the circuit architecture, but this does not solve the essential problem.

  The present invention has been made in view of the above circumstances. A signal for APC control (feedback signal and sample) that can solve the problems of FIGS. 9 and 10 of Non-Patent Document 1 while also considering the application of write strategy technology. The purpose is to provide a new mechanism for pulse generation and transmission techniques.

  In the present invention, a light emission waveform pulse generation unit that generates a write strategy signal (a plurality of pulse signals) that defines a light emission waveform when applying the write strategy technique and a sampling pulse generation unit that generates a sampling pulse are different from each other. Mount on the member. And the member in which each is mounted is connected with a transmission member.

  On the side on which the sampling pulse generation unit is mounted, a laser element, a drive unit, an optical member, a light emission waveform generation unit, and a photoelectric conversion unit are also mounted, and generally corresponds to an optical unit called an optical pickup. Preferably, the sampling pulse generation unit is mounted on a laser drive device (typically a semiconductor IC) that houses the light emission waveform generation unit and the drive unit.

  The side on which the light emission waveform pulse generation unit is mounted also includes an APC control unit that generates a laser power instruction signal for APC control and supplies it to the light emission waveform generation unit. It corresponds to what is called.

  The sampling pulse generation unit generates a sampling pulse based on the edge of the light emission waveform based on the write strategy signal transmitted through the transmission member, and supplies the sampling pulse to the sample hold unit.

  With such a configuration, the sampling pulse generated by the sampling pulse generation unit is supplied to the sample hold unit without passing through the transmission member. The sampling pulse for APC control is not affected by the transmission band reduction caused by the transmission member.

  The feedback signal for APC control is not a state of a high-frequency power monitor signal, but is a state of a substantially DC level sample hold signal (power monitor voltage) generated by the sample hold unit, and is APC controlled via a transmission member. Sent to the department. The feedback signal for APC control is not affected by the transmission band reduction caused by the transmission member.

  According to one aspect of the present invention, even when the write strategy technique is applied, neither the sampling pulse for APC control nor the feedback signal is affected by the transmission band reduction caused by the transmission member.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The description will be given in the following order.

1. 1. Outline of configuration of recording / reproducing apparatus 2. Signal interface problems and principles of countermeasures Signal interface of this embodiment (normal system base and sequential system base)
4). Sampling pulse setting: first example (first setting method for marks)
5). Sampling pulse setting: second example (second setting method for marks)
6). Sampling pulse setting: third example (first setting method for space)
7). Sampling pulse setting: 4th example (second setting method for space)
8). Details of sequential method

<Recording and playback device>
FIG. 1 is a diagram illustrating a configuration example of a recording / reproducing apparatus (optical disk apparatus) which is an example of an optical apparatus. FIG. 1A is a diagram illustrating a configuration example of an optical pickup.

  As an optical disk OD (Optical Disk), in addition to a so-called read-only optical disk such as a CD (Compact Disk) and a CD-ROM (Read Only Memory), a write-once optical disk such as a CD-R (Recordable), a CD- A rewritable optical disk such as RW (Rewritable) may be used. Furthermore, it is not limited to a CD-based optical disk, but may be an MO (magneto-optical disk), a normal DVD (Digital Video or Versatile Disk), or a next-generation DVD using a blue laser with a wavelength of about 405 nm, for example. It may be a DVD-type optical disc. The DVD system includes DVD-RAM / -R / + R / -RW / + RW. Further, it may be a so-called double density CD (DDCD; DD = Double Density), CD-R, or CD-RW in which the recording density is approximately double that of the current format while following the current CD format. .

  The recording / reproducing apparatus 1 of this embodiment includes an optical pickup 14 and a pickup control unit 32. The optical pickup 14 records information on the optical disc OD or reproduces information. The optical pickup 14 is controlled by the pickup control unit 32 and controls the radial position (tracking servo) and the focal direction position (focus servo) of the laser beam emitted from the optical pickup 14 with respect to the optical disc OD.

  The recording / reproducing apparatus 1 includes a spindle motor 10, a motor driver 12, and a spindle motor control unit 30 as a rotation control unit (rotation servo system). The spindle motor 10 rotates the optical disc OD, and the number of rotations is controlled by the spindle motor control unit 30.

  The recording / reproducing apparatus 1 includes, as a recording / reproducing system, an information recording unit that records information via an optical pickup 14 and a recording / reproducing signal processing unit that is an example of an information reproducing unit that reproduces information recorded on an optical disc OD. 50. The recording / reproduction signal processing unit 50 and the optical pickup 14 are connected via a signal wiring pattern formed on a flexible substrate 51 as an example of a transmission member that transmits a signal. The total length of the flexible substrate 51 varies depending on the arrangement of the recording / reproducing signal processing unit 50 and the optical pickup 14, but has a length of about 100 mm, for example.

  The recording / reproducing apparatus 1 includes, as a controller system, a controller 62 and an interface unit that performs an interface function that is not illustrated. The controller 62 is configured by a microprocessor (MPU: Micro Processing Unit), and controls the operation of the servo system having the spindle motor control unit 30 and the pickup control unit 32 and the recording / reproduction signal processing unit 50. The interface unit has an interface (connection) function with a personal computer (hereinafter referred to as a personal computer) which is an example of an information processing apparatus (host apparatus) that performs various types of information processing using the recording / reproducing apparatus 1. A host IF controller is provided in the interface unit. The recording / reproducing apparatus 1 and the personal computer constitute an information recording / reproducing system (optical disc system).

[Optical pickup]
As shown in FIG. 1A, the optical pickup 14 includes a semiconductor laser 41, a beam splitter 42, a lens 43, a mirror 44, a light detection unit 45, and a drive current control unit 47 which is an example of a laser drive device. The drive current control unit 47 is configured by a laser drive IC (LDD) as an example. The drive current control unit 47 receives a recording pulse corresponding to the write strategy from the digital signal processing unit 57 of the recording / reproduction signal processing unit 50, and a laser power instruction voltage PW from the APC control unit 58 via the flexible substrate 51. Is transmitted. The drive current control unit 47 combines the recording pulse corresponding to the write strategy and the laser power instruction voltage PW for APC control to generate a recording waveform, amplifies the recording waveform, and drives the semiconductor laser 41.

  The semiconductor laser 41 emits a laser beam for recording additional information on the optical disc OD or reading information recorded on the optical disc OD. The beam splitter 42 passes or reflects the laser light from the semiconductor laser 41 and the reflected light from the optical disk OD. The mirror 44 reflects laser light and reflected light in a direction of approximately 90 degrees.

  The light detection unit 45 includes a first light detection unit 45a and a second light detection unit 45b. The first light detection unit 45a is configured by a photo detector IC (PDIC) as an example, and the second light detection unit 45b is configured by a front monitor photo detector IC (FMPDIC) as an example. The first light detection unit 45a acquires an RF signal for reproduction signal processing (including servo processing), and the second light detection unit 45b acquires a power monitor signal PM for APC control. Although not shown, each of the first light detection unit 45a and the second light detection unit 45b includes a light receiving element, a current-voltage conversion unit, and an amplification unit. Further, as will be described in detail later, the second light detection unit 45b of the present embodiment has a sample and hold circuit that samples and holds the power monitor signal PM output from the amplification unit and acquires the power monitor voltage PD.

  For example, laser light emitted from the semiconductor laser 41 passes through the lens 43a and the beam splitter 42, is reflected by the mirror 44a toward the optical disc OD side, is condensed by the lens 43b, and irradiates the optical disc OD. The reflected light (laser light) reflected by the optical disc OD passes through the lens 43b, is reflected by the mirror 44a to the beam splitter 42 side, is reflected by the beam splitter 42 to the mirror 44b side, and is further reflected by the mirror 44b. 1 is incident on the light detection unit 45a. The first light detection unit 45a converts this incident light into an electric signal, amplifies it, and acquires an RF signal. The RF signal is transmitted to the recording / reproducing signal processing unit 50 via the flexible substrate 51.

  Further, part of the laser light emitted from the semiconductor laser 41 is reflected by the beam splitter 42 toward the second light detection unit 45b and enters the second light detection unit 45b. The second light detection unit 45b converts the incident light into an electric signal and amplifies it to obtain the power monitor signal PM, and further samples and holds the power monitor signal PM to obtain the power monitor voltage PD. The power monitor voltage PD is transmitted to the APC control unit 58 of the recording / reproduction signal processing unit 50 via the flexible substrate 51.

[Recording / Signal Processing Unit]
The recording / reproduction signal processing unit 50 includes an RF amplification unit 52, a waveform shaping unit 53 (waveform equalizer; Equalizer), and an AD conversion unit 54 (ADC; Analog to Digital Converter). The recording / reproduction signal processing unit 50 includes a clock reproduction unit 55, a write clock generation unit 56, a digital signal processing unit 57 composed of a DSP (Digital Signal Processor), and an APC control unit 58 (Automatic Power Control). Is provided.

  The RF amplifier 52 amplifies a minute RF (high frequency) signal (reproduced RF signal) read by the optical pickup 14 to a predetermined level. The waveform shaping unit 53 shapes the reproduction RF signal output from the RF amplification unit 52. The AD conversion unit 54 converts the analog reproduction RF signal output from the waveform shaping unit 53 into digital reproduction RF data Din.

  The clock recovery unit 55 includes a data recovery type phase synchronization circuit (PLL circuit) that generates a clock signal synchronized with the reproduction RF data Din output from the AD conversion unit 54. The clock recovery unit 55 supplies the recovered clock signal to the AD conversion unit 54 as an AD clock CKad (sampling clock), and also supplies it to other functional units.

  The digital signal processing unit 57 includes, for example, a data detection unit and a demodulation processing unit as a function unit for reproduction. The data detection unit performs processing such as PRML (Partial Response Maximum Likelihood) and detects digital data from the reproduction RF data Din.

  The demodulation processing unit demodulates the digital data sequence and performs digital signal processing such as decoding digital audio data and digital image data. For example, the demodulation processing unit includes a demodulation unit, an error correction code (ECC) correction unit, an address decoding unit, and the like, and performs demodulation / ECC correction and address decoding. The demodulated data is transferred to the host device via the interface unit.

  The write clock generator 56 generates a write clock for modulating data when recording on the optical disc OD based on a reference clock supplied from a crystal oscillator or the like. The digital signal processing unit 57 includes an ECC encoding unit and a modulation processing unit as recording functional units. The digital signal processing unit 57 generates recording data, and further generates a light emission timing signal of each power level corresponding to the write strategy.

  The recording / reproducing apparatus 1 of the present embodiment records digital data output from an information source on an optical disc OD by laser light emitted from a semiconductor laser 41 and reproduces recorded information on the optical disc OD. The drive current control unit 47 supplies a drive current corresponding to the write strategy to the semiconductor laser 41. The APC control unit 58 has a function of controlling the emission power of the semiconductor laser 41 to be constant based on the power monitor voltage PD, and supplies the laser power instruction voltage PW to the drive current control unit 47 of the optical pickup 14.

<Signal interface problems and countermeasure principle>
2 to 2C are diagrams for explaining the basic principle of the problem of the signal interface and the countermeasure technique. Here, FIG. 2 is a diagram illustrating an example of a laser driving method to which the write strategy technique is applied. 2A to 2C are diagrams illustrating a first comparative example to a third comparative example of the signal interface method when the semiconductor laser 41 is driven by applying the write strategy technique.

  As an optical disk recording method, when information is recorded on an optical disk medium, recording is performed by a so-called light intensity modulation method in which a mark / space is formed on the recording medium by a change in intensity of light power. In order to perform recording with few errors, the intensity change of the optical power uses not the recording data itself but a waveform as shown in FIG. 2, for example.

  In the multi-pulse method, a recording clock is divided to emit pulses. In this example, there are three power levels: Cool, Erase, and Peak. The castle method is mainly used in high-speed recording, and does not emit pulses in units of recording clocks, but raises the laser power at the beginning and end of the mark. In this example, there are four power levels, cool, erase, peak, and overdrive (Over Drive), which are increased compared to the multi-pulse system.

  The timing of each edge is adjusted in units smaller than the channel clock interval (Tw). For example, Tw / 40, Tw / 32, Tw / 16, etc.

  Such a contrivance of the light emission pattern is referred to as recording compensation (write strategy technology), and a recording compensation circuit (write strategy circuit) generates the timing of each edge according to recording data.

  In each of the following embodiments, a castle method is applied as a laser emission waveform unless otherwise specified. This is because the castle method is common for high-speed recording. However, the mechanism of each embodiment to be described later can be applied to a multi-pulse system. This is because the castle method and the multi-pulse method are different from each other only in the setting value of the power level at each pulse timing, and are common in the point that “the recording power is divided into pulses and controlled to a multi-value level”.

  On the other hand, as the laser drive system of the optical disk apparatus, for example, as shown in FIGS. 2A to 2C, an optical pickup 14 (optical head) on which a semiconductor laser 41 and optical components are mounted, and a drive board (main board) on which a control circuit is mounted. ). Since the optical pickup 14 is movable according to the radius of the optical disk OD, both are connected by the flexible substrate 51.

  Here, in the first comparative example shown in FIG. 2A, the write strategy circuit 290X (light emission waveform pulse generation unit) is mounted on the drive substrate. In this case, a write strategy signal (recording pulse signal) instructing the light emission timing corresponding to each power level from the drive substrate to the laser drive circuit 200X (corresponding to the drive current control unit 47 in FIG. 1A) mounted on the optical pickup 14 Laser power instruction voltage PW is sent. The laser drive circuit 200X includes a light emission waveform generation unit 203 that generates a light emission waveform by synthesizing the write strategy signal and the laser power instruction voltage PW. The light emission waveform generation unit 203 causes the semiconductor laser 41 to emit light by generating a drive current by increasing or decreasing the power according to the laser power instruction voltage PW.

  Focusing on the APC control system, first, the power monitor circuit 300A on the optical pickup 14 side (corresponding to the second light detection unit 45b in FIG. 1A) includes a light receiving element 310 and a current-voltage conversion unit 312 (IV). And an output buffer 314 having an amplification function. The light receiving element 310 and the current-voltage conversion unit 312 constitute a photoelectric conversion unit. The current-voltage conversion unit 312 is a single-end input-single-end output type, converts the current signal photoelectrically converted by the light receiving element 310 into a voltage signal, generates a power monitor signal PM, and supplies it to the output buffer 314. The output buffer 314 is a single-ended input-differential output type, and sends the power monitor signal PM to the APC control unit 58 side as a differential signal (PM_P, PM_N) as a feedback signal for APC.

  The APC control unit 58A of the recording / playback signal processing unit 50 mounted on the drive board includes an input buffer 320 and a sample hold unit 330. The sample hold unit 330 includes a mark sample hold circuit 332 and a space sample hold circuit 334. The sample hold circuit 332 samples the value of the write period (mark position) of the power monitor signal PM to obtain the power monitor voltage PD_1. The sample hold circuit 334 obtains the power monitor voltage PD_2 by sampling the value of the bias period (space position) of the power monitor signal PM. The input buffer 320 is a differential input-differential output type, and sends the received power monitor signal PM (PM_P, PM_N) to the sample hold circuit 330 as a differential signal.

  A part of the laser light emitted from the semiconductor laser 41 is reflected by the beam splitter 42 and enters the light receiving element 310. The light receiving element 310 receives the laser beam and converts it into a corresponding current, and the current-voltage conversion unit 312 converts it into a voltage and inputs it to the output buffer 314 as a light reception signal. The output buffer 314 amplifies the received light signal and outputs it as a differential power monitor signal PM to the sample hold unit 330 via the input buffer 320. The sample hold unit 330 samples and holds the power monitor signal PM based on the sampling pulse SP supplied from the write strategy circuit 290X, and acquires power monitor voltages PD_1 and PD_2.

  The APC control unit 58A obtains the optimum recording output level of the semiconductor laser 41 based on the power monitor voltages PD_1 and PD_2, generates a laser power instruction voltage PW for maintaining the emission power of the semiconductor laser 41 constant, and generates a light emission waveform. This is supplied to the generation unit 203.

  In the first comparative example having such a configuration, the write strategy signal (also referred to as a recording pulse signal or a laser drive timing signal) sent from the write strategy circuit 290X has finer timing information than the channel clock. The following problems associated with the improvement of the recording speed are problematic. The first point is that the number of transmission lines of the recording system increases as the power level increases. For example, in the figure, 4 to 5 channels corresponding to LVDS (Low Voltage Differential Signal) are shown. Second, it is difficult to accurately transmit the write strategy signal due to the frequency characteristic degradation (transmission band degradation) caused by the flexible substrate 51. This makes it impossible to accurately transmit the write strategy signal interval, which hinders improvement in recording speed. Further, as shown in FIG. 2A (2), edge shift due to intersymbol interference occurs in the shortest pulse (for example, about 1T).

  The power monitor signal PM is obtained by detecting laser light corresponding to the write strategy signal sent from the write strategy circuit 290X. Therefore, the power monitor signal PM also has a problem caused by the flexible substrate 51, like the write strategy signal. As shown in FIG. 2A (3), due to the frequency characteristics of the flexible substrate 51, the power monitor signal PM is deteriorated and it is difficult to accurately transmit it. In addition, delay variation occurs, and there is a problem that the sampling gate cannot be opened due to the shortening of the pulse due to the high speed.

  In the second comparative example shown in FIG. 2B, the write strategy circuit 290Y (light emission waveform pulse generation unit) is mounted not on the drive substrate but on a laser drive circuit 200Y including a circuit similar to the laser drive circuit 200X of the first comparative example. ing. The write strategy circuit 290Y generates a timing signal for controlling the optical power from the recording clock and the recording data. The timing signal is a unit smaller than the channel clock interval (Tw) and is generated for each power level, and the power level and the timing are associated one to one. A write strategy circuit 290Y for realizing this includes a phase synchronization circuit, a memory, an address encoder, and a timing generation circuit. The phase synchronization circuit generates a multiphase clock for generating a unit smaller than the channel clock interval (Tw). The memory stores level information. The address encoder determines the recording data length and generates a memory address. The timing generation circuit converts timing information read from the memory into a timing signal in accordance with the recording data length.

  Focusing on the APC control system, in the second comparative example, the sample hold unit 330 is housed in the power monitor circuit 300B on the optical pickup 14 side, not on the drive substrate (recording / reproduction signal processing unit 50) side. Specifically, the power monitor circuit 300B of the second comparative example includes a light receiving element 310, a current-voltage conversion unit 313 (IV), a variable gain type amplification unit 315 (GCA), a sample hold unit 330, And an output buffer 340. The light receiving element 310 and the current-voltage conversion unit 313 constitute a photoelectric conversion unit.

  The current-voltage converter 313 is a differential input-differential output type, converts the current signal photoelectrically converted by the light receiving element 310 into a voltage signal, generates differential power monitor signals PM_P and PM_N, and an amplifier 315 is supplied. The amplifying unit 315 is a differential input-differential output type, amplifies the power monitor signals PM_P and PM_N, and supplies them to the sample hold unit 330.

  The sample hold circuit 332 includes a sample hold circuit 332_P that samples and holds the non-inverted power monitor signal PM_P and a sample hold circuit 332_N that samples and holds the inverted power monitor signal PM_N. Similarly, the sample hold circuit 334 includes a sample hold circuit 334_P that samples and holds the non-inverted power monitor signal PM_P and a sample hold circuit 334_N that samples and holds the inverted power monitor signal PM_N. Although not shown in the first comparative example, the sample hold circuits 332 and 334 are the same as those in the second comparative example.

  The output buffer 340 includes an output buffer 342 for the power monitor voltage PD_1 and an output buffer 344 for the power monitor voltage PD_2. The output buffers 342 and 344 are of a differential input / single end output type. The output buffer 342 generates a power monitor voltage PD_1 based on the power monitor voltage PD_P1 from the sample hold circuit 332_P and the power monitor voltage PD_N1 from the sample hold circuit 332_N, and supplies the power monitor voltage PD_1 to the APC control unit 58B. The output buffer 344 generates a power monitor voltage PD_2 based on the power monitor voltage PD_P2 from the sample hold circuit 334_P and the power monitor voltage PD_N2 from the sample hold circuit 334_N, and supplies the power monitor voltage PD_2 to the APC control unit 58B. In this configuration, power monitor voltages PD_1 and PD_2 are sent to the APC controller 58 via the flexible substrate 51 as feedback signals for APC.

  In the second comparative example, the recording system signal transmitted by the flexible substrate 51 becomes a recording clock and recording data, and the problem of strategy transmission in the first comparative example is solved. For example, the number of LVDS channels for write strategy transmission is reduced, and both the recording clock and the recording data are signals in units of channel clocks, so that they are not easily affected by the transmission characteristics of the flexible substrate 51. In the APC control system, the sample hold unit 330 is mounted on the power monitor circuit 300B on the optical pickup 14 side so that transmission at the power monitor voltage PD is possible, and the power monitor signal PM is transmitted by the flexible substrate 51. The problem of the first example is solved.

  However, since the write strategy circuit 290Y includes a phase synchronization circuit, a memory, an address encoder, and a timing generation circuit, the laser drive circuit 200Y has a large scale (chip area and package area are large), power consumption increases, and heat is generated. There is a difficulty that occurs.

  In the third comparative example shown in FIG. 2C, the write strategy circuit 290X is arranged in the recording / reproduction signal processing unit 50 as in the first comparative example, and the sample hold unit 330 is arranged in the power monitor circuit 300B as in the second comparative example. It is arranged. In this case, the recording system has the same problem as the first comparative example.

  In addition, the sampling pulse SP for the sample hold unit 330 is generated by the sampling pulse generation unit 400X attached to the write strategy circuit 290X, and the sampling pulse SP is transmitted to the sample hold unit 330 via the flexible substrate 51. . Therefore, an increase in the number of flexible wirings and signal degradation of the sampling pulse SP due to flexible transmission become new problems. Furthermore, considering that LVDS is supported for high-speed transmission of the sampling pulse SP, the sample hold unit 330 needs to make the input circuit for the sampling pulse SP compatible with LVDS, which increases the number of terminals. .

  As described above, in the first to third comparative examples, the number of signal transmissions and the transmission band decrease or the write strategy circuit 290 is arranged in the laser driving circuit 200 in the recording signal transmission and the APC control signal transmission. There are difficulties in terms of circuit scale.

  Therefore, in the present embodiment, first, the problem of the first to third comparative examples is solved in the method for generating and transmitting the APC control signal and the sampling pulse SP while considering the application of the write strategy technique. Make it possible. The basic idea of this method is that the write strategy circuit is arranged on the fixed circuit board side, and the sampling pulse SP is based on the signal defining the light emission power pattern (waveform control signal pattern) for the write strategy on the optical pickup 14 side. Is to generate. That is, the sampling pulse SP is generated based on the laser drive timing signal received by the laser drive circuit 200 that does not include the write strategy circuit 290 (light emission waveform pulse generation unit).

  The sampling pulse generation unit 400 that generates the sampling pulse SP may be disposed in the laser drive circuit 200, may be disposed in the power monitor circuit 300, or is the laser drive circuit 200 or the power monitor circuit 300? It may be arranged separately.

  The sampling pulse generation unit 400 according to the present embodiment generates the sampling pulse SP based on the laser drive timing signal with reference to the timing at which the level changes in the recording waveform control signal pattern.

  For example, the sampling pulse SP_1 for the mark supplied to the sample hold circuit 332 is used to compensate for delay time, pulse width, and delay to the sample hold circuit 332 from a certain edge for forming the mark. Generate by setting the overall delay time. This method is referred to as a first setting method.

  Further, a certain edge for forming a mark is used as a starting point, a delay time from that point, and an edge different from the starting point is used as a reference for the end point of the pulse, the delay time from that point, and delay compensation to the sample hold circuit 332 Set and generate the overall delay time for. This method is referred to as a second setting method.

  Furthermore, if the time from the starting edge to a certain edge different from the starting point is equal to or less than the set value, it is possible to set so that the mark sampling pulse SP_1 is not generated.

  The generation of the sampling pulse SP_2 for space is the same as that for the mark as follows. That is, the sampling pulse SP_2 for the space starts from a certain edge for forming the space, sets the delay time from there, the pulse width, and the overall delay time for delay compensation to the sample hold circuit 334. Generate (first setting method).

  Further, a certain edge for forming a space is used as a starting point, a delay time therefrom, and an edge different from the starting point is used as a reference for the end point of the pulse, the delay time from there and a delay compensation to the sample hold circuit 334 An overall delay time for the first is set and generated (second setting method).

  Furthermore, if the time from the starting edge to a certain edge different from the starting point is equal to or less than the set value, setting that does not generate the sampling pulse SP_2 for space is enabled.

  More preferably, the circuit scale of the laser drive circuit is increased as much as the second comparative example with respect to the problem of the number of signal lines transmitted and the transmission band in the application of the write strategy technology while solving the above problems of the APC control system. And make it a mechanism that can solve it. The basic idea of this method is that, first, the power level information (recording waveform control signal pattern) of laser emission at each timing when the write strategy technology is applied is stored on the optical pickup 14 (for example, laser drive circuit 200) side. Keep it. The first transmission signal including information defining the reference pulse acquisition timing indicating the switching timing of the space and mark repetition, and the information specifying the acquisition timing of the switching pulse indicating the switching timing of the laser emission level The second transmission signal including is used. The first transmission signal and the second transmission signal are treated as the write strategy signals of FIGS. 1 and 1A. In addition, it can be considered that the reference pulse also indicates the switching timing of the laser emission level, and it is conceivable to adopt a method that is handled as one aspect of the switching pulse.

  With respect to the recording system, a reference pulse and a switching pulse are generated from two types of pulse signals, the recording pulse control signal pattern is set to the initial level with the reference pulse, and then a write strategy technique is applied for each switching pulse according to the recording waveform control signal pattern. Switch to emission power level. Then, every time a reference pulse is generated, the same processing as described above is performed again. Such a method is referred to as a sequential method in this specification.

  The methods of the first and third comparative examples and the sequential method are common in that the write strategy circuit 290 is arranged on the drive substrate side, but the sequential method is said to have fewer types of signal transmission lines via the flexible substrate 51. There is a difference. Hereinafter, in comparison with the sequential method, the methods of the first and third comparative examples are referred to as normal methods.

<Signal interface: System configuration>
3 and 3A are diagrams showing a system configuration that realizes the signal interface system of the present embodiment.

  In the present embodiment, the recording system uses the same signal interface method as in the first and third comparative examples, and the APC control system includes the sampling pulse generator 400 on the optical pickup 14 side (particularly in the laser drive circuit 200). ). The laser drive circuit 200 includes a circuit similar to the laser drive circuit 200X of the first comparative example.

  Here, the first example shown in FIG. 3 is based on the normal method. The sampling pulse generator 400 generates sampling pulses SP_1 and SP_2 based on the LVDS-compatible write strategy signal (4 to 5ch) transmitted from the write strategy circuit 290 via the flexible board 51. The write strategy circuit 290 is accommodated in the digital signal processing unit 57.

  The second example shown in FIG. 3A is based on a sequential method. The sampling pulse generator 400 generates sampling pulses SP_1 and SP_2 based on the LVDS-compatible write strategy signal (2-3ch) transmitted from the recording / reproduction signal processor 50 via the flexible substrate 51. In the first example and the second example, the type of write strategy signal is different, resulting in a difference in the number of transmission lines, and the second example is smaller.

  For example, the digital signal processing unit 57 </ b> B of the second example includes a sequential transmission signal generation unit 500 at the subsequent stage of the write strategy circuit 290. The transmission signal generation unit 500 generates a first transmission signal and a second transmission signal based on a write strategy signal (for example, 4 to 5 ch) from the write strategy circuit 290. Here, the first transmission signal includes information defining the acquisition timing of the reference pulse indicating the switching timing of space and mark repetition. The second transmission signal includes information defining the acquisition timing of the switching pulse indicating the switching timing of the divided drive signal. The transmission signal generator 500 supplies the first and second transmission signals to the laser drive circuit 200 via the flexible substrate 51.

  The laser drive circuit 200 </ b> B of the second example includes a pulse reproduction unit 202 and a light emission waveform generation unit 203 that match the transmission signal generation unit 500 of the digital signal processing unit 57. The pulse regeneration unit 202 generates a reference pulse and a switching pulse based on the first and second transmission signals transmitted via the flexible substrate 51. The light emission waveform generation unit 203 generates a current signal according to the recording waveform control signal pattern using the reference pulse and the switching pulse.

  Details of the first and second transmission signals and the light emission waveform generation units 203 and 500 will be described later.

  In the first example and the second example, the types of pulse signals of the recording system transmitted from the digital signal processing unit 57 to the laser driving circuit 200 are different. In either case, the optical pickup 14 uses the optical pickup according to the recording waveform control signal pattern. There is no difference in driving 14. Since the sampling pulse generation unit 400 of the present embodiment generates the sampling pulse SP with reference to the timing at which the level changes in the recording waveform control signal pattern, the same regardless of the type of the recording-system pulse signal to be transmitted. A pulse setting method can be adopted. Below, the example of a setting is demonstrated.

<Sampling pulse setting: First example>
FIG. 4 is a diagram illustrating a first setting example of the sampling pulse SP. In this example, the laser emission waveform has four power levels: cool, erase, peak, and overdrive. Among these, the power level for forming the mark can be considered as peak and overdrive, and the power level for forming the space can be considered as cool and erase. The first example employs the first setting method when setting the sampling pulse SP_1 for the mark.

  Here, a description will be given of a case where the sampling pulse SP_1 samples and holds a peak level having a relatively wide width between the peak forming the mark and the overdrive. Since the sampling pulse SP_1 is used to sample and hold the peak level of the power monitor signal PM, the timing is set so that the power monitor signal PM can be sampled after it has settled from the overdrive level to the peak level. Therefore, it is preferable to generate the peak level based on the start position because it is not affected by the space width. In setting the timing for sampling the peak level, compensation for the signal band and delay of the signal path from the pulse regeneration unit 202 to the sample hold circuit 332 is considered.

  For example, when the castle method is applied, as shown in FIG. 4, the peak level start timing T12 is set to the starting edge (reference edge) for sampling the peak level. Starting from the reference edge T12, a rising delay time TD1_1 (T12 to T13) that defines the rising timing T13 of the sampling pulse SP_1 is set. The rise delay time TD1_1 is set in consideration of the time during which the power monitor signal PM input to the sample hold circuit 332 settles from the overdrive level to the peak level.

  Further, starting from the rising timing T13, a pulse width PW1 (T13 to T14) that defines the active H period of the sampling pulse SP_1 and a pulse delay time TD1_2 (T13 to T15) until the active pulse H actually becomes active are set. . The pulse delay time TD1_2 is set in consideration of compensating for the difference between the delay time of the sampling pulse and the delay time of the power monitor signal PM in the signal path from the pulse regeneration unit 202 to the sample hold circuit 332. Here, the delay time of the sampling pulse is a time required for the input from the pulse regenerating unit 202 through the sampling pulse generating unit 400 to the sample hold circuit 332. Further, the delay time of the power monitor signal PM means that the semiconductor laser 41 emits light from the pulse reproducing unit 202 through the light emission waveform generating unit 203, the light enters the light receiving element 310, and the current voltage converting unit 313 and the variable gain type. This is the time required for input to the sample hold circuit 332 via the amplifier 315.

  As a result, the sampling pulse SP_1 rises after “TD1_1 + TD1_2” has elapsed from the timing T12, and falls after the pulse width PW1 has elapsed.

  If the mark length is short, the setting is made so that the mark sampling pulse SP_1 is not generated. For example, the period from the reference edge T12 to the overdrive start timing T14 at the end of the peak level is set in the sampling pulse output determination setting period DET1. When the sampling pulse output determination setting period DET1 does not reach a predetermined value, the sampling pulse SP_1 is not output. For example, in a waveform that requires 10 ns for stabilization from the overdrive level to the peak level in the power monitor signal PM, the correct peak level can be sampled and held by setting the rise delay time TD1_1 to 10 ns or more. At this time, the sampling pulse output determination setting period DET1 is set to 10 ns, so that the sampling pulse SP_1 is not generated in a pulse having a peak level width of 10 ns or less.

<Sampling pulse setting: second example>
FIG. 4A is a diagram illustrating a second setting example of the sampling pulse SP. The laser emission waveform has the same power level as in FIG. The second example employs the second setting method when setting the mark sampling pulse SP_1.

  For example, when the castle method is applied, as shown in FIG. 4A, the peak level start timing T22 is set to the starting edge (rising reference edge) for sampling the peak level. A rising delay time TD2_1 (T22 to T23) that defines the rising timing T23 of the sampling pulse SP_1 is set starting from the rising reference edge T22. The rise delay time TD2_1 is set in consideration of the time during which the power monitor signal PM input to the sample hold circuit 332 settles from the overdrive level to the peak level. Further, the pulse delay time TD2_2 (T23 to T26) until the actual activation becomes H is set starting from the rising timing T23. The pulse delay time TD2_2 is set in consideration of compensating for the difference between the delay time of the sampling pulse and the delay time of the power monitor signal PM in the signal path from the pulse regeneration unit 202 to the sample hold circuit 332.

  Furthermore, the overdrive start timing T24 at the end of the peak level is set to the end point (falling reference edge) of the peak level sampling. A falling delay time TD2_3 (T24 to T25) that defines the end timing of the active H of the sampling pulse SP_1 is set starting from the falling reference edge T24. The falling delay time TD2_3 is set in consideration of the necessary pulse width. In this case, the pulse width PW2 is “T24 + TD2_3−T23”.

  As a result, the sampling pulse SP_1 rises after “TD2_1 + TD2_2” has elapsed from the timing T22, and falls after the pulse width PW2 (= T24 + TD2_3-T23) has elapsed.

  If the mark length is short, the setting is made so that the mark sampling pulse SP_1 is not generated. For example, the period from the rising reference edge T22 to the overdrive start timing T24 at the end of the peak level is set in the sampling pulse output determination setting period DET2. When the sampling pulse output determination setting period DET2 does not reach a predetermined value, the sampling pulse SP_1 is not output. For example, in a waveform that requires 10 ns for stabilization from the overdrive level to the peak level in the power monitor signal PM, the correct peak level can be sampled and held by setting the rising delay time TD2_1 to 10 ns or more. At this time, the sampling pulse output determination setting period DET2 is set to 10 ns, so that the sampling pulse SP_1 is not generated in a pulse having a peak level width of 10 ns or less.

<Sampling pulse setting: third example>
FIG. 4B is a diagram for explaining a third setting example of the sampling pulse SP. The laser emission waveform has the same power level as in FIG. In the third example, the first setting method is adopted when setting the sampling pulse SP_2 for space.

  Here, the case where the sampling pulse SP_2 samples and holds an erase level having a relatively wide width between cool and erase forming a space will be described. Since the sampling pulse SP_2 is used to sample and hold the erase level of the power monitor signal PM, the timing is set so that the power monitor signal PM can be sampled after being settled from the cool level to the erase level. Therefore, it is preferable to generate with reference to the start position of the erase level because it is not affected by the mark width. In setting the timing for sampling the erase level, compensation for the signal band and delay of the signal path from the pulse reproducing unit 202 to the sample hold circuit 334 is taken into consideration.

  For example, when the castle method is applied, as shown in FIG. 4B, the erase level start timing T32 is set to the edge (reference edge) of the starting point for sampling the erase level. Starting from the reference edge T32, a rising delay time TD3_1 (T32 to T33) that defines the rising timing T33 of the sampling pulse SP_2 is set. The rise delay time TD3_1 is set in consideration of the time for the power monitor signal PM input to the sample hold circuit 334 to settle from the cool level to the erase level.

  Further, starting from the rising timing T33, the pulse width PW3 (T33 to T34) for defining the active H period of the sampling pulse SP_2 and the pulse delay time TD3_2 (T33 to T37) until the active pulse H actually becomes active are set. . The pulse delay time TD3_2 is set in consideration of compensating for the difference between the delay time of the sampling pulse and the delay time of the power monitor signal PM in the signal path from the pulse regeneration unit 202 to the sample hold circuit 334.

  In this way, the sampling pulse SP_2 rises after “TD3_1 + TD3_2” has elapsed from the timing T32, and falls after the pulse width PW3 has elapsed.

  If the space length is short, the setting is made so as not to generate the space sampling pulse SP_2. For example, the period from the reference edge T32 to the overdrive start timing T35 at the end of the erase level is set in the sampling pulse output determination setting period DET3. When the sampling pulse output determination setting period DET3 does not reach a predetermined value, the sampling pulse SP_2 is not output. For example, in a waveform that requires 10 ns for stabilization from the cool level to the erase level in the power monitor signal PM, the correct erase level can be sampled and held by setting the rise delay time TD3_1 to 10 ns or more. At this time, the sampling pulse output determination setting period DET3 is set to 10 ns, so that the sampling pulse SP_2 is not generated for a pulse whose erase level width is 10 ns or less.

<Sampling pulse setting: 4th example>
FIG. 4C is a diagram illustrating a fourth setting example of the sampling pulse SP. The laser emission waveform has the same power level as in FIG. The fourth example employs the second setting method when setting the sampling pulse SP_2 for space.

  For example, when the castle method is applied, as shown in FIG. 4C, the start timing T42 of the erase level is set to the starting edge (rising reference edge) for sampling the erase level. A rising delay time TD4_1 (T42 to T43) that defines the rising timing T43 of the sampling pulse SP_2 is set starting from the rising reference edge T42. The rise delay time TD4_1 is set in consideration of the time during which the power monitor signal PM input to the sample hold circuit 334 settles from the cool level to the erase level. Further, the pulse delay time TD4_2 (T43 to T47) until the actual activation becomes H is set with the rising timing T43 as a starting point. The pulse delay time TD4_2 is set in consideration of compensating for the difference between the delay time of the sampling pulse and the delay time of the power monitor signal PM in the signal path from the pulse regeneration unit 202 to the sample hold circuit 334.

  Furthermore, the overdrive start timing T45, which is the last of the erase level, is set to the end edge (falling reference edge) of the erase level sampling. A falling delay time TD4_3 (T45 to T46) that defines the end timing of the active H of the sampling pulse SP_2 is set starting from the falling reference edge T45. The fall delay time TD4_3 is set in consideration of the necessary pulse width. In this case, the pulse width PW4 is “T45 + TD4_3−T43”.

  By doing so, the sampling pulse SP_2 rises after “TD4_1 + TD4_2” has elapsed from the timing T42, and falls after the pulse width PW4 (= T45 + TD4_3-T43) has elapsed.

  If the space length is short, the setting is made so as not to generate the space sampling pulse SP_2. For example, the period from the rising reference edge T42 to the overdrive start timing T45 at the end of the erase level is set in the sampling pulse output determination setting period DET4. When the sampling pulse output determination setting period DET4 does not reach a predetermined value, the sampling pulse SP_2 is not output. For example, in a waveform that requires 10 ns for stabilization from the cool level to the erase level in the power monitor signal PM, the correct erase level can be sampled and held by setting the rise delay time TD4_1 to 10 ns or more. At this time, the sampling pulse output determination setting period DET4 is set to 10 ns, so that the sampling pulse SP_2 is not generated for a pulse whose erase level width is 10 ns or less.

<Details of sequential method>
FIG. 5 is a diagram for explaining the details of the signal interface system of the second example that employs the sequential system for the recording system.

  As shown in FIG. 5 (2), the sequential method of this embodiment uses two types of input signals, a reset signal RS as a first transmission signal and an edge signal ES as a second transmission signal. A reset pulse RP as a reference pulse and an edge pulse EP as a switching pulse are generated.

  The first transmission signal (reset signal RS) is the same as the start edge of the recording waveform control signal pattern (edge pulse EP1 in FIG. 5 (1)) in the laser drive circuit 200Y of the second comparative example having a configuration with a built-in write strategy circuit. It is a signal indicating an edge. The second transmission signal (edge signal ES) is a signal indicating the same edge as that obtained by synthesizing other edge timings (edge pulses EP2, EP3, EP4, and EP5 in FIG. 5A).

  As shown in FIG. 5 (3), information on each light emission power level indicating the recording waveform control signal pattern is stored in order in each register of the memory circuit. Based on the reset pulse RP, information on the reference power level is read out. Information on the light emission power level at each timing following the information on the reference power level is sequentially read based on the edge pulse EP.

  That is, the laser drive circuit 200 is provided with a sequential access memory with a reset function that operates at high speed, and the power level information is held in the order of reading. Then, each time the switching pulse (edge pulse EP) is generated, the light emission power level information is selected and read sequentially from the next of the reference power level information. Further, regardless of which light emission power level is selected, the information on the head area (reference power level information) is read at the timing when the reference pulse is generated by the reset function of the reference pulse (reset pulse RP).

[Configuration of drive board]
FIG. 6 is a diagram illustrating a configuration example of the transmission signal generation unit 500 used to realize the sequential method provided in the digital signal processing unit 57 on the drive board side.

  The basic of the sequential method is to supply one first transmission signal and one second transmission signal to the laser driving circuit 200 in the recording mode, and drive the semiconductor laser 41 by the write strategy technique. As the first transmission signal, a reset signal RS in which the acquisition timing of the reference pulse indicating the switching timing of space and mark repetition is indicated by an edge is used. As the second transmission signal, an edge signal ES in which the switching pulse acquisition timing indicating the switching timing of the laser emission level is indicated by an edge is used. Incidentally, it is assumed here that the edge of the edge signal ES does not indicate the reset pulse RP.

  As shown in FIG. 5, among the edge pulses EP1 to EP5 that define the recording waveform control signal pattern generated by the write strategy circuit 290, the edge pulse EP1 corresponds to the reset pulse RP. Therefore, the transmission signal generator 500 generates the reset signal RS based on the edge pulse EP1. Further, since the edge pulses EP2 to EP5 correspond to the edge pulse EP, the transmission signal generation unit 500 generates the edge signal ES based on the edge pulses EP2 to EP5.

  At this time, either the concept of defining the reset pulse RP with one edge of the reset signal RS or the concept of defining the reset pulse RP with both edges can be adopted. Similarly, either the concept of defining the edge pulse EP with one edge of the edge signal ES or the concept of defining the edge pulse EP with both edges can be adopted. The edge pulse EP is output more frequently than the reset pulse RP. Therefore, in this embodiment, a configuration defined by both edges of the edge signal ES is adopted at least for the edge pulse EP. As for the reset pulse RP, either the case where it is defined by one edge of the reset signal RS or the case where it is defined by both edges is taken.

  For example, the transmission signal generation unit 500 includes an RS flip-flop 510 and a D flip-flop 512 in order to generate the reset signal RS. The non-return zero data NRZIDATA is input to the R input terminal of the RS flip-flop 510, and the edge pulse EP1 is input to the S input terminal. The non-inverting output terminal Q of the RS flip-flop 510 is connected to the clock input terminal CK of the D-type flip-flop 512. The inverting output terminal xQ of the D-type flip-flop 512 is connected to the D input terminal so that a 1/2 frequency dividing circuit is configured.

  As a result, the non-inverting output terminal Q of the RS flip-flop 510 becomes active H in synchronization with the rising edge of the edge pulse EP1, and becomes inactive L in synchronization with the rising edge of the non-return zero data NRZIDATA. The output pulse at the non-inverting output terminal Q of the RS flip-flop 510 is supplied to the clock input terminal CK of the D-type flip-flop 512 and is divided by two.

  If the output pulse at the non-inverting output terminal Q of the RS flip-flop 510 is the reset signal RS, the reset pulse RP is defined at the rising edge. If the output pulse at the inverting output terminal xQ of the RS flip-flop 510 is the reset signal RS, the reset pulse RP is defined at the falling edge. If the output pulse at the non-inverting output terminal Q or the inverting output terminal xQ of the D-type flip-flop 512 is the reset signal RS, the reset pulse RP is defined at both edges. Therefore, when the system configuration is such that the reset pulse RP is defined by one edge of the reset signal RS, the D-type flip-flop 512 is not necessary.

  The transmission signal generation unit 500 includes a 4-input OR gate 520 and a D-type flip-flop 522 in order to generate the edge signal ES. Edge pulses EP1 to EP5 are supplied to the input terminals of the OR gate 520. The output terminal of the OR gate 520 is connected to the clock input terminal CK of the D-type flip-flop 522. The inverting output terminal xQ of the D-type flip-flop 522 is connected to the D input terminal so that a 1/2 frequency dividing circuit is configured.

  By doing so, the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 522 change in order of L and H in synchronization with any rising edge of the edge pulses EP2 to EP5. Therefore, if the output pulse at the non-inverting output terminal Q and the inverting output terminal xQ of the D-type flip-flop 522 is the edge signal ES, the edge pulse EP is defined at both edges.

[Optical pickup side configuration]
7 to 7D are diagrams illustrating the configuration on the optical pickup 14 side that realizes the sequential method. Here, FIG. 7 is a diagram showing a laser drive circuit (particularly corresponding to the drive current control unit 47 in FIG. 1A) that realizes the sequential method. FIG. 7A is a diagram for explaining a relationship between stored information of a memory circuit (light emission level pattern storage unit) used in the sequential type laser driving circuit 200 and a current switch. 7B and 7C are timing charts for explaining the operation of the sequential laser driving circuit 200. FIG. FIG. 7D is a diagram showing register setting information of the memory circuit corresponding to the recording waveform control signal patterns shown in FIGS. 7B and 7C.

  As shown in FIG. 7, the laser driving circuit 200 according to the present embodiment includes a pulse reproduction unit 202 including a reset pulse generation unit 210 and an edge pulse generation unit 220, a light emission level pattern storage unit 230, a current source unit 240, and a current switch unit. 250 and a laser driver 270. In the laser driving circuit 200, a portion excluding the laser driving unit 270 is a light emission waveform generating unit 203. The reset pulse generator 210 is an example of a first pulse generator, and the edge pulse generator 220 is an example of a second pulse generator.

  The pulse regeneration unit 202 generates (reproduces) the reset pulse RP and the edge pulse EP using the reset signal RS as the first transmission signal and the edge signal ES as the second transmission signal. For example, the reset pulse generator 210 generates the reset pulse RP based on the reset signal RS. The edge pulse generator 220 generates an edge pulse EP based on the edge signal ES. That is, the generation timing of the reset pulse RP is synchronized with the edge of the reset signal RS, and the generation timing of the edge pulse EP is synchronized with the edge of the edge signal ES. Here, it is assumed that both the reset pulse RP and the edge pulse EP are active H pulse signals.

  The reset pulse generation unit 210 includes an edge detection circuit 212 which is an example of a first edge detection unit. The edge pulse generation unit 220 includes an edge detection circuit 222 which is an example of a second edge detection unit. As the edge detection circuits 212 and 222, for example, a known circuit such as a NAND (or AND) gate, a NOR (or OR) gate circuit, a gate circuit such as an inverter or an EX-OR gate may be used.

  For example, when a non-inverted logic gate is used as a delay element and the input pulse signal and the output of the delay element are input to the EX-OR gate, both edges can be detected with active H. When an inverting logic gate is used as a delay element, when the input pulse signal and the output of the delay element are input to the AND gate, the rising edge can be detected with active H, and when the input pulse signal is input to the NOR gate, the falling edge can be detected with active H. .

  Here, the reset pulse generation unit 210 generates a reset pulse RP by detecting either the rising edge or the falling edge (here, the rising edge) of the input reset signal RS by the edge detection circuit 212. The emission level pattern storage unit 230 is supplied (a corresponding timing chart is shown in FIG. 7B). As a modification, the reset pulse RP may be generated by detecting both rising and falling edges of the reset signal (a corresponding timing chart is shown in FIG. 7C).

  The edge pulse generation unit 220 detects both rising and falling edges of the input edge signal ES by the edge detection circuit 222, generates an edge pulse EP, and supplies it to the light emission level pattern storage unit 230. One reset pulse RP may be generated per one cycle of space and mark, but a plurality of edge pulses EP need to be generated. Therefore, by generating edge pulses EP from both edges of the edge signal ES, The frequency of the edge signal ES is kept low.

  The light emission level pattern storage unit 230 stores power level information (recording waveform control signal pattern) of laser emission at each timing when the write strategy technique is applied. For example, the light emission level pattern storage unit 230 includes a plurality of registers 232_1 to 232_k (collectively referred to as a register set 231) and read switches 234_1 to 234_k provided at the outputs of the registers 232_1 to 232_k.

  The register set 231 functions as a main storage unit. The output lines of the registers 232_1 to 232_k and the corresponding read switches 234_1 to 234_k are a plurality that can set a multi-value level of laser power when the write strategy technique is applied. The number of multilevel levels and the number of output lines of the registers 232_1 to 232_k and the read switches 234_1 to 234_k may be the same, or may be different by using a decoder. In the present embodiment, it is assumed that the number of multi-value levels is the same as the number of output lines of the registers 232_1 to 232_k and the read switches 234_1 to 234_k.

  The light emission level pattern storage unit 230 of the present embodiment defines the information of each light emission power level and the switching mode of the current switch unit 250 corresponding to the initial level of the recording waveform control signal pattern according to the recording waveform control signal pattern. Information is sequentially stored in the registers 232_1 to 232_k. An example of the recording waveform control signal pattern will be described later.

  The reset pulse RP is supplied from the reset pulse generator 210 to the control input terminal of the first-stage read switch 234_1 connected to the first-stage register 232_1 that holds the initial level information. The edge pulse EP is commonly supplied from the edge pulse generator 220 to the control input terminals of the read switches 234_2,..., 234_k connected to the registers 232_2,. Read switches 234_2,..., 234_k are sequential switches that sequentially select the outputs of the registers 232_2,.

  In the recording mode, the light emission level pattern storage unit 230 turns on / off each current switch of the current switch unit 250 based on the reset pulse RP, the edge pulse EP, and the power level information stored in the register 232. Outputs the current switching pulse SW. Specifically, the light emission level pattern storage unit 230 uses the power level information (particularly, the current switching pulse SW for controlling the current switch unit 250 in this example) stored in the registers 232_2,. Read in order. Then, it returns to reading of the register 232_1 storing the initial level information at the timing of the reset pulse RP.

  The current source unit 240 includes a reference current generation unit 242 and a current output type DA conversion unit 244 (IDAC). The reference current generator 242 outputs digital reference current values corresponding to each power level of the multi-value in the recording mode and the read in the reproduction (reading) mode in the emission pulse waveform of the semiconductor laser 41 as the emission level pattern. Generated based on information in the storage unit 230. For example, current information corresponding to each light emission power level is set as multi-bit digital data in the light emission level pattern storage unit 230, and each reference current generation unit 242 corresponding to each light emission power level captures the current information. Each reference current generator 242 performs offset setting and gain adjustment as necessary.

  The DA converter 244 converts the current information (digital data) generated by the reference current generator 242 to analog and outputs the analog information. Here, each DA converter 244 is supplied with a laser power command voltage PW from the APC controller 58 via the flexible substrate 51. Each DA converter 244 adjusts the gain of DA conversion based on the laser power instruction voltage PW. Thereby, the light emission power of the semiconductor laser 41 is feedback-controlled to a constant value corresponding to the laser power instruction voltage PW.

  In the recording mode, the current switch unit 250 sets the current switch 252 (Current SW) to any one or any combination (superimposition) of each power reference current converted into an analog signal by the DA conversion unit 244. I have. The current switch unit 250 controls the light emission power by turning on / off the current switch 252 based on a plurality of level information (specifically, the current switching pulse SW) read from the light emission level pattern storage unit 230.

  In this example, four levels of cool, erase, peak, and overdrive are used as multilevel levels in the recording mode (see FIGS. 7A and 7B). reference). Correspondingly, the reference current generator 242 includes separate reference current generators 242C, 242E, 242P, and 242OD that generate four levels of reference currents, and a read reference current generator 242R. . The DA converter 244 includes DA converters 244C, 244E, 244P, 244OD, and 244R in order to convert each reference current generated by the reference current generator 242 into an analog signal. The current switch 252 also includes 252C, 252E, 252P, 252OD, and 252R, respectively.

  As shown in FIG. 7A (1), each reference current generated by the reference current generation unit 242 includes different Ic, Ie, Ip, Iod corresponding to each of the four values of cool, erase, peak, and overdrive. It may be. Further, as shown in FIG. 7A (2), the cool current Ic, the erase current Ie, the peak current Ip, and the overdrive current Iod, and the difference information (Ie−Ic) in which the increments are sequentially added. , Ip-Ie, Iod-Ip). Which one of the current switches 252 of the current switch unit 250 is turned on depends on which one is selected, and the output pattern information of the current switching pulse SW that controls the current switch 252 depends on the adopted configuration. It is stored in the pattern storage unit 230.

  7A (1) and (2), in the recording mode, four types of current switching pulses SW_1 to SW_4 are output from each register 232 of the light emission level pattern storage unit 230 in order to control the quaternary level. Is done.

  In the example shown in FIG. 7A (1), the reference currents Ic, Ie, Ip, and Iod are supplied to the corresponding current switches 252C, 252E, 252P, and 252OD separately for cool, erase, peak, and overdrive. Therefore, one current switch 252 may be turned on by activating any one of the four types of current switching pulses SW_1 to SW_4. In this case, it is considered that the influence of the shift in the switching timing of the current switch 252 is less than that in FIG. 7A (2). On the other hand, since each reference current generator 242 needs to generate a reference current separately, the amount of current generated by the reference current generators 242P and 242OD for the peak current Ip and the overdrive current Iod is particularly large.

  In the example shown in FIG. 7A (2), since current addition is used, the current switch 252 that is turned on by increasing the number of combinations of the current switching pulses SW_1 to SW_4 to be activated in the order of cool, erase, peak, and overdrive. Will increase. In this case, since the timing of current addition depends on the switching timing of the addition current switch 252, the influence of “deviation” is considered to be greater than that in FIG. 7A (1). On the other hand, the amount of current generated by each reference current generator 242 is small.

  The laser driving unit 270 includes a laser switching circuit 272 and a driver circuit 274. As an example of the laser switching circuit 272, three inputs -1 for switching three systems of a first semiconductor laser 41_1 for a CD system, a second semiconductor laser 41_2 for a DVD system, and a third semiconductor laser 41_3 for a next generation DVD system. It has an output type switch. The driver circuit 274 includes a first driver circuit 274_1 that drives the first semiconductor laser 41_1, a second driver circuit 274_2 that drives the second semiconductor laser 41_2, and a third driver circuit 274_3 that drives the third semiconductor laser 41_3. Each of the driver circuits 274_1 to 274_3 increases or decreases the power according to the laser power instruction voltage supplied from the APC control unit 58 with respect to the input current signal having the recording waveform control signal pattern to generate a drive current. As a result, the semiconductor laser 41 emits light. The laser driver 270 corresponds to semiconductor lasers 41_1, 41_2, and 41_3 for three types of recording media, CD, DVD, and next-generation DVD, and switches the semiconductor laser 41 depending on the recording medium.

  With such a configuration, the laser drive circuit 200 generates a multi-valued power emission waveform to which the write strategy technique is applied by a combination of a bias current for supplying a threshold current of the semiconductor laser 41 and a plurality of current pulses. Yes. In a laser power control system (APC control system) (not shown), the multi-value power is controlled so that the laser power of the semiconductor laser 41 becomes a light emission waveform of this multi-value power.

[Operation]
As shown in FIGS. 7B and 7C, the data input for writing is assumed to be non-return zero data NRZIDATA. The space length is 2T, and the mark length is 2T or more (2T, 3T, 4T, and 5T are illustrated in the figure). The maximum speed signal is 2T repetition.

  When the write strategy technique is applied, in this example, in each space length 2T, the cool level (Cool) is set at 1T in the first half, and the erase level (Erase) is set at 1T in the second half. When the mark length is 2T, the erase level is set to 1T in the first half, and the overdrive level is set to 1T in the second half. When the mark length is 3T, the erase level is set at the first 1T, the overdrive level (O.D.) is set at the second 1T, and the peak level (Peak) is set at the third 1T.

  When the mark length is 4T, the erase level is set at the first 1T, the overdrive level is set at the second 1T, the peak level is set at the third 1T, and the overdrive level is set at the fourth 1T. When the mark length is 5T, the erase level is set for the first 1T, the overdrive level is set for the second 1T, the peak level is set for the third 1T, the peak level is set for the fourth 1T, and the overdrive level is set for the first 1T. That is, when the mark length is 5T, the peak level is maintained at the 3rd to 4th 2T, and the transition is made to the overdrive level at the 5th 1T thereafter.

  Regardless of the mark length, the erase level is maintained at 2T from the second half of the space to the first mark, and transitions to the overdrive level at 1T thereafter. Each emission power level has a relationship of O.D.> Peak> Erase> Cool.

  Corresponding to such a recording waveform control signal pattern, cool level information is stored as an initial level in the first-stage register 232_1 as shown in FIG. 7D. Erase level is stored in the second register 232_2, overdrive level is stored in the third register 232_2, peak level is stored in the fourth register 232_2, and overdrive information is stored in the fifth register 232_5. To do.

  One reset signal RS and one edge signal ES are used as input pulse signals. A reset pulse RP is generated based on a rising edge or a rising edge and a falling edge of one reset signal RS. An edge pulse EP is generated based on both edges of one edge signal ES. And each power level information memorize | stored in each register | resistor 232_1-232_5 of the light emission level pattern memory | storage part 230 is read in order from a head area (this example is cool).

  For example, when the reset pulse RP is active H, the read switch 234_1 is turned on to read the power level information of the first-stage register 232_1. Thereafter, every time the edge pulse EP becomes active H, the read switches 234_2 to 234_5 having the sequential switch configuration are sequentially turned on to read the power level information of the registers 232_2 to 232_5 in order.

  For example, when recording at a mark length of 4T or a mark length of 5T, if all the power level information is read in order, the laser emission power is switched in the order of cool → erase → overdrive → peak → overdrive.

  Depending on the mark length of the non-return zero data NRZIDATA, all levels are not output. For example, when recording with a mark length of 2T, it is necessary to transition the power from overdrive to cool. In this case, by supplying a reset signal RS so that the reset pulse RP becomes active H at a timing immediately after overdrive to be cool, cool information is read after overdrive. Similarly, at the time of recording with a mark length of 3T, the reset signal RS may be supplied so that the reset pulse RP becomes active H at the timing immediately after the peak to be cooled so that the power transitions from the peak to cool.

  In the description of the sequential method so far, the reset signal RS and the edge signal ES are both one, but a detailed description with illustration is omitted, but various modifications are possible.

  For example, the first transmission signal (reset signal RS) and the second transmission signal (edge signal ES) can each be plural. For example, by transmitting a plurality of second transmission signals (edge signals ES) including information defining the acquisition timing of the switching pulse, the problem of the transmission band can be solved more easily.

  Further, as the first transmission signal, it is assumed that the acquisition timing of the reference pulse indicating the switching timing of the space and mark repetition is not indicated by an edge, and the reference pulse of the reference pulse is indicated by the second transmission signal (edge signal ES). A method for defining the acquisition timing may be used. In this case, the first transmission signal (reset signal RS) is used as a determination signal for distinguishing and acquiring the reset pulse RP and the edge pulse EP from the edge of the edge signal ES. For example, the reset pulse RP is generated in synchronization with the edge timing of the edge pulse EP, and the edge pulse EP is generated at a timing that does not contribute to the generation of the reset pulse RP of both edges of the edge signal ES. By doing so, not only the edge signal ES but also the generation timing of the reset pulse RP is generated in synchronization with the edge of the edge signal ES, so that the influence of skew is eliminated.

  Further, if a plurality of first transmission signals (reset signals RS) are used and the respective reset timings are different, a function for switching a plurality of types of power level patterns can be realized. For example, it is suitable for application to changing the peak level or overdrive level according to the mark length.

  An m-input-n-output (denoted as mn: m, n is a positive integer and m <n) type decoder is arranged between the light emission level pattern storage unit 230 and the readout switch 234, so The number of multilevel levels may be different from the number of output lines of the register 232 and the number of read switches 234. In this case, since a decoder is necessary, the circuit configuration is slightly complicated. However, since the amount of information stored in the register 232 is reduced, the storage capacity of the register set 231 can be reduced, and the circuit of the light emission level pattern storage unit 230 can be reduced. The scale can be reduced.

  When the light emission power information of the register 232 is the current level information itself, and this is sequentially switched and supplied to the current source unit 240, the current source unit 240 has one simple reference current generation unit 242 and one DA conversion unit 244, respectively. In addition, the current switch unit 250 is not necessary. Further, if each current level information in the register 232 is matched with each current value Ic, Ie, Ip, Iod, the reference current generating unit 242 is also unnecessary. However, DA conversion requires a plurality of pieces of information to represent one level power, and the analog current values (a plurality of SWs in the DAC) are controlled by the plurality of pieces of digital information (bit data). If there is a timing skew, the waveform characteristics may deteriorate.

It is a figure which shows one structural example of the recording / reproducing apparatus (optical disc apparatus) which is an example of an optical apparatus. It is a figure explaining the structural example of an optical pick-up. It is a figure explaining an example of the laser drive system to which the write strategy technique is applied. It is a figure explaining the 1st comparative example of the signal interface method at the time of driving a semiconductor laser by applying a write strategy technique. It is a figure explaining the 2nd comparative example of the signal interface method at the time of driving a semiconductor laser by applying a write strategy technique. It is a figure explaining the 3rd comparative example of the signal interface method at the time of applying a write strategy technique and driving a semiconductor laser. It is a figure (1st example: normal system base) which shows the system configuration which realizes the signal interface system of this embodiment. It is a figure (2nd example: Sequential system base) which shows the system configuration which implement | achieves the signal interface system of this embodiment. It is a figure explaining the 1st setting example (for marks) of a sampling pulse. It is a figure explaining the 2nd setting example (for marks) of a sampling pulse. It is a figure explaining the 3rd setting example (for space) of a sampling pulse. It is a figure explaining the 4th example of setting (for space) of a sampling pulse. It is a figure explaining the detail of the signal interface system which employ | adopts a sequential system for a recording system. It is a figure explaining the structural example of the transmission signal generation part used in order to implement | achieve the sequential system with which the digital signal processing part by the side of a drive board is equipped. It is a figure which shows the laser drive circuit which implement | achieves a sequential system. It is a figure explaining the relationship between the memory information of the memory circuit (light emission level pattern memory | storage part) used for a sequential system laser drive circuit, and a current switch. 6 is a timing chart (first example) for explaining the operation of a sequential laser driving circuit. It is a timing chart (2nd example) explaining operation | movement of the laser drive circuit of a sequential system. 7B is a diagram showing register setting information of the memory circuit corresponding to the recording waveform control signal pattern shown in FIGS. 7B and 7C. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Recording / reproducing apparatus, 10 ... Spindle motor, 12 ... Motor driver, 14 ... Optical pick-up, 200 ... Laser drive circuit, 202 ... Pulse reproduction part, 203 ... Light emission waveform generation part, 210 ... Reset pulse generation part, 220 ... Edge Pulse generation unit 230 ... Light emission level pattern storage unit 240 ... Current source unit 270 ... Laser drive unit 290 ... Write strategy circuit 30 ... Spindle motor control unit 300 ... Power monitor circuit 310 ... Light receiving element 312 ... Current voltage conversion unit, 313 ... Current voltage conversion unit, 32 ... Pickup control unit, 330 ... Sample hold unit, 400 ... Sampling pulse generation unit, 41 ... Semiconductor laser, 45 ... Photodetection unit, 47 ... Drive current control unit, 50 ... Recording / reproduction signal processing unit, 500 ... transmission signal generation unit, 51 ... flexible substrate, 52 RF amplifying section 53 ... waveform shaping unit, 54 ... AD conversion unit, 55 ... clock recovery unit, 56 ... write clock generator, 57 ... digital signal processing unit, 58 ... APC control unit, 62 ... controller

Claims (9)

A laser element;
A drive unit for driving the laser element;
An optical member for guiding laser light emitted from the laser element;
A light emission waveform pulse generation unit that generates a plurality of pulse signals that define a light emission waveform composed of a combination of drive signals divided into a plurality of spaces and marks based on a recording clock and recording data;
A light emission waveform generation unit that generates the light emission waveform and supplies the light emission waveform to the drive unit;
A photoelectric conversion unit that converts laser light emitted from the laser element into an electrical signal;
A sample and hold unit that samples and holds the electrical signal obtained by the photoelectric conversion unit;
A sampling pulse generator for sampling and holding the electrical signal to generate a sampling pulse based on an edge of the light emission waveform and supplying the sampling pulse to the sample hold unit;
An APC control unit that generates a laser power instruction signal for setting the power level of the laser light to an appropriate level based on the sample hold signal obtained by the sample hold unit, and supplies the laser power instruction signal to the emission waveform generation unit;
The laser element, the drive unit, the optical member, the light emission waveform generation unit, the photoelectric conversion unit, the sample hold unit, the sampling pulse generation unit, the light emission waveform pulse generation unit, and the APC control A transmission member for transmitting a signal interposed between a portion mounted with a portion;
Optical device with The optical device according to claim 1, wherein the sampling pulse generation unit generates the sampling pulse based on a plurality of pulse signals generated by the light emission waveform pulse generation unit. Based on a plurality of pulse signals generated by the light emission waveform pulse generation unit, a first transmission signal including information defining the acquisition timing of a reference pulse indicating the switching timing of the space and the mark, and A transmission signal generation unit that generates a second transmission signal including information defining acquisition timing of a switching pulse indicating switching timing of the divided drive signal;
A pulse regeneration unit that regenerates the reference pulse and the switching pulse based on the first transmission signal and the second transmission signal and supplies the reference pulse and the switching pulse to the emission waveform generation unit and the sampling pulse generation unit;
Further comprising
The transmission signal generation unit is disposed between the transmission member and the light emission waveform pulse generation unit,
The pulse regeneration unit is disposed between the transmission member, the light emission waveform generation unit and the sampling pulse generation unit,
The optical device according to claim 1, wherein the light emission waveform generation unit generates the light emission waveform based on the reference pulse and the switching pulse. The sampling pulse generation unit, each sampling pulse corresponding to each position of the mark and the space in the electrical signal, a delay time starting from a reference edge forming each of the mark and the space in the emission waveform, The optical device according to claim 1, wherein the optical device is generated based on a pulse width and a delay time for delay compensation from the sampling pulse generation unit to the sample hold unit. The sampling pulse generation unit, each sampling pulse corresponding to each position of the mark and the space in the electrical signal, a delay time starting from a reference edge forming each of the mark and the space in the emission waveform, And generating based on a set value that defines an end point of each sampling pulse starting from an edge different from the reference edge, and a delay time for delay compensation from the sampling pulse generation unit to the sample hold unit. The optical device according to any one of 1 to 3. The sampling pulse generator is
When the length of the mark is shorter than a predetermined setting value, the sampling pulse for the mark is not generated.
And / or
The optical device according to claim 4 or 5, wherein when the length of the space is shorter than a predetermined set value, the sampling pulse for the space is not generated. A laser element;
A drive unit for driving the laser element;
An optical member for guiding laser light emitted from the laser element;
A light emission waveform generation unit that generates a light emission waveform and supplies the light emission waveform to the driving unit;
A photoelectric conversion unit that converts laser light emitted from the laser element into an electrical signal;
A sample and hold unit that samples and holds the electrical signal obtained by the photoelectric conversion unit;
A sampling pulse generator for sampling and holding the electrical signal to generate a sampling pulse based on an edge of the light emission waveform and supplying the sampling pulse to the sample hold unit;
With
Based on the recording clock and recording data, a signal that defines a light emission waveform consisting of a combination of drive signals divided into a plurality of spaces and marks is taken in from the outside.
An optical unit that outputs a sample hold signal obtained by the sample hold unit to the outside. An input terminal to which a signal defining a light emission waveform composed of a combination of drive signals divided into a plurality of spaces and marks is input;
A sampling pulse generator for generating a sampling pulse for sampling and holding an electric signal with reference to an edge of the light emission waveform; and
Based on a signal that defines the light emission waveform pattern, a light emission waveform generation unit that generates the light emission waveform;
Based on the emission waveform generated by the emission waveform generation unit, a drive unit that drives a laser element;
A laser drive device comprising: The first transmission signal including information defining the acquisition timing of the reference pulse indicating the switching timing of the space and the mark, and the acquisition timing of the switching pulse indicating the switching timing of the divided drive signal. A pulse generation unit for reproducing the reference pulse and the switching pulse based on a second transmission signal including information to be defined;
The laser driving device according to claim 8, wherein the light emission waveform generation unit generates the light emission waveform based on the reference pulse and the switching pulse.

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