JP2010057019A - Imaging element, and imaging apparatus - Google Patents

Abstract

An image pickup device and an image pickup apparatus that suppress a circuit operation band during horizontal transfer and reduce power consumption are provided.
A column A / D circuit 150 has a horizontal adder 153 for horizontal reading. The horizontal adder 153 is disposed between two adjacent columns (vertical direction) of column A / D circuits 150, and outputs an adder 11 that is a 1-bit full adder and a carry bit according to a clock signal. The flip-flop 12 and the selector 13 that switches the connection to the data storage unit 152 according to the MSB control signal from the timing control unit 140 are included. The adder 11 reads and adds the digital image signal bit by bit from the LSB side of the data storage unit 152 of the column A / D circuit 150 of two adjacent columns, and stores it in the data storage unit 152 on the MSB side of one column. Let
[Selection] Figure 2

Description

  The present invention relates to an imaging device and an imaging apparatus that digitize and output an analog image signal output from a pixel such as a CMOS image sensor.

  Conventionally, a CMOS (Complementary Metal-Oxide Semiconductor) sensor, which is a solid-state imaging device, performs image signal processing using a CDS (Correlated Double Sampling) circuit.

  For example, in Patent Documents 1 and 2, after a light reception signal from a photodiode in a pixel is passed through an analog CDS circuit arranged for each column of pixels, noise contained in an image signal is removed, and then A / A CMOS sensor that performs D (Analog / Digital) conversion is disclosed.

  However, when the CDS circuit is used in this way, there is a problem that noise in a streaky fixed pattern is generated due to variations in the CDS circuit for each column of pixels. In addition, since a capacitance element for holding the signal value after CDS processing is required, there is a problem that the circuit area increases, and in order to horizontally scan (transfer) an analog signal at high speed by a shift register, switching noise and the like There was also the problem of being easily affected.

  Therefore, for example, Patent Document 3 proposes to solve these problems by a column parallel A / D conversion method (hereinafter referred to as a column A / D method).

In the column A / D method, an A / D converter is provided for each pixel column (vertical direction, readout direction), and the analog image signal of each pixel is read collectively to each vertical signal line for the selected column. The A / D conversion is performed directly. For this reason, the problem which arises when the above-mentioned CDS circuit is used is solved, and highly accurate noise removal can be executed.
Then, the A / D converted digital signal is stored in the data storage unit for each column, read out for each row (horizontal direction, transfer direction) through the horizontal signal line, and subjected to signal processing to output image data.

Japanese Patent No. 3734717 Japanese Patent No. 3710361 JP-A-2005-328135

In the above-described column A / D type CMOS sensor, it is necessary to perform, for example, digital addition as signal processing after reading in the horizontal direction (transfer direction).
In this case, a multi-bit digital adder is required.
Providing a multi-bit adder logic dedicated to horizontal transfer has the disadvantage that the circuit scale of the CMOS sensor increases and the chip cost increases.
Even in the case of horizontal addition, since it is necessary to perform horizontal transfer for all columns, the transfer rate is not improved and the frame rate cannot be increased. Furthermore, since it is necessary to operate the amplifier (amplifier) after horizontal transfer in a high band, there is a disadvantage that the power consumption of the entire circuit is not suppressed.

  The present invention provides an imaging device and an imaging apparatus that suppress a circuit operation band during horizontal transfer and suppress power consumption.

  In order to achieve the above-described object, the imaging device according to the first aspect includes a plurality of pixels that are two-dimensionally arranged in a matrix form that photoelectrically converts incident light and outputs generated charges as analog image signals. A pixel unit, a readout signal line wired for each of the plurality of pixels and connected in common to the pixels in one column, and the pixel unit connected to the readout signal line via the readout signal line A column A / D circuit for A / D (analog / digital) conversion and storing the analog image signal output from the signal, and a transfer signal line for transferring the signal stored in the column A / D circuit. The column A / D circuit includes a comparator that performs A / D conversion by comparing an analog image signal input from the pixel unit with a reference signal, and a digital image that is A / D converted by the comparator. Remember signal It has a plurality of data storage unit, the digital image signal stored in the data storage unit of the plurality of rows, an adder for adding the forward direction.

  According to the image pickup device of the first aspect, in the column A / D type image pickup device, digital image signals stored in a plurality of columns of column A / D circuits can be horizontally added.

  According to the imaging device of the second aspect, the imaging device includes an imaging device having a plurality of pixels, and an optical system that forms an image of light from a subject on the pixels of the imaging device. A plurality of pixels in which the generated light is photoelectrically converted and the generated charges are output as analog image signals in a two-dimensional array, and the plurality of pixels are wired for each column. A readout signal line connected in common to the pixels and an analog image signal connected to the readout signal line and output from the pixel portion via the readout signal line are subjected to A / D (analog / digital) conversion. A column A / D circuit for storing, and a transfer signal line for reading out the signal stored in the column A / D circuit, and the column A / D circuit receives an analog image signal input from the pixel unit. Compare with the reference signal A comparator for A / D conversion, a plurality of data storage units for storing digital image signals A / D converted by the comparator, and the digital image signals stored in a plurality of columns of the data storage units. And an adder for adding in the transfer direction.

  According to the present invention, it is possible to suppress a circuit operation band at the time of horizontal transfer and suppress power consumption.

The CMOS image sensor 100 according to the embodiment of the present invention will be described below.
FIG. 1 is a block diagram illustrating a configuration example of a CMOS image sensor 100 according to an embodiment of the present invention.
A CMOS image sensor 100 shown in FIG. 1 is a solid-state imaging device (column A / D system) equipped with a column parallel A / D converter.

A CMOS image sensor 100 shown in FIG. 1 includes a pixel unit 110 as an imaging unit, a vertical scanning circuit 120, a horizontal scanning circuit 130, and a timing control unit 140.
Further, the CMOS image sensor 100 includes a column A / D circuit 150, a reference signal generation circuit (digital-analog conversion device) 160, a counter 170, and a signal processing circuit 190.

The pixel unit 110 is configured by arranging pixels including photodiodes and in-pixel amplifiers in a matrix (matrix) as shown in FIG. 1, for example.
The pixel unit 110 photoelectrically converts a video or a screen image for each pixel by photon accumulation / discharge using a line shutter, and sequentially outputs an analog output signal (hereinafter referred to as an image signal) VSL generated by each pixel.
In order to sequentially read out analog image signals output from the pixel unit 110, a timing control unit 140 that generates an internal clock, a vertical scanning circuit 120, and a horizontal scanning circuit 130 are arranged.
The timing control unit 140 is a timing required for signal processing of the pixel unit 110, the vertical scanning circuit 120, the horizontal scanning circuit 130, the data storage unit (column A / D conversion circuit) 150, the reference signal generation circuit 160, and the signal processing circuit 190. Generate a signal.

The column A / D circuit 150 reads an analog image signal from the pixel unit 110 and stores it.
The column A / D circuit 150 includes a plurality of column A / D circuits 150-1 to 150-k (k is a positive integer corresponding to the number of pixel columns) arranged for each pixel column (for each vertical signal line 121). Have.
Note that the vertical signal line 121 corresponds to the read signal line of the present invention.
As shown in FIG. 1, the column A / D circuit 150 (each column A / D circuit 150-1 to 150-n) reads an analog image signal from the pixel unit 110 for each column, and performs A / D (Analog / Digital) Convert and store.
The column A / D circuit 150 has a function of converting an analog image signal read from the pixel unit 110 into an APGA-compatible integral A / D (Analog-Digital) conversion using a ramp signal from a reference signal generation circuit 160 described later. The column A / D circuit 150 further has a digital CDS (Correlated Double Sampling) function, and outputs a digital signal of several bits.

The reference signal generation circuit 160 is a digital-analog converter, generates a reference signal (ramp signal) for A / D conversion in accordance with a clock signal and a control signal of the timing control unit 140, and a column A / D circuit 150.
The details of the reference signal generation method in the reference signal generation circuit 160 are not described in this embodiment. An existing technique can be used as a reference signal generation method.

The horizontal scanning circuit 130 controls reading in the horizontal direction (transfer direction, row direction) in parallel with several channels in order to ensure the transfer speed.
In the timing control unit 140, timing necessary for signal processing in each block such as the pixel unit 110, the vertical scanning circuit 120, the horizontal scanning circuit 130, the column A / D circuit 150, the counter 170, and the like is created.
The counter 170 is a counter for generating a digital image signal to be stored in the column A / D circuit 150 and counts a clock signal generated by the timing control unit 140.
The signal processing circuit 190 performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation on the digital image signal read out from the horizontal signal line 131, thereby obtaining two-dimensional image data. Is generated.
The horizontal signal line 131 corresponds to the transfer signal line of the present invention.

Details of the column A / D circuit 150 will be described below.
FIG. 2 shows details of the configuration of specific columns (for example, the n-th column and the (n + 1) -th column) of the column A / D circuit 150 in the CMOS image sensor 100 of the present embodiment and the peripheral blocks.
FIG. 2 is a diagram illustrating a relationship between a specific configuration of the column A / D circuit 150 and other configurations.
As shown in FIG. 2, the column A / D circuit 150 includes a comparator 151, a data storage unit 152, and a horizontal adder 153.
As described above, the column A / D circuit 150 includes 1 to k k column A / D circuits 150-1 to 150-k, each of which includes the configuration described above, the comparator 151, the data storage unit 152, A horizontal adder 153 is included.

The comparator 151 compares the voltage of the reference signal generated by the reference signal generation circuit 160 with the potential of the analog image signal obtained from the pixel of the pixel unit 110 via the vertical signal line 121.
The comparison time in the comparator 151 is counted by the counter 170.
During the operation of the comparator 151, the counter 170 operates simultaneously, and the potential of the vertical signal line 121 is converted into a digital signal by changing the voltage of the reference signal and the counter value while taking a one-to-one correspondence. That is, the analog image signal output from the pixel unit 110 is converted into a digital signal by the comparator 151.

The data storage unit 152 stores the digital image signal that has been A / D converted by the comparator 151.
The data storage unit 152 is a multi-bit data storage circuit, and includes data storage units 152-1 to 152-1 to m that store every bit (m is a positive integer corresponding to the number of bits).
In the present embodiment, the data storage unit on the LSB (Least Significant Bit) side is 152-1 and the data storage unit on the MSB (Most Significant Bit) side is 152-m.

The horizontal adder 153 reads out the digital image signal stored in the data storage unit 152 of the two adjacent column A / D circuits 150 from the LSB side in accordance with the control signal and clock signal supplied from the timing control unit 140.
In the following, for example, consider column A / D circuits 150 of n columns and n + 1 columns.
The data storage unit 152 is configured to be able to change the operation mode in accordance with a mode control signal supplied from the timing control unit 140 via the addition mode signal line 141. The operation modes include, for example, a normal mode for storing digital image signals and an addition mode for horizontal addition by a horizontal adder.
In the addition mode, the data storage unit 152 outputs the data (digital image signal) on the LSB side to the horizontal adder 153 and then shifts the data bit by bit from the MSB side to the LSB side.

With the mechanism as described above, the digital image signal stored in the data storage unit 152 of the column A / D circuit 150 of n columns and n + 1 columns can be read out bit by bit from the LSB side in the horizontal adder 153.
The horizontal adder 153 receives the digital image signal in the horizontal direction read from the data storage unit 152 as described above from the LSB side according to the clock signal supplied from the timing control unit 140 via the addition clock signal line 142. Add sequentially.
Then, the horizontal adder 153 stores the addition result in the data storage units 152-1 to 152-m of the column A / D circuit 150 of the n columns.

In the CMOS image sensor 100 of the present embodiment, the digital image signal stored in the data storage unit 152 is added in the horizontal direction by the horizontal adder 153 in the column A / D circuit 150 of the adjacent column with the configuration as described above. can do.
Thereafter, the data storage unit 152 of the column A / D circuit 150 in each column can be read out horizontally by the horizontal scanning circuit 130 and signal processing can be performed by the signal processing circuit 190 to output image data.

A time chart at the time of horizontal addition by the horizontal adder 153 is shown in FIG.
FIG. 3 is a diagram showing a time chart when the horizontal adder 153 operates.
As shown in FIG. 3A, the timing controller 140 first sets the addition mode signal to the high level via the addition mode signal line 141.
In response to this, the data storage unit 152 enters the addition mode.
Next, when a clock signal is supplied to the horizontal adder 153 via the addition clock signal line 142, the horizontal adder 153 receives the digital image signal read from the LSB side of the data storage unit 152 according to the clock signal as 1. Add one bit at a time to the clock.
Therefore, the number of pulses of the clock signal is m.

In the column A / D circuit 150, it is possible to use the horizontal adder 153 and add the values in the horizontal direction and then take an average.
The horizontal adder 153 is the same as described above until the result of addition is stored in the data storage unit 152-m on the MSB side of the column A / D circuit 150 of the n columns.
Next, an MSB control signal is supplied from the timing control unit 140 via the MSB control signal line 143, and a clock signal is further input by one clock via the addition clock signal line 142. Then, the horizontal adder 153 inputs the carry bit (carry) to the data storage unit 152-m on the MSB side of the column A / D circuit 150 in the n columns.
As a result, the addition average value is stored in the data storage units 152-1 to 152-m of the column A / D circuit 150 of the n columns.

FIG. 3B shows a time chart at the time of horizontal addition average calculation by the horizontal adder 153.
As shown in FIG. 3B, the timing control unit 140 first sets the addition mode signal to the high level via the addition mode signal line 141.
In response to this, the data storage unit 152 enters the addition mode.
Next, when a clock signal is supplied to the horizontal adder 153 via the addition clock signal line 142, the horizontal adder 153 receives the digital image signal read from the LSB side of the data storage unit 152 according to the clock signal as 1. Add one bit at a time to the clock.
When the timing control unit 140 supplies a clock signal for m bits (m times the number of pulses), the timing control unit 140 supplies only one pulse of the MSB control signal via the MSB control signal line 143 and also supplies the clock signal for one clock.
As a result, the horizontal adder 153 inputs the carry bit to the data storage unit 152-m on the MSB side of the column A / D circuit 150 of the n columns, and the addition average value is stored.
Accordingly, the number of pulses of the clock signal in this case is m + 1.

Next, an example of the configuration of the horizontal adder 153 will be described.
FIG. 4 is a diagram showing an example of the configuration of the horizontal adder 153.
As shown in FIG. 4, the horizontal adder 153 includes an adder 11, a flip-flop 12, and a selector 13.
The adder 11 corresponds to the adder circuit of the present invention, and the flip-flop 12 corresponds to the flip-flop circuit of the present invention.
The adder 11 is connected to the input signal line 14 from the column A / D circuit 150 in the n columns and the input signal line 15 from the column A / D circuit 150 in the n + 1 columns.
The addition clock signal line 142 from the timing control unit 140 is connected to the flip-flop 12.
An MSB control signal line 143 from the timing control unit 140 is connected to the selector 13.

The adder 11 is a 1-bit full adder that adds a binary number having an arbitrary number of digits.
An input A of the adder 11 is a digital image signal from the input signal line 14 from the column A / D circuit 150 of n columns.
The input B of the adder 11 is a digital image signal from the input signal line 15 from the column A / D circuit 150 in the (n + 1) th column.
Carry input Cin is output from flip-flop 12.
Carry output Cout is input to flip-flop 12.

The carry bit from the adder 11 and the clock signal from the timing control unit 140 are input to the flip-flop 12. The flip-flop 12 holds or outputs the carry bit according to the clock signal.
That is, the flip-flop 12 outputs the input carry bit as an output value only when the clock signal changes from low level to high level. For other times, the previous output is retained.

The selector 13 receives the MSB control signal from the timing control unit 140, the output value from the adder 11 (added digital image signal), and the carry bit output value from the flip-flop 12.
The selector 13 switches signals to be input to the n columns of data storage units in accordance with the MSB control signal from the timing control unit 140.
That is, the selector 13 outputs the output value from the adder 11 when the MSB control signal from the timing control unit 140 is low level, and the carry bit output value from the flip-flop 12 when the MSB control signal becomes high level. Input to the column data storage.
The selector 13 is a switch unit that operates in accordance with an MSB control signal from the timing control unit 140, for example.

Details of the horizontal addition operation by the horizontal adder 153 will be described below.
5 to 9 are diagrams for explaining the details of the horizontal addition operation by the horizontal adder 153. FIG.
5 to 9, horizontal addition operations of the n column A / D circuits 150 and the (n + 1) column A / D circuits 150 will be described. 5 to 10, the case where each column A / D circuit 150 includes four data storage units 152-1 to 152-4 will be described for the sake of simplicity.

5 to 9, solid arrows indicate the movement of data before addition, and broken arrows indicate the movement of data after addition.
First, as shown in FIG. 5, the first bit of the digital image signal is transferred from each data storage unit 152-1 of the column A / D circuit 150 of n columns and n + 1 columns to the adder 11 of the horizontal adder 153. Transferred (solid arrow 1). In FIG. 5, numbers not surrounded by circles indicate pre-addition data of the bit number corresponding to the numbers.
Then, the stored digital image signals are shifted from the data storage units 152-2 to 152-4 to the data storage unit of one upper bit (solid arrows 2 to 4).
The adder 11 adds the first bit of the digital image signal transferred from the n-th column data storage unit 152-1 and the first bit of the digital image signal transferred from the n + 1-th column data storage unit 152-1. To do.
And it outputs from the output Y, transfers to the data storage part 152-4 of n columns, and memorizes it. In FIG. 5, the numbers surrounded by circles indicate the added data of the bit number corresponding to the numbers.
The carry bit is output from Cout and input to the flip-flop 12.
In FIG. 5, since the MSB control signal is not input from the timing control unit 140, the selector 13 connects the output Y of the adder 11 to the n-column data storage unit 152-4.

Next, as shown in FIG. 6, the digital image signal of the second bit before addition is input to the adder 11.
The adder 11 adds the second bits of the n-th column digital image signal and the n + 1-th column digital image signal, outputs the result from the output Y, and stores it in the n-column data storage unit 152-4.
The data storage unit 152 in each column transfers the corresponding bit of the stored digital image signal to the upper data storage unit.
The flip-flop 12 outputs the carry bit input from Cout of the adder 11 according to the input of the clock signal, and inputs the carry bit to Cin of the adder 11. The adder 11 adds the second bit of the digital image signal of n columns and the digital image signal of n + 1 columns using the input carry bit.

7 and 8 show the addition operation of the third bit and the fourth bit, as in FIG.
In FIG. 9, the data storage unit 152-1 on the LSB side of the column A / D circuit 150 of the n columns stores the first bit of the digital image signal of the data storage unit 152-1 of the n columns before addition and the data before the addition. Data obtained by adding the first bit of the data storage unit 152-1 in the (n + 1) th column is stored.
Similarly, the n-th column data storage unit 152-2 stores the added second bit data. The n-th column data storage unit 152-3 stores the added third bit data. The added fourth bit data is stored in the data storage unit 152-4 on the MSB side of the n columns.
In FIG. 9, the MSB control signal is input from the timing control unit 140 to the selector 13 in order to take the addition average, and the selector 13 converts the carry bit output from the flip-flop 12 into the n-column data storage unit 152-4. Connect to.
Thereafter, the data is output from the data storage unit 152 of each bit, and after the carry bit is stored in the data storage unit 152-4 on the MSB side, the carry bit is also output, thereby outputting the addition average.

  As shown in FIGS. 5 to 9, the data storage units 152-1 to 152-4 operate based on the clock signals supplied from the timing control unit 140, respectively. For example, it is a latch circuit composed of flip-flops.

As described above, according to the CMOS image sensor 100 of the present embodiment, the column A / D circuit 150 that stores and reads the analog image signal generated by the pixel unit 110 after A / D conversion is used for horizontal reading. Has a horizontal adder 153.
The horizontal adder 153 is disposed between two column A / D circuits 150 (vertical direction and readout direction) adjacent to each other, and adds the digital image signals stored in the data storage unit 152 of the two columns.
The horizontal adder 153 includes an adder 11 that is a 1-bit full adder, a flip-flop 12 that outputs a carry bit according to a clock signal, and a data storage unit 152 that receives an MSB control signal from the timing control unit 140. And a selector 13 for switching the connection.
Then, the adder 11 reads out and adds a digital image signal bit by bit from the LSB side of the data storage unit 152 of the column A / D circuit 150 of the two adjacent columns, and adds the data to the data storage unit 152 on the MSB side of one column. Remember me. Each bit of the data storage unit 152 shifts the stored digital image signal one bit higher each time an addition operation is performed by the horizontal adder 153. These addition operations are performed according to the clock signal supplied from the timing control unit 140.

Therefore, in the column A / D type CMOS image sensor, a dedicated multi-bit adder is not required at the time of horizontal addition, and the horizontal adder 153 is configured only by the adder 11 and the flip-flop 12 which are 1-bit full adders. It is possible. Note that the selector 13 is a component that is used only when taking the addition average, and is not counted as a necessary component here.
In addition, since the number of horizontal readings is reduced by horizontal addition, an increase in the frame rate can be expected.
Further, the horizontal addition can suppress the horizontal reading speed as compared with the case of reading all the pixels, so that the operating band of the horizontal scanning circuit 130 can be suppressed and the power consumption can be reduced.

  Furthermore, according to the CMOS image sensor 100 of the present embodiment, when the addition up to the MSB of the data storage unit 152 is completed, an addition average can be taken. That is, the selector 13 is switched in accordance with the MSB control signal from the timing control unit 140, and the carry bit is stored in the data storage unit 152 on the MSB side, so that the averaging can be performed.

The present invention is not limited to the above-described embodiments, and can be applied to various aspects.
Below, the modification of embodiment which concerns on this invention is demonstrated.
<Modification 1>
Modification 1 of the embodiment of the CMOS image sensor 100 will be described.
In the first modification, instead of counting the comparison time of the comparator 151 at the time of A / D conversion in the column A / D circuit 150 by the counter 170 as in the above-described embodiment, the column A / D circuit 150 in each column is used. Set up / down counter to count comparison time.
FIG. 10 shows a configuration diagram in the vicinity of the column A / D circuit 150 in the CMOS image sensor 100 of the first modification.
As shown in FIG. 10, the present invention can also be applied when an up / down counter 154 is installed in the column A / D circuit 150 of each row.

<Modification 2>
Modification 2 of the embodiment of the CMOS image sensor 100 will be described.
The configuration of the CMOS image sensor 100 in Modification 2 is the same as the description associated with FIGS. 1 and 2 in the above-described embodiment, and thus the description thereof is omitted.
In the embodiment described above, the case of performing horizontal addition of two adjacent columns (n column and n + 1 column) has been described, but in the second modification, four adjacent columns (for example, n column, n + 1 column, n + 2 column, n + 3) are described. A case of performing horizontal addition of (column) will be described.
11 and 12 are diagrams for explaining horizontal addition of four adjacent columns.
As shown in FIG. 11, the data storage unit 152 of the column A / D circuit 150 in the n columns and the data storage unit 152 of the column A / D circuit in the n + 1 columns are connected to the horizontal adder 153-1. Similarly, the data storage unit 152 of the n + 2 column A / D circuit 150 and the data storage unit 152 of the n + 3 column A / D circuit are connected to the horizontal adder 153-2.

As shown in FIGS. 11A to 11E, the digital image signal of the n column data storage unit 152 and the digital image signal of the n + 1 column data storage unit 152 are added by the horizontal adder 153-1 from the LSB side. And stored in the MSB side of the data storage unit 152 of n columns.
At the same time, the digital image signal of the n + 2 column data storage unit 152 and the digital image signal of the n + 3 column data storage unit 152 are added from the LSB side by the horizontal adder 153-1, and the MSB side of the n + 2 column data storage unit 152 is added. Is remembered.

After the digital image signals stored in the data storage unit 152 on the MSB side are added, the connection of the data storage unit 152 to the horizontal adders 152-1 and 152-2 is changed as shown in FIG. The
That is, as shown in FIG. 12A, the horizontal adder 153-1 is changed to connect the data storage units of n columns and n + 2 columns.
Then, as shown in FIGS. 12A to 12E, the digital image signals stored in the data storage units of the n columns and the n + 2 columns are added from the LSB side by the horizontal adder 153-1, and the n columns of data are added. The data are sequentially stored from the MSB side of the storage unit 152.
As a result, the digital image signals stored in the data storage unit 152 of the four columns of adjacent column A / D circuits 150 are added and stored in the data storage unit 152 of the column A / D circuit 150 of one column. Become.
By applying the second modification, it is also possible to add digital image signals in the data storage unit 152 of the column A / D circuit 150 having an arbitrary multiple of 2 columns.

<Modification 3>
A modification 3 of the embodiment of the CMOS image sensor 100 will be described.
The configuration of the CMOS image sensor 100 in Modification 3 is the same as the description associated with FIGS. 1 and 2 in the above-described embodiment, and thus the description thereof is omitted.
In the third modification, the pixel unit 110 has a Bayer array color filter.
As shown in FIG. 13, the Bayer array is an array in which the three primary colors RGB of light are alternately arranged. In the Bayer array, G (green) is arranged twice as large as R (red) and B (blue) in accordance with the visual characteristics of the human eye.

In the third modification, a case where the analog image signal for each color read from the pixel unit 110 in the Bayer array is stored in the data storage unit 152 of the column A / D circuit 150 in a different column for each color will be described.
FIG. 14 shows an example of the horizontal addition operation corresponding to the Bayer array.
FIG. 14 is a diagram for explaining the horizontal addition operation corresponding to the Bayer array.
In the example shown in FIG. 14A, R (red) digital image signals are stored in the data storage unit 152 of the column A / D circuits 150 of the n columns and the n + 2 columns. Further, the B (blue) digital image signal is stored in the data storage unit 152 of the column A / D circuit 150 of the n + 1 column and the n + 3 column.

Then, as shown in FIG. 14A, the data storage unit 152 of the column A / D circuit 150 of n columns and n + 2 columns is supplied to the horizontal adder 153-1 and the column A / D circuit 150 of n + 1 columns and n + 3 columns. The data storage unit 152 is connected to the horizontal adder 153-2.
Accordingly, as shown in FIGS. 14A to 14E, the horizontal adder 153-1 includes the digital pixel signal (R) of the n-column data storage unit 152 and the digital pixel of the n + 2 column data storage unit 152. The signal (R) is horizontally added by the same method as in the above-described embodiment.
Similarly, as shown in FIGS. 14A to 14E, the horizontal adder 153-2 performs digital pixel signal (B) of the data storage unit 152 in the (n + 1) th column and digital data in the data storage unit 152 in the (n + 3) th column. The pixel signal (B) is horizontally added by the same method as in the above-described embodiment.
With such a configuration, the CMOS image sensor 100 according to the third modification can perform horizontal addition of digital image signals for each color corresponding to the Bayer array.

Note that the CMOS image sensor 100 of the above-described embodiment can be applied to an imaging apparatus such as a digital camera as a solid-state imaging device.
Hereinafter, application examples thereof will be described.

FIG. 15 is a block diagram illustrating an example of the configuration of the imaging apparatus 300.
As illustrated in FIG. 15, the imaging apparatus 300 includes an optical system 71 including a lens, an imaging device 72, a camera signal processing circuit 73, a system controller 74, and the like.
The optical system 71 corresponds to the optical system of the present invention.

  The optical system 71 forms image light from the subject on the imaging surface of the imaging device 72 using a lens or the like. The imaging device 72 outputs an image signal obtained by converting the image light imaged on the imaging surface by the optical system 71 into an electrical signal for each pixel. As the imaging device 72, the CMOS image sensor 100 equipped with the column parallel A / D converter according to the above-described embodiment is used.

The camera signal processing circuit 73 performs various signal processing on the image signal output from the imaging device 72. The system controller 74 controls the imaging device 72 and the camera signal processing circuit 73.
In particular, the column parallel ADC of the imaging device 72 has a normal frame rate mode in a progressive scanning system that reads out information of all pixels. The column parallel ADC of the imaging device 72 has a high-speed frame rate mode in which the pixel exposure time is set to 1 / N and the frame rate is increased N times compared to the normal frame rate mode. In this case, in the column parallel A / D converter of the imaging device 72, if an A / D conversion operation corresponding to each operation mode is possible, an operation mode switching control or the like is performed according to an external command.

The present invention is not limited to the embodiment described above.
That is, when implementing the present invention, various modifications and alternatives may be made to the components of the above-described embodiments within the technical scope of the present invention or an equivalent scope thereof.

FIG. 1 is a block diagram illustrating a configuration example of a CMOS image sensor according to an embodiment of the present invention. FIG. 2 is a diagram showing a relationship between a specific configuration of the column A / D circuit and other configurations. FIG. 3 is a diagram showing a time chart during the operation of the horizontal adder. FIG. 4 is a diagram showing an example of the configuration of the horizontal adder. FIG. 5 is a diagram for explaining the details of the horizontal addition operation by the horizontal adder. FIG. 6 is a diagram for explaining the details of the horizontal addition operation by the horizontal adder. FIG. 7 is a diagram for explaining the details of the horizontal addition operation by the horizontal adder. FIG. 8 is a diagram for explaining the details of the horizontal addition operation by the horizontal adder. FIG. 9 is a diagram for explaining the details of the horizontal addition operation by the horizontal adder. FIG. 10 is a diagram showing a configuration diagram in the vicinity of the column A / D circuit 150 in the CMOS image sensor of the first modification. FIG. 11 is a diagram for explaining horizontal addition of four adjacent columns. FIG. 12 is a diagram for explaining horizontal addition of four adjacent columns. FIG. 13 is a diagram illustrating an example of a Bayer array. FIG. 14 is a diagram for explaining the horizontal addition operation corresponding to the Bayer array. FIG. 15 is a block diagram illustrating an example of the configuration of the imaging apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Image sensor 110 ... Pixel part 120 ... Vertical scanning circuit 121 ... Vertical signal line 130 ... Horizontal scanning circuit 131 ... Horizontal signal line 140 ... Timing control part 141 ... Addition mode signal line 142 ... Addition Clock signal line, 143 MSB control signal line, 150 Column A / D circuit, 151 Comparator, 152 Data storage unit, 153 Horizontal adder, 154 Up / down counter, 160 Reference signal generation circuit, 170 DESCRIPTION OF SYMBOLS ... Counter, 190 ... Signal processing circuit, 11 ... Adder, 12 ... Flip-flop, 13 ... Selector, 14 ... Input signal line, 15 ... Input signal line, 300 ... Imaging device, 71 ... Optical system, 72 ... Imaging device, 73 ... Camera signal processing circuit, 74 ... System controller

Claims (9)

A pixel unit in which a plurality of pixels that photoelectrically convert incident light and output the generated charges as an analog image signal are two-dimensionally arranged in a matrix;
Read signal lines wired for each of the plurality of pixels and commonly connected to one column of pixels;
A column A / D circuit connected to the readout signal line, for A / D (analog / digital) conversion and storing the analog image signal output from the pixel unit via the readout signal line;
A transfer signal line for transferring the signal stored in the column A / D circuit;
Have
The column A / D circuit is
A comparator that performs A / D conversion by comparing an analog image signal input from the pixel unit with a reference signal;
A plurality of data storage units for storing digital image signals A / D converted by the comparator;
An adder for adding the digital image signals stored in the data storage units in a plurality of columns in a transfer direction;
An imaging device having The adder is
The imaging device according to claim 1, wherein the image sensor is arranged in a plurality of columns of A / D circuits and adds a digital image signal stored in the data storage unit of the plurality of columns of column A / D circuits in a transfer direction. The imaging device according to claim 2, wherein a plurality of the data storage units are provided for each column, and the digital image signal is stored bit by bit in each data storage unit. The data storage unit
When the least significant bit is read by the adder, the stored digital image signal is shifted from the upper bit to the one lower bit,
The adder is
The imaging device according to claim 3, wherein the least significant bit of the data storage unit of a plurality of columns is read and added, and the addition result is stored in the most significant bit of the data storage unit of any column of the plurality of columns. . A timing control unit for supplying a clock signal;
The data read from the data storage unit of the adder and the shift from the upper bit to the lower bit in the data storage unit are performed according to the clock signal supplied by the timing control unit. Image sensor. The imaging device according to claim 5, wherein among the plurality of column A / D circuits, the column A / D circuit connected to the adder can be arbitrarily switched. The adder is
An adder circuit which is a 1-bit full adder;
A flip-flop circuit that holds a carry bit input from the adder circuit and outputs the carry bit to the adder circuit in accordance with a rising edge of the clock signal supplied from the timing control unit;
The imaging device according to claim 6. The adder is
A selector that switches the output from the output of the adder circuit to the carry bit output of the flip-flop circuit according to a control signal supplied from the timing control unit;
The timing controller is
In the data storage unit of the column A / D circuit of the plurality of columns, when the transfer direction addition from the least significant bit to the most significant bit is completed, the control signal is supplied to the selector, and the adder and Supplying a clock signal for one clock to the flip-flop circuit;
The flip-flop circuit is
The imaging device according to claim 7, wherein the carry bit is output to the most significant bit of the data storage unit according to the clock signal. An imaging device having a plurality of pixels;
An optical system that forms an image of light from a subject on the pixels of the imaging device;
Have
The image sensor is
A pixel unit in which a plurality of pixels that photoelectrically convert incident light and output the generated charges as an analog image signal are two-dimensionally arranged in a matrix;
Read signal lines wired for each of the plurality of pixels and commonly connected to one column of pixels;
A column A / D circuit connected to the readout signal line, for A / D (analog / digital) conversion and storing the analog image signal output from the pixel unit via the readout signal line;
A transfer signal line for reading the signal stored in the column A / D circuit;
Have
The column A / D circuit is
A comparator that performs A / D conversion by comparing an analog image signal input from the pixel unit with a reference signal;
A plurality of data storage units for storing digital image signals A / D converted by the comparator;
An adder for adding the digital image signals stored in the data storage units in a plurality of columns in a transfer direction;
An imaging apparatus having

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