JP2010056354A

JP2010056354A - Semiconductor device

Info

Publication number: JP2010056354A
Application number: JP2008220676A
Authority: JP
Inventors: Shinji Hiramitsu; 真二平光; Hiroyuki Ota; 裕之太田; Yasushi Ikeda; 靖池田; Satoshi Matsuyoshi; 聡松吉
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2008-08-29
Filing date: 2008-08-29
Publication date: 2010-03-11

Abstract

【課題】放熱性能を十分に確保し、かつ、接合材に発生する熱応力を低減することで、接合材の熱疲労を抑制できる半導体装置を提供する。
【解決手段】半導体チップ１と、半導体チップの片面に第一の接合材２を介して接合された導電性を有する第一の電極３と、半導体チップのもう一方の面に第二の接合材４を介して接合された導電性を有する第二の電極５と、半導体チップと第一の電極の膨張量差に起因して発生する第一の接合材の応力を低減するための第一の応力緩衝材６とを備え、前記第一の接合材に第一の電極と第一の応力緩衝材が各々直接接触する領域を設け、前記第一の接合材と第一の電極の凸部３aが接する部分の面積を、半導体チップの面積の３０％以下としたことを特徴とする。
【選択図】図１A semiconductor device capable of suppressing thermal fatigue of a bonding material by ensuring sufficient heat dissipation performance and reducing thermal stress generated in the bonding material.
A semiconductor chip, a conductive first electrode bonded to one surface of the semiconductor chip via a first bonding material, and a second bonding material to the other surface of the semiconductor chip. A first electrode for reducing stress of the first bonding material generated due to the difference in expansion between the semiconductor chip and the first electrode. A stress buffer material 6, a region where the first electrode and the first stress buffer material are in direct contact with the first bonding material, respectively, and a convex portion 3 a of the first bonding material and the first electrode. The area of the portion in contact with the semiconductor chip is 30% or less of the area of the semiconductor chip.
[Selection] Figure 1

Description

本発明は半導体装置に係り、特に、車両用回転発電機の整流装置に好適な半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a rectifier of a vehicular rotary generator.

車両用回転発電機の整流装置は、一般的に、半導体チップと、導電性を有する第一の電極及び第二の電極と、これらを接合するはんだを積層し、半導体チップ周辺を封止樹脂で覆った構造となっている。 In general, a rectifier of a rotary generator for a vehicle is formed by laminating a semiconductor chip, a first electrode and a second electrode having conductivity, and a solder for joining them, and sealing the periphery of the semiconductor chip with a sealing resin. It has a covered structure.

車両用回転発電機が動作すると、本整流装置には大電流が流れるため半導体チップが発熱し、半導体チップと周辺のはんだ、第一の電極及び第二の電極は、最高で２００℃以上の高温になる。車両用回転発電機が停止すると電流も停止し、本整流装置は周囲環境温度まで冷却される。車両用回転発電機は長期に渡って動作と停止を繰り返すため、本整流装置には加熱による膨張と冷却による収縮が繰り返される。このとき、半導体チップと第一の電極，第二の電極の線膨張係数が異なるため、これらを接合するはんだには熱応力が発生する。この熱応力が原因で、はんだに疲労き裂が発生，進展し、最終的には本半導体装置が破壊に至る不具合が生じ得る。 When the vehicular rotary generator is operated, a large current flows through the rectifier, so that the semiconductor chip generates heat. become. When the vehicular rotary generator stops, the current stops and the rectifier is cooled to the ambient temperature. Since the vehicular rotary generator repeatedly operates and stops for a long period of time, the rectifier is repeatedly expanded by heating and contracted by cooling. At this time, since the linear expansion coefficients of the semiconductor chip, the first electrode, and the second electrode are different, thermal stress is generated in the solder for joining them. Due to this thermal stress, a fatigue crack may be generated and propagated in the solder, and eventually the semiconductor device may be broken.

はんだの熱応力を低減する構造としては、例えば特許文献１に示されるような、半導体チップと第一の電極の間、半導体チップと第二の電極の間に、線膨張係数が半導体チップの線膨張係数より大きく、かつ、第一の電極，第二の電極材料の線膨張係数よりも小さい材料からなる応力緩衝板を設け、これら応力緩衝板をそれぞれはんだにより半導体チップと第一の電極，半導体チップと第二の電極に接合する整流装置が提案されている。 As a structure for reducing the thermal stress of the solder, for example, as shown in Patent Document 1, the linear expansion coefficient is between the semiconductor chip and the first electrode and between the semiconductor chip and the second electrode. A stress buffer plate made of a material that is larger than the expansion coefficient and smaller than the linear expansion coefficient of the first electrode and the second electrode material is provided, and the stress buffer plate is soldered to the semiconductor chip, the first electrode, and the semiconductor, respectively. A rectifier that joins the chip and the second electrode has been proposed.

米国特許第４３４９８３１号公報U.S. Pat. No. 4,349,831

近年の急速な自動車の電装化に伴い、車両用回転発電機の電力容量は増加傾向にある。それに伴い、本整流装置における半導体チップの発熱量が増加し、はんだ熱応力も増加すると予想される。 With the recent rapid electrification of automobiles, the power capacity of rotating generators for vehicles is increasing. Along with this, it is expected that the amount of heat generated by the semiconductor chip in this rectifier increases and the solder thermal stress also increases.

これに対し、今後も従来製品と同等以上の信頼性を確保していくには、これまで以上にはんだの熱応力を低減し、熱疲労を抑制する必要がある。 On the other hand, in order to ensure reliability equal to or higher than that of conventional products in the future, it is necessary to further reduce the thermal stress of the solder and suppress thermal fatigue.

はんだの熱応力を低減する手段としては、半導体チップで発生した熱を周囲へ逃がしやすい構造とし、はんだへ加わる温度振幅を小さくすること、または、大きな温度振幅下でも、はんだの熱応力が小さくなる構造にすることが考えられる。 As means for reducing the thermal stress of the solder, the structure is such that the heat generated in the semiconductor chip is easily released to the surroundings, and the temperature amplitude applied to the solder is reduced, or the thermal stress of the solder is reduced even under a large temperature amplitude. It can be considered to be a structure.

上記従来技術では、応力緩和の効果を得るために、半導体チップと第一の電極、および半導体チップと第二の電極の間にそれぞれ応力緩衝板を設けている。しかし、この構造の場合、応力緩衝板と、この応力緩衝板を第一の電極及び第二の電極へ接合するための接合材層が増えるため、放熱性能が低下してしまう。 In the above prior art, in order to obtain a stress relaxation effect, a stress buffer plate is provided between the semiconductor chip and the first electrode and between the semiconductor chip and the second electrode. However, in the case of this structure, since the stress buffer plate and the bonding material layer for bonding the stress buffer plate to the first electrode and the second electrode are increased, the heat dissipation performance is deteriorated.

本発明は、上記従来技術の課題を鑑みなされたもので、その目的とするところは、放熱性能を維持しつつ応力緩和性能を達成することは勿論、はんだの熱応力を低減し、熱疲労を抑制することのできる半導体装置を提供することにある。 The present invention has been made in view of the above-described problems of the prior art, and the object of the present invention is to reduce the thermal stress of solder and reduce thermal fatigue as well as to achieve stress relaxation performance while maintaining heat dissipation performance. An object of the present invention is to provide a semiconductor device that can be suppressed.

本発明の半導体装置は、上記目的を達成するために、第一の電極と、該第一の電極に第一の接合材を介して設置される半導体チップと、前記第一の電極と反対側に設置され、前記半導体チップと第二の接合材を介して接続される第二の電極と、前記第一の接合材の応力を低減する第一の応力緩衝材とを備え、前記第一の接合材の前記第一の電極側の面に、前記第一の電極と前記第一の応力緩衝材がそれぞれ直接接触し、前記第一の接合材と第一の電極との接合面の面内で、前記第一の電極の外側に前記第一の応力緩衝材が配置され、かつ、前記第一の接合材と前記第一の電極の接合面の面積が、前記半導体チップの面積に対し３０％以下であることを特徴とする。 In order to achieve the above object, a semiconductor device of the present invention includes a first electrode, a semiconductor chip installed on the first electrode via a first bonding material, and a side opposite to the first electrode. A second electrode that is connected to the semiconductor chip via a second bonding material, and a first stress buffer material that reduces the stress of the first bonding material. The first electrode and the first stress buffer material are in direct contact with the surface on the first electrode side of the bonding material, respectively, and in the plane of the bonding surface between the first bonding material and the first electrode Then, the first stress buffer material is disposed outside the first electrode, and the area of the bonding surface between the first bonding material and the first electrode is 30 with respect to the area of the semiconductor chip. % Or less.

本発明によれば、第一の電極と、半導体チップと第一の電極を接合する接合材の応力を低減する応力緩衝材とが、接合材の第一の電極側の面に直接接触する領域が形成され、かつ、前記第一の電極が接する部分の面積が、前記半導体チップの面積に対し３０％以下であるため、放熱性能と応力緩和性能がうまくバランスし、はんだの熱応力の低減が達成可能となる。 According to the present invention, the region in which the first electrode and the stress buffer material that reduces the stress of the bonding material for bonding the semiconductor chip and the first electrode are in direct contact with the surface on the first electrode side of the bonding material. And the area of the portion in contact with the first electrode is 30% or less with respect to the area of the semiconductor chip, the heat dissipation performance and the stress relaxation performance are well balanced, and the thermal stress of the solder is reduced. Achievable.

以下、本発明の実施例について図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

図１は、本発明の第一の実施例における半導体装置の断面図である。図１に示す半導体装置は、半導体チップ１，第一の接合材２，凸部３ａと壁部３ｂを有する第一の電極３，第二の接合材４，リード部５ａを有する第二の電極５，第一の応力緩衝材６，第三の接合材７，応力緩衝板９，第四の接合材１０等を含んで構成されている。 FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The semiconductor device shown in FIG. 1 includes a semiconductor chip 1, a first bonding material 2, a first electrode 3 having a convex portion 3a and a wall portion 3b, a second bonding material 4, and a second electrode having a lead portion 5a. 5, the first stress buffer material 6, the third bonding material 7, the stress buffer plate 9, the fourth bonding material 10, and the like.

第一の電極３の凸部３ａと第一の応力緩衝材６は、半導体チップ１下側の第一の接合材２下面に各々直接接触するように接合されている。 The convex portion 3 a of the first electrode 3 and the first stress buffer material 6 are joined so as to be in direct contact with the lower surface of the first joining material 2 below the semiconductor chip 1.

図２は、図１に示した本発明の第一の実施例である半導体装置のＩ−Ｉ線断面図である。第一の電極３の凸部３ａは、円柱形状を有しており、第一の応力緩衝材６は第一の電極３の凸部３ａの外側に配置され、凸部３ａの外周を覆うよう環状形状をなしている。凸部３ａ及び第一の応力緩衝材の断面形状は円である。 2 is a cross-sectional view taken along line II of the semiconductor device according to the first embodiment of the present invention shown in FIG. The convex part 3a of the first electrode 3 has a cylindrical shape, and the first stress buffer 6 is arranged outside the convex part 3a of the first electrode 3 so as to cover the outer periphery of the convex part 3a. It has an annular shape. The cross-sectional shape of the convex part 3a and the first stress buffer material is a circle.

第一の電極３の凸部３ａと第一の接合材２が接合されている面積は、半導体チップ１の面積の約１０％である。 The area where the protrusion 3 a of the first electrode 3 and the first bonding material 2 are bonded is about 10% of the area of the semiconductor chip 1.

第一の応力緩衝材６は、第一の電極凸部３ａに対し圧入により嵌められているため、半導体チップ１に対しおよそ垂直な面において、第一の電極凸部３ａと直接接触している。即ち、円柱形状の凸部３ａの外周面と、環状をなす第一の応力緩衝材６の内周面とは直接接触している。また、半導体チップ１に対しておよそ平行な面においては、第一の応力緩衝材６と第一の電極３は第三の接合材７を介して接合されている。即ち、第一の応力緩衝材６のうち半導体チップ１と反対側の面（第一の電極３側の面）と第一の電極３は第三の接合材７により接合されている。 Since the first stress buffer material 6 is press-fitted into the first electrode convex portion 3a, the first stress buffer material 6 is in direct contact with the first electrode convex portion 3a on a surface approximately perpendicular to the semiconductor chip 1. . That is, the outer peripheral surface of the cylindrical convex portion 3a and the inner peripheral surface of the annular first stress buffer material 6 are in direct contact. Further, the first stress buffer material 6 and the first electrode 3 are bonded via a third bonding material 7 on a plane approximately parallel to the semiconductor chip 1. That is, the surface of the first stress buffer material 6 opposite to the semiconductor chip 1 (the surface on the first electrode 3 side) and the first electrode 3 are joined by the third joining material 7.

半導体チップ１の第一の電極３と反対側には、半導体チップ１と第二の電極５の間の接合材の応力を緩和するための応力緩衝板９が第二の接合材４を介して接合され、さらに応力緩衝板９の上側には第四の接合材１０を介して第二の電極５が接合されている。第一の電極３の壁部３ｂの内側は封止樹脂８で覆われている。 On the side opposite to the first electrode 3 of the semiconductor chip 1, a stress buffer plate 9 for relaxing the stress of the bonding material between the semiconductor chip 1 and the second electrode 5 is interposed via the second bonding material 4. Further, the second electrode 5 is bonded to the upper side of the stress buffer plate 9 via the fourth bonding material 10. The inside of the wall 3 b of the first electrode 3 is covered with a sealing resin 8.

第一の接合材２，第二の接合材４，第三の接合材７，第四の接合材１０には、鉛フリーはんだであるＳｎ−Ｃｕ系はんだを用いている。第一の応力緩衝材６と応力緩衝板９の線膨張係数は３×１０^-6／℃以上であり、かつ、１２×１０^-6／℃以下であることが必要であり、ここでは、Ｍｏ（モリブデン，線膨張係数５.１×１０^-6／℃）を用いている。他にＷ（タングステン，線膨張係数４.５×１０^-6／℃），Ｆｅ−４２％Ｎｉ合金（通称４２アロイ，線膨張係数５×１０^-6／℃），ＣＩＣ（Ｃｕ−Invar−Ｃｕの積層材，Invar線膨張係数２.８×１０^-6／℃，Ｃｕ線膨張係数１６.５×１０^-6／℃），ＣｕとＭｏの複合材（等価線膨張係数例えば７.０×１０^-6／℃）等を用いても同様の効果を得ることができる。また、第一の応力緩衝材６と応力緩衝板９の材質は同じである必要はない。 For the first bonding material 2, the second bonding material 4, the third bonding material 7, and the fourth bonding material 10, Sn—Cu based solder that is lead-free solder is used. The linear expansion coefficient of the first stress buffer material 6 and the stress buffer plate 9 needs to be 3 × 10 ⁻⁶ / ° C. or more and 12 × 10 ⁻⁶ / ° C. or less. (Molybdenum, linear expansion coefficient 5.1 × 10 ⁻⁶ / ° C.) is used. In addition, W (tungsten, linear expansion coefficient 4.5 × 10 ⁻⁶ / ° C.), Fe-42% Ni alloy (common name 42 alloy, linear expansion coefficient 5 × 10 ⁻⁶ / ° C.), CIC (Cu-Invar-Cu Laminated material, Invar linear expansion coefficient 2.8 × 10 ⁻⁶ / ° C., Cu linear expansion coefficient 16.5 × 10 ⁻⁶ / ° C., Cu and Mo composite (equivalent linear expansion coefficient, for example 7.0 × 10 ^-6 / ° C) can be used to obtain the same effect. The materials of the first stress buffer material 6 and the stress buffer plate 9 need not be the same.

以下では、本実施例の効果を従来の半導体装置との比較において説明する。図７は、従来の半導体装置の断面図である。図中図１に示される本発明の一実施例と同等の部材には同一の符号を付している。従来の半導体装置は、第一の電極３に第三の接合材７を介して第一の応力緩衝板１２を配し、この第一の応力緩衝板１２上に第一の接合材２を介して半導体チップ１を配し、半導体チップ１上に第二の接合材４を介して第二の応力緩衝板１３を配し、第二の応力緩衝板１３上に第四の接合材１０を介して第二の電極５を配し、封止樹脂８にて封止した構造を有している。 In the following, the effect of this embodiment will be described in comparison with a conventional semiconductor device. FIG. 7 is a cross-sectional view of a conventional semiconductor device. In the figure, members equivalent to those of the embodiment of the present invention shown in FIG. In the conventional semiconductor device, a first stress buffer plate 12 is disposed on the first electrode 3 via a third bonding material 7, and the first bonding material 2 is interposed on the first stress buffer plate 12. The semiconductor chip 1 is disposed, the second stress buffer plate 13 is disposed on the semiconductor chip 1 via the second bonding material 4, and the fourth bonding material 10 is disposed on the second stress buffer plate 13. The second electrode 5 is disposed and sealed with a sealing resin 8.

図８は、本発明の第一実施例における、半導体チップ１と第一の電極３の凸部３ａの面積比と寿命との関係を、実験的に評価した結果を示す。評価は次の手順で行った。半導体装置へ通電負荷（ここでは３５Ａ）を与え、半導体チップ１の発熱を利用して第一の電極３の表面温度が５０℃から１８０℃に変化させる。１８０℃になったら電流を止め、５０℃になるまで半導体装置を冷却する。５０℃になったら通電を再開し、前記作業を繰り返す。 FIG. 8 shows the result of experimental evaluation of the relationship between the area ratio of the protrusion 3a of the semiconductor chip 1 and the first electrode 3 and the lifetime in the first embodiment of the present invention. The evaluation was performed according to the following procedure. An energization load (35A in this case) is applied to the semiconductor device, and the surface temperature of the first electrode 3 is changed from 50 ° C. to 180 ° C. using the heat generated by the semiconductor chip 1. When the temperature reaches 180 ° C., the current is stopped and the semiconductor device is cooled to 50 ° C. When the temperature reaches 50 ° C., energization is resumed and the above operation is repeated.

この繰り返しの通電熱負荷により、半導体装置が機能しなくなる通電繰り返し数を寿命とし、評価を実施した。図において、横軸（第一の電極３凸部３ａの面積／半導体チップ１の面積）が０％のデータは、従来の半導体装置の性能である。この値を基準として、第一の電極３の凸部３ａの面積を変えた場合の寿命をプロットした。結果、従来技術の半導体装置と比較し、長寿命効果すなわち熱疲労抑制効果が得られるのは、半導体チップ１と第一の電極３の凸部３ａの面積比の値が約３０％以下からであることが分かる。 Evaluation was carried out with the number of repeated energizations at which the semiconductor device failed due to this repeated energization heat load as the lifetime. In the figure, data in which the horizontal axis (the area of the first electrode 3 convex portion 3a / the area of the semiconductor chip 1) is 0% is the performance of the conventional semiconductor device. Using this value as a reference, the lifetime when the area of the convex portion 3a of the first electrode 3 was changed was plotted. As a result, compared with the semiconductor device of the prior art, the long life effect, that is, the thermal fatigue suppression effect is obtained when the value of the area ratio of the convex portion 3a of the semiconductor chip 1 and the first electrode 3 is about 30% or less. I understand that there is.

上述の第一の実施例においては、図１で説明したとおり半導体チップ１の上側に応力緩衝板９を配しているが、必ずしも応力緩衝板９が必要であるとは限らない。 In the first embodiment described above, the stress buffer plate 9 is disposed on the upper side of the semiconductor chip 1 as described with reference to FIG. 1, but the stress buffer plate 9 is not necessarily required.

また、第一の実施例では、図１で説明したとおり第一の電極３が壁部３ｂを有しているが、必ずしも壁部３ｂが必要であるとは限らない。 In the first embodiment, the first electrode 3 has the wall portion 3b as described in FIG. 1, but the wall portion 3b is not necessarily required.

また、上記第一の実施例では、図１で示したとおり第一の応力緩衝材６が第一の電極壁部３ｂに接触していないが、第一の応力緩衝材６と第一の電極壁部３ｂが接触していてもよい。 In the first embodiment, the first stress buffer 6 is not in contact with the first electrode wall 3b as shown in FIG. 1, but the first stress buffer 6 and the first electrode The wall 3b may be in contact.

また、第一の実施例では、図１で説明したとおり半導体チップ１に水平方向においては、第一の電極３と第一の応力緩衝材６が第三の接合材７を介して接合されているが、第一の電極３と第一の応力緩衝材６が接合材を介することなく直接接触するよう構成してもよい。また、第一の電極３と第一の応力緩衝材６が接触していなくても一定の効果は得られる。 In the first embodiment, as described with reference to FIG. 1, the first electrode 3 and the first stress buffer material 6 are bonded to the semiconductor chip 1 through the third bonding material 7 in the horizontal direction. However, you may comprise so that the 1st electrode 3 and the 1st stress buffer material 6 may contact directly, without interposing a joining material. Even if the first electrode 3 and the first stress buffer material 6 are not in contact with each other, a certain effect can be obtained.

図３，図４は、本発明の第一の実施例である半導体装置の第一の電極凸部と応力緩衝材の変形例を示すＩ−Ｉ線断面図である第一の電極凸部３ａおよび第一の応力緩衝材６の断面形状は必ずしも円である必要はない。図３，図４に示す構造を用いても、上記と同様の効果を得ることができる。 3 and 4 are first electrode protrusions 3a, which are cross-sectional views taken along the line I-I showing a modification of the first electrode protrusion and the stress buffer material of the semiconductor device according to the first embodiment of the present invention. The cross-sectional shape of the first stress buffer material 6 is not necessarily a circle. Even if the structure shown in FIGS. 3 and 4 is used, the same effect as described above can be obtained.

図５は、本発明の第二の実施例における半導体装置の断面図である。図１との相違点は、半導体チップ１の第一の電極３と反対側に、応力緩衝板９ではなく第二の応力緩衝材１１を配置し、第二の電極５と第二の応力緩衝材１１は、第二の接合材４の半導体チップ１と反対側の面に各々直接接触するように接合されており、第二の電極５と第二の接合材４が接合されている面積は、半導体チップ１の面積の約１０％となっている点である。これにより、半導体チップ１に直接接合している第一の接合材２，第二の接合材４の応力緩和性能を確保しながら、第一の電極３側の熱疲労抑制効果だけでなく、第二の電極５側の熱疲労抑制効果をも得ることができる。 FIG. 5 is a sectional view of a semiconductor device according to the second embodiment of the present invention. 1 differs from the first electrode 3 of the semiconductor chip 1 in that a second stress buffer material 11 is arranged instead of the stress buffer plate 9, and the second electrode 5 and the second stress buffer are arranged. The material 11 is bonded so as to be in direct contact with the surface opposite to the semiconductor chip 1 of the second bonding material 4, and the area where the second electrode 5 and the second bonding material 4 are bonded is as follows. The area of the semiconductor chip 1 is about 10%. Thereby, while ensuring the stress relaxation performance of the first bonding material 2 and the second bonding material 4 directly bonded to the semiconductor chip 1, not only the thermal fatigue suppressing effect on the first electrode 3 side but also the first The effect of suppressing thermal fatigue on the second electrode 5 side can also be obtained.

図６は、本発明の第二の実施例である半導体装置の第一の電極の変形例を示す断面図である。第一の電極３は必ずしも凸部３と壁部３ｂを有する必要はない。 FIG. 6 is a sectional view showing a modification of the first electrode of the semiconductor device according to the second embodiment of the present invention. The first electrode 3 does not necessarily have to have the convex part 3 and the wall part 3b.

本発明の第一の実施例における半導体装置の断面図である。It is sectional drawing of the semiconductor device in the 1st Example of this invention. 図１に示した本発明の第一の実施例である半導体装置のＩ−Ｉ線断面図である。It is the II sectional view taken on the line of the semiconductor device which is the 1st Example of this invention shown in FIG. 本発明の第一の実施例である半導体装置の第一の電極凸部と応力緩衝材の変形例を示すＩ−Ｉ線断面図である。It is the II sectional view taken on the line which shows the 1st electrode convex part of the semiconductor device which is a 1st Example of this invention, and the modification of a stress buffer material. 本発明の第一の実施例である半導体装置の第一の電極凸部と応力緩衝材の他の変形例を示すＩ−Ｉ線断面図である。It is the II sectional view taken on the line which shows the other modification of the 1st electrode convex part and stress buffer material of the semiconductor device which is a 1st Example of this invention. 本発明の第二の実施例における半導体装置の断面図である。It is sectional drawing of the semiconductor device in the 2nd Example of this invention. 本発明の第二の実施例である半導体装置の第一の電極の変形例を示す断面図である。It is sectional drawing which shows the modification of the 1st electrode of the semiconductor device which is a 2nd Example of this invention. 従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device. 本発明の第一実施例における、半導体チップ１と第一の電極３の凸部３ａの面積比と寿命との関係を、実験的に評価した結果を示す図である。It is a figure which shows the result of having evaluated experimentally the relationship between the area ratio of the convex part 3a of the semiconductor chip 1 and the 1st electrode 3, and lifetime in the 1st Example of this invention.

Explanation of symbols

１半導体チップ
２第一の接合材
３第一の電極
３ａ凸部
３ｂ壁部
４第二の接合材
５第二の電極
５ａリード部
６第一の応力緩衝材
７第三の接合材
８封止樹脂
９応力緩衝板
１０第四の接合材
１１第二の応力緩衝材
１３第二の応力緩衝板 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 1st joining material 3 1st electrode 3a Protruding part 3b Wall part 4 2nd joining material 5 2nd electrode 5a Lead part 6 1st stress buffering material 7 3rd joining material 8 Sealing Resin 9 Stress buffer plate 10 Fourth bonding material 11 Second stress buffer material 13 Second stress buffer plate

Claims

A first electrode, a semiconductor chip installed on the first electrode via a first bonding material, and installed on the opposite side of the first electrode, via the semiconductor chip and a second bonding material A second electrode connected to each other, and a first stress buffer material that reduces the stress of the first bonding material,
The first electrode and the first stress buffer material are in direct contact with the first electrode side surface of the first bonding material, respectively, and the first bonding material and the first electrode are bonded. In the plane of the surface, the first stress buffer material is disposed outside the first electrode, and the area of the bonding surface between the first bonding material and the first electrode is equal to that of the semiconductor chip. A semiconductor device characterized by being 30% or less of the area.

The semiconductor device according to claim 1,
A semiconductor device, wherein a convex portion is provided on a surface of the first electrode on the semiconductor chip mounting side, and the convex portion is in direct contact with a surface of the first bonding material on the first electrode side.

The semiconductor device according to claim 2,
The convex portion of the first electrode has a cylindrical shape, and the first stress buffer material has an annular shape arranged concentrically so as to cover the periphery of the convex portion, and the outer peripheral surface of the convex portion and the A semiconductor device characterized in that the inner peripheral surface of the first stress buffer material is in direct contact.

The semiconductor device according to any one of claims 1 to 3,
A linear expansion coefficient of the first stress buffer material is 3 × 10 ⁻⁶ / ° C. or more and 12 × 10 ⁻⁶ / ° C. or less.

The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the first stress buffer material is Mo, W, or an Fe-Ni alloy.

The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the first stress buffer material is a composite material made of any one of Mo, W, and Fe-Ni alloys and Cu.

The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the first bonding material is an alloy material that does not contain lead and contains tin and copper as main constituent elements, and the weight ratio of copper is 7% or less.

A first electrode having a wall at the periphery, a semiconductor chip having a rectifying function installed on the first electrode via a first bonding material, and a second bonding material on the upper side of the semiconductor chip. A second electrode connected via the first electrode, a first stress buffer material that reduces the stress of the first bonding material, and a second stress buffer material that reduces the stress of the second bonding material. ,
The first electrode and the first stress buffer material are in direct contact with the first electrode side surface of the first bonding material, respectively, and the second electrode side of the second bonding material is on the second electrode side. The second electrode and the second stress buffer material are in direct contact with the surface, respectively, and within the surface of the bonding surface between the first bonding material and the first electrode, outside the first electrode. And the second stress buffer material is disposed outside the second electrode within the surface of the joint surface between the second bond material and the second electrode. And the area of the bonding surface between the first bonding material and the first electrode and the area of the second bonding material and the second electrode are 30% or less of the area of the semiconductor chip, respectively. A semiconductor device characterized by the above.

The semiconductor device according to claim 8,
The first stress buffer material and the second stress buffer material have a linear expansion coefficient of 3 × 10 ⁻⁶ / ° C. or more and 12 × 10 ⁻⁶ / ° C. or less. apparatus.

The semiconductor device according to claim 8 or 9,
The semiconductor device according to claim 1, wherein the first stress buffer material and the second stress buffer material are Mo, W, or an Fe-Ni alloy.

The semiconductor device according to claim 8 or 9,
The semiconductor device according to claim 1, wherein the first stress buffer material and the second stress buffer material are composite materials made of any one of Mo, W, Fe-Ni alloys and Cu.

The semiconductor device according to claim 8 or 9,
The first bonding material and the second bonding material are alloy materials that do not contain lead and contain tin and copper as main constituent elements, and the weight ratio of copper is 7% or less. Semiconductor device.