JP2010051152A - Current mode control type switching regulator - Google Patents

Abstract

A current mode control type switching regulator capable of generating a slope voltage with good linearity and performing stable operation is obtained.
A switched capacitor circuit in which a slope voltage generation circuit for generating a slope voltage Vslp having a slope corresponding to an inductor current iL flowing through an inductor L1 converts the inductor current iL into a voltage and detects the switched capacitor circuit, and the switched capacitor A constant current source that charges or discharges the circuit with a predetermined constant current, and a voltage conversion circuit that generates a slope voltage Vslp by converting a voltage converted by the switched capacitor circuit into a ground voltage reference voltage. I did it.
[Selection] Figure 1

Description

  The present invention relates to a current mode control type switching regulator, and more particularly to a current mode control type switching regulator capable of performing a stable operation even when an input / output voltage difference is large.

FIG. 8 is a block diagram illustrating an example of a current mode control type step-down switching regulator using a conventional synchronous rectification method (see, for example, Patent Document 1).
The switching regulator 100 of FIG. 8 steps down the input voltage Vin input to the input terminal IN, and outputs it as an output voltage Vout from the output terminal OUT. In the switching regulator 100, the switching transistor M101 and the synchronous rectification transistor M102 perform ON / OFF operations complementarily, thereby storing energy in the inductor L101 and the capacitor C101, and outputting the stored energy as the output voltage Vout from the output terminal OUT. And supplied to the load 200.

FIG. 9 is a diagram showing a circuit example of the slope voltage generation circuit 120 of FIG.
Since the inductor current iL flowing through the inductor L101 when the switching transistor M101 is on is equal to the drain current of the switching transistor M101, if the on-resistance of the switching transistor M101 is known, the voltage drop of the switching transistor M101 is detected. Thus, the inductor current iL can be detected.
Therefore, the inductor current detection circuit 120A of FIG. 9 detects a voltage drop when the switching transistor M101 is on. When the switching transistor M101 is on, the gate signal S101 is at a low level. At this time, the PMOS transistor M122 is turned off and the PMOS transistor M123 is turned on. The voltage VLX of the connection portion LX in FIG. 8 is input.

Since the operational amplifier circuit 121 controls the gate voltage of the PMOS transistor M121 so that the source voltage of the PMOS transistor M121 is the same as the voltage VLX, the drain current of the PMOS transistor M121 becomes a current proportional to the inductor current iL. The drain current is converted into a voltage by the resistor R122, and the converted voltage is output through the resistor R123.
Assuming that the resistance values of the resistors R121 and R122 are the same, the drain voltage VA of the PMOS transistor M121 is expressed by the following equation (a).
VA = Vin−VLX ……………… (a)

Note that when the switching transistor M101 is off, the gate signal S101 is at a high level. At this time, since the PMOS transistor M122 is turned on and the PMOS transistor M123 is turned off, the voltage at the non-inverting input terminal of the operational amplifier circuit 121 becomes the input voltage Vin, and the operational amplifier circuit 121 turns off the PMOS transistor M121. The drain voltage VA of the PMOS transistor M121 becomes 0V.
Since the NMOS transistor M124 of the ramp voltage generation circuit 120B is on while the gate signal S101 is at a high level, the current output from the constant current circuit i121 is bypassed by the NMOS transistor M124, and the terminal voltage of the ramp capacitor C121. VB is 0V.

When the gate signal S101 becomes low level, the NMOS transistor M124 is turned off, so that the ramp capacitor C121 is charged by the output current of the constant current circuit i121. Therefore, the terminal voltage VB of the lamp capacitor C121 rises linearly to become a lamp voltage, and the lamp voltage VB is output through the resistor R124. The respective output voltages of the inductor current detection circuit 120A and the ramp voltage generation circuit 120B are added by the resistors R123 and R124, and are output from the connection portion of the resistors R123 and R124. Assuming that the resistance values of the resistors R123 and R124 are the same and the voltage at the connection portion between the resistors R1123 and R124 is VC, the voltage VC is expressed by the following equation (b), and the slope voltage output circuit 120C is operated. The signal is input to the non-inverting input terminal of the amplifier circuit 124.
VC = (VA + VB) / 2 = (Vin−VLX + VB) / 2 (b)

Since the operational amplifier circuit 124 controls the gate voltage of the NMOS transistor M126 so that the source voltage of the NMOS transistor M126 becomes equal to the voltage VC, the drain current of the NMOS transistor M126 becomes a current proportional to the voltage VC. The current is supplied to the resistor R126 through a current mirror circuit composed of PMOS transistors M127 and M128, and is converted into a voltage by the resistor R126 to become a slope voltage Vslp. Assuming that the resistance value of the resistor R126 is K times the resistance value of the resistor R125, the slope voltage Vslp is expressed by the following equation (c).
Vslp = K * VC = K * (Vin-VLX + VB) / 2 (c)

On the other hand, the resistor R126 is supplied with current from the constant current circuit i122 in addition to the output current from the current mirror circuit, and the output voltage Vslp of the slope voltage generation circuit 120 is supplied with the output current ia of the constant current circuit i122. Is added with an offset voltage Vof (= r126 × ia) which is a voltage obtained by multiplying the resistance value r126 of the resistor R126 by the resistance value r126. The output voltage Vslp of the slope voltage generation circuit 120 when the resistance values of the resistors R125 and R126 are the same is expressed by the following equation (d).
Vslp = VC + (r126 × ia) = (Vin−VLX + VB) / 2 + (r126 × ia) (d)
As can be seen from the equation (d), the slope voltage Vslp is a voltage obtained by adding the ramp capacitor charging voltage VB and the offset voltage Vof, which are slope compensation voltages, to the inductor current (Vin−VLX).
JP 2006-246626 A

However, the slope voltage generation circuit 120 of FIG. 9 has a problem that the linearity at the rising portion of the slope voltage Vslp is poor.
FIG. 10 is a diagram illustrating a waveform example of the slope voltage Vslp generated by the slope voltage generation circuit 120 of FIG. As can be seen from FIG. 10, the slope voltage Vslp gradually rises immediately after the gate signal S101 becomes low level, approaches a desired slope as time elapses, and reaches the desired slope after time Tdel. . As described above, the rise of the slope voltage Vslp is caused by the delay time when the voltage VC is converted into current by the voltage-current conversion circuit by the operational amplifier circuit 124 and the current mirror formed by the PMOS transistors M127 and M128. This is due to the delay time when passing through the circuit.

  When the rise of the slope voltage Vslp becomes gradual, the switching regulator 100 does not operate under the condition that the on-time of the switching transistor M101 is shorter than the time Tdel, for example, when the voltage difference between the input voltage Vin and the output voltage Vout is large. There has been a problem that the output voltage Vout is not stable because of stabilization.

  Furthermore, the resistors R123 and R124 for adding the voltage obtained by converting the inductor current iL and the lamp voltage are premised on that no current flows from the voltages VA and VB, and only when the premise is satisfied, the inductor The current iL can be accurately detected. For this reason, the resistance values of the resistors R123 and R124 need to be set so that the input impedance from the voltages VA and VB becomes sufficiently large, which causes an increase in delay time in the output voltage VC of the adder circuit. It was. In order to reduce the delay time, if the resistance values of the resistors R123 and R124 are set to be small, an error occurs due to current flowing into the resistors R123 and R124 from the voltages VA and VB, and the inductor current iL is accurately set. Since the voltage cannot be converted to a voltage, the linearity of the slope voltage Vslp has deteriorated.

  The present invention has been made to solve such a problem, and it is possible to generate a slope voltage with good linearity and to obtain a current mode control type switching regulator capable of performing stable operation. Objective.

A current mode control type switching regulator according to the present invention is a current mode control type switching regulator that converts an input voltage input to an input terminal into a predetermined constant voltage and outputs it as an output voltage from an output terminal.
A switch transistor that performs switching according to a control signal input to the control electrode;
An inductor charged by the input voltage by switching of the switching transistor;
A rectifying element for discharging the inductor;
A slope voltage generation circuit unit that generates a voltage proportional to the inductor current flowing through the inductor when charging the inductor and outputs the voltage as a slope voltage;
A switching control circuit unit that performs switching control of the switching transistor according to the slope voltage;
With
The slope voltage generation circuit unit is
A switched capacitor circuit that performs switching according to a control signal input to a control electrode of the switching transistor, converts the inductor current into a voltage, and outputs the voltage;
A first constant current source for charging or discharging the switched capacitor circuit with a predetermined constant current;
Is provided.

Specifically, the switched capacitor circuit is:
A capacitor that is charged or discharged with a constant current from the first constant current source;
A first switch element connected between one end of the capacitor and one end of the inductor on the switching transistor side;
A second switch element connected between the one end of the capacitor and the input voltage;
A third switch element connected in parallel to the capacitor;
With
The first constant current source is connected between the other end of the capacitor and a ground voltage, and the first switch element performs the same switching operation as the switching transistor, and the second and third switches. The element performs a switching operation contrary to the switching transistor.

  Further, the slope voltage generation circuit unit outputs a voltage at a connection portion between the capacitor and the first constant current source as the slope voltage.

  The slope voltage generation circuit unit includes a voltage conversion circuit that converts a voltage at a connection portion between the capacitor and the first constant current source into a ground voltage reference voltage and outputs the voltage as the slope voltage. Also good.

In this case, the voltage conversion circuit
An operational amplifier circuit in which a voltage at a connection portion between the capacitor and the first constant current source is input to one input terminal;
A first transistor having a control electrode connected to the output terminal of the operational amplifier circuit and a current input terminal connected to the other input terminal of the operational amplifier circuit;
A first resistor connected between the input voltage and a current input terminal of the first transistor;
A second resistor that converts the current output from the first transistor into a voltage to generate the slope voltage;
I was prepared to.

  The operational amplifier circuit is provided with a predetermined offset voltage at at least one input end.

  The voltage conversion circuit may include a second constant current source that supplies a predetermined constant current to the second resistor.

  According to the current mode control type switching regulator of the present invention, since the switched capacitor circuit is used in the circuit that adds the voltage obtained by converting the inductor current and the ramp voltage, it is used in the conventional slope voltage generation circuit. The addition of the voltage-current conversion circuit, current mirror circuit, and resistance element that delays the rise of the slope voltage can be eliminated, so that the switching transistor is turned on and charging of the inductor is started. Immediately after that, a slope voltage with good linearity can be generated, stable operation can be performed even when the on-time of the switching transistor is short, and the circuit scale can be greatly reduced.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a current mode control type switching regulator according to the first embodiment of the present invention.
In FIG. 1, a current mode control type switching regulator (hereinafter referred to as a switching regulator) 1 steps down an input voltage Vin input to an input terminal IN to a predetermined constant voltage, and outputs the output voltage Vout from the output terminal OUT to a load 10. Synchronous rectification step-down switching regulator that outputs to

  The switching regulator 1 divides the output voltage Vout by dividing the output voltage Vout by generating a divided voltage Vfb by dividing the switching transistor M1 made of a PMOS transistor, the synchronous rectification transistor M2 made of an NMOS transistor, the inductor L1, the smoothing capacitor C1. Output voltage detection resistors R1 and R2 for output are provided. Further, the switching regulator 1 generates a reference voltage generation circuit 2 that generates and outputs a predetermined reference voltage Vref, amplifies the voltage difference between the divided voltage Vfb and the reference voltage Vref, and generates and outputs an error voltage Ve. And a slope voltage generation circuit 4 that generates and outputs a slope voltage Vslp.

  The switching regulator 1 compares the error voltage Ve from the error amplifier circuit 3 with the slope voltage Vslp and generates a pulse signal Spw for performing PWM control having a pulse width corresponding to the error voltage Ve. PWM comparator 5 for output, oscillation circuit 6 for generating and outputting a predetermined clock signal CLK, clock signal CLK from oscillation circuit 6 at set input terminal S, and pulse signal from PWM comparator 5 at reset input terminal R An RS flip-flop circuit 7 to which Spw is input and a control signal S1 for performing switching control of the switching transistor M1 and the synchronous rectification transistor M2 are generated in accordance with the output signal Sq from the RS flip-flop circuit 7. Switching transistor M1 and synchronous rectification transistor And an inverter 8 that drives 2.

  The synchronous rectification transistor M2 is a rectifying element, and the slope voltage generation circuit 4 is a slope voltage generation circuit unit. The reference voltage generation circuit 2, the error amplification circuit 3, the PWM comparator 5, the oscillation circuit 6, and the RS flip-flop circuit. 7, the inverter 8 and the resistors R1 and R2 form a switching control circuit unit. In the switching regulator 1 of FIG. 1, each circuit except the inductor L1 and the capacitor C1 may be integrated in one IC.

  A switching transistor M1 is connected between the input voltage Vin and the drain of the synchronous rectification transistor M2, and the source of the synchronous rectification transistor M2 is connected to the ground voltage GND. An inductor L1 is connected between the drain of the switching transistor M1 and the output terminal OUT, and a series circuit of a resistor R1 and a resistor R2 and a capacitor C1 are connected in parallel between the output terminal OUT and the ground voltage GND. The divided voltage Vfb, which is the voltage at the connection between the resistor R1 and the resistor R2, is input to the inverting input terminal of the error amplifier circuit 3, and the reference voltage Vref is input to the non-inverting input terminal of the error amplifier circuit 3.

  The error voltage Ve from the error amplifier circuit 3 is input to the inverting input terminal of the PWM comparator 5, and the slope voltage Vslp is input to the non-inverting input terminal of the PWM comparator 5. The output signal Sq of the RS flip-flop circuit 7 is inverted in signal level by the inverter 8 and input to the gates of the switching transistor M1 and the synchronous rectification transistor M2, and is also input to the slope voltage generation circuit 4. . The slope voltage generation circuit 4 also receives the voltage VLX at the connection LX between the switching transistor M1 and the synchronous rectification transistor M2.

Next, the operation of the switching regulator 1 will be described.
FIG. 2 is a timing chart showing an example of the waveform of each signal of the switching regulator 1 shown in FIG. 1, and the operation of the switching regulator 1 will be described with reference to FIG. Here, iout indicates an output current output from the output terminal OUT to the load 10.
A clock signal CLK that goes to a high level in a predetermined cycle is input from the oscillation circuit 6 to the set input terminal S of the RS flip-flop circuit 7, and when the clock signal CLK goes to a high level, the output signal of the RS flip-flop circuit 7 Sq goes high.

  For this reason, the low-level control signal S1 is input to the gates of the switching transistor M1 and the synchronous rectification transistor M2, respectively. The switching transistor M1 is turned on and becomes conductive, and the synchronous rectification transistor M2 is turned off and shut off. It becomes a state. In this case, the input voltage Vin is applied to the series circuit of the inductor L1 and the capacitor C1, and the inductor current iL, which is the current flowing through the inductor L1, increases linearly with time. When the inductor current iL becomes larger than the output current iout, charges are accumulated in the capacitor C1, and the output voltage Vout increases.

  The slope voltage generation circuit 4 detects the inductor current iL, converts the detected inductor current iL into a voltage, and generates a compensation voltage for preventing subharmonic oscillation. Further, the slope voltage generation circuit 4 adds the compensation voltage to the voltage obtained by converting the inductor current iL to generate and output the slope voltage Vslp. The slope voltage Vslp rises linearly while the switching transistor M1 is on. On the other hand, the error amplifier circuit 3 amplifies the voltage difference between the divided voltage Vfb and the reference voltage Vref to generate and output an error voltage Ve. The PWM comparator 5 performs voltage comparison between the error voltage Ve and the slope voltage Vslp. When the slope voltage Vslp becomes larger than the error voltage Ve, the PWM comparator 5 outputs a high level signal Spw and resets the RS flip-flop circuit 7. For this reason, the output signal Sq of the RS flip-flop circuit 7 returns to the low level, and the control signal S1 becomes the high level. Therefore, the switching transistor M1 is turned off to be cut off, and the synchronous rectification transistor M2 is turned on. It becomes conductive.

  When the switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on, the energy stored in the inductor L1 is released, and accordingly, the inductor current iL decreases linearly with time. When the inductor current iL becomes smaller than the output current iout, power is supplied from the capacitor C1 to the load 10, and the output voltage Vout decreases. After one cycle of the clock signal CLK from the oscillation circuit 6, the clock signal CLK becomes high level again, the switching transistor M1 is turned on, the synchronous rectification transistor M2 is turned off, the inductor current iL flows, and the output voltage Vout rises. .

  Here, when the output current iout suddenly increases at time T0, the output voltage Vout decreases and the error voltage Ve from the error amplifier circuit 3 increases. Therefore, the time until the slope voltage Vslp exceeds the voltage value of the error voltage Ve. Becomes longer. As a result, the ON time of the switching transistor M1 becomes longer, and the time for supplying power to the inductor L1 becomes longer, so that the output voltage Vout rises. Conversely, when the output voltage Vout increases, the on-time of the switching transistor M1 is shortened and the output voltage Vout decreases. In this manner, the voltage of the output voltage Vout is stabilized by controlling the time for which the switching transistor M1 and the synchronous rectification transistor M2 are complementarily turned on / off according to the fluctuation of the output voltage Vout.

Next, FIG. 3 is a diagram showing a circuit example of the slope voltage generation circuit 4 of FIG.
In FIG. 3, the slope voltage generation circuit 4 includes a constant current source 11 that supplies a predetermined constant current i11, an inverter 12, an operational amplifier circuit 13, PMOS transistors M11 to M14, a capacitor C11, and resistors R11 and R12. . The constant current source 11 is a first constant current source, the PMOS transistors M11 to M13, the capacitor C11 and the inverter 12 form a switched capacitor circuit, and the operational amplifier circuit 13, the PMOS transistor M14 and the resistors R11 and R12 are voltage converted. Make a circuit. The PMOS transistor M11 is a first switch element, the PMOS transistor M12 is a second switch element, the PMOS transistor M13 is a third switch element, the PMOS transistor M14 is a first transistor, and the resistor R11 is a resistor R11. The first resistor and the resistor R12 form a second resistor, respectively.

  A PMOS transistor M11 is connected between the voltage VLX and one end of the capacitor C11, and a control signal S1 is input to the gate of the PMOS transistor M11. A constant current source 11 is connected between the other end of the capacitor C11 and the ground voltage GND, and PMOS transistors M12 and M13 are connected in series between the input voltage Vin and the other end of the capacitor C11. The connection part of the PMOS transistors M12 and M13 is connected to the one end of the capacitor C11, the gates of the PMOS transistors M12 and M13 are connected, and the signal level of the control signal S1 is inverted by the inverter 12 to the connection part. The inverted signal is input.

The voltage at the connection between the capacitor C11 and the constant current source 12 is V1, and the voltage at the connection between the capacitor C11 and the PMOS transistor M11 is V2. The voltage V1 is input to the non-inverting input terminal of the operational amplifier circuit 13, and the output terminal of the operational amplifier circuit 13 is connected to the gate of the PMOS transistor M14. The source of the PMOS transistor M14 is connected to the inverting input terminal of the operational amplifier circuit 13, and a resistor R11 is connected between the input voltage Vin and the source of the PMOS transistor M14. Further, a resistor R12 is connected between the drain of the PMOS transistor M14 and the ground voltage GND, and a slope voltage Vslp is output from a connection portion between the drain of the PMOS transistor M14 and the resistor R12. The voltage at the inverting input terminal of the operational amplifier circuit 13 is V3.
A switched capacitor circuit including the PMOS transistors M11 to M13, the capacitor C11, and the inverter 12 and the constant current source 11 detect the inductor current iL.

FIG. 4 is a diagram showing an example of the waveform of each voltage in FIG. 3, and the operation of the circuit in FIG. 3 will be described with reference to FIG.
First, operations of the PMOS transistors M11 to M13 and the capacitor C11 according to the control signal S1 when the constant current i11 is not supplied from the current source circuit 11 will be described.
When the control signal S1 is at a high level, the PMOS transistor M11 is turned off and cut off, and the PMOS transistors M12 and M13 are turned on and turned on, so that both ends of the capacitor C11 are charged with the input voltage Vin. When the control signal S1 is at a low level, the PMOS transistor M11 is turned on and the PMOS transistors M12 and M13 are turned off, so that the connection between the capacitor C11 and the PMOS transistor M11 is charged with the voltage VLX, and the voltage V1 is the voltage VLX. become.

Next, the state of the voltage V1 when the constant current i11 is supplied from the constant current source 11 will be described. It is assumed that the on-resistances of the PMOS transistors M11 to M13 are sufficiently small and only a negligible voltage drop occurs even when the constant current i11 flows.
When the control signal S1 is at a high level, the PMOS transistor M11 is turned off and the PMOS transistors M12 and M13 are turned on as described above, so that both ends of the capacitor C11 are charged with the input voltage Vin.

  When the control signal S1 is at a low level, the PMOS transistor M11 is turned on and the PMOS transistors M12 and M13 are turned off, so that the connection between the capacitor C11 and the PMOS transistor M11 is charged with the voltage VLX, and at the same time with the capacitor C11. At the connection portion with the constant current source 11, the electric charge of the capacitor C11 is discharged by the constant current i11.

Here, assuming that the time when the control signal S1 switches from the high level to the low level is zero, the voltage V1 at the time T is V1 (T), and the capacitance of the capacitor C11 is c11, the voltage V1 (T) is The following equation (1) is obtained.
V1 (T) = VLX−T × i11 / c11 (1)
The first term on the right side of the equation (1) indicates that the inductor current iL is detected by converting it into a voltage, and the second term on the right side indicates that a lamp voltage having a certain slope is subtracted. ing. Therefore, the voltage V1 can be output as a slope voltage.

Next, the operational amplifier circuit 13, the PMOS transistor M14, and the resistors R11 and R12 form a voltage conversion circuit that converts the voltage V1 into a ground voltage reference voltage and outputs it. An input offset voltage Vof is provided.
The operational amplifier circuit 13 controls the gate voltage of the PMOS transistor M14 so that the voltage V3 is equal to the voltage obtained by subtracting the offset voltage Vof from the voltage V1. When the current flowing through the resistor R11 is ir11, the current ir11 is set by the PMOS transistor M14 so that the voltage V3 obtained by subtracting the voltage drop at the resistor R11 from the input voltage Vin is equal to the voltage obtained by subtracting the offset voltage Vof from the voltage V1. Therefore, if the resistance value of the resistor R11 is r11, the following equation (2) is established.
Vin−r11 × ir11 = V3 = V1−Vof
ir11 = (Vin−V1 + Vof) / r11 (2)

Furthermore, since the current ir11 flows through the resistor R12, assuming that the resistance value of the resistor R12 is r12, the slope voltage Vslp, which is the voltage at the connection between the PMOS transistor M14 and the resistor R12, is expressed by the following equation (3).
Vslp = ir11 × r12 (3)

Substituting the equations (1) and (2) into the equation (3) yields the following equation (4).
Vslp = {Vin− (VLX−T × i11 / c11) + Vof} / r11 × r12 = (Vin−VLX + T × i11 / c11) / r11 × r12 + Vof / r11 × r12 (4)
The first term on the right side of the equation (4) represents that the inductor current is converted to a voltage and a ramp voltage having a certain slope is added, and the second term on the right side represents an offset voltage. .

FIG. 5 is a diagram showing a circuit example of the operational amplifier circuit 13 of FIG.
In FIG. 5, the operational amplifier circuit 13 includes NMOS transistors M21 and M22, PMOS transistors M23 and M24, a constant current source 21 for supplying a predetermined constant current i21, and a resistor R21 for providing an offset voltage Vof. The NMOS transistors M21 and M22 form a differential pair, and the voltage V1 is input to the gate of the NMOS transistor M21, and the voltage V3 is input to the gate of the NMOS transistor M22. The PMOS transistors M23 and M24 form a current mirror circuit and form a load on the differential pair. In the PMOS transistors M23 and M24, the sources are connected to the input voltage Vin, the gates are connected, and the connection is connected to the drain of the PMOS transistor M23.

The drain of the PMOS transistor M23 is connected to the drain of the NMOS transistor M21, the drain of the PMOS transistor M24 is connected to the drain of the NMOS transistor M22, and this connection serves as the output terminal of the operational amplifier circuit 13 and the gate of the PMOS transistor M14. It is connected to the. A resistor R21 and a constant current source 21 are connected in series between the source of the NMOS transistor M21 and the ground voltage GND, and a source of the NMOS transistor M22 is connected to a connection portion between the resistor R21 and the constant current source 21.
In order for the same current to flow through the NMOS transistors M21 and M22, the gate voltage of the NMOS transistor M21 must be larger than the gate voltage of the NMOS transistor M22 by the voltage drop generated by the resistor R21. That is, the voltage drop generated in the resistor R21 becomes the offset voltage Vof, and the operational amplifier circuit 13 is provided with the offset voltage Vof at the input terminal by providing the resistor R21.

FIG. 6 is an enlarged view of the waveform of the slope voltage Vslp generated by the slope voltage generation circuit 4 of FIG.
As can be seen from FIG. 6, since the delay generated in the slope Vslp than before can be reduced, the linearity of the slope voltage Vslp is maintained immediately after the control signal S1 becomes low level.

As described above, the current mode control type switching regulator according to the first embodiment includes a voltage-current conversion circuit, a current mirror circuit, and a current mirror circuit that are used in the conventional slope voltage generation circuit and delay the rising of the slope voltage Vslp. Since an adding circuit composed of a resistance element is not required, as shown in FIGS. 4 and 6, it is possible to generate a slope voltage Vslp with good linearity immediately after the control signal S1 changes to a low level. Even when the on-time of the switching transistor M1 is short, stable operation can be performed.
Furthermore, since the operational amplifier circuit 124, NMOS transistor M126, PMOS transistors M127 and M128, resistors R123, R124, R125, R126, and elements corresponding to the current source i122 can be reduced from the conventional circuit of FIG. Can be reduced to less than half.

  In the above description, the operational amplifier circuit 13 of the slope voltage generation circuit 4 is provided with the offset voltage Vof and the voltage conversion circuit is provided with the predetermined offset voltage Vof. However, the operational amplifier circuit 13 is provided with the offset voltage Vof. Instead, as shown in FIG. 7, a constant current source 14 that supplies a predetermined constant current i14 may be provided between the input voltage Vin and the drain of the PMOS transistor M14. The constant current source 14 forms a second constant current source. In this case, since a current obtained by adding the constant current i14 to the output current of the PMOS transistor M14 flows through the resistor R12, an increase in voltage drop generated by the resistor R12 due to the constant current i14 flowing (i14 × r12) Becomes the offset voltage Vof.

  In the above description, the synchronous rectification step-down switching regulator has been described as an example. However, this is an example, and the present invention is an asynchronous rectification step-down type using a diode instead of the synchronous rectification transistor M2. The present invention can also be applied to a switching regulator and a step-up switching regulator.

It is the figure which showed the circuit example of the current mode control type switching regulator in the 1st Embodiment of this invention. 2 is a timing chart showing an example of the waveform of each signal in FIG. 1. It is the figure which showed the circuit example of the slope voltage generation circuit 4 of FIG. It is the figure which showed the example of a waveform of each voltage of FIG. FIG. 4 is a diagram illustrating a circuit example of an operational amplifier circuit 13 in FIG. 3. It is the figure which expanded the waveform of the slope voltage Vslp produced | generated by the slope voltage generation circuit 4 of FIG. It is the figure which showed the other circuit example of the slope voltage generation circuit 4 of FIG. It is the block diagram which showed the example of the conventional current mode control type switching regulator. FIG. 9 is a diagram illustrating a circuit example of the slope voltage generation circuit 120 in FIG. 8. It is the figure which showed the example of a waveform of the slope voltage Vslp produced | generated by the slope voltage generation circuit 120 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Switching regulator 2 Reference voltage generation circuit 3 Error amplification circuit 4 Slope voltage generation circuit 5 PWM comparator 6 Oscillation circuit 7 RS flip-flop circuit 8, 12 Inverter 10 Load 11, 14 Constant current source 13 Operation amplification circuit M1 Switching transistor M2 Synchronous rectification Transistors M11 to M14 PMOS transistor L1 Inductor C1, C11 Capacitor R1, R2, R11, R12 Resistance

Claims (7)

In the current mode control type switching regulator that converts the input voltage input to the input terminal into a predetermined constant voltage and outputs it as an output voltage from the output terminal.
A switch transistor that performs switching according to a control signal input to the control electrode;
An inductor charged by the input voltage by switching of the switching transistor;
A rectifying element for discharging the inductor;
A slope voltage generation circuit unit that generates a voltage proportional to the inductor current flowing through the inductor when charging the inductor and outputs the voltage as a slope voltage;
A switching control circuit unit that performs switching control of the switching transistor according to the slope voltage;
With
The slope voltage generation circuit unit is
A switched capacitor circuit that performs switching according to a control signal input to a control electrode of the switching transistor, converts the inductor current into a voltage, and outputs the voltage;
A first constant current source for charging or discharging the switched capacitor circuit with a predetermined constant current;
A current mode control type switching regulator. The switched capacitor circuit is:
A capacitor that is charged or discharged with a constant current from the first constant current source;
A first switch element connected between one end of the capacitor and one end of the inductor on the switching transistor side;
A second switch element connected between the one end of the capacitor and the input voltage;
A third switch element connected in parallel to the capacitor;
With
The first constant current source is connected between the other end of the capacitor and a ground voltage, and the first switch element performs the same switching operation as the switching transistor, and the second and third switches. The current mode control type switching regulator according to claim 1, wherein the element performs a switching operation opposite to the switching transistor.   3. The current mode control type switching regulator according to claim 2, wherein the slope voltage generation circuit unit outputs a voltage at a connection portion between the capacitor and the first constant current source as the slope voltage.   The slope voltage generation circuit unit includes a voltage conversion circuit that converts a voltage at a connection between the capacitor and the first constant current source into a ground voltage reference voltage and outputs the voltage as the slope voltage. The current mode control type switching regulator according to claim 2. The voltage conversion circuit includes:
An operational amplifier circuit in which the voltage at the connection between the capacitor and the first constant current source is input to one input terminal;
A first transistor having a control electrode connected to the output terminal of the operational amplifier circuit and a current input terminal connected to the other input terminal of the operational amplifier circuit;
A first resistor connected between the input voltage and a current input terminal of the first transistor;
A second resistor that converts the current output from the first transistor into a voltage to generate the slope voltage;
The current mode control type switching regulator according to claim 4, further comprising:   6. The current mode control type switching regulator according to claim 5, wherein the operational amplifier circuit is provided with a predetermined offset voltage at at least one input terminal.   6. The current mode control type switching regulator according to claim 5, wherein the voltage conversion circuit includes a second constant current source that supplies a predetermined constant current to the second resistor.

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