JP2010050422A - Heat-resistant semiconductor package and method of manufacturing package - Google Patents

Abstract

[PROBLEMS] To realize a high heat-resistant package without using a resin containing a solvent, without using Al wire bonding, forming a radiator, performing hermetic sealing, and a relatively simple manufacturing method. A means to satisfy certain conditions is provided.
In a semiconductor package in which bumps formed on the active surface side of a semiconductor chip are bonded to a conductive layer pattern formed on a multilayer ceramic substrate and sealed with a lid, the center portion of the lid is a semiconductor A semiconductor package characterized in that it is soldered via a metal layer 6 formed on the back side of the chip, and an end of the lid is welded to a seal metal layer 5 formed on a multilayer ceramic substrate.
[Selection] Figure 1

Description

  The present invention relates to a heat-resistant power semiconductor package that enables high-temperature operation and a method for manufacturing the package.

  As a power semiconductor, SiC, which is said to have a loss that is two orders of magnitude smaller than Si, has attracted attention. If the SiC semiconductor is replaced with the Si semiconductor, the loss of the power conversion device is reduced, which is extremely effective as an energy saving measure. Further, since the SiC semiconductor can operate at a high temperature reaching about 400 ° C., energy saving can be expected by eliminating the need for a cooling system. Several requirements are listed below as packaging technology requirements for enabling high temperature operation. (1) Organic resins usually used for adhesives and molds are not heat resistant and cannot be used. (2) Wire bonding with Al is difficult to use due to deterioration due to intermetallic reaction with Au. (3) Seal hermetic (completely airtight) to block contact with outside air. (4) Since the semiconductor is a heating element, it must have a structure that can dissipate heat from at least one surface of the chip. (5) The structure and manufacturing method of the semiconductor device is simple and can be provided at a relatively low cost. Regarding (2), since the operating current of the power semiconductor is several tens of A, an Al wire having a diameter larger than that of the Au wire is usually used.

  Although it seems that there is still no packaging technology that satisfies the requirements (1) to (5), the conventional technology with a slight sacrifice of the hermetic sealing of (3) is disclosed in non-patent literature. Basically, a SiC chip is embedded in a region where the ceramic substrate is cut to the size of the SiC chip and fixed with an adhesive. The fixing is mainly based on an adhesive applied to the side surface of the SiC chip. A heat sink made of a Cu layer is formed on the exposed portions of the front and back surfaces of the SiC chip, or a wiring board made of the Cu layer is formed to eliminate a portion where the SiC chip is exposed to the outside air. The adhesive for fixing the SiC chip has heat resistance, and Resbond 919 (trade name) is designated as a ceramic resin having a thermal expansion coefficient close to that of SiC. As a result, the SiC chip is blocked from contact with the outside air by the ceramic resin and the Cu layer. However, it is difficult to completely volatilize the solvent component of the ceramic resin, and movement at the molecular level occurs with volatilization. It is said that water molecules and gas molecules in the outside air come and go with this movement, which is called semi-hermetic sealing. The thickness of the SiC chip is 600-700 microns, and a ceramic substrate of the same thickness will be used, but the substrate after the SiC chip is fixed with an adhesive is attached to an appropriate support substrate. Need to be done. Due to the processing of the front and back surfaces of the substrate, attachment to and removal from the support substrate occurs, and it is predicted that the substrate will crack and the adhesive will crack due to mechanical stress on the ceramic substrate. In such a manufacturing method, it is difficult to use a large-diameter ceramic substrate, and there is a problem in terms of productivity (5).

  There is also a method in which a plurality of semiconductor chips are arranged on a substrate to form a module, and the module substrate is housed in an airtight container (Patent Document). This method increases the number of manufacturing steps and is somewhat complicated.

Jian Yin, Zhenxian Liang and Jacobus Daniel van Wyk, IEEE TRANSACTIONS ON POWER ELECTRICNICS, Vol. 22, NO. 2, March 2007, 392-398 JP2007-53379

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a heat-resistant packaging structure and a manufacturing method for operating a power semiconductor at a high temperature.

  To realize heat-resistant packaging, do not use a resin containing solvent, perform bump bonding using a metal with a high melting point instead of Al wire bonding, form a heat sink, perform hermetic sealing And the manufacturing method is relatively simple.

In order to achieve the above object, the present invention employs the following structure and manufacturing method.
Claim 1:
In a semiconductor package in which bumps formed on the active surface side of a semiconductor chip are bonded to a conductive layer pattern formed on a multilayer ceramic substrate and sealed with a lid, the center portion of the lid is formed on the back side of the semiconductor chip. The end of the lid is welded to a sealing metal layer formed on a multilayer ceramic substrate.
Claim 2:
The upper surface of the metal layer formed on the back side of the semiconductor chip is located higher than the upper surface of the seal metal layer.
Claim 3:
The metal layer formed on the upper surface of the semiconductor chip is characterized in that Au or Cu, Ni, and Au are sequentially laminated.
Claim 4:
The center of the lid is soldered with gold eutectic solder.
Claim 5:
Forming bumps on the active surface side of the semiconductor chip; bump-bonding the semiconductor chip to a conductive layer pattern formed on the multilayer ceramic substrate; and photolithography and electroplating. A step of forming a Cu layer on the back side, a step of polishing or grinding the Cu layer to make the height of a plurality of semiconductor chips bump-bonded to the multilayer ceramic substrate uniform, a photolithography method and an electroplating method The step of forming Ni and Au on the Cu layer in sequence using a metal, the step of cutting the multilayer ceramic substrate into individual packages, and the metal formed on the back side of the semiconductor chip with the lid center part A step of soldering to the layer, and a sealing metal layer in which the lid end is previously formed on the multilayer ceramic substrate Characterized in that it comprises the step of welding.
Claim 6:
The Cu layer is an Au layer, and the step of sequentially forming Ni and Au is eliminated.
Claim 7:
In a semiconductor package having a cavity formed by removing the upper layer of the multilayer ceramic substrate, bonding a bump formed on the active surface side of the semiconductor chip to the conductive layer pattern in the cavity, and sealing with a lid, The center of the lid is soldered to a metal layer formed on the back side of the semiconductor chip, and the end of the lid is soldered to a seal metal layer formed on a multilayer ceramic substrate outside the cavity. .
Claim 8:
6. The method of manufacturing a semiconductor package according to claim 5, wherein the lid center portion and the lid end portion are soldered simultaneously using gold eutectic solder.

  According to the present invention, it is possible to realize packaging of a power semiconductor capable of high-temperature operation, particularly SiC semiconductor, with high productivity.

Hereinafter, the present invention will be described in more detail.
One structural example of the semiconductor package of the present invention is shown in FIG. FIG. 1A is a schematic external view showing a state in which the SiC-MOSFET 1 is bump-bonded to the multilayer ceramic substrate 2, and FIG. 1B is a schematic external view showing the lid 3. In general, in a SiC-MOSFET, a gate electrode and a source electrode are formed on the active surface side, and a drain electrode is formed on the back side thereof. In the embodiment, bumps are formed on the gate electrode and the source electrode on the active surface side. It is desirable to adopt a structure that greatly releases heat from the drain electrode surface on the back side. The material of the bump is generally Au or Cu, and may be formed by electrolytic plating, or a stud bump using an Au wire can be formed. The SiC-MOSFET having the bump formed thereon is bonded to the conductive layer pattern 3 of the multilayer ceramic substrate by thermocompression bonding or ultrasonic thermocompression bonding. In the case of Au bumps, the conductive layer pattern is preferably Au, and in the case of Cu bumps, the conductive layer pattern is preferably Cu.

  A sealing metal layer 4 is formed on the multilayer ceramic substrate. The seal metal layer 5 is welded to the lid and hermetically sealed, but it is preferable that the seal metal layer 5 be formed to be as thick as possible by matching the ceramic substrate and the coefficient of thermal expansion (CTE) as much as possible. The thermal expansion coefficient is preferably close to that of a semiconductor. In this example, Fe—Co—Ni-based metal (CTE: 5.1 ppm / ° C.) was used for the seal metal layer, and surface finishing was performed with Ni and Au. The seal metal layer 5 and the lid use parallel gap seam welding or electron beam welding as will be described later. In this case, the thickness of the seal metal layer is preferably about 0.8 mm to 1 mm. The material of the lid 3 is preferably close to the thermal expansion coefficient of the semiconductor in order to reduce the thermal strain on the semiconductor chip. Fe—Co—Ni-based metal was used, and surface finishing was performed with Ni and Au to prevent oxidation and corrosion. CuMo metal or CuW metal may be used in addition to the Fe—Ni—Co based metal. These materials generally do not have good heat conduction. From the viewpoint of improving heat dissipation from the lid at the expense of thermal strain, it is possible to use Cu or a composite material of Cu and C. As a material for the ceramic, AlN (CTE: 4.5 ppm / ° C.) is a suitable material close to the thermal expansion coefficient of SiC (CTE: 4.0 ppm / ° C.). When the semiconductor chip can be downsized and the semiconductor package can be downsized, Al2O3 (CTE: 7 ppm / ° C.) can also be used because thermal distortion is not a big problem.

  A metal layer 6 is formed on the drain electrode side of the SiC-MOSFET, and the height of the upper surface of the metal layer is set to be higher than the height of the upper surface of the seal metal layer 5. The center of the lid 3 is in contact with the metal layer 6 of the drain electrode to form a heat radiating body, and therefore a counterbore 7 corresponding to the above height is inserted. The metal layer is preferably formed thick as will be described later. For example, Au or Cu is suitable for electrolytic plating. In the case of Cu, Ni and Au are formed thinly thereon to prevent oxidation and corrosion. The contact with the lid is made by soldering. The solder is suitably a high melting point solder such as AuGe (for example Ge 12%, melting point 356 ° C.) or AuSi (for example Si 3.15%, melting point 363 ° C.), but may be other gold eutectic solder such as AuTe. The lid end is welded to the metal layer 5 to provide a complete hermetic seal.

  As a usage of the semiconductor package according to the present invention, a semiconductor package and circuit components are mounted on a power module substrate to constitute a power switch, a power supply bridge, a power rectifier and the like. At this time, in order for the semiconductor package of the present invention to dissipate heat by bringing the lid portion into contact with the module substrate, a flat region is required on the upper surface of the lid as shown in FIG. Further, since the gate and source signal electrodes are taken out from the back surface side 8 of the multilayer ceramic substrate, they are preferably taken out from the back surface of the multilayer ceramic substrate through the through holes. Lead attachment as an external terminal can be performed by spot welding. The above is an example of mounting on a power module substrate, and the present invention is not limited to this. Therefore, in the semiconductor package of the present invention, there are no limitations on how to form through holes in the multilayer ceramic substrate, draw out electrodes on the back surface of the substrate, or attach lead terminals or pin terminals for external connection.

  Next, the manufacturing process of the semiconductor package according to the present invention will be described. 2A to 2I are sectional views of the steps. (A) shows the multilayer ceramic substrate 2 on which the through hole 8 that connects the conductive layer pattern 3 and the conductive layer pattern on the front and back of the substrate and the seal metal layer 5 are formed. The seal metal layer is obtained by performing Ni and Au surface treatment on Fe-Ni-Co-based metal. About 0.8 mm was selected as the thickness (height) of the seal metal layer. (B) shows a cross section in which a semiconductor chip, in the case of the present embodiment, SiC-MOSFET 1 is bump bonded to this substrate. The bump is previously formed in the SiC-MOSFET. When bumps are formed by electrolytic plating, Au bumps or Cu bumps can be formed in the wafer manufacturing process. In the case of forming a stud bump using Au wire, it can be formed after the wafer manufacturing process is completed and formed into chips. The bump metal is not particularly limited, but Au is preferable because the surface is difficult to be oxidized and is ductile and can be easily joined by thermocompression bonding. In this case, it is desirable that the conductive layer pattern is also surface-treated with Au. A bump thickness of about 30 μm is sufficient, but the bump area should be designed according to the operating current value. In particular, since power semiconductors carry tens of A, care must be taken because if the bump area is small, metal migration occurs simultaneously with heat generation, causing cracks and disconnection. The chip thickness of the SiC-MOSFET is about 700 μm.

In the step (c), a photoresist is coated. According to the above numerical value, the level difference due to the seal metal layer, SiC-MOSFET, etc. is about 0.8 mm. Therefore, it is desirable to cover this level difference and flatten the photoresist. There is TMMR (manufactured by Tokyo Ohka Kogyo Co., Ltd.) as a thick film forming photoresist, which can form a thick film of about 700 μm. In this step, since the aspect ratio of the resist pattern is not concerned, the photoresist was flattened by applying twice by spin coating. The final thickness by double coating was about 1 mm, and the stepped portion was sufficiently covered. UV exposure is performed through a glass mask, and the upper surface of the SiC-MOSFET is punched with a TMMR developer (PM thinner). In the step (d), a metal thin film 11 that is an electrode for electrolytic plating is deposited on the entire surface of the substrate, and a photoresist film 12 is formed in addition to the holed portion of the SiC-MOSFET as shown in the figure. The photoresist was formed to a thickness of about 100 μm using TMMR.

  In the step (e), electrolytic plating of Au is performed. A cyan gold plating solution was used as the plating solution, and an Au layer was formed to a thickness of about 300 μm. Since the chip thickness of the SiC-MOSFET is about 0.7 mm, the height of the chip is about 1 mm, which is higher than the height of the seal metal layer 5 of 0.8 mm. In the step (f), a predetermined amount of the Au layer is polished or ground in order to make the height of the SiC-MOSFET uniform while being covered with a photoresist or the like. The polishing amount is determined so as to eliminate the non-flatness of the metal layer 6 due to the height variation of the plurality of SiC-MOSFETs bump-bonded to the multilayer ceramic substrate and the chip inclination. For example, when the inclination is several tens of μm and the SiC-MOSFET chip thickness variation is about 50 μm, it is sufficient to polish about 100 μm. However, when polishing, it is necessary to set the polishing amount so as not to polish the seal metal layer. Therefore, it is important that the height of the SiC-MOSFET when polishing is finished is always higher than that of the seal metal layer. Since how much higher than the seal metal layer will determine the shape of the lid as will be described later, it is also necessary to estimate in advance. In the above numerical example, the height of the SiC-MOSFET is about 100 μm higher than the seal metal layer. Polishing or grinding may be performed by a back grinder used for polishing a Si substrate, or a cutting flattening apparatus that has been technically disclosed as a precise grinding flattening method in recent years (Journal of Electronics Packaging Society, Vol. 11, No. 3, 2008, p218) can be used. A cross section of the flattened multilayer ceramic substrate is shown in FIG. A cross section obtained by dissolving and removing the photoresist with an organic solvent is shown in FIG. Next, the multilayer ceramic substrate is cut to separate the packaging of the SiC-MOSFET. This is shown in (h). Cutting can be performed by blade dicer or laser.

  As shown in the process diagram of (i), the lid 4 must be shaped so that the upper surface of the SiC-MOSFET can be soldered to the lid 4 and the end of the lid can be joined to the seal metal layer 4. It is. As described above, since the height of the SiC-MOSFET including the metal layer is set to be higher than that of the seal metal layer, the lid 4 needs the countersink 14. In the case of the above numerical example, the amount of countersink is slightly over 100 μm. As described above, the eutectic gold eutectic solder having a high melting point is preferable, and AuGe (Ge 12%) or AuSi (Si 3.15%) is preferable. Next, the lid end is welded to the seal metal layer 5. By using parallel gap seam welding, electron beam welding, etc. for welding, complete hermeticity and heat resistance can be secured.

  In the manufacturing process described above, Au was formed to a thickness of 300 μm in the process (e). Considering that Au is an expensive metal, it is preferable to replace it with Cu. By using a mixed solution of CuS04 · 5H20 and H2S04 as a plating bath, Cu can be thickly plated using the aforementioned photoresist. After forming Cu to a thickness of 300 μm, the Cu layer is polished in the step (f). After dissolving the photoresist, a hole with the photoresist and a metal thin film as an electrode for electrolytic plating are formed in the same manner as in the steps (c) to (d), and Ni and Au are sequentially formed by plating. If the Ni thickness is about 1 μm and the Au thickness is about 2 to 3 μm, soldering with gold eutectic solder can be performed without any problem. Thereafter, the multilayer ceramic substrate is cut (step (h)) and the lid is welded (step (i)) to complete hermetic sealing.

  Next, another structural example of the semiconductor package of the present invention will be described below. 3A and 3B are schematic external views of the lid 4 and the multilayer ceramic substrate 2 separated into pieces. The lid 4 is formed with a countersink 14 at a portion where it is joined to a semiconductor chip (SiC-MOSFET) as in FIG. The material and surface finish are as described above. In the multilayer ceramic substrate shown in (b), the cavity 15 is formed by removing the upper ceramic layer. Conductive layer pattern 3 is formed on the ceramic substrate surface in the cavity, and SiC-MOSFET 1 is bump bonded. Further, a metal layer 6 is formed on the upper surface of the SiC-MOSFET 1, and the countersink 14 of the lid is soldered. The sealing metal layer 5 is formed on the ceramic substrate outside the cavity 15, and the lid end is soldered to the sealing metal layer to be hermetically sealed. In the case of soldering in this embodiment, a metal thin film having a thickness of several μm is sufficient for the seal metal layer 5 as shown in FIG. For example, a metal thin film can be formed by applying a W paste to a ceramic substrate, sintering the paste at a high temperature, and successively performing electrolytic plating of Ni and Au thereon. As will be described later in the manufacturing process, since the lid is soldered at two locations of the SiC-MOSFET and the seal metal layer, the same solder is used for simultaneous soldering.

  As the solder, gold eutectic solder having a melting point as high as possible is preferably used. As described above, AuGe (for example, Ge 12%, melting point 356 ° C.) or AuSi (for example, Si 3.15%, melting point 363 ° C.) can be used. As described above, the material of the lid 4 can be selected from Fe—Ni—Co, CuW, and CuMo metals that have been subjected to surface finishing of Ni and Au. In addition, since this embodiment uses soldering, a lid in which a surface finish of Ni and Au is applied to a ceramic material can also be used. In particular, AlN is a suitable ceramic material because it has high thermal conductivity and a thermal expansion coefficient close to that of a semiconductor.

  4A to 4F show the manufacturing process of this embodiment. In the step (a), reference numeral 2 denotes a multilayer ceramic substrate, and the upper layer is removed to form the cavity 15. The seal metal layer 5 is formed outside the cavity 15, and the conductive layer pattern 3 is formed inside the cavity 15. The conductive layer pattern 3 is drawn out to the back side of the multilayer ceramic substrate through the through hole 8. In the step (b), the SiC-MOSFET 1 is bump-bonded. In the step (c), the upper surface of the SiC-MOSFET 1 is punched using a photoresist 10 that can be formed thick, and a metal thin film 11 that serves as an electrode for electrolytic plating is formed on the entire surface of the photoresist. Further, a photoresist is formed so as to be plated only on the upper surface of the SiC-MOSFET. In the step (d), electrolytic plating of Au is performed. The plating is preferably formed thick for the reason described in FIG. Next, after polishing or grinding the substrate, the photoresist is dissolved to obtain a cross-sectional view of FIG. It is necessary to set the height of the metal layer 6 after polishing higher than that of the seal metal layer 5 for the reason already described. In the step (f), the lid 4 is simultaneously soldered to the SiC-MOSFET 1 and the seal metal layer 5 using gold eutectic solder to complete hermetic sealing.

  As described above, it can be understood that the heat resistance of the packaging of the present invention is at least 300 ° C. or higher. In addition, the upper limit temperature of heat resistance is determined by the solder, and the heat resistance can be further improved by selecting a gold eutectic solder having a higher melting point.

FIG. 2 is a schematic external view of a multilayer ceramic substrate (a) a lid and (b) singulated according to claim 1. It is explanatory drawing which shows the manufacturing process which concerns on Claim 1. It is a schematic external view of (a) a lid and (b) a separated multilayer ceramic substrate according to claim 2. It is sectional drawing which shows the manufacturing process which concerns on Claim 2.

Explanation of symbols

1 SiC-MOSFET
2 Multilayer ceramic substrate 3 Conductive layer pattern 4 Lid 5 Seal metal layer 6 Metal layer 7 Multilayer ceramic substrate back surface 8 Through hole 9 Bump 10 Photoresist 11 Thin film metal 12 Photoresist 13 Au layer 14 Countersink 15 Cavity

Claims (8)

  In a semiconductor package in which bumps formed on the active surface side of a semiconductor chip are bonded to a conductive layer pattern formed on a multilayer ceramic substrate and sealed with a lid, the center portion of the lid is formed on the back side of the semiconductor chip. A semiconductor package, wherein the lid is soldered via a metal layer, and an end of the lid is welded to a seal metal layer formed on a multilayer ceramic substrate.   2. The semiconductor package according to claim 1, wherein the upper surface of the metal layer formed on the back side of the semiconductor chip is located higher than the upper surface of the seal metal layer.   3. The semiconductor package according to claim 1, wherein the metal layer formed on the upper surface of the semiconductor chip is a laminate of Au, Cu, Ni, and Au sequentially.   4. The semiconductor package according to claim 1, wherein the lid central portion is soldered with gold eutectic solder.   Forming bumps on the active surface side of the semiconductor chip; bump-bonding the semiconductor chip to a conductive layer pattern formed on the multilayer ceramic substrate; and photolithography and electroplating. A step of forming a Cu layer on the back side, a step of polishing or grinding the Cu layer to make the height of a plurality of semiconductor chips bump-bonded to the multilayer ceramic substrate uniform, a photolithography method and an electroplating method Sequentially forming Ni and Au on the Cu layer by using a metal, cutting the multilayer ceramic substrate to separate the package, and forming the metal at the center of the lid on the back side of the semiconductor chip. A step of soldering to the layer, and a sealing metal layer in which the lid end is previously formed on the multilayer ceramic substrate The method of manufacturing a semiconductor package, which comprises the step of welding.   6. The method of manufacturing a semiconductor package according to claim 5, wherein the Cu layer is an Au layer and the step of sequentially forming Ni and Au is omitted.   In a semiconductor package having a cavity formed by removing the upper layer of the multilayer ceramic substrate, bonding a bump formed on the active surface side of the semiconductor chip to the conductive layer pattern in the cavity, and sealing with a lid, The center of the lid is soldered to a metal layer formed on the back side of the semiconductor chip, and the end of the lid is soldered to a seal metal layer formed on a multilayer ceramic substrate outside the cavity. Semiconductor package.   6. The method of manufacturing a semiconductor package according to claim 5, wherein the center portion of the lid and the end portion of the lid are soldered simultaneously using gold eutectic solder.

Images