JP2010045504A - Pll frequency synthesizer circuit and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stable PLL frequency synthesizer circuit without increasing noise with respect to a signal, and to provide a control method thereof. <P>SOLUTION: The PLL frequency synthesizer circuit monitors the control voltage of a voltage controlled oscillator and switches a loop filter set so as to stably operate with the modulation sensitivity of the voltage controlled oscillator in accordance with the control voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a PLL frequency synthesizer circuit and a control method thereof.

A broadband PLL (Phase Locked Loop) frequency synthesizer circuit related to the present invention will be described with reference to FIG.
FIG. 4 is a block diagram of a wideband PLL frequency synthesizer circuit relevant to the present invention.
The broadband PLL frequency synthesizer shown in FIG. 4 includes a voltage controlled oscillator (Voltage Controlled Oscillator: hereinafter referred to as “VCO”) 42 having a plurality of modulation sensitivity (hereinafter referred to as “Kv”) curves, and a VCO 42. Frequency divider 44 that divides the output signal by 1 / N, phase comparator 41 that compares the output signal of frequency divider 44 with reference signal S41 from the reference signal source, It comprises a loop filter 43 that smoothes the output signal S43 and outputs it to the VCO 42.

Here, Patent Documents 1 and 2 describe examples of techniques related to the PLL frequency synthesizer circuit.
The “radio device” of Patent Document 1 is “in a radio device having a VCO circuit and a PLL circuit, having a loop filter circuit and a switch having a plurality of characteristics resulting from the switching and using an optimum loop filter according to a set frequency”. It is characterized by this.

  According to this "radio device", the optimum loop based on the modulation sensitivity of the switch and VCO circuit is used because the modulation sensitivity deviation is large at both ends of the VCO control voltage range and various characteristics have deteriorated. Widely use the control voltage-oscillation frequency characteristic of the VCO circuit by suppressing the deterioration of various characteristics due to the modulation sensitivity deviation within the VCO control voltage range by switching the loop filter according to the set frequency by having multiple filter characteristics It is possible to increase the bandwidth of the VCO.

  The “wideband modulation PLL” of Patent Document 2 is “a voltage-controlled oscillator, a frequency divider that divides the output signal of the voltage-controlled oscillator, and a signal corresponding to the phase difference between the output signal of the frequency divider and the reference signal. A PLL unit including a phase comparator to output, a loop filter that averages the output of the phase comparator and outputs to the voltage controlled oscillator, and a first modulated signal is input to the voltage controlled oscillator based on the input modulation data And a first modulation input unit that performs modulation, and a second modulation input unit that inputs a second modulation signal at a position different from the voltage-controlled oscillator of the PLL unit based on the modulation data. The oscillator has a first control terminal to which a first modulation signal is input, and a second control terminal to which a signal based on the second modulation signal is input. The first modulation input unit includes: Modulation for calculating first modulation sensitivity at one control terminal A degree calculating unit, based on the first modulation sensitivity is calculated and a modulation factor adjusting means for outputting a first modulated signal by adjusting the modulation depth of the modulated data "and is characterized in that.

According to this “PLL”, since a lookup table for each channel is not required, it is possible to provide a wideband modulation PLL that is small and inexpensive and has low power consumption. Furthermore, since it is possible to follow environmental changes during actual use, such as every initial operation or normal modulation operation, it is possible to provide a wideband modulation PLL that always realizes good and stable modulation accuracy.
JP 2004-221822 A JP 2005-72876 A

FIG. 5 shows a Kv curve of the VCO 42 in the wide-band PLL frequency synthesizer circuit shown in FIG. In FIG. 5, the horizontal axis represents the output frequency, and the vertical axis represents the control voltage.
When the output frequency of the VCO 42 crosses two Kv curves, the modulation sensitivity Kv may be used at the maximum and minimum due to the nonlinear characteristic of the modulation sensitivity.

  Here, when the output frequency of the wideband PLL frequency synthesizer circuit is widened by a VCO having a plurality of modulation sensitivity curves, switching of the modulation sensitivity curve occurs when the output frequency is set. For example, the control voltage of the VCO 42 fluctuates due to a temperature change. In this case, even if the same frequency is set, the modulation sensitivity curve is switched, and the modulation sensitivity changes from the minimum to the maximum.

When the modulation sensitivity increases, the loop gain using the modulation sensitivity as a parameter increases, so that there is a problem that the loop band becomes wide and the frequency does not lock and oscillates.
Further, when the modulation sensitivity is decreased, the loop gain is decreased, so that the loop band is narrowed, and the noise near the output frequency is deteriorated, that is, there is a problem that noise with respect to the signal is increased.

  Note that differences between Patent Documents 1 and 2 and the present application will be described later.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a stable PLL frequency synthesizer circuit that does not increase noise with respect to a signal and a control method thereof.

  The first device of the present invention monitors the control voltage of the voltage controlled oscillator, and switches the loop filter set to operate stably with the modulation sensitivity of the voltage controlled oscillator according to the control voltage. It is characterized by that.

  According to the first method of the present invention, the phase difference between the reference signal input from the outside to the phase comparator and the output from the voltage controlled oscillator connected to the phase comparator via the loop filter is made constant. In addition, the voltage-controlled oscillator oscillates by applying feedback to the phase comparator with a frequency divider, monitors the control voltage of the voltage-controlled oscillator, and adjusts the modulation sensitivity of the voltage-controlled oscillator according to the control voltage. A method for controlling a PLL frequency synthesizer circuit, wherein a loop filter set to operate stably is switched.

  According to the present invention, it is possible to provide a stable PLL frequency synthesizer circuit and a control method thereof without increasing noise with respect to a signal.

<Features>
The PLL frequency synthesizer circuit according to the present invention is a PLL module in which a voltage controlled oscillator (VCO) function and a PLL (Phase locked Loop) function are mounted inside, and in particular, the output frequency of the VCO is widened by a plurality of modulation sensitivity (Kv) curves. In the PLL module, when the Kv curve is switched by resetting the frequency, especially when the modulation sensitivity of the VCO is changed by resetting the frequency near the control voltage of the VCO at which the Kv curve switches, the VCO control is performed. A voltage is detected by the A / D converter, a switching signal of a loop filter (LF) corresponding to the digital signal of the A / D converter is output from the control unit, and a loop filter (corresponding to a preset control voltage of the VCO ( LF) and cancel the amount of change in the modulation sensitivity so that the amount of change in the loop band Featuring less.

FIG. 1 shows a block diagram of an embodiment of a PLL frequency synthesizer according to the present invention.
<Configuration>
The PLL frequency synthesizer shown in FIG. 1 includes a reference signal source 1, a phase comparator 2, a loop filter 3, a voltage controlled oscillator 4, and a frequency divider 5.

  A reference signal source (not shown) outputs a reference signal S1. The phase comparator 1 compares the phases of the reference signal S1 and the frequency-divided signal S4 divided by the frequency divider 4, and outputs the difference signal S3. The loop filter 3 smoothes the difference signal S3 from the phase comparator 1 and generates a DC voltage S5. In the VCO2, the oscillation frequency of the output signal S2 is controlled by the DC voltage S5. The frequency divider 4 divides the output signal from the VCO 2 and outputs a frequency-divided signal S 4 to the phase comparator 1.

  Further, the analog-digital converter (A / D converter) 5 converts the DC voltage generated by the loop filter 3 into a digital signal S5. The control unit 6 outputs a switching signal S6 of the loop filter 3 to the loop filter 3 by the digital signal S7 from the A / D converter 5.

FIG. 3 shows an example of a block diagram of a loop filter used in the PLL frequency synthesizer shown in FIG.
The loop filter 34 shown in FIG. 3 includes a changeover switch 31, a changeover switch 32, a loop filter 33 having a first modulation sensitivity range, and a loop filter having a second modulation sensitivity range that is smaller than the first modulation sensitivity range. 34.

The changeover switches 31 and 32 change the loop filter according to a changeover signal S6 output from the control unit 7.
An example of the changeover switch 31 is a demultiplexer, and an example of the changeover switch 32 is a multiplexer.

  In FIG. 1, the control voltage S5 of the VCO 2 smoothed by the loop filter 3 (LF) is distributed to the VCO 2 and the A / D converter 5. The control voltage S5 of the distributed VCO 2 is converted into a digital signal S7 by the A / D converter 5. The control unit 6 outputs a signal S6 for switching to the loop filter 3 corresponding to the digital signal S7. The switched loop filter 3 (LF) is set to a constant that makes the change in the loop band small with respect to the change in the modulation sensitivity Kv of the VCO 2.

<Operation>
The operation of the PLL frequency synthesizer shown in FIG. 1 will be described below.
The output signal S3 of the phase comparator 2 becomes a voltage smoothed by the loop filter 3, and is converted to a digital signal S7 by the A / D converter 5. The controller 6 receives the digital signal S7 and outputs the digital signal S6 to the loop filter 3. The loop filter 3 performs switching to the loop filter 33 or the loop filter 34 in which the change of the loop band is less than the modulation sensitivity Kv of the VCO from the digital signal S6.

FIG. 2 shows the relationship between the modulation sensitivity curve of the VCO of the PLL frequency synthesizer shown in FIG. 1 and the control voltage of the VCO that switches the loop filter.
The loop filter 33 is selected when the modulation voltage is high (80 MHz to 50 MHz) when the control voltage of the VCO 2 is “1 V to 3 V”, and the modulation sensitivity is low (60 MHz) when the control voltage of the VCO is “2.5 V to 4 V”. Loop filter 34 is selected.

<Description of effects>
As described above, according to the present invention, there are effects as described below.
When the modulation sensitivity of the VCO changes at the desired output frequency, a stable PLL frequency synthesizer circuit without oscillation or deterioration of nearby noise can be obtained by switching to a loop filter that cancels the loop gain change using the modulation sensitivity as a parameter. Can be realized.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

  Here, the invention described in Patent Document 1 uses two loop filters, but is only switched according to the set frequency, and differs from the present embodiment in that the modulation sensitivity is not referred to. Moreover, since the output side of the invention described in Patent Document 1 is connected to the VCO, a capacitor is always connected in parallel when the loop filter is a lag type filter or a lag / lead type filter. Become.

The invention described in Patent Document 2 is different from the present embodiment in that although an AD converter is used, the output of the AD converter is used for generating a control signal without feeding back the output to the loop filter.
Therefore, even if the inventions described in Patent Documents 1 and 2 are combined, it is difficult to arrive at the present embodiment.

  The present invention can be used for a transmitter, a receiver, a transceiver, a standard signal generator, and the like.

1 is a block diagram of an embodiment of a PLL frequency synthesizer according to the present invention. The relationship between the modulation sensitivity curve of the VCO of the PLL frequency synthesizer shown in FIG. 1 and the control voltage of the VCO for switching the loop filter is shown. It is an example of the block diagram of the loop filter used for the PLL frequency synthesizer shown in FIG. 1 is a block diagram of a wideband PLL frequency synthesizer circuit related to the present invention. FIG. FIG. 5 is a diagram showing a Kv curve of a VCO 42 in the wide band PLL frequency synthesizer circuit shown in FIG. 4.

Explanation of symbols

1 Phase comparator 2 Voltage controlled oscillator (VCO)
3 Loop filter (LF)
4 Frequency divider 5 A / D converter 6 Control unit

Claims (6)

  A PLL frequency characterized by monitoring a control voltage of a voltage controlled oscillator and switching a loop filter set to operate stably between the modulation sensitivity of the voltage controlled oscillator according to the control voltage Synthesizer circuit.   The PLL frequency synthesizer according to claim 1, further comprising: an AD converter that converts a control voltage of the voltage controlled oscillator into a digital signal; and a control unit that switches the loop filter in accordance with an output voltage of the AD converter. circuit.   The loop filter includes a demultiplexer, a multiplexer, and a plurality of loop filter bodies having different modulation sensitivities connected between an output side of the demultiplexer and an input side of the multiplexer, and an instruction from the control unit 3. The PLL frequency synthesizer circuit according to claim 2, wherein the loop filter main body is selected by switching between the demultiplexer and the multiplexer.   The phase from the voltage controlled oscillator is set so that the phase difference between the reference signal input to the phase comparator from the outside and the output from the voltage controlled oscillator connected to the phase comparator through a loop filter is constant. The comparator is oscillated with feedback by a frequency divider, the control voltage of the voltage controlled oscillator is monitored, and the comparator is set to operate stably with the modulation sensitivity of the voltage controlled oscillator according to the control voltage. A method for controlling a PLL frequency synthesizer circuit, wherein the loop filter is switched.   5. The method of controlling a PLL frequency synthesizer circuit according to claim 4, wherein a control voltage of the voltage controlled oscillator is converted into a digital signal, and the loop filter is switched according to an output voltage of the digital signal.   The loop filter includes a plurality of loop filter bodies having different modulation sensitivities connected between an output side of the demultiplexer and an input side of the multiplexer, and switches the demultiplexer and the multiplexer according to an instruction from the control unit. 6. The method of controlling a PLL frequency synthesizer circuit according to claim 5, wherein the loop filter main body is selected by:

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