JP2010041062A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a trouble occurs in the high-speed operation of a circuit when the one of a low breakdown voltage is utilized for a configuring transistor in a conventional level shift circuit. <P>SOLUTION: The level shift circuit outputs output logic signals which have an amplitude larger than that of input logic signals to a first output terminal corresponding to the input logic signals which are input to an input terminal and have a prescribed amplitude. The level shift circuit includes: a power supply terminal for supplying the first logic level or second logic level of the output logic signals; a first transistor which is connected between the power supply terminal and the first output terminal, and for which signals corresponding to the input logic signals are inputted to the control terminal; and a second transistor which is connected between the power supply terminal and the first transistor and turned to an ON or OFF state in synchronism with the first transistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a level shift circuit.

  The level shift circuit is a circuit that changes the voltage amplitude of a signal. For example, when the output voltage of the first circuit is different from the operating voltage range of the second circuit, a level shift circuit is connected between the first circuit and the second circuit. This level shift circuit can adjust the level of the signal between the circuits.

  As such a level shift circuit, the technique of Patent Document 1 is disclosed. The circuit configuration of the level shift circuit 1 of Patent Document 1 is shown in FIG. As shown in FIG. 6, the level shift circuit 1 includes PMOS transistors MP1 to MP4, NMOS transistors MN1 to MN4, an intermediate potential generation circuit 2, and an inverter INV1.

  The intermediate potential generation circuit 2 includes resistors R1 and R2. The resistor R1 has one end connected to the high potential voltage terminal VPP and the other end connected to the node S10. The high potential voltage terminal VPP supplies a voltage higher than the power supply voltage VDD. The resistor R2 has one end connected to the node S10 and the other end connected to the ground voltage terminal GND. Therefore, the potential of the node S10 becomes an intermediate level potential VF obtained by dividing the high potential voltage VPP by the resistors R1 and R2. For convenience, the symbols “VPP”, “VDD”, and “GND” indicate a terminal name and at the same time indicate a high potential voltage, a power supply voltage, and a ground voltage.

  The NMOS transistor MN1 has a drain connected to the node S11 and a source connected to the ground voltage terminal GND. An input signal IN is input to the gate of the NMOS transistor MN1. The NMOS transistor MN2 has a drain connected to the output terminal / D, a source connected to the node S11, and a gate connected to the node S10. The PMOS transistor MP2 has a source connected to the node S12, a drain connected to the output terminal / D, and a gate connected to the node S10. The PMOS transistor MP1 has a source connected to the high potential voltage terminal VPP, a drain connected to the node S12, and a gate connected to the output terminal D.

  The inverter INV1 receives the input signal IN and outputs an output signal / IN in which the logic is inverted.

  The NMOS transistor MN3 has a drain connected to the node S21 and a source connected to the ground voltage terminal GND. The output signal / IN of the inverter INV1 is input to the gate of the NMOS transistor MN3. The NMOS transistor MN4 has a drain connected to the output terminal D, a source connected to the node S21, and a gate connected to the node S10. The PMOS transistor MP4 has a source connected to the node S22, a drain connected to the output terminal D, and a gate connected to the node S10. The PMOS transistor MP3 has a source connected to the high potential voltage terminal VPP, a drain connected to the node S22, and a gate connected to the output terminal / D.

  A waveform of the operation of the level shift circuit 1 is shown in FIG. As shown in FIG. 7, before time t1, the input signal IN is at a low level (ground potential GND) and / IN is at a high level (power supply voltage VDD). At this time, the output terminal / D outputs a high level (high potential voltage VPP), and the output terminal D outputs a low level (ground potential GND). At this time, the gate potential of the NMOS transistor MN1, that is, the voltage (VF−Vtn) lower than the potential VF of the node S10 by the threshold voltage Vtn is applied to the node S11. It is assumed that the threshold voltage of the NMOS transistor is Vtn and the threshold voltage of the PMOS transistor is Vtp. The potential of the node S21 is the ground potential GND because the NMOS transistor MN3 is in the on state. The potential of the node S12 is the high potential voltage VPP because the PMOS transistor MP1 is in the on state. A voltage (VF + | Vtp |) that is higher than the gate potential of the PMOS transistor MP4, that is, the potential VF of the node S10, is higher than the node S22.

  At time t1, the input signal IN changes from a low level (ground potential GND) to a high level (power supply voltage VDD), and / IN changes from a high level (power supply voltage VDD) to a low level (ground potential GND). At this time, the output terminal / D outputs a low level (ground potential GND) and the output terminal D outputs a high level (high potential voltage VPP). At this time, the potential of the node S11 becomes the ground potential GND because the NMOS transistor MN1 is in the on state. A voltage (VF−Vtn) that is a threshold voltage Vtn lower than the gate potential of the NMOS transistor MN3, that is, the potential VF of the node S10, is applied to the node S21. A voltage (VF + | Vtp |) that is higher than the gate potential of the PMOS transistor MP4, that is, the potential VF of the node S10, is higher than the node S12. The potential of the node S22 is the high potential voltage VPP because the PMOS transistor MP3 is in the on state.

  At time t2, the input signal IN changes from the high level (power supply voltage VDD) to the low level (ground potential GND), and / IN changes from the low level (ground potential GND) to the high level (power supply voltage VDD). At this time, as before time t1, the output terminal / D outputs a high level (high potential voltage VPP), and the output terminal D outputs a low level (ground potential GND). Therefore, the voltage (VF−Vtn) is applied to the node S11. The potential of the node S21 is the ground potential GND. The potential of the node S12 is the high potential voltage VPP. A voltage (VF + | Vtp |) is applied to the node S22.

Thus, in the level shift circuit 1, the potential applied between the drain and source of the NMOS transistors MN1 to MN4 is equal to or less than (VF−Vtn) or VPP− (VF−Vtn). In addition, the potential applied between the drain and source of the PMOS transistors MP1 to MP4 is (VF + | Vtp |) or VPP− (VF + | Vtp |) or less. Therefore, the level shift circuit 1 uses a transistor having a high breakdown voltage characteristic without directly applying the high potential voltage VPP between the drains and sources of the NMOS transistors MN1 to MN4 and the PMOS transistors MP1 to MP4. Has the advantage of not needing. Patent Document 2 also discloses a similar circuit configuration.
JP-A-8-148988 US Pat. No. 5,243,236

  However, the level shift circuit 1, for example, outputs a high level (high potential voltage VPP) from the output terminal D at time t1, but has a high on-resistance because the gate of the PMOS transistor MP4 is biased to the potential VF. The output terminal D has a long time to output the high potential voltage VPP. At time t2, a high level (high potential voltage VPP) is output from the output terminal / D. However, since the gate of the PMOS transistor MP2 is biased to the potential VF, the on-resistance is high, and the output terminal / D is It takes a long time to output the high potential voltage VPP. As described above, the level shift circuit 1 has the above-described problems and cannot operate at high speed.

  The present invention is a level shift circuit for outputting an output logic signal having an amplitude larger than the input logic signal to a first output terminal in response to an input logic signal having a predetermined amplitude input to the input terminal, A power supply terminal that applies the first logic level or the second logic level of the output logic signal, and a signal that is connected between the power supply terminal and the first output terminal and that corresponds to the input logic signal is input to the control terminal. And a second transistor that is connected between the power supply terminal and the first transistor and is turned on or off in synchronization with the first transistor. .

  According to the level shift circuit of the present invention, both the first and second transistors connected between the first output terminal and the power supply terminal are turned on, and the potential of the output terminal becomes the power supply voltage in a short time. A corresponding potential can be reached. When both the first and second transistors are turned off, a potential corresponding to the input signal potential is applied to an intermediate node between the first transistor and the second transistor. For this reason, the potential of the amplitude level of the output logic signal is not directly applied to the first transistor or the second transistor.

  The level shift circuit of the present invention can operate at high speed without using a high voltage transistor.

Embodiment 1 of the Invention
Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows an example of the configuration of the level shift circuit 100 according to the present embodiment. As shown in FIG. 1, the level shift circuit 100 includes an intermediate potential generation circuit 110, PMOS transistors MP101 to MP104, NMOS transistors MN101 to MN104, and an inverter INV101.

  The intermediate potential generation circuit 110 includes resistance elements R101 and R102. The resistor element R101 has one end connected to the high potential voltage terminal VPP and the other end connected to the node S101. The resistor element R102 has one end connected to the node S101 and the other end connected to the ground voltage terminal GND. Therefore, the potential of the node S101 becomes an intermediate potential VF obtained by dividing the high potential voltage VPP by the resistance values of the resistance elements R101 and R102. The voltage supplied from the high potential voltage terminal VPP is higher than the power supply voltage supplied from the power supply voltage terminal VDD. For the sake of convenience, the symbols “VPP”, “VDD”, and “GND” indicate the terminal name, as well as the high potential voltage, the power supply voltage, and the ground voltage.

  The inverter INV101 receives the input signal IN and outputs a logically inverted signal / IN. In the inverter INV101, the power supply voltage VDD is supplied to the power supply on the high potential side, and the ground voltage GND is supplied to the power supply on the low potential side. Therefore, the signal / IN is a digital signal whose signal amplitude changes from the power supply voltage VDD to the ground voltage GND. The input signal IN is also a digital signal whose signal amplitude changes from the power supply voltage VDD to the ground voltage GND. Therefore, the signal / IN is simply a signal whose logic is inverted with respect to the input signal IN. Hereinafter, the signal / IN is referred to as “input signal / IN”. For convenience, the above symbol “IN” indicates the input signal name as well as the input signal name.

  The NMOS transistor MN101 has a drain connected to the node S111 and a source connected to the ground voltage terminal GND. An input signal IN is input to the gate. The NMOS transistor MN103 has a drain connected to the node S121 and a source connected to the ground voltage terminal GND. An input signal / IN is input to the gate.

  The NMOS transistor MN102 has a drain connected to the output terminal / D, a source connected to the node S111, and a gate connected to the node S101. The NMOS transistor MN104 has a drain connected to the output terminal D, a source connected to the node S121, and a gate connected to the node S101. For the sake of convenience, the symbols “D” and “/ D” indicate the output terminal name and the output signal output from the output terminal.

  The PMOS transistor MP102 has a source connected to the node S112 and a drain connected to the output terminal / D. An input signal IN is input to the gate. The PMOS transistor MP104 has a source connected to the node S122 and a drain connected to the output terminal D. An input signal / IN is input to the gate.

  The PMOS transistor MP101 has a source connected to the high potential voltage VPP, a drain connected to the node S112, and a gate connected to the output terminal D. The PMOS transistor MP103 has a source connected to the high potential voltage VPP, a drain connected to the node S122, and a gate connected to the output terminal / D.

  Next, the operation of the level shift circuit 100 described above will be described in detail with reference to the drawings. FIG. 2 shows an example of a timing chart of the level shift circuit 100. As shown in FIG. 2, before time t1, the input signal IN is at a low level (ground potential GND) and / IN is at a high level (power supply voltage VDD). At this time, the NMOS transistor MN101 and the PMOS transistor MP104 are turned off, and the NMOS transistor MN103 and the PMOS transistor MP102 are turned on.

  Since the NMOS transistor MN103 is turned on, the output terminal D is at a low level (ground potential GND). For this reason, the PMOS transistor MP101 whose gate is connected to the output terminal D is turned on. Further, the PMOS transistor MP102 is in an ON state because a low level input signal IN, that is, the ground voltage GND is applied to the gate. For this reason, the output terminal / D becomes high level (high potential voltage VPP).

  Further, the PMOS transistor MP103 whose gate is connected to the output terminal / D is turned off. Further, the high level input signal / IN, that is, the power supply voltage VDD is applied to the gate of the PMOS transistor MP104. Therefore, the potential of the node S122 is a potential that has dropped from the high potential voltage VPP to (VDD + | Vtp |) at which the PMOS transistor MP104 is cut off. Note that the threshold voltage of the PMOS transistor is Vtp, and the threshold voltage of the NMOS transistor is Vtn.

  On the other hand, the output terminal / D is at the high level (high potential voltage VPP), and the intermediate potential VF is applied to the gate of the NMOS transistor MN102. For this reason, the potential of the node S111 is (VF−Vtn).

  Next, at time t1, the input signal IN changes from a low level (ground potential GND) to a high level (power supply voltage VDD), and / IN changes from a high level (power supply voltage VDD) to a low level (ground potential GND). At this time, the NMOS transistor MN101 and the PMOS transistor MP104 are turned on, and the NMOS transistor MN103 and the PMOS transistor MP102 are turned off.

  Since the NMOS transistor MN101 is turned on, the output terminal / D changes from the high level (high potential voltage VPP) to the low level (ground voltage GND). For this reason, the PMOS transistor MP103 whose gate is connected to the output terminal / D is turned on. Further, the PMOS transistor MP104 is in an ON state because a low level input signal / IN, that is, the ground voltage GND is applied to the gate. For this reason, the high potential voltage terminal VPP and the output terminal D are connected via the PMOS transistors MP103 and MP104 in a low on-resistance state. Therefore, the output terminal D can be changed from the low level (ground potential GND) to the high level (high potential voltage VPP) in a short time.

  Further, the PMOS transistor MP101 whose gate is connected to the output terminal D is turned off. The PMOS transistor MP102 has a high level input signal IN, that is, a power supply voltage VDD applied to the gate. Therefore, the potential of the node S112 drops from the high potential voltage VPP and stops when the PMOS transistor MP102 is cut off (VDD + | Vtp |).

  On the other hand, the output terminal D changes from the low level (ground potential GND) to the high level (high potential voltage VPP), and the intermediate potential VF is applied to the gate of the NMOS transistor MN104. For this reason, the potential of the node S121 rises from the ground potential to (VF−Vtn).

  Next, at time t2, the input signal IN changes from a high level (power supply voltage VDD) to a low level (ground potential GND), and / IN changes from a low level (ground potential GND) to a high level (power supply voltage VDD). At this time, the NMOS transistor MN101 and the PMOS transistor MP104 are turned off, and the NMOS transistor MN103 and the PMOS transistor MP102 are turned on.

  Since the NMOS transistor MN103 is turned on, the output terminal D changes from the high level (high potential voltage VPP) to the low level (ground voltage GND). For this reason, the PMOS transistor MP101 whose gate is connected to the output terminal D is turned on. Further, the PMOS transistor MP102 is in an ON state because a low level input signal IN, that is, the ground voltage GND is applied to the gate. For this reason, the high potential voltage terminal VPP and the output terminal / D are connected via the PMOS transistors MP101 and MP102 in a low on-resistance state. Therefore, the output terminal / D can be changed from the low level (ground potential GND) to the high level (high potential voltage VPP) in a short time.

  Further, the PMOS transistor MP103 whose gate is connected to the output terminal / D is turned off. The PMOS transistor MP104 has a high level input signal / IN, that is, a power supply voltage VDD applied to the gate. Therefore, the potential of the node S122 drops from the high potential voltage VPP and stops when the PMOS transistor MP104 is cut off (VDD + | Vtp |).

  On the other hand, the output terminal / D changes from the low level (ground potential GND) to the high level (high potential voltage VPP), and the intermediate potential VF is applied to the gate of the NMOS transistor MN102. For this reason, the potential of the node S111 rises from the ground potential to (VF−Vtn).

  With the above operation, the level shift circuit 100 outputs the input signal IN or / IN that swings between the power supply voltage VDD and the ground potential GND, and the output signal D or / D that swings between the high potential voltage VPP and the ground potential GND. Can be level shifted. At this time, the potential applied between the drain and source of the NMOS transistors MN101 and MN103 is equal to or less than (VF−Vtn), and the potential applied between the drain and source of the NMOS transistors MN102 and MN104 is (VPP− (VF−). Vtn)) and below. Further, the potential applied between the drain and source of the PMOS transistors MP102 and MP104 is (VDD + | Vtp |) or less, and the potential applied between the drain and source of the PMOS transistors MP101 and MP103 is (VPP− (VDD + |). Vtp |)) or less. Therefore, the high potential voltage VPP is not directly applied between the drains and sources of the PMOS transistors MP101 to MP104 and the NMOS transistors MN101 to MN104 included in the level shift circuit 100. For this reason, it is not necessary to use a transistor having high breakdown voltage characteristics. Further, when the output terminal D or / D transitions from the low level (ground potential GND) to the high level (high potential voltage VPP), as described above, the output terminal D or / D passes through the PMOS transistor that is on. Are connected to the high potential voltage terminal VPP. Therefore, the output terminal D or / D can be changed from the low level (ground potential GND) to the high level (high potential voltage VPP) in a short time. Therefore, in the prior art, the problem that the output terminal D or / D has a high level, that is, has a long time to output the high potential voltage VPP, and the level shift circuit cannot be operated at high speed can be solved.

Embodiment 2 of the Invention
Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 3 shows an example of the configuration of the level shift circuit 200 according to this embodiment. In addition, the structure which attached | subjected the code | symbol same as FIG. 1 among the code | symbols shown by the figure has shown the structure which is the same as that of FIG. 1, or similar. The difference from the first embodiment is that the NMOS transistors MN101 and MN103 are omitted. Therefore, in the second embodiment, the description of only that part is focused and the description of the other parts is omitted.

  As shown in FIG. 3, the level shift circuit 200 includes an intermediate potential generation circuit 110, PMOS transistors MP101 to MP104, NMOS transistors MN102 and MN104, and an inverter INV101.

  The source of the NMOS transistor MN102 is connected to the node S111, that is, the output of the inverter INV101. The source of the NMOS transistor MN104 is connected to the node S121, that is, the input of the inverter INV101. Since other connection relations are the same as those of the level shift circuit 100 of the first embodiment, description thereof is omitted. The threshold voltage Vtn of the NMOS transistors MN102 and MN104 is adjusted so that VF <(VDD + Vtn) is satisfied.

  In the level shift circuit 200, the signal source of the input signal IN is directly connected to the source of the NMOS transistor MN104. Therefore, the signal source of the input signal IN is required to have a sufficient current driving capability.

  Next, the operation of the level shift circuit 200 described above will be described in detail with reference to the drawings. FIG. 4 shows an example of a timing chart of the level shift circuit 200. As shown in FIG. 4, before time t1, the input signal IN is at a low level (ground potential GND) and / IN is at a high level (power supply voltage VDD). Accordingly, the PMOS transistor MP104 is in the off state, the PMOS transistor MP102 is in the on state, the node S121 is at the ground potential GND, and the node S111 is at the power supply voltage VDD. For this reason, the output terminal D becomes low level (ground potential GND), and the PMOS transistor MP101 is turned on. Further, the PMOS transistor MP102 is in an ON state because a low level input signal IN, that is, the ground voltage GND is applied to the gate. For this reason, the output terminal / D becomes high level (high potential voltage VPP).

  Further, the PMOS transistor MP103 whose gate is connected to the output terminal / D is turned off. Further, the high level input signal / IN, that is, the power supply voltage VDD is applied to the gate of the PMOS transistor MP104. Therefore, as in the first embodiment, the potential of the node S122 is a potential that has dropped from the high potential voltage VPP at which the PMOS transistor MP102 is cut off to (VDD + | Vtp |).

  The NMOS transistor MN102 is cut off because the potential of the node S111, that is, the source potential of the NMOS transistor MN102 is the power supply voltage VDD.

  Next, at time t1, the input signal IN changes from a low level (ground potential GND) to a high level (power supply voltage VDD), and / IN changes from a high level (power supply voltage VDD) to a low level (ground potential GND). At this time, the PMOS transistor MP104 is on, the PMOS transistor MP102 is off, the node S121 is at the power supply voltage VDD, and the node S111 is at the ground potential GND. Therefore, the output terminal / D changes from the high level (high potential voltage VPP) to the low level (ground potential GND). For this reason, the PMOS transistor MP103 whose gate is connected to the output terminal / D is turned on. Further, the PMOS transistor MP104 is in an ON state because a low level input signal / IN, that is, the ground voltage GND is applied to the gate. For this reason, as in the first embodiment, the high potential voltage terminal VPP and the output terminal D are connected via the PMOS transistors MP103 and MP104 in a low on-resistance state. Therefore, the output terminal D can be changed from the low level (ground potential GND) to the high level (high potential voltage VPP) in a short time.

  Further, the PMOS transistor MP101 whose gate is connected to the output terminal D is turned off. The PMOS transistor MP102 has a high level input signal IN, that is, a power supply voltage VDD applied to the gate. Therefore, the potential of the node S112 drops from the high potential voltage VPP and stops when the PMOS transistor MP102 is cut off (VDD + | Vtp |).

  The NMOS transistor MN104 is cut off when the potential of the node S121, that is, the source potential of the NMOS transistor MN104 changes from the ground potential GND to the power supply voltage VDD.

  Next, at time t2, the input signal IN changes from a high level (power supply voltage VDD) to a low level (ground potential GND), and / IN changes from a low level (ground potential GND) to a high level (power supply voltage VDD). At this time, the PMOS transistor MP104 is off, the PMOS transistor MP102 is on, the node S111 is at the power supply voltage VDD, and the node S121 is at the ground potential GND. For this reason, the output terminal D changes from the high level (high potential voltage VPP) to the low level (ground potential GND). Also, the PMOS transistor MP101 whose gate is connected to the output terminal D is turned on. Further, the PMOS transistor MP102 is in an ON state because a low level input signal IN, that is, the ground voltage GND is applied to the gate. For this reason, as in the first embodiment, the high potential voltage terminal VPP and the output terminal / D are connected via the PMOS transistors MP101 and MP102 in a low on-resistance state. Therefore, the output terminal / D can be changed from the low level (ground potential GND) to the high level (high potential voltage VPP) in a short time.

  Further, the PMOS transistor MP103 whose gate is connected to the output terminal / D is turned off. The PMOS transistor MP104 has a high level input signal / IN, that is, a power supply voltage VDD applied to the gate. Therefore, the potential of the node S122 drops from the high potential voltage VPP and stops when the PMOS transistor MP104 is cut off (VDD + | Vtp |).

  The NMOS transistor MN102 is cut off when the potential of the node S111, that is, the source potential of the NMOS transistor MN102 changes from the ground potential GND to the power supply voltage VDD.

  With the above operation, the level shift circuit 200 outputs the input signal IN or / IN that swings between the power supply voltage VDD and the ground potential GND, and the output signal D or / D that swings between the high potential voltage VPP and the ground potential GND. Can be level shifted. At this time, the potential applied between the drain and source of the NMOS transistors MN102 and MN104 is equal to or lower than (VPP-VDD). Further, as in the first embodiment, the potential applied between the drain and source of the PMOS transistors MP102 and MP104 is (VDD + | Vtp |) or less, and the potential applied between the drain and source of the PMOS transistors MP101 and MP103. Becomes (VPP− (VDD + | Vtp |)) or less. Therefore, the high potential voltage VPP is not directly applied between the drains and sources of the PMOS transistors MP101 to MP104 and the NMOS transistors MN102 and MN104 included in the level shift circuit 200. For this reason, it is not necessary to use a transistor having a high breakdown voltage characteristic as in the first embodiment. Further, when the output terminal D or / D transitions from the low level (ground potential GND) to the high level (high potential voltage VPP), the output terminal D or / D and the high potential voltage are passed through the PMOS transistor in the on state. Terminal VPP is connected. Therefore, as in the first embodiment, the output terminal D or / D can be changed from the low level (ground potential GND) to the high level (high potential voltage VPP) in a short time.

  Furthermore, the level shift circuit 200 can omit the NMOS transistors MN101 and MN103 as compared with the level shift circuit 100, and can be configured with fewer elements. Therefore, the chip area for forming the circuit can be reduced. The same operation can be performed by applying the power supply voltage VDD instead of the intermediate potential VF applied to the gates of the NMOS transistors MN102 and MN104. Therefore, in this case, the intermediate potential generation circuit 110 can be omitted. For this reason, the chip area can be further reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, like the level shift circuit 300 shown in FIG. 5, the present invention may be realized by a connection configuration in which the conductivity type of the MOS transistor of the level shift circuit 100 of FIG. 1 is reversed. This is effective when the current drive capability of the NMOS transistor is lower than that of the PMOS transistor. Normally, the size of the NMOS transistor is set larger than that of the PMOS transistor from the viewpoint of ensuring the stability of the circuit operation. For this reason, the NMOS transistor has a higher driving capability. Therefore, normally, even if the intermediate potential VF is applied to the gates of the NMOS transistors MN102 and MN104 as in the level shift circuit 100, the output terminal D or / D changes from the high level (high potential voltage VPP) to the low level (ground potential). The time to drop to the potential GND) is sufficiently fast.

1 is an example of a configuration of a level shift circuit according to a first exemplary embodiment; 3 is a timing chart showing the operation of the level shift circuit according to the first exemplary embodiment; 3 is an example of a configuration of a level shift circuit according to a second exemplary embodiment; 6 is a timing chart showing the operation of the level shift circuit according to the second exemplary embodiment; It is an example of the structure of the level shift circuit concerning other embodiment. This is a configuration of a conventional level shift circuit. It is a timing chart which shows operation | movement of the conventional level shift circuit.

Explanation of symbols

100, 200, 300 Level shift circuit 110 Intermediate voltage generation circuit MP101-MP104 PMOS transistor MN101-MN104 NMOS transistor INV101 Inverter R101, R102 Resistive element

Claims (10)

A level shift circuit for outputting, to a first output terminal, an output logic signal having an amplitude larger than the input logic signal in response to an input logic signal having a predetermined amplitude input to the input terminal;
A power supply terminal for providing a first logic level or a second logic level of the output logic signal;
A first transistor connected between the power supply terminal and the first output terminal and having a control terminal input with a signal corresponding to the input logic signal;
A second transistor connected between the power supply terminal and the first transistor and turned on or off in synchronization with the first transistor;
A level shift circuit. The level shift circuit according to claim 1, wherein the first transistor and the second transistor are transistors of the same conductivity type. A third transistor having a conductivity type opposite to that of the first and second transistors;
An intermediate potential generating circuit for generating a predetermined voltage between the first logic level and the second logic level;
Have
3. The level shift circuit according to claim 2, wherein a voltage generated by the intermediate potential generation circuit is applied to a control terminal of the third transistor, and one terminal is connected to the first output terminal. A fourth transistor having the same conductivity type as the third transistor;
4. The level shift circuit according to claim 3, wherein a signal corresponding to the input signal is input to a control terminal of the fourth transistor, and one terminal is connected to the other terminal of the third transistor. 4. The level shift circuit according to claim 3, wherein the other terminal of the third transistor and the input terminal are connected. An inverter circuit that inputs the input logic signal and outputs a signal obtained by inverting the input logic signal with the same amplitude as the input logic signal;
A fifth transistor operating in pairs with the first transistor;
A sixth transistor operating in pairs with the second transistor;
A second output terminal that outputs logic opposite to that of the first output terminal;
Have
The first transistor has one terminal connected to the first output terminal, the other terminal connected to one terminal of the second transistor, and a control terminal connected to the output of the inverter circuit,
The fifth transistor has one terminal connected to the second output terminal, the other terminal connected to one end of the sixth transistor, and a control terminal connected to the input terminal,
The second transistor has one terminal connected to the other terminal of the first transistor, the other terminal connected to the power supply terminal, and a control terminal connected to the second output terminal.
2. The level shift circuit according to claim 1, wherein one terminal of the sixth transistor is connected to the other terminal of the fifth transistor, the other terminal is connected to the power supply terminal, and a control terminal is connected to the first output terminal. . The level shift circuit according to claim 6, wherein the first, second, fifth, and sixth transistors are transistors of the same conductivity type. Seventh and eighth transistors having a conductivity type opposite to that of the first, second, fifth and sixth transistors;
An intermediate potential generating circuit for generating a predetermined voltage between the first logic level and the second logic level;
Have
In the seventh transistor, a voltage generated by the intermediate potential generation circuit is input to a control terminal, one terminal is connected to the first output terminal,
The level shift circuit according to claim 7, wherein the eighth transistor receives a voltage generated by the intermediate potential generation circuit as a control terminal, and one terminal is connected to the second output terminal. Having ninth and tenth transistors of the same conductivity type as the seventh and eighth transistors;
The ninth transistor has a control terminal connected to the output of the inverter circuit, one terminal connected to the other terminal of the seventh transistor,
The level shift circuit according to claim 8, wherein the tenth transistor has a control terminal connected to the input terminal and one terminal connected to the other terminal of the eighth transistor. The seventh transistor has the other terminal connected to the input terminal,
The level shift circuit according to claim 8, wherein the eighth transistor has the other terminal connected to the output of the inverter circuit.

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