JP2010040839A - Protection element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protection element for protecting a circuit to be protected from surge breakdown. <P>SOLUTION: A first P-well area 55a is formed on a semiconductor substrate 11. On the first P-well area 55a, N-type diffusion areas 53d and 53s are formed so as to sandwich parts of the first P-well area 55a. A second P-well area 55b is formed on the semiconductor substrate 11 so as to surround the first P-well area 55a. A P-well area 21 of which impurity concentration is lower than those of the first P-well area 55a and the second P-well area 55b is formed between the first P-well area 55a and the second P-well area 55b. N-type diffusion areas 53 are formed on the P-well area 21. The N-type diffusion area 53d is connected to a connection node 90, and the N-type diffusion areas 53s are connected to GND. Moreover, the second P-well area 55b is connected to GND, and the N-type diffusion areas 53 are connected to the connection node 90. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a protection element. Specifically, the present invention relates to a protective element that prevents destruction of an internal circuit due to electrostatic discharge.

  A protection structure for protecting an internal circuit of a semiconductor device from a surge such as electrostatic discharge is known. For example, Patent Document 1 discloses a protection circuit that releases a surge caused by electrostatic discharge (ESD) to a power source and prevents destruction of an internal circuit due to the surge. Patent Document 1 discloses the configurations of FIGS. 10 and 11 as protective elements. In FIG. 10, an input protection element is formed on a P-type substrate 1, an N-type well 3 is located in the center of the element region surrounded by the element isolation layer 2, an N-type well 4 is located in the periphery of the element region, and an element region. An N-type well 5 is formed under the element isolation layer 2 surrounding the element. A P-type well 7 is provided so as to separate the N-type well 3 and the N-type well 4, and a P-type well 8 is provided so as to separate the N-type well 4 and the N-type well 5. A P-type well 8A for supplying a potential to the P-type well 7 is provided on the outside. N + type diffusion layers 13 and 14 and a P + diffusion layer 18 for extracting each well potential are formed as shown in the figure.

An N + type diffusion layer 14 formed over the N type well 4 and the P type well 7 serves as a source terminal, and an N + type diffusion layer 13 formed over the N type well 3 and the P type well 7 serves as a drain terminal. Further, by providing the gate electrode 27, the N-type MOSFET 30 is configured. The source terminal (N + type diffusion layer 14) and the gate electrode 27 are connected to GND, and the drain terminal (N + type diffusion layer 13) is connected to the internal circuit.
Note that when facing each other across the gate electrode 27 in the N-type well 3, the N-type well 3 between the N + type diffusion layers 13 functions as a protective resistor. Further, a P + -type diffusion layer 18 is formed on the surface portion of the P-type well 8A surrounding the element isolation layer 2, serving as a back gate potential supply terminal, and connected to GND.

In such a configuration, when a surge is applied to the external terminal 40, the N + type diffusion layer 13 connected to the external terminal 40 is connected to the collector in the N-type MOSFET 30 connected in parallel between the external terminal 40 and GND. Thus, the parasitic NPN transistor 31 whose base is the P type substrate 1 and whose emitter is the N + type diffusion layer 14 which is the source terminal operates.
Here, in the configuration of FIG. 10, the N-type well 5 is adjacent to the P-type well 8A that supplies the back gate potential, so that the back gate current passes through the P-type substrate 1 from the P-type well 8A. Further, since a depletion layer is formed at the junction between the N-type well 5 and the P-type substrate 1, the path of the back gate current is further elongated. Then, since the base bias resistance 32 of the parasitic NPN transistor 31 is increased, the base potential of the parasitic NPN transistor 31 is likely to increase, and the parasitic NPN transistor is likely to snap back. As a result, the surge flowing from the external terminal 40 is released to GND to protect the internal circuit.

Moreover, in patent document 1, the structure shown in FIG. 11 is proposed as a further improved type.
In FIG. 11, an N + type diffusion layer 15 for biasing the N type well 5 is provided on the surface of the N type well 5, and this N + type diffusion layer 15 is connected to VDD which is a positive power source. When the N-type well 5 is biased to VDD, the depletion layer at the junction between the N-type well 5 and the P-type substrate 1 becomes large. Then, since the path of the back gate current is further elongated and the base bias resistance 32 of the parasitic NPN transistor 31 is increased, the base potential of the parasitic NPN transistor 31 is easily increased, and the parasitic NPN transistor 31 is easily snapped back.

JP 2003-249625 A

In the configuration of FIG. 11, the base bias resistor 32 of the parasitic NPN transistor 31 is increased by applying a VDD bias to the N-type well 5, but when the power is turned off and the circuit is in a non-operating state, No bias due to VDD.
Normally, when a person touches an internal circuit, the power is turned off, so the circuit is in a non-operating state. Therefore, even if configured as shown in FIG. 11, in a situation where electrostatic discharge occurs, the N-type well 5 is simply in a floating state, as in FIG.
In this case, the depletion layer between the N-type well 5 and the P-type substrate 1 is not so large, and the base bias resistor 32 is also small. FIG. 12 is a diagram showing snapback characteristics of the protection circuit. In FIG. 12, V0 is a voltage applied to the circuit immediately before snapback. As shown in FIG. 12, since the parasitic transistor is not turned on unless the voltage is considerably increased, a high voltage is applied to the internal circuit.

  The protection element of the present invention is a protection element that is connected to a connection node to a circuit to be protected and protects the circuit to be protected from surge destruction, and a first well type first well region formed on a semiconductor substrate, A first electrode and a second electrode of the second conductivity type formed on a part of the first well region in an upper layer of the first well region, and a first formed to surround the first well region A second well region having a conductivity type, and formed between the first well region and the second well region, and having a second conductivity type, or more than the first well region and the second well region A first well type third well region having a low impurity concentration; and a second conductive type third electrode provided in an upper layer of the third well region, the first electrode and the second electrode One of these is connected to the connection node and the other is connected to the power source. The second well region is connected to the power source, and the third electrode is connected to the connection node.

In such a configuration, a parasitic transistor having the first electrode and the second electrode in the first well region as main electrodes is configured, and when the surge occurs, the parasitic transistor snaps back, so that excess charge is used as a power source. Escape and protect internal circuitry.
Here, since the third well region is provided between the first well region and the second well region, the charge applied from the connection node to the first electrode or the second electrode is supplied through the substrate as a power source. Will flow into. In the present invention, since the third electrode is connected to the connection node, electric charges are also applied to the third electrode when a surge occurs. At this time, the depletion layer expands at the junction between the third electrode and the third well, and the depletion layer expands toward the substrate side. Then, the resistance component of the substrate increases due to the spread of the depletion layer. As a result, a high voltage is generated at the gate of the parasitic transistor, and the parasitic transistor is turned on and is easily snapped back. Thus, according to the present invention, since the parasitic transistor is quickly turned on, surge charges can be quickly discharged, and the internal circuit can be reliably protected.

Embodiments of the present invention will be illustrated and described with reference to reference numerals attached to respective elements in the drawings.
(First embodiment)
A first embodiment of a protection element according to the present invention will be described.
FIG. 1 is a diagram showing an example in which the protection element of the present invention is applied to an actual circuit.
As shown in FIG. 1, a predetermined A circuit and a B circuit are connected by a line 103, and exchange signals and the like. Protection elements 50 and 200 are provided between the line 103 and the power source. When excessive charges are placed on the line 103 due to electrostatic discharge or the like, the protection elements 50 and 200 are turned on to release the excessive charges to the power source. This protects the main part of the circuit such as the A circuit 101 and the B circuit 102 from destruction due to electrostatic discharge.

  Note that, as electrostatic discharge, not only positive charges are discharged but also negative charges may be discharged. In the present embodiment, the configuration of the protection element 50 for efficiently releasing excess positive charges to GND will be described. . By adopting a configuration having a complementary relationship, the protection element 200 can cope with a negative charge surge. Further, in FIG. 1, it goes without saying that a resistor, a diode, or the like may be added before and after the protective element 50.

The configuration of the protection element of the present invention will be described with reference to the drawings.
FIG. 2 is a cross-sectional view of the protection element 50, and FIG. 3 is a plan view of the protection element 50.
In the plan view of FIG. 3, an insulating film, a wiring layer, and the like are omitted for easy understanding of the element configuration.

  On the P− type substrate (semiconductor substrate) 11, a first P well region (first well region) 55 a is provided in the central region of the element 50, and the P − type well region surrounds the outside of the first P well region 55 a. A (third well region) 21 is provided, and a second P well region (second well region) 55b is provided so as to surround the outside of the P − type well region 21.

  Two N-channel transistors are formed in parallel in the first P well region 55a. That is, an N-type diffusion region (first electrode) 53d serving as a common drain of two N-channel transistors is provided in the central region on the surface side of the first P well region 55a. Further, an N-type diffusion region (second electrode) 53s that becomes the source of the N-channel transistor is provided on the peripheral side of the first P well region 55a. A gate 54 is provided between the N-type diffusion region 53d as the drain and the N-type diffusion region 53s as the source.

  The P − type well region 21 has an impurity implantation concentration lower than both the first P well region 55a and the second P well region 55b. The P − type well region 21 is provided with an N type diffusion region (third electrode) 53 on the surface side thereof.

  The second P well region 55b is provided with a P + type diffusion region 52 grounded to GND as a guard ring. P + type diffusion region 52 and N type diffusion region 53 are insulated and separated by field oxide film 51. The N-type diffusion region 53 and the N-type diffusion region 53s are insulated and separated by the field oxide film 51.

Each diffusion region (53, 53s, 53d, 52) is connected to each wiring layer (53a, 53sa, 53da, 52a) through a contact hole 64, and is connected to the connection node 90 or GND through the wiring layer. The N-type diffusion region 53d that is the drain of the N-channel transistor is connected to the connection node 90 through the wiring layer 53da.
N-type diffusion region 53 is connected to connection node 90 through wiring layer 53a. The N-type diffusion region 53s, which is the source region of the N-channel transistor, and the P + type diffusion region 52, which is the card ring, are connected to GND (power supply) through the wiring layer 53sa and the wiring layer 52a, respectively.

Here, FIG. 4 is a diagram explicitly showing the parasitic NPN transistor 57, the parasitic diode 58, and the parasitic resistance 56 formed in the protection element 50, and FIG. 5 shows the parasitic NPN transistor 57, the parasitic diode 58 and 3 is an equivalent circuit diagram of a parasitic resistor 56. FIG. As shown in FIG. 4, a parasitic diode 58 is formed by the N-type diffusion region 53d and the first P well region 55a. In addition, a parasitic NPN transistor 57 is formed with the N-type diffusion region 53s as an emitter, the first P well region 55a as a base, and the N-type diffusion region 53d as a collector. A parasitic resistance 56 is formed between the P + -type diffusion region 52 that applies the back gate voltage and the base of the parasitic NPN transistor 57. That is, the parasitic resistance 56 is formed by the first P well region 55a, the P − type substrate 11 below the P − type diffusion region 21, and the second P well region 55b.
Further, the depletion layer 20 is formed at the junction between the N-type diffusion region 53 and the P − -type diffusion region 21.
At this time, since the number of carriers in the P − type diffusion region 21 is small, the depletion layer 20 spreads greatly on the P − type diffusion region 21 side, and conceptually the depletion layer 20 is formed as shown in FIG.

In such a configuration, the operation of the protection element 50 when a static surge is applied to the line 103 will be described.
When positive static electricity is applied to the line 103, a voltage flows from the connection node 90 to the protection element 50. Static electricity is applied to the N-type diffusion region 53d and the N-type diffusion region 53. When a positive surge is applied to the N-type diffusion region 53d, the parasitic diode 58 formed by the N-type diffusion region 53d and the first P-type well 55a breaks down. Then, the charge flows to GND via the parasitic resistance 56. That is, it flows from the first P-type well 55a to the second P-well 55b via the P− substrate 11 and from the P + -type diffusion region 52 to GND.

  Here, when static electricity is also applied to the N-type diffusion region 53, when a positive charge is applied to the N-type diffusion region 53, the depletion layer 20 spreads, and the P-type diffusion region 21 extends to the P-type substrate 11. It reaches. This is shown in FIG. Then, since no current flows in the region of the depletion layer 20, the current flowing through the parasitic resistance 56 flows along a path that bypasses the depletion layer 20. As described above, the distance of the path corresponding to the parasitic resistance 56 is long and thin, so that the resistance value of the parasitic resistance 56 is increased.

  In this state where the resistance value of the parasitic resistor 56 is increased, the current flowing through the breakdown of the parasitic diode 58 flows through the parasitic resistor 56. When the voltage value applied to the parasitic resistance 56 exceeds the threshold voltage of the parasitic NPN transistor 57, the parasitic NPN transistor 57 is turned ON and the parasitic NPN transistor 57 enters a snapback state. Then, the surge charge entering the N-type diffusion region 53d passes through the N-type diffusion region 53s and flows out to GND. As a result, a large charge due to an electrostatic surge does not flow into the A circuit 101 and the B circuit 102, and the circuit is protected.

According to the first embodiment having such a configuration, the depletion layer 20 spreads when a surge is applied to the connection node 90, so that the resistance value of the parasitic resistance 56 increases. Therefore, the current value for exceeding the threshold voltage of the parasitic NPN transistor 57 becomes small. Then, the parasitic NPN transistor 57 is quickly turned on and enters a snapback state, and the surge charge is quickly released to GND. As a result, even when a surge occurs, the voltage applied to the internal circuit (A circuit 101, B circuit 102) can be kept low, and the circuit can be reliably protected.
FIG. 7 is a diagram showing the snapback characteristics of the protection element 50. As shown in FIG. 7, the voltage V1 immediately before snapback is smaller than in the prior art, and the load on the internal circuit is reduced.

  In this embodiment, since the N-channel transistors are provided in parallel, the parasitic NPN transistor 57 is also formed in parallel. As a result, surge charges can be released more efficiently.

(Second embodiment)
Next, a second embodiment of the present invention will be described.
The basic configuration of the second embodiment is the same as that of the first embodiment. In the second embodiment, the N well region 22 is formed in the P− diffusion region 21 so as to further increase the resistance value of the parasitic resistance 56. Characterized by points.
FIG. 8 is a diagram showing a second embodiment.
In FIG. 8, an N well region 22 is formed in the P − diffusion region 21. The N well region 22 has an upper end reaching the N-type diffusion region 53 and a lower end reaching the P − type substrate 11 in the P − diffusion region 21. The N well region 22 is separated from the first P well region 55a and the second P well region 55b by a predetermined distance. By providing the N well region 22 in this manner, the depletion layer 20 extends to the P − type diffusion region 21 and the P − type substrate 11 adjacent to the N well region 22.

In the second embodiment having such a configuration, when a surge due to static electricity is applied to the connection node 90, the surge is applied to the N-type diffusion region 53 via the wiring layer 53a. At this time, the depletion layer 20 spreads greatly, and particularly in the second embodiment, since the lower end of the N well region 22 reaches the P − type substrate 11, the depletion layer 20 spreads greatly toward the P − type substrate 11.
As the depletion layer 20 spreads toward the P− type substrate 11 in this way, the resistance value of the parasitic resistance 56 increases. Then, the parasitic NPN transistor 57 is turned on and it becomes easy to enter the snapback state. FIG. 9 is a diagram showing snapback characteristics of the protection element in the second embodiment. As shown in FIG. 9, the voltage V2 immediately before snapback is smaller than that of the protection element of the first embodiment, and the load on the internal circuit can be further reduced. Therefore, the voltage applied to the internal circuit (A circuit 101, B circuit 102) can be lowered, and the ESD tolerance can be improved.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.
Even in the configuration in which the N-type semiconductor and the P-type semiconductor of the above embodiment are in a complementary relationship, the same operational effects as those of the present invention can be obtained. In this case, when a negative surge is applied to the connection node, it functions as a protective element by letting this surge escape to the positive power supply VDD side.

  In the second embodiment, the case where the lower end of the N well region 22 has reached the P-type substrate 11 has been shown, but the lower end may not reach the substrate 11, and if there is a certain depth, the corresponding amount There is an effect.

  In the first embodiment, a P − type well region having a lower impurity concentration than the first and second P well regions is formed as a third well region as a third well region between the first P well region and the second P well region. However, the third well region may be formed with a conductivity type well opposite to that of the first well region and the second well region, that is, an N-type well. Even in such a configuration, the depletion layer spreads to the substrate side when a surge is applied, so that the same effect as the above-described embodiment can be obtained.

It is a figure which shows an example which applies the protection element of this invention to an actual circuit. FIG. 3 is a cross-sectional view of a protection element in the first embodiment. FIG. 2 is a plan view of a protection element in the first embodiment. The figure which showed explicitly the parasitic NPN transistor, parasitic diode, and parasitic resistance which are formed in a protection element in 1st Embodiment. FIG. 3 is an equivalent circuit diagram of a parasitic NPN transistor, a parasitic diode, and a parasitic resistance in the first embodiment. FIG. 3 is a diagram showing a state where a depletion layer spreads in the first embodiment. FIG. 3 is a diagram showing snapback characteristics of a protection element in the first embodiment. The figure which shows 2nd Embodiment. FIG. 6 is a diagram showing snapback characteristics of a protection element in a second embodiment. The figure which shows the conventional protective element. The figure which shows the conventional protective element. The figure which shows the snapback characteristic of the conventional protective element.

Explanation of symbols

1 ... P-type substrate, 2 ... element isolation layer, 3 ... N-type well, 4 ... N-type well, 5 ... N-type well, 7 ... P-type well, 8 ... P-type well, 8A ... P-type well, 8A ... P type well, 11 ... P type substrate, 13 ... N + type diffusion layer, 14 ... N + type diffusion layer, 15 ... N + type diffusion layer, 18 ... P + type diffusion layer, 20 ... depletion layer, 21 ... P-type well region , 22 ... N well region, 27 ... Gate electrode, 31 ... Parasitic NPN transistor, 32 ... Base bias resistor, 40 ... External terminal, 50 ... Protection element, 51 ... Field oxide film, 52 ... P + type diffusion region, 52 ... P + Type semiconductor diffusion region, 52a ... wiring layer, 53 ... N type diffusion region, 53a ... wiring layer, 53d ... N type diffusion region, 53da ... wiring layer, 53s ... N type diffusion region, 53sa ... wiring layer, 54 ... gate, 55a ... first P well region, 55b ... second P well region, 56 ... parasitic resistance, 57 ... parasitic NPN transistor, 58 ... parasitic diode, 64 ... contact hole, 90 ... connection node, 101 ... A circuit, 102 ... B circuit, 103 ... Line, 20 0 ... Protective element.

Claims (6)

A protection element connected to a connection node to a protection target circuit and protecting the protection target circuit from surge destruction,
A first conductivity type first well region formed in a semiconductor substrate;
A first electrode and a second electrode that are of the second conductivity type formed across a part of the first well region in the upper layer of the first well region;
A second well region of a first conductivity type formed surrounding the first well region;
It is formed between the first well region and the second well region and is of the second conductivity type, or the first conductivity type having an impurity concentration lower than that of the first well region and the second well region. A third well region;
A third electrode of a second conductivity type provided in an upper layer of the third well region,
Either one of the first electrode and the second electrode is connected to the connection node and the other is connected to a power source,
The second well region is connected to the power source;
The protective element, wherein the third electrode is connected to the connection node. In the protective element according to claim 1,
The third well region is a first conductivity type having a lower impurity concentration than the first well and the second well,
In the third well region, a fourth well region of a second conductivity type extending from the lower end of the third electrode toward the semiconductor substrate is formed. In the protective element according to claim 1 or claim 2,
A parasitic transistor having the first electrode and the second electrode as main electrodes is configured in the first well region,
The protection element, wherein the parasitic transistor and the power source are electrically connected via a resistance component of the semiconductor substrate on a lower layer side of the third well region. In the protective element according to any one of claims 1 to 3,
The first conductivity type is N type,
The second conductivity type is P type,
The protective element, wherein the power source is a ground power source. 5. The protection element according to claim 1, wherein a plurality of second electrodes are provided in parallel with a first electrode formed in a central portion in an upper layer of the first well region. A protective element characterized by being provided. An electrostatic protection element composed of a bipolar element parasitic to a terminal of a semiconductor device,
A parasitic resistance element that biases the base terminal of the parasitic bipolar element according to a voltage applied to the terminal;
The protection element, wherein a resistance value of the parasitic resistance element is variable according to a voltage applied to the terminal.

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