JP2009508323A - Method for forming shallow grooves - Google Patents

Abstract

【Task】
For example, a method of forming a shallow trench used for shallow trench isolation includes the steps of providing a p-type silicon substrate and forming a layer on the p-type silicon substrate, wherein the layer is n-type silicon. It includes p-type silicon disposed in between. The p-type silicon disposed between the n-type silicons is then subjected to anodization to form porous silicon. Next, the porous silicon region is oxidized. By controlling the porosity of the silicon layer, an element isolation region is formed that is substantially flush with or above the upper surface of the n-type upper end layer. For example, by adjusting the anodizing time, a shallow groove having a receding cross-sectional shape can be obtained, and element isolation between adjacent devices is improved.
[Selection] Figure 2C

Description

  The field of the invention relates to methods for forming shallow trenches in semiconductor devices. In particular, the field of the invention relates to processes for making grooves for use in electrical element isolation, such as shallow groove element isolation (STI).

  The semiconductor industry is becoming increasingly active to reduce the size of semiconductor devices placed on integrated circuits. For example, a current semiconductor product needs to have a high circuit density and needs to be miniaturized. As recording density increases and device size decreases, semiconductor device structures such as transistors must be placed closer together. In order to make adjacent transistors close to each other, a method of arranging an electrical element isolation structure between adjacent transistors has been developed. Several techniques or element isolation processes provide the element isolation required for integrated semiconductor devices.

One of the processes is silicon selective oxidation (LOCOS). LOCOS is a thermally grown SiO ₂ pad that separates adjacent devices (eg, PMOS and NMOS transistors in a CMOS structure). The selective oxidation is performed by using silicon nitride (Si ₃ N ₄ ) to prevent silicon from being oxidized in a selected region. Next, this Si ₃ N ₄ is removed by etching, followed by thermal oxidation. The LOCOS process is widely used as an element isolation technique for very large scale integration (VLSI) circuits. Disadvantageously, the LOCOS device isolation process faces limitations in the smaller submicron technology of the known “bird's beak” problem that reduces recording density.

  An alternative element isolation technique or process known as shallow trench element isolation (STI) has been developed to provide electrical element isolation between adjacent CMOS transistors. In STI, a shallow groove having a depth of about 2500 mm is formed. Next, thermal oxidation is performed to fill the shallow groove. Disadvantageously, this filling process creates a non-planar surface and requires chemical mechanical polishing (CMP) to planarize the structure. Thus, the conventional STI process comprises one mask level, one vapor phase etch step, one oxidation step, and one CMP step. The cross-sectional shape of the oxide is usually controlled by dry etching conditions.

  Regardless of the process used, the element isolation structure formed is the element between the source and drain regions between adjacent transistors, and similarly between the source and drain regions of the same transistor (when turned off). Characterized by the effectiveness of separation. An important numerical indicator of the effectiveness of a particular device isolation structure is the maximum voltage that the structure can withstand before high current flows, the source-to-drain leakage current when the transistor is “off” , And the magnitude of the short channel effect.

  As described above, the conventional STI process includes a CMP planarization step. Disadvantageously, the CMP process is generally an expensive process and often includes drawbacks that create many limitations. These include residual slurry, surface voids, and surface particles. Also, during polishing, microscratches are formed when small particles or other small pieces are trapped between the polishing pad and the substrate surface.

  Thus, there is a need for an STI-based process that does not require a CMP planarization step. This process can form a complete or nearly perfect flat shape on the substrate as compared to the shape from a CMP based process. Furthermore, there is a need for an alternative STI structure formation process capable of adjusting the cross-sectional shape of the groove to improve electrical characteristics.

In one aspect of the present invention, a method for forming an isolation structure in a substrate includes providing a p-type silicon substrate and forming an n-type layer on the p-type silicon substrate. This n-type layer can be formed by ion implantation, for example. A silicon dioxide (SiO ₂ ) layer is deposited on the n-type layer, and then a silicon nitride (Si ₃ N ₄ ) layer is formed. The silicon nitride layer and the silicon dioxide layer are selectively removed, and an element isolation structure (for example, a shallow groove) is positioned so that a part of the n-type layer is exposed there. Then, ions are implanted into the n-type layer to form a p-type region. Next, porous silicon is formed in the p-type region. Next, the porous silicon is oxidized to form an element isolation structure.

  In another aspect of the present invention, a method for forming an element isolation structure in a substrate includes providing a p-type silicon substrate, forming a silicon dioxide layer on the p-type silicon substrate, and on the silicon dioxide layer. Forming a silicon nitride layer. A mask is provided on the p-type silicon substrate. At least part of the silicon dioxide layer and the silicon nitride layer is removed. Then, n-type ion implantation is performed on the exposed p-type silicon substrate layer to form an n-type region in the vicinity of the p-type region. Next, the p-type region is changed to porous silicon. Next, the porous silicon is oxidized to form an element isolation structure.

  In another aspect of the present invention, a method for forming an element isolation structure in a substrate includes the steps of providing a p-type silicon substrate and forming an upper end layer on the p-type silicon substrate. , P-type silicon disposed between n-type silicon. Next, porous silicon is formed in the p-type silicon region of the upper end layer. Next, the porous silicon is oxidized to form an element isolation structure.

  In one aspect of the invention, the oxidized porous silicon is substantially coplanar with the upper surface of the n-type layer. In another aspect of the invention, the oxidized porous silicon used to form the device isolation structure protrudes above the upper surface of the n-type layer. In yet another aspect of the present invention, the oxidized porous silicon used to form the element isolation structure is recessed below the upper surface of the n-type layer. The above-described configuration can be achieved by controlling the porosity of porous silicon.

  Further characteristics and advantages will become apparent with reference to the attached drawings and description of the best mode.

  FIG. 1 shows a cross-sectional view of a semiconductor device 2 formed by the groove formation method described herein. FIG. 1 shows a semiconductor device 2 in the form of a CMOS transistor 4 formed on a substrate 6. Transistor 4 comprises a gate oxide region 8 and a gate electrode 10 overlying it. Transistor 4 comprises a source 12 region and a drain 14 region and a corresponding channel region 16 below and below gate oxide region 8. Referring to FIG. 1, the semiconductor device 2 includes element isolation regions arranged on all side surfaces of the transistor 4 (two regions 18 and 20 are shown in FIG. 1). The element isolation regions 18 and 20 can take the form of shallow grooves as shown in FIG. 1, and the transistor 4 (for example, the source and drain regions 12 and 14) is separated from the adjacent transistor 4 (not shown). Useful for element isolation.

  2A, 2B, 2C, and 2D show the substrate 30 and associated layers that form a single device isolation region 31 (eg, device isolation regions 18 and 20 shown in FIG. 1 and device isolation region 31 of FIG. 2D). It is sectional drawing. 2A to 2D are diagrams showing the structure of a single element isolation region 31, but a plurality of element isolation regions 31 may be formed on a single substrate 30 by the processes and methods described herein. .

Referring to FIG. 2A, a p-type silicon substrate 30 is provided. Next, n-type ion implantation is performed on the p-type silicon substrate 30 (see the arrow in FIG. 2A) so as to overcompensate the p-type substrate 30, thereby forming a surface layer 32 of n-type silicon. The doping concentration of the n-type surface layer 32 is slightly higher than the doping concentration of the underlying p-type silicon substrate 30. Next, a thermal annealing process is performed on the substrate 30 including the n-type surface layer 32 in order to activate the implanted dopant. In one aspect of this method, the thickness t _n of the formed n-type layer 32 is greater than the thickness or depth required for the element isolation region 31 (shallow trench). However, in an alternative aspect of the invention, the thickness of this n-type layer is less than the final oxide thickness. This structure is desirable for many circuits (eg, illustrated in FIGS. 2C and 2D) that require retraction of the oxide region cross-sectional shape. In another aspect of the present invention, a blank SiO ₂ mask layer (not shown) is used to control the shape of the element isolation region 31. The use of a blank SiO ₂ mask layer in this manner is known to those skilled in the semiconductor manufacturing process.

Referring now to FIG. 2B, a relatively thin oxide or pad layer 34 is deposited on the exposed n-type surface layer 32. In a preferred embodiment of the present invention, the thickness of the pad layer 34 is about 100 inches. The pad layer 34 is under a thicker Si ₃ N ₄ layer 36 (eg, a layer containing Si ₃ N ₄ ). For example, a Si ₃ N ₄ layer 36 is deposited on the substrate 30 using LPCVD technology. In one aspect of this process, the thickness of the Si ₃ N ₄ layer 36 is about 1000 mm. Combining the pad oxide layer 24 and the Si ₃ N ₄ layer 36 is well known in the silicon VLSI industry.

Next, the SiO ₂ / Si ₃ N ₄ stack is patterned using the photoresist layer 38, and the substrate 30 is etched to expose a region or a portion exposing the element isolation region 31 (for example, a groove). For example, the element isolation region 31 is exposed or made available by a technique used in the conventional LOCOS process. Next, p-type ion implantation is performed on the substrate 30 (indicated by an arrow in FIG. 2B) to convert the silicon 39 region used to form the element isolation region 31 into p-type silicon. The p-type ion implantation is preferably performed with a single dose or multiple doses that overcompensate the doping level of the n-type layer 32. In order to achieve a uniform doping concentration throughout the thickness of layer 32, multiple energy injections are required. Following the p-type ion implantation, the photoresist layer 38 is removed, and then a thermal annealing process is performed on the substrate 30 to activate the dopant.

  Referring now to FIG. 2C, the substrate 30 is then anodized to selectively form porous silicon 40 in the p-type region 39 formed by ion implantation. The porous silicon 40 comprises a silicon network that penetrates through the pores. Many known methods for forming porous silicon are available for the methods described herein. For example, electrochemical anodization of p-type silicon can be performed in a tank or cell using a hydrofluoric acid (HF) based electrolyte. For example, electrochemical anodization may be performed using a single tank or a double tank cell. Since the single tank and the double tank cell are known as a porous silicon forming apparatus, details thereof will not be described here.

  In a preferred embodiment of the present invention, the characteristics of the porous silicon 40 formed in the p-type region 39 can be controlled or optimized for a specific element isolation region 31. For example, the anodizing process may be adjusted to provide porous silicon 40 having predetermined physical characteristics. These physical characteristics include, for example, the size of the holes and branches, the porosity of the silicon, the orientation of the holes and branches, and the overall thickness of the porous silicon 40. In general, these parameters are controlled by the amount and type of doping used to form the p-type layer, electrolyte concentration (eg, hydrogen fluoride concentration), electrolyte pH, anodizing current density, and anodizing time. it can.

  In one aspect of the process, a substantially flat shape is desired between the oxide field 31 and the n-type layer 32 (ie, the upper end of the porous silicon 40 is substantially the same as the upper end of the n-type layer 32). On the plane). In this embodiment, the porous silicon 40 has a porosity in the range of about 50% to about 60%, more preferably a porosity of about 55%. This is because the volume of silicon becomes about 2.2 times larger during the oxidation process.

Referring now to FIG. 2D, the substrate 30 is then subjected to an oxidation process. The oxidation treatment includes, for example, immersing the substrate 30 in an environment containing an oxidant and / or holding the substrate 30 at a high temperature in an environment containing oxygen. Alternatively, photooxidation or other known techniques known to those skilled in the art can be utilized. During the oxidation process, it is preferable that the region including the porous silicon 40 is completely oxidized so that the oxide thickness of the bulk substrate 30 is at a minimum, for example, on the order of 100 mm. In addition, during the oxidation process, oxidation occurs in the edge regions of the Si ₃ N ₄ mask layer 36 to form structures or protrusions known as “bird beaks”. Similar to the erosion due to the oxidation treatment, the side struggle naturally increases with the implantation depth in the normal ion implantation process, so that the cross-sectional shape of the element isolation region 31 (for example, the element isolation groove) becomes “hourglass (hour glass) ”shape. In general, the “hour glass” cross-sectional shape provides better element isolation between adjacent semiconductor devices 2 (eg, transistors) while providing a high field region along the periphery of the activated silicon region. Will prevent the formation of.

  In an alternative aspect of the process, it is desirable to form an isolation region 31 that protrudes above or is depressed below the adjacent n-type silicon layer 32. This can be created by controlling the porosity of the porous silicon 40 during the anodization step. Further, as shown in FIGS. 2C and 2D, the amount or degree of the lowermost region of the element isolation region 31 that recedes, and the range in which the “bird's beak” is formed can be adjusted by controlling the oxidation treatment conditions. it can. For example, the degree of retreat can be controlled by controlling the anodizing time. Retreating the element isolation region 31 under the source and drain regions 12 and 14 of the semiconductor device 2 reduces the capacitance from the source / drain to the substrate.

  In another aspect of the invention, a channel stop implant (not shown) can optionally be formed either before or after the oxidation step shown in FIG. 2D. When forming the semiconductor device 2, the process described above can be followed by a process of separating the p and n tabs using a conventional process such as p-type ion implantation. Finally, when the semiconductor device 2 forms a field effect transistor (FET), it is connected to the shallow groove 31 by adding another photolithography level, and is arranged directly under the channel region. Oxide stripes or similar structures can be formed that minimize the short channel effect.

  One important feature of the process is that the cross-sectional shape of the shallow groove can be adjusted by controlling the porosity and the depth of the porous region. In the latest VLSI, the dimensions of individual transistors are on the order of 100 nm. Because of these small dimensions, shallow groove strain can have a significant effect on FET channel region strain. The pressure applied to the channel region is compressed by the shallow groove formed by the oxidation treatment. Shown are channel regions compressed and distorted to improve hole mobility in p-MOSFETs. This strain in the channel region can be adjusted from zero to full compression by controlling the porosity and shape of the groove cross section. This is another advantage of the process.

3A, 3B, and 3C are diagrams illustrating an alternative process for forming one or more element isolation regions 31. FIG. Unlike the process disclosed in FIGS. 2A to 2D, the element isolation region 31 can be formed using a single ion implantation step (n-type). There is no need for a second ion implantation step to convert n-type silicon to p-type. Referring to FIG. 3A, a p-type silicon substrate 50 is provided with a relatively thin pad oxide layer 52 covered with a Si ₃ N ₄ ion implantation screening layer 54. The mask 56 is provided on the Si ₃ N ₄ ion implantation screening layer 54 at a position where the element isolation region 31 is formed.

  Referring to FIG. 3B, the substrate 50 is then n-type ion implanted (indicated by an arrow in FIG. 3B). During this step, the exposed top surface layer 58 of the substrate 50 is converted to n-type silicon. In order to make the doping concentration substantially uniform throughout the top layer, multiple energy injections are required. Substrate 50 portion 60 located under mask 56 is not converted to n-type silicon (it remains p-type). Next, as described in detail above with reference to FIGS. 2A to 2D, the substrate 50 is subjected to an anodizing process and a subsequent oxidizing process step to form porous silicon in the element isolation region 31. The process described in FIGS. 3A to 3D is particularly useful for forming narrow element isolation regions 31 (eg, trenches). This is because non-zero side struggles by ion implantation result in a recessed implant shape. The resulting p-region is therefore smaller (ie, narrower) than the width of the mask.

  The advantages of the methods described here over conventional methods are that they do not require a subsequent CMP process. The CMP process is generally an expensive process and often includes many disadvantages that limit yield. By the process disclosed here, a completely or almost completely flat element isolation region can be formed. Further, according to the process, the electronic processing capability can be optimized by adjusting the cross section of the element isolation region.

  While embodiments of the invention have been illustrated and described, various modifications can be made without departing from the scope of the invention. Therefore, the present invention is not limited to the claims and their equivalents.

FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device constructed by the trench formation method disclosed herein. FIG. 2A is a diagram illustrating a step of forming a shallow groove in a semiconductor device according to an embodiment of the present invention. FIG. 2B is a diagram illustrating a step of forming a shallow groove in a semiconductor device according to an embodiment of the present invention. FIG. 2C is a diagram illustrating a step of forming a shallow groove in a semiconductor device according to an embodiment of the present invention. FIG. 2D is a diagram illustrating a step of forming a shallow groove in a semiconductor device according to an embodiment of the present invention. FIG. 3A is a diagram illustrating a step of forming a shallow groove in a semiconductor device according to another embodiment of the present invention. FIG. 3B is a diagram illustrating a step of forming a shallow groove in a semiconductor device according to another embodiment of the present invention. FIG. 3C illustrates a step of forming a shallow groove in a semiconductor device according to another embodiment of the present invention.

Claims (20)

A method of forming an element isolation structure on a substrate includes:
a) forming an n-type layer on a p-type silicon substrate;
b) disposing a layer containing Si ₃ N ₄ on the n-type layer;
c) exposing at least part of the n-type layer by removing at least part of the layer comprising Si ₃ N ₄ ;
d) performing a p-type ion implantation on a part of the exposed n-type layer to form a p-type region; and performing a thermal annealing process;
e) forming porous silicon in the p-type region of step (d); and f) oxidizing at least a portion of the porous silicon;
A method of forming an element isolation structure comprising: The method of claim 1 further comprising the step of removing the Si ₃ N ₄ containing layer from the substrate.   2. The method of claim 1, wherein the oxidized porous silicon is substantially coplanar with the upper surface of the n-type layer.   2. The method of claim 1 wherein the oxidized porous silicon protrudes above the upper surface of the n-type layer.   2. The method of claim 1, wherein the oxidized porous silicon is recessed below the upper surface of the n-type layer.   2. The method of claim 1, wherein the thickness of the n-type layer is less than the thickness of the oxidized porous silicon.   The method of claim 1, wherein the porous silicon is formed by anodization.   2. The method of claim 1, wherein the n-type layer is formed by n-type ion implantation into the p-type silicon substrate.   2. The method of claim 1, wherein the isolation structure includes a lower recessed portion. A method of forming an element isolation structure on a substrate includes:
a) disposing a layer containing Si ₃ N ₄ on a p-type silicon substrate;
b) providing a mask on the p-type silicon substrate;
c) removing at least part of the layer comprising Si ₃ N ₄ ;
d) performing n-type ion implantation on the exposed p-type silicon substrate layer to form an n-type region in the vicinity of the p-type region;
e) forming porous silicon in the p-type region of step (d); and f) oxidizing at least a portion of the porous silicon;
A method of forming an element isolation structure, comprising: The method of claim 10 further, the method characterized by comprising the step of removing the layer containing the Si ₃ N ₄ from the substrate.   11. The method of claim 10, wherein the oxidized porous silicon is substantially coplanar with the upper surface of the n-type layer.   11. The method of claim 10, wherein the oxidized porous silicon protrudes above the upper surface of the n-type layer.   11. The method of claim 10, wherein the oxidized porous silicon is recessed below the upper surface of the n-type layer.   The method according to claim 10, wherein the element isolation structure has a receding cross-sectional shape.   The method according to claim 10, wherein the porous silicon is formed by anodization.   A semiconductor device made by the method of claim 1.   A semiconductor device made by the method of claim 10. A method of forming an element isolation structure on a substrate includes:
a) forming a layer on top of a p-type silicon substrate, the layer comprising p-type silicon disposed between n-type silicon;
b) forming porous silicon on the p-type silicon portion formed in step (a); and c) oxidizing at least a portion of the porous silicon;
A method characterized by comprising:   The method of claim 19, wherein the oxidized porous silicon is substantially coplanar with the upper surface of the n-type layer.

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