JP2009302704A - Decoding device, information processing system and dynamic image recording and reproducing system - Google Patents

Abstract

A decoding apparatus capable of simultaneously decoding bit streams of different frame rates using a single decoder.
A decoding apparatus according to the present invention includes a plurality of decoding request units 10101 and 10112 that issue a frame decoding request for each frame period of a bit stream, and a decoding that decodes a frame corresponding to the frame decoding request within a cycle by time division. Unit 10103, an arbitration unit 10102 that arbitrates frame decoding request contention and notifies the decoding unit, and a reference channel selection unit 1010202 that selects one of a plurality of bitstreams as a reference channel. Arbitration is performed so that a frame decode request corresponding to the reference channel is fixedly assigned to a reference cycle that is a cycle corresponding to the frame period of the reference channel, and a frame decode request corresponding to other than the reference channel is assigned to a cycle other than the reference cycle. Mediate.
[Selection] Figure 1

Description

  The present invention relates to a decoding device, an information processing system, and a moving image recording / reproducing system that are incorporated in a moving image recording / reproducing system for recording / reproducing moving image data and that decode and display a moving image from a selected video stream.

  In a conventional information processing system, for example, when MPEG2 is used as an image signal encoding method, information such as an image frame rate is used as a header in a video elementary stream (hereinafter referred to as a video ES) during compression. Multiplex and transmit to the decoding device. In the decoding apparatus, the header information is analyzed, and the internal operation is switched based on the analysis result (see, for example, Patent Document 1).

  Converts a 24 frames / second progressive scan image (referred to as 24P) commonly used in film images such as movies into a 59.94 frame / second progressive scan image (referred to as 60P) commonly used in TV signals. This is generally called telecine conversion or 2-3 pulldown. In telecine conversion, the frame frequency is set to 30 Hz (the field frequencies are 60 Hz and 60 i by repeating the creation of field images of 2 fields, 3 fields, 2 fields, and 3 fields in chronological order from one frame of movie film. (See, for example, Patent Document 2).

A decoding apparatus incorporated in a conventional information processing system is configured to output a video ES encoded in 24P by combining these techniques in 24P, or convert it to 60P and output it.
JP 2000-354241 A JP 2001-145060 A

  However, in such a conventional information processing system, when it is configured to include a single decoder and decode the data of bit streams of a plurality of channels in a time division manner, for example, bits of different frame rates such as 24P and 30P. Since the decoding timings of streams differ depending on the frame rate, they cannot be decoded simultaneously as they are. Therefore, there is a problem that decoding cannot be performed at the same time unless frame rate conversion processing is performed such that the 24P bit stream is decoded while converting the frame rate to 30P by 2-3 pulldown or the like.

  The present invention has been made in view of the above-described conventional problems, and includes a single decoder, and in the case of taking a configuration in which bitstream data of a plurality of channels is decoded in a time division manner, different frame rates are provided. An object of the present invention is to provide a decoding device, an information processing system, and a moving image recording / reproducing system capable of simultaneously decoding the bit streams.

In order to solve the above problems, a decoding device of the present invention is a decoding device that decodes a plurality of bitstreams in a time-sharing manner, provided corresponding to the plurality of bitstreams, and for each frame period of the corresponding bitstream. A plurality of decode request units for issuing a decode request for a frame, a decode unit for decoding a frame corresponding to the decode request in a cycle by time division, and an arbitration unit for arbitrating a conflict of the decode request and notifying the decode unit And a selection unit that selects one of the plurality of bitstreams as a reference channel, wherein the arbitration unit is a cycle corresponding to a frame period of the reference channel for a decoding request corresponding to the reference channel. Arbitration to be fixedly assigned to the reference cycle, and to the reference channel When a corresponding decode request and a decode request corresponding to a bit stream other than the reference channel compete, arbitration is performed so that a decode request corresponding to a bit stream other than the reference channel is assigned to a cycle other than the reference cycle. Features. Here, when the decoding request corresponding to the reference channel and the decoding request corresponding to the bit stream other than the reference channel compete with each other, the arbitration unit outputs a decoding request corresponding to the bit stream other than the reference channel, Arbitration may be performed to allocate to the next cycle of the reference cycle.

  With this configuration, it is possible to simultaneously decode bit streams of different frame rates of a plurality of channels without performing frame rate conversion.

  Here, the decoding device may further include a channel designation unit that accepts designation of a channel, and the selection unit may select the reference channel according to the designation accepted by the channel designation unit.

  With this configuration, it is possible to dynamically select a channel whose decoding timing is fixed.

  Here, the decoding apparatus further includes a frame rate determining unit that determines a bit stream having the highest frame rate among the plurality of bit streams, and the selecting unit selects the bit stream having the highest frame rate as the reference channel. You may make it select as.

  With this configuration, the most efficient channel can be automatically selected when the decoding timing is fixed.

  Here, the decoding device further includes a conversion designating unit that receives designation of frame rate conversion, and the decoding request unit receives a bitstream other than the reference channel when the designation of frame rate conversion is accepted in the conversion designating unit. May be issued so that the frame rate is converted to the same frame rate as the reference channel.

  With this configuration, it is possible to select whether or not to convert the frame rate when decoding bit streams having different frame rates of a plurality of channels.

  Further, an information processing system of the present invention includes the decoding device described above and a frame buffer device that stores moving image data output from the decoding device, and the decoding device further includes a state of the frame buffer device. A frame buffer management unit that manages a bit stream other than the reference channel when a decode request corresponding to the reference channel and a decode request corresponding to a bit stream other than the reference channel compete with each other. The arbitration is performed so that the decoding request corresponding to the above is assigned to a cycle other than the reference cycle and to a cycle in which the frame buffer device has an empty space for one frame.

  With such a configuration, it is possible to convert the decoding timing in accordance with the frame buffer availability and save the number of frame buffer planes and avoid overwriting.

  Here, the information processing system further reads out the moving image data stored in the frame buffer device and outputs it as a moving image signal, and encodes the moving image signal output from the display control device. An encoder device, and the reference channel selection unit may select a bit stream corresponding to a moving image signal input to the encoder device as the reference channel.

  With such a configuration, it is possible to automatically select a channel to be input to an encoder apparatus whose decoding timing cannot be changed.

  Here, the display control device further includes a display system connection terminal unit for supplying a moving image signal to an external display system, and the display control device supports a moving image corresponding to a bit stream other than the reference channel. Data may be read from the frame buffer device and supplied to the display system connection terminal unit as a moving image signal.

  With this configuration, it is possible to simultaneously decode moving image data for display systems having different frame rates and moving image data input to an encoder device whose decoding timing cannot be changed.

  The moving image recording / playback system of the present invention includes the information processing system, a bit buffer device that stores a plurality of bit streams, a bit stream input device that supplies the plurality of bit streams to the bit buffer device, A storage device that stores moving image data output from the encoder device, and the bit buffer device supplies the plurality of bit streams to the plurality of decoding request units and the decoding unit.

  With such a configuration, it is possible to configure a moving image recording / playback system that simultaneously decodes moving image data for display systems having different frame rates and moving image data input to an encoder device whose decoding timing cannot be changed.

  According to the information processing system of the present invention, when bitstream data of a plurality of channels is decoded in a time division manner with a single decoder, bitstreams with different frame rates can be decoded simultaneously.

  Hereinafter, embodiments of an information processing system and the like will be described with reference to the drawings. In addition, since the component which attached | subjected the same code | symbol in embodiment performs the same operation | movement, description may be abbreviate | omitted again.

(Embodiment 1)
The decoding device according to the present embodiment is a decoding device that decodes a plurality of bitstreams in a time division manner, and includes a single decoding unit that decodes a frame of each bitstream in a time division cycle, and the reference A reference channel is fixedly assigned to a cycle (referred to as a reference cycle) corresponding to a frame period of a reference channel, which is a bit stream, and a bit stream other than the reference channel is assigned to a cycle other than the reference cycle. Accordingly, when a plurality of bit stream frames are decoded in a time division manner by a single decoding unit, bit streams having different frame rates can be decoded simultaneously.

  A moving image recording / reproducing system including a decoding device and an information processing system according to the present embodiment will be described with reference to the drawings.

  FIG. 1 is a block diagram of a moving image recording / playback system according to the present embodiment.

  The moving image recording / playback system shown in FIG. 1 includes an information processing system 1, a display system 2, a bit buffer device 105, a bit stream input device 106, and a storage device 107.

  The information processing system 1 includes a decoder device 101, a frame buffer device 102, a display control device 103, an encoder device 104, a bit buffer device 105, a bit stream input device 106, and a storage device 107.

  The decoder device 101 includes a first decode request unit 10101, a second decode request unit 10112, an arbitration unit 10102, a decode unit 10103, a channel designation unit 10104, a frame rate conversion designation unit 10105, and a frame buffer management unit 10106. .

  The arbitration unit 10102 includes a frame rate determination unit 1101021 and a reference channel selection unit 1010202.

  The display control apparatus 103 includes a display system connection terminal unit 10301.

  The information processing system 1 can connect the display system 2 via the display system connection terminal unit 10301.

  The decoder device 101 performs time-division decoding of a plurality of channel bit streams.

  The first decoding request unit 10101 and the second decoding request unit 10112 analyze the additional information such as the image format of the original image such as the frame rate from the header information multiplexed in the bit stream, and the analysis result is sent to the arbitration unit 10102. hand over. If there is other information necessary for decoding, it may be simultaneously passed to the decoding unit. Also, a decoding request for requesting decoding of one frame is issued to the arbitration unit in synchronization with the synchronization signal at an appropriate cycle from the frame rate information. At the same time, the frame buffer management unit is notified of the decoding request. The decoding request from the first decoding request unit 10101 is notified to the arbitration unit 10102 and the frame buffer management unit 10106 as a request signal 10121. The decoding request of the second decoding request unit 10112 is notified to the arbitration unit 10102 and the frame buffer management unit 10106 as a request signal 10122. The decode request may include various information such as designation of a frame buffer to be output in addition to a simple request.

  The analysis of the bit stream is to analyze header information of the bit stream stored in the bit buffer device. When the decoding request is configured by software, a notification or a signal or the like may be notified by an argument instead of a signal. Further, in order to prevent the decode request from competing with other decode request units as much as possible, the decode request may be sent every clock cycle.

  The arbitration unit 10102 arbitrates a decoding request for a plurality of channels. The request signal from each decode request unit is shifted to a timing that does not conflict with other decode requests, and a request signal for each channel is sent to the decode unit. For example, a conflict is confirmed with respect to the decode requests received from the first decode request unit 10101 and the second decode request unit 10112, and when there is a decode request simultaneously from a plurality of channels, one decode request is shifted to a later cycle. .

  The frame rate determination unit 1101021 confirms the frame rate received from the decoding request unit, and selects the channel with the highest frame rate. When there are a plurality of channels with the highest frame rate, one of the channels is fixedly selected. There are channel selection methods such as a channel with the smallest channel number, a channel with the largest channel number, and a decision method such as sequentially selecting channels.

  The frame rate is an index indicating how many times the screen is updated per unit time. Usually expressed in numerical values per second, expressed in units of fps (Frames Per Second) or frequency.

  The reference channel selection unit 1010202 selects one channel from among a plurality of bit streams to be decoded by the decoder device. As a selection method, a channel may be fixedly determined, or may be selected by using a selection method described later.

  The decoding unit 10103 includes a single decoder and decodes bitstream data of a plurality of channels in a time division manner. The decoding process is to decode a bit stream of a channel for which a decoding request has been made into moving image data.

  In the configuration of FIG. 1, the Ch0 and Ch1 bitstreams are decoded in a time division manner. Hereinafter, a logical decoder that decodes the Ch0 bitstream in a time division manner is referred to as Dec0, and a logical decoder that decodes the Ch1 bitstream in a time division manner is referred to as Dec1.

  The channel designation unit 10104 inputs channel selection information. The channel selection information is configured as a signal, for example. The channel designation unit 10104 is configured using registers, terminals, arguments, and the like, and notifies the reference channel selection unit of the channel to be selected.

  The frame rate conversion designation unit 10105 receives frame rate conversion selection information. The frame rate conversion selection information is configured as a signal, for example. The frame rate conversion specification unit 10105 is configured as, for example, a register or a terminal, and notifies the arbitration unit whether to convert a decoding request for a channel other than the reference channel into a frame rate equivalent to that of the reference channel.

  The frame buffer management unit 10106 manages the state of the frame buffer device 102. The frame buffer management unit 10106 estimates the free state of the frame buffer device from the request signals 10121 and 10122 from the first decode request unit 10101 and the second decode request unit 10112.

  The frame buffer device 102 stores moving image data decoded by the decoding unit 10103 in a time division manner. The moving image data is a decoded bit stream.

  The display control device 103 reads out the moving image data stored in the frame buffer device 102 and outputs it as a moving image signal. Output refers to display on a display, projection using a projector, printing on a printer, sound output, transmission to an external device, storage in a recording medium, processing results to other processing devices or other programs, etc. It is a concept that includes delivery.

  The display system connection terminal unit 10301 passes the output of the display control device 103 to the outside of the information processing system 1.

  The encoder device 104 encodes the moving image signal output from the display control device 103 into moving image data or a bit stream. The encoded data is stored in the storage device 107.

  The bit stream input device 106 supplies the bit stream to the bit buffer device 105. The bit buffer device 105 stores a bit stream of a plurality of channels.

  Next, the operation of the information processing system will be described using a timing chart and a flowchart. In the following description, the frame rate of the Ch0 bit stream is 24 Hz, and the frame rate of the Ch1 bit stream is 60 Hz.

(Example of Claim 1)
The operation of the information processing system will be described with reference to the timing chart of FIG. 2 and the flowchart of FIG.

  FIG. 2 shows signals and states when the Ch0 and Ch1 bitstreams are decoded simultaneously. 2, (a) is a 120 Hz clock signal 201, (b) is a 60 Hz synchronization signal 202, and (c) is a Ch0 request indicating the value of the request signal 10121 of the first decoding request unit 10101 for analyzing the Ch0 bitstream. Signals 203 and (d) are Ch1 request signals 204 indicating the value of the request signal 10122 of the second decoding request unit 10112 for analyzing the Ch1 bit stream, and (e) is a Ch0 request holding signal 205 held in the arbitration unit 10102. , (F) shows the Ch1 request holding signal 206 held in the arbitration unit 10102, and (g) shows the decoding state 207 of the decoding unit.

  In this embodiment, Ch1 is fixedly selected as the reference channel for the sake of simplicity. Needless to say, the reference channel may be selected using a selection method described later.

  FIG. 3 shows an operation flow of the arbitration unit 10102.

  Steps S01 to S09 in the flowchart of FIG. 3 will be described below.

(Step S01)
The request holding signal of each Ch held in the arbitration unit 10102 is initialized to Lo.

(Step S02)
Wait for the next synchronization signal 202.

(Step S03)
The request holding signal of Ch for which decoding has been requested is set to Hi.

(Step S04)
If there is a Ch whose request holding signal is Hi, the process proceeds to step S02.

  If there is a Ch whose request holding signal is Hi, the process proceeds to step S05.

(Step S05)
It is confirmed whether the decoding unit 10103 is empty. If not, the process proceeds to step S06.

  If the decoding unit 10103 is empty, the process proceeds to step S07.

(Step S06)
Wait for the next cycle of the clock signal 201.

(Step S07)
Of the Ch whose request holding signal is Hi, the decoding request for the highest priority Ch is sent to the decoding unit.

(Step S08)
Wait for completion of decoding of Ch that has executed the decode request.

  Detection of decoding completion may be performed by any method such as completion notification from the decoding unit, completion timing measurement using a timer, and rising of a clock.

(Step S09)
The request holding signal of Ch that has executed the decoding request is set to Lo.

  After execution, the process proceeds to step S04.

  The timing chart of FIG. 2 will be described according to the flowchart of FIG.

  At timing 310 in FIG. 2, the arbitrating unit 10102 is in the state of step S01 in FIG. At timing 310, the Ch0 request holding signal 205 and the Ch1 request holding signal 206 are in the Lo state.

  Next, the process proceeds to step S02 and waits for the synchronization signal 202 to become Lo. At timing 311 in FIG. 3, the synchronization signal 202 becomes Lo and the waiting is released.

  Next, the process proceeds to step S03, and the Ch0 request signal 203 and the Ch1 request signal 204 become Hi at the timing 311 in FIG. The request signal from the decode request unit is output at the same time as the synchronization signal 202 becomes Hi, and is output for one cycle at the longest. In response to this, the Ch0 request holding signal 205 and the Ch1 request holding signal 206 inside the arbitration unit 10102 become Hi.

  Next, the process proceeds to step S04, and since the Ch0 request holding signal 205 and the Ch1 request holding signal 206 are Hi at the timing 311 in FIG. 2, the process proceeds to step S05.

  Next, the process proceeds to step S05, and since the decode state 207 is empty at timing 311 in FIG. 2, the process proceeds to step S07.

  Next, in step S07, there is a request to decode Ch0 and Ch1 at the timing 311 in FIG. 2, and in this embodiment, Ch1 is fixedly used as the reference channel, so Ch1 is given priority to the decoding unit 10103 for the first Ch1. Make a decode request. The decoding unit 10103 starts the first decoding of Ch1, and the decoding state 207 becomes the first decoding state of Dec1.

  Next, in step S08, the completion of decoding of Ch1 that has executed the decoding request is awaited. In this embodiment, decoding is completed within one clock, and one cycle is awaited as a fixed completion timing using a timer. Simultaneously with the completion of decoding, the decoding state 207 becomes empty.

  In step S09, the Ch1 request holding signal 206 corresponding to Ch1 is set to Lo. After execution, the process proceeds to step S04.

  Subsequently, at timing 312 in FIG. 2, the decode request 10121 of the first decode request unit 10101 and the decode request 10122 of the second decode request unit 10112 become Lo.

  The arbitrating unit 10102 proceeds to step S05 because the Ch0 request holding signal 205 is Hi in step S04. In step S05, since the decoding state 207 is empty, the process branches to step S07. In step S07, since the decoding request is only Ch0, the decoding request for Ch0 is sent to the decoding unit 10103. The decoding unit executes decoding of Ch0, and the decoding state 207 is the first decoding of Dec0. In step S08, the decoding completion is awaited, and the decoding state 207 becomes empty after the decoding is completed. The request holding signal 205 of Ch0 that has been decoded in step S09 is set to Lo, and the process proceeds to step S04. Since all the request holding signals are Lo in step S04, the process branches to step S02. In step S02, the next synchronization signal is awaited.

  At timing 313 in FIG. 2, the synchronization signal 202 becomes Lo, and the process proceeds to step S03. Since the Ch1 request signal 204 becomes Hi at timing 313, the request holding signal 206 for Ch1 is set to Hi in Step S03. In step S04, since the Ch1 request holding signal 206 is Hi, the process branches to step S05. In step S05, since the decoding state 207 is empty, the process branches to step S07. In step S07, a decoding request for Ch1, which is the reference channel, is sent to the decoding unit 10103. In step S08, the decoding completion is awaited, and the decoding state 207 becomes empty after the decoding is completed. In step S07, the Ch1 request holding signal 206 is set to Lo, and the process proceeds to step S04. Since all the request holding signals are Lo in step S04, the process branches to step S02 and waits for the next synchronization signal in step S02.

  Since the synchronization signal 201 becomes Lo at the timing 314 in FIG. 2, the synchronization signal waiting in step S02 is canceled, and the process proceeds to step S03. Since there is no decode request at timing 314, there is no Ch that sets the request holding signal to Hi. In step S04, since the request holding signal of all Ch is Lo, the process branches to step S02 and waits for the next synchronization signal.

  At timing 315 in FIG. 2, the synchronization signal 201 becomes Lo, the synchronization signal waiting in step S02 is canceled, and the process proceeds to step S03. Thereafter, the operation is the same as that at the timing 311.

  By performing such control, when the bit stream data of a plurality of channels is decoded in a time division manner with a single decoder, bit streams of different frame rates can be simultaneously decoded.

(Embodiment 2)
In the first embodiment, Ch1 is fixedly selected as the reference channel, but reference channel selection information may be passed to the reference channel selection unit 1010202 using the channel designation unit 10104 in FIG. The channel designation unit 10104 may be configured to accept channel designation from the outside as reference channel selection information. The reference channel selection unit 1010202 may select the reference channel according to the designation received by the channel designation unit 10104.

  With such a configuration, the reference channel can be dynamically set without being restricted by the input channel of the bit stream.

(Embodiment 3)
The frame rate is passed from the first decoding request unit 10101 and the second decoding request unit 10112 in FIG. 1 to the frame rate determination unit 110201, and the frame rate determination unit 1101021 determines the channel with the highest frame rate, and the reference channel The selection unit 1010202 may select the channel determined by the frame rate determination unit 11010201 as the reference channel.

  With this configuration, the most effective reference channel can be automatically selected.

(Embodiment 4)
1 is used to notify the arbitration unit 10102 of frame rate conversion selection information, convert each channel to the same frame rate as the reference channel, and the arbitration unit 10102 sends a decoding request to the decoding unit 10103. It may be done.

  With such a configuration, the conventional frame rate conversion function and the features of the present invention can coexist. The frame rate conversion uses a method such as 2-3 pull down.

(Embodiment 5)
FIG. 4 is a timing chart in which the state of the frame buffer device 102 and the state of the display control device 103 are added to FIG. 4, (h) is the Ch0 frame buffer state 208, (i) is the Ch1 frame buffer state 209, (j) is the Ch0 output synchronization signal 210, (k) is the Ch0 display state 211, and (l) is the Ch1 output synchronization signal. Reference numerals 212 and (m) denote the Ch1 display state 213. Further, (e) is a Ch0 request holding signal 215 obtained by replacing (e) Ch0 request holding signal 205 in FIG.

  The Ch0 frame buffer state 208 and the Ch1 frame buffer state 209 represent the number of frame buffers in use. The term “in use” refers to the period from when the frame buffer is reserved for outputting the decoding result to when it is output for display.

  The Ch0 output synchronization signal 210 and the Ch1 output synchronization signal 212 are determined according to the frame rate of the output bit stream. If it is generated in synchronization with the clock signal 201 and has the same frame rate as that of the synchronization signal 202, it may be synchronized with the synchronization signal 202.

  In this embodiment, the number of frame buffers is one for the sake of simplicity. Needless to say, the number of planes may be appropriately added according to the encoding method to be decoded.

  FIG. 5 is a frame chart in which step S10 is added to FIG. 3 and step S05 in FIG. 3 is replaced with step S15.

(Step S10)
Among the Chs having the request holding signal Hi, it is confirmed whether the frame buffer having the highest priority Ch is empty. If not, the process proceeds to step S06.

  If it is empty, the process proceeds to step S07.

(Step S15)
It is confirmed whether the decoding unit 10103 is empty. If not, the process proceeds to step S06.

  If the decoding unit 10103 is empty, the process proceeds to step S10.

  The operation of the timing chart of FIG. 4 will be described with reference to FIGS.

  Timing 320 is the same as timing 310 in FIG. The Ch0 frame buffer state 208 and the Ch1 frame buffer state 209 hold 0 in the initial state. The Ch0 output synchronization signal 210 and the Ch1 output synchronization signal 212 output synchronization signals at an arbitrary timing.

  Timing 321 is the same as timing 311 in FIG. In addition, since the decoding unit 10103 is empty in step S15 in FIG. 5, the process branches to step S10. Since the frame buffer of Ch1 with high priority is empty, the process branches to step S07. In step S07, the decoding unit 10103 starts decoding Ch1, one frame buffer of Ch1 is secured, and the Ch1 frame buffer state 209 transitions to 1.

  Timing 322 is the same as timing 312 in FIG. In addition, since the decoding unit 10103 is empty in step S15 in FIG. 5, the process branches to step S10. Since the frame buffer of Ch0, which is the only Ch whose request holding signal is Hi, is empty, the process branches to step S07. In step S07, the decoding unit 10103 starts decoding Ch0, one frame buffer of Ch0 is secured, and the Ch0 frame buffer state 208 transitions to 1.

  Timing 323 is in the same state as timing 313 in FIG. In addition, since the decoding unit 10103 is empty in step S15 in FIG. 5, the process branches to step S10. Since the frame buffer of Ch1 with high priority is empty, the process branches to step S07. At the same time as the Ch1 output synchronization signal 212 becomes Lo, the data in the Ch1 frame buffer is passed from the frame buffer device 102 to the display control device 103, the Ch1 frame buffer state 209 becomes 0, and the Ch1 display state 213 is decoded for the first display. The result is displayed.

  Further, Ch1 decoding is started simultaneously with the transition of the synchronization signal 202 to Hi, and the Ch1 frame buffer is secured, so the Ch1 frame buffer state 209 becomes 1.

  Timing 324 is the same as timing 314 in FIG.

  Timing 325 is the same as timing 315 in FIG. The second decoding of Ch1 is executed by the same operation as the timing 323.

  The timing 326 is substantially the same as the timing 316 in FIG. 2, but the second decoding of Ch0 is not started, and the Ch0 request holding signal 215 remains Hi.

  This is because the frame holding state of Ch0, which is the only Ch of which the request holding signal is Hi, is 1, and there is no vacancy, so that the process branches to step S06 in step S10 of FIG. In step S06, the process waits for the next cycle of the clock signal 201 and proceeds to step S04.

  At timing 327, since the Ch1 request signal 204 becomes Hi, and Ch1 is prioritized to request decoding, Ch0 is not decoded and the Ch0 request holding signal remains Hi. At the same time that the Ch0 output synchronization signal 210 becomes Lo, the data in the Ch0 frame buffer is transferred from the frame buffer device 102 to the display control device 103, the Ch0 frame buffer state 208 becomes 0, and the Ch0 display state 211 becomes the first decoding result. Display state. At the same time, the Ch1 output synchronization signal 212 becomes Lo, and at the same time, the data of the Ch1 frame buffer is transferred from the frame buffer device 102 to the display control device 103, the Ch1 frame buffer state 209 becomes 0, and the Ch1 display state 213 displays the first decoding result. It becomes a state. Immediately thereafter, the decoding of Ch1 is started, and the Ch1 frame buffer state 209 becomes 1.

  At timing 328, since only the Ch0 request holding signal is Hi, the decoding unit is empty at step S15 in FIG. 5, and the process branches to step S10. In step S10, the Ch0 frame buffer empty state is confirmed, and since the Ch0 frame buffer state 208 is 0, it is determined to be empty, and the process branches to step S07. In step S07, a Ch0 frame buffer is secured, and a decoding request for Ch0 is requested to the decoding unit 10103. Therefore, the Ch0 frame buffer state becomes 1, and the decoding state 207 transits to the second decoding state of Dec0. In step S08, the decoding is waited for, and in step S09, the Ch0 request holding signal becomes Lo.

  At timing 329, the same processing as timing 323 is performed.

  With such a configuration, it is possible to convert the decoding timing according to the frame buffer availability, thereby saving the number of frame buffer planes and avoiding overwriting.

(Embodiment 6)
When the encoder device 104 is connected in FIG. 1, Ch that gives priority to the encoder output and supplies moving image data to the encoder side may be used as the reference channel.

  With such a configuration, it is possible to automatically select a channel to be input to an encoder apparatus whose decoding timing cannot be changed.

(Embodiment 7)
When the display system 2 is connected to the display system connection terminal unit 10301 in FIG. 1, Ch selected as the reference channel is supplied to the encoder device 104, and other Ch is supplied to the display system 2. Good.

  With such a configuration, even if the frame rates of the bit stream input to the encoder apparatus whose decoding timing cannot be changed and the bit stream input to the display system are different, decoding can be performed simultaneously.

(Embodiment 8)
In FIG. 1, a moving image recording / reproducing system may be configured by combining the information processing system 1 with the bit stream input device 106, the bit buffer device 105, and the storage device 107.

  With such a configuration, it is possible to configure a moving image recording / playback system that simultaneously decodes moving image data for display systems having different frame rates and moving image data input to an encoder device whose decoding timing cannot be changed.

  In the flowcharts of FIGS. 3 and 5, the process ends when the power is turned off or the process is terminated.

  In each embodiment, the frame frequency of 60 Hz may be a frame frequency of 59.94 Hz, the frame frequency of 30 Hz may be a frame frequency of 29.97 Hz, and the frame frequency of 24 Hz. Needless to say, the frame frequency may be 23.976 Hz.

  The decoding process in each embodiment may be configured to be performed according to a decoding procedure such as MPEG or JPEG, which is a general encoding method, or may be configured for other encoding methods. Needless to say.

  Needless to say, the number of frame buffers to be managed changes according to the number of frame buffers secured in the frame buffer device.

  Needless to say, the storage device is composed of a nonvolatile storage device such as a hard disk drive, a DVD disk drive, or a flash memory.

  Although the embodiment has been described using signals, when configured by software, arguments and values may be used instead of signals. Similarly, arguments and values may be used instead of terminals and registers.

  An interrupt or a timer may be used instead of the clock signal or the synchronization signal.

  According to the present embodiment, the configuration can be expanded even when the number of bitstream inputs is three or more.

  Furthermore, the processing in the present embodiment may be realized by software. Then, this software may be distributed by software download or the like. Further, this software may be recorded and distributed on a recording medium such as a CD-ROM. This also applies to other embodiments in this specification.

  In each of the above embodiments, each process (each function) may be realized by centralized processing by a single device (system), or by distributed processing by a plurality of devices. May be.

  The present invention is not limited to the above-described embodiments, and various modifications are possible, and it goes without saying that these are also included in the scope of the present invention.

  As described above, according to the present invention, when bitstream data of a plurality of channels is decoded in a time division manner with a single decoder, the bitstreams of different frame rates are simultaneously decoded without performing frame rate conversion. can do.

  Further, it is possible to automatically select a channel whose decoding timing cannot be changed, and simultaneously decode display moving image data having different frame rates and moving image data input to the encoder apparatus.

  Further, the decoding timing can be converted according to the frame buffer availability to save the number of frame buffer planes and avoid overwriting.

  As described above, the information processing system according to the present invention has an effect that a single decoder can simultaneously decode bitstreams having different frame rates when the bitstream data of a plurality of channels is decoded in a time division manner. And is useful as a moving image recording / reproducing system, specifically, a DVD recorder, a Blu-ray recorder, or the like.

It is a block diagram of an information processing system in an embodiment of the invention. It is a timing chart of the decoder apparatus in Embodiment 1 of this invention. It is a flowchart of the arbitration part in Embodiment 1 of this invention. It is a timing chart of the decoder apparatus in Embodiment 5 of this invention. It is a flowchart of the arbitration part in Embodiment 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing system 101 Decoder apparatus 102 Frame buffer apparatus 103 Display control apparatus 104 Encoder apparatus 105 Bit buffer apparatus 106 Bit stream input apparatus 107 Storage apparatus 10101 1st decoding request part 10102 Arbitration part 10103 Decoding part 10104 Channel designation part 10105 Frame rate Conversion designation unit 10106 Frame buffer management unit 10112 Second decode request unit 2 Display system 201 Clock signal 202 Synchronization signal 203 Ch0 request signal 204 Ch1 request signal 205 Ch0 request hold signal 206 Ch1 request hold signal 207 Decode state 208 Ch0 frame buffer state 209 Ch1 frame buffer status 210 Ch0 output synchronization signal 211 Ch0 display status 212 Ch1 output Synchronization signal 213 Ch1 display state 215 Ch1 request holding signal

Claims (9)

A decoding device that decodes a plurality of bitstreams in a time-sharing manner,
A plurality of decode request units that are provided corresponding to the plurality of bit streams and issue a frame decode request for each frame period of the corresponding bit stream;
A decoding unit that decodes a frame corresponding to a decoding request within a cycle by time division;
An arbitration unit that arbitrates the contention of the decode request and notifies the decode unit;
A selection unit that selects one of the plurality of bitstreams as a reference channel;
The mediation unit
Arbitrate so that a decoding request corresponding to the reference channel is fixedly assigned to a reference cycle that is a cycle corresponding to a frame period of the reference channel;
When a decode request corresponding to the reference channel and a decode request corresponding to a bit stream other than the reference channel compete, a decode request corresponding to a bit stream other than the reference channel is assigned to a cycle other than the reference cycle. A decoding device that arbitrates.   The arbitration unit, when a decode request corresponding to the reference channel and a decode request corresponding to a bit stream other than the reference channel compete, outputs a decode request corresponding to a bit stream other than the reference channel to the reference cycle. The decoding device according to claim 1, wherein arbitration is performed so as to allocate to the next cycle. The decoding device further includes a channel designation unit that accepts designation of a channel,
The decoding device according to claim 1, wherein the selection unit selects the reference channel in accordance with the designation received by the channel designation unit. The decoding apparatus further includes a frame rate determination unit that determines a bit stream having the highest frame rate among the plurality of bit streams.
The decoding device according to claim 1, wherein the selection unit selects a bit stream having the highest frame rate as the reference channel. The decoding device further includes a conversion specification unit that receives specification of frame rate conversion,
The decode request unit issues a decode request so as to convert a bit stream other than a reference channel to the same frame rate as the reference channel when the conversion specification unit receives specification of frame rate conversion. The decoding device described. A decoding device according to any one of claims 1 to 5;
A frame buffer device for storing moving image data output by the decoding device,
The decoding device further includes a frame buffer management unit that manages the state of the frame buffer device,
When the decode request corresponding to the reference channel and the decode request corresponding to the bit stream other than the reference channel compete with each other, the arbitration unit outputs the decode request corresponding to the bit stream other than the reference channel to the reference cycle. An information processing system that performs arbitration so that it is allocated to a cycle other than the above and a cycle in which the frame buffer device has an empty space for one frame. The information processing system further includes:
A display control device for reading out the moving image data stored in the frame buffer device and outputting it as a moving image signal;
An encoder device for encoding a moving image signal output from the display control device,
The reference channel selection unit selects a bit stream corresponding to a moving image signal input to the encoder device as the reference channel.
The information processing system according to claim 6. The display control device further includes a display system connection terminal unit for supplying a moving image signal to an external display system,
The display control device reads moving image data corresponding to a bit stream other than the reference channel from the frame buffer device and supplies the data as a moving image signal to the display system connection terminal unit.
The information processing system according to claim 7. An information processing system according to claim 7 or 8,
A bit buffer device for storing a plurality of bit streams;
A bitstream input device for supplying the plurality of bitstreams to the bitbuffer device;
A storage device for storing moving image data output from the encoder device,
A moving image recording / reproducing system that supplies the plurality of bit streams from the bit buffer device to the plurality of decoding request units and the decoding unit.

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