JP2009301319A - Multiprocessor system - Google Patents

Abstract

When transferring programs A and B executed by processors 10 and 30 from a non-volatile memory 60 to storage means 20 and 40 when power is turned on, the program is transferred via an addressing device 50 The system startup time can be shortened and the system startup time can be shortened.
SOLUTION: A plurality of processors 10 and 30 having storage means 20 and 40 for storing programs A and B, and programs A and B that can be accessed from the processors 10 and 30 and are executed by the processors 10 and 30. Are stored in a non-volatile memory 60, and an addressing device 50 that can access each of the storage means 20, 40.
[Selection] Figure 1

Description

  The present invention relates to high-speed startup in a multiprocessor system.

  With the high performance of digital home appliances, multiprocessor systems with multiple processors are becoming mainstream. Generally, a program executed by each processor is stored in a nonvolatile memory, and the program is transferred from the nonvolatile memory to a higher-speed memory when the system is started. Thereafter, the program is executed on the high-speed memory. The

To speed up program transfer at system startup, for example, as in Patent Document 1, flag information indicating whether or not the program has been transferred is set in the transfer destination memory, and the flag information is confirmed at the next startup and If the program has been transferred, the program is not transferred. Such a method is disclosed.
JP-A-2-28859

  However, in systems such as digital home appliances, the memory used to execute programs uses volatile memory such as high-speed SRAM (static random access memory) and DDR (double data rate synchronous dynamic random-access memory). When the information is stored in the volatile memory, the method disclosed in Patent Document 1 resets the volatile memory when the power is turned on next time, so that the flag information disappears and eventually the program needs to be transferred. There are challenges.

  With the recent increase in functionality and performance of systems such as digital home appliances, the capacity of programs continues to increase, and as a result, the time for transferring programs to memory becomes longer and the system startup time seems to occupy a large weight. It has become. Especially in order to shoot without missing the scene you want to shoot, such as digital cameras and digital video cameras, it is necessary to shorten the time to start shooting as much as possible, and shortening the system startup time is an issue It was.

  The multiprocessor system of the present invention has a plurality of processors having storage means for storing programs, a nonvolatile memory that can be accessed from each processor, and stores a program executed by each processor, and can access each storage means An addressing device.

  A multiprocessor system in which one of the plurality of processors serves as a master processor and transfers a program executed by each processor from the nonvolatile memory to the storage unit when the power is turned on. The addressing device is used.

  Thus, when transferring a program to be executed by each processor from the non-volatile memory to the storage means when the power is turned on, the program transfer speed can be increased through the addressing device, and the system It becomes possible to shorten the start-up time.

  In addition, when one of the plurality of processors becomes a master processor and a program executed by each processor is transferred from the nonvolatile memory to the storage unit when the power is turned on, the addressing device is used. Thus, a plurality of storage means can be accessed by one address designation.

  The addressing device comprises means for simultaneously accessing a plurality of addresses for one address access.

  As described above, the addressing device can simultaneously designate a plurality of addresses for the address designated by the processor, and the data transfer from the storage means to the storage means can be speeded up.

  The addressing device includes means for registering a plurality of addresses to be accessed for one address access.

  This allows for addressing combinations.

  The addressing device includes means for controlling ON / OFF of a function for accessing a plurality of addresses for one address access.

  As a result, when it is desired to operate the system with normal access, the function can be turned off and the system can be made flexible.

  A semiconductor integrated circuit according to the present invention includes a processor having a storage unit for storing a program, an external nonvolatile memory that is accessible from the processor and stores a program executed by the processor, and an internal / external storage unit. And an addressing device that can be accessed.

  The multiprocessor system according to the present invention allows simultaneous access to a plurality of addresses with a single access from the processor, thereby speeding up data transfer and thereby shortening the program load time at power-on. It is effective for fast system startup. Further, since it is effective for speeding up data transfer, it is also effective for speeding up input image buffering processing in a digital video camera, for example.

  The present invention can obtain the same effect even in a system having a plurality of storage means regardless of the multiprocessor system.

  Embodiments of a multiprocessor system will be described below with reference to the drawings. In addition, since the component which attached | subjected the same code | symbol in embodiment performs the same operation | movement, description may be abbreviate | omitted again.

  FIG. 1 shows a configuration diagram of a multiprocessor system according to an embodiment of the present invention.

  This system comprises two processors, a master processor 10 and a slave processor 30, a non-volatile memory 60, a storage means 20, a storage means 40, and an addressing device 50, which are connected by a bus 70.

  The nonvolatile memory 60 has a startup program (100) executed at the time of reset release, an initial program loader (IPL) (101), a loader program (102) for loading the main program of each processor, and executed by each processor. Main program A (103) and main program B (104) are stored.

  The storage means 20 and the storage means 40 are memories that can be accessed at high speed, and the main program transferred from the nonvolatile memory 60 at the time of activation is normally executed by the storage means 20 and the storage means 40. In the present invention, the number of one or more processors and storage means can be increased. However, in the present embodiment, two processors and two storage means are described.

  FIG. 2 shows a startup flow of the multiprocessor system in the present embodiment. The operation at the time of starting the system in the present embodiment will be described below using the symbols in FIG.

  When the reset is released, the startup program 100 stored in the non-volatile memory 60 is executed by the master processor 10 (S10), then the IPL 101 is started (S20), and the loading program 102 is stored in the storage means 20 by this execution. (S30). Thereafter, the execution of the program shifts to execution on the storage means 20 (S40).

  The master processor 10 sets the address to be accessed simultaneously to the addressing device 50, and activates the addressing device 50 (S50). In the case of the system used in the present embodiment, the addresses of the storage device 20 and the storage device 40 are registered in the addressing device 50. Details regarding address registration to the addressing device 50 will be described in the description of FIG.

  Subsequently, the master processor 10 starts transfer processing of the main program A and the main program B stored in the nonvolatile memory 60 to the storage means 20 and the storage means 40, respectively (S60). At this time, the master processor 10 can simultaneously access the storage means 40 by accessing the storage means 20 via the addressing device 50. Details of processing steps relating to the transfer of the main programs A and B via the addressing device 50 (S60) will be described in the description of FIG.

  When the transfer of the main programs A and B is completed, the program jumps to each program, the application is activated by each main program, and a series of activation processing is completed (S70).

  FIG. 3 shows the configuration of the addressing device 50. The addressing device 50 includes an ON / OFF control unit 501, a management table unit 502 that designates whether to activate the operation of the addressing device 50, and a buffer memory for temporarily buffering data during data transfer Part 503.

  FIG. 4 illustrates the management table unit 502 configured in the addressing device 50. The management table unit 502 has a table for setting an address set as a concurrent access control, setting a target area, and setting a buffer memory surface used during the simultaneous access operation, and before activating the addressing device 50 Various settings are made in advance in the management table unit 502 from the processor. In the example shown in FIG. 4, when the processor accesses the area for 0xFFFF (64KB) from the specified address 0x10000, the area for 0xFFFF from address 0x20000 is accessed simultaneously with the area for 0xFFFF from address 0x10000. Is set to use the buffer 0 and the buffer 1 respectively.

  Using FIG. 5, the main program A arranged in the 64 kbyte area from the address 0x10000 on the non-volatile memory 60 is transferred to the 64 kbyte area from the 0xA0000 address of the storage means 20, and the address 0x50000 on the non-volatile memory. An example will be described in which the main program B arranged in the 64 kbyte area from the address is transferred from the 0xD0000 address of the storage means 40 to the 64 kbyte area.

  First, the master processor 10 sets a designated address, a post-conversion address, a region, and a buffer memory used at the time of transfer in the management table unit 502 of the address designation device 50. In this embodiment, the post-conversion address 0x10000 and 0x50000 are registered for the designated address 0x10000. Also, post-conversion addresses 0xA0000 and 0xD0000 are registered for the designated address 0xA0000. Further, in order to define the target area, 0x10000 (64 kbyte) is registered in this embodiment (S51). By doing so, when an area of 64 kbytes is accessed from address 0x10000, an area of 64 kbytes from address 0x10000 and an area of 64 kbytes from address 0x50000 can be accessed simultaneously.

  Similarly, when a 64 kbyte area is accessed from address 0xA0000, a 64 kbyte area from address 0xA0000 and a 64 kbyte area from address 0xD0000 can be accessed simultaneously.

  When the registration to the management table unit 502 is completed, the operation of the addressing device 50 is turned on (active state) (S52). By turning on the addressing device 50, when there is an access to the designated address registered in the management table unit 502, simultaneous access to the registered post-conversion address becomes valid. If the addressing device 50 is OFF (non-active), the simultaneous access operation is invalid, that is, normal access is performed.

  Note that immediately after the hard reset, the addressing device 50 is turned off and nothing is registered in the management table unit 502. Therefore, the management table is turned on before the addressing device 50 is turned on (active). Registration of information from the processor to the unit 502 is required.

  The management table unit 502 can be rewritten at any time during the operation of the program, and the processor registers information in the management table unit 502 when a case where simultaneous access is desired occurs.

  Subsequently, the master processor 10 performs a transfer operation of the main program A and the main program B. As the master processor 10, a memory TO memory instruction is executed. That is, in the present embodiment, a data transfer instruction from address 0x10000 to address 0xA0000 is being executed. In the present embodiment, the operation described below is performed through the addressing device 50 in this process.

  In accordance with the read access from the master processor 10 to address 0x10000, the address designating device 50 confirms the registered contents of the management table unit 502. If the access is to the designated address registered in advance, the address designating device 50 registers. Address conversion is performed according to the contents. In the case of this embodiment, when an area of 64 kbytes is accessed from address 0x10000, an area of 64 kbytes is simultaneously accessed from address 0x50000.

  Subsequently, the addressing device 50 reads the converted addresses, that is, data at addresses 0x10000 and 0x50000, temporarily stores the read data in the buffer memory unit 503 (S53, S54), and then continues to buffer memory The data in the unit 503 is read out and written in the addresses 0xA0000 and 0xD0000 (S55). Note that the buffer memory used at this time is registered in the management table unit 502 in advance.

  The master processor 10 sequentially executes memory-to-memory instructions from address 0x10000 to address 0xA0000, then address 0x10004 to address 0xA0004, address 0x10008 to address 0xA0008, etc. Thus, it is possible to execute simultaneously from address 0x50000 to address 0xD0000, subsequently from address 0x50004 to address 0xD0004, address 0x50008 to address 0xD0008, and so on.

  In this way, the main program A and the main program B stored in the nonvolatile memory 60 are transferred to the storage means 20 and the recording means 40, but conventionally, the storage means 20 and the storage means. However, since the data can be transferred by one access through the addressing device 50 according to the present embodiment, the data transfer can be speeded up.

  In the above description, the description is based on the flow at the time of starting the multiprocessor system. However, the processor having storage means for storing a program, accessible from the processor, and executed by the processor. The same effect can be obtained also in a semiconductor integrated circuit comprising an external nonvolatile memory for storing a program and an addressing device capable of accessing internal / external storage means.

  As described above, according to the present embodiment, since a host processor can simultaneously access a plurality of addresses with a single access, the data transfer speed can be increased, and the main program from the nonvolatile memory 60 to the storage means 20 and 40 can be achieved. The transfer time for A and B can be shortened, and as a result, the system can be started at high speed.

  Further, according to the present embodiment, since data transfer can be speeded up, there is an effect in speeding up buffering processing from memory to memory in addition to program transfer.

  As described above, by using the addressing device according to the present invention, it is possible to speed up data transfer, and it is effective in shortening the startup time of the system. For example, photographing such as a digital camera or a digital video camera is possible. This is effective in shortening the time from when the power switch is turned on to when shooting can be started. Further, since the buffering process from memory to memory can be speeded up, it is effective for increasing the rate of input images in a digital video camera, for example.

Configuration diagram of a multiprocessor system in an embodiment of the present invention The flowchart at the time of the system starting in embodiment of this invention Configuration diagram of an addressing device in an embodiment of the present invention Explanatory drawing of the management table part which the addressing device in the embodiment of the present invention has Explanatory drawing of program transfer in an embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Master processor 20 Memory | storage means 30 Slave processor 40 Memory | storage means 50 Address designation apparatus 60 Non-volatile memory 501 ON / OFF part 502 in address designation apparatus 502 Management table part 503 in address designation apparatus Buffer memory part in address designation apparatus

Claims (7)

A plurality of processors having storage means for storing a program;
A non-volatile memory that is accessible from each processor and stores a program executed by each processor;
A multiprocessor system comprising an addressing device capable of accessing each storage means. A multiprocessor system in which one of the plurality of processors is a master processor and transfers a program executed by each processor from the nonvolatile memory to the storage unit when power is turned on,
2. The multiprocessor system according to claim 1, wherein the addressing device is used when transferring a program.   When one of the plurality of processors becomes a master processor and a program to be executed by each processor is transferred from the nonvolatile memory to the storage unit when the power is turned on, via the addressing device 2. The multiprocessor system according to claim 1, wherein a plurality of storage means can be accessed by one addressing.   2. The multiprocessor system according to claim 1, wherein the addressing device comprises means for simultaneously accessing a plurality of addresses for one address access.   5. The multiprocessor system according to claim 1, wherein the addressing device comprises means for registering a plurality of addresses to be accessed for one address access.   5. The multiprocessor system according to claim 1, wherein the addressing device comprises means for controlling ON / OFF of a function for accessing a plurality of addresses for one address access. A processor having storage means for storing a program;
An external nonvolatile memory that is accessible from the processor and stores a program executed by the processor;
A semiconductor integrated circuit comprising an addressing device capable of accessing internal / external storage means.

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