JP2009239115A - Semiconductor device, and manufacturing method of the same - Google Patents

Abstract

The present invention provides a semiconductor device and a method for manufacturing the semiconductor device that achieves both improvement in characteristics of a semiconductor device operating in a high frequency band and reduction in manufacturing cost.
A semiconductor device in which a plurality of semiconductor elements are formed using a plurality of semiconductor layers stacked on the same semi-insulating GaAs substrate, the FET being formed using an FET region, and The HBT formed using the HBT region 22 adjacent to the FET region 23 and the element isolation region 24 between the FET region 23 and the HBT region 22 are provided to separate the FET region 23 and the HBT region 22 from each other. The isolation groove 25 has an inter-element leakage current passing through the element isolation region 24 by forming a conductive metal layer having a ground potential on the inner wall surface and an end portion of the inner wall surface. Suppress.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a heterojunction bipolar transistor and a field effect transistor on the same substrate and a manufacturing method thereof.

  III-V compound semiconductors are frequently used in devices that require high-speed operation and high-efficiency operation because of their high electron mobility compared to Si (silicon) semiconductors. In particular, heterojunction bipolar transistors using a heterojunction between the emitter and the base have a wider band gap of the emitter layer than that of the base layer. Therefore, it has excellent features such as use with a single power source. Therefore, heterojunction bipolar transistors have been widely used as semiconductor components that operate in a high frequency band such as power amplifiers for mobile phones.

  However, while recent mobile phone terminals are required to be multi-band and more complicated operation control, it is required to reduce the number of parts in order to reduce the manufacturing cost, and these conflicting requirements must be satisfied at the same time. I must.

  In order to realize this, recently, a Bi-junction bipolar transistor (Heterojunction Bipolar Transistor: hereinafter referred to as HBT) and a field effect transistor (Field Effect Transistor: hereinafter referred to as FET) are formed on the same semiconductor chip. Research and development are being carried out to realize high frequency signal amplification and switching operations on a single chip using FET process technology.

  FIG. 7A is a plan view of a semiconductor device using a conventional Bi-FET process, and FIG. 7B is a cross-sectional view of the C-C ′ portion. A semiconductor device 700 in FIGS. 6A and 6B includes a semi-insulating GaAs substrate 701, an HBT region 722, an FET region 723, and an element isolation region 724.

  The HBT region 722 is formed on the semi-insulating GaAs substrate 701, and sequentially from the semi-insulating GaAs substrate 701 side, the GaAs / AlGaAs superlattice layer 702, the AlGaAs barrier layer 703, the InGaAs channel layer 704, and the GaAs sub-layer. A collector / cap layer 705, a collector electrode 714, a first wiring layer 717, and a second wiring layer 718 are provided, and a base mesa region 720 is provided between the collector electrodes 714.

  The base mesa region 720 is formed on the GaAs subcollector / cap layer 705, and sequentially from the GaAs subcollector / cap layer 705 side, the GaAs collector layer 706, the GaAs base layer 707, the InGaP emitter layer 708, and the GaAs emitter cap. A layer 709, an InGaAs emitter contact layer 710, and an emitter electrode 716, a base electrode 715 is provided on the surface of the GaAs base layer 707 between the emitter electrodes 716, and a second electrode is formed on the emitter electrode 716 and the base electrode 715. One wiring layer 717 is provided.

  The FET region 723 includes a GaAs / AlGaAs superlattice layer 702, an AlGaAs barrier layer 703, an InGaAs channel layer 704, a GaAs subcollector / cap layer 705, a drain electrode 711, a source electrode 712, a gate electrode 713, A first wiring layer 717.

  As a device structure in the Bi-FET process, the arrangement of the HBT and the FET with respect to the lowermost semi-insulating GaAs substrate 701 is a point, but from the viewpoint of process difficulty, etc. In general, a structure in which an HBT is disposed and an FET is disposed on a lower layer side is common.

  In the process of forming a Bi-FET, it is known that an inter-element leakage current between an FET and another element, particularly an HBT performing an amplification operation, adversely affects the switching characteristics of a high-frequency signal in the FET. Measures are taken to suppress the leakage current between elements.

As countermeasures for suppressing the leakage current between elements, there are two types of conventional methods: a case where a high resistance layer by ion implantation is used as the element isolation region 24 and a case where the active layer is removed by wet etching.
US Pat. No. 7,015,519

  However, when a high resistance layer by ion implantation is used as the element isolation region 24, it is necessary to increase the resistance of a wide area in the depth direction from the GaAs subcollector / cap layer 705 to the GaAs / AlGaAs superlattice layer 702. It is difficult to suppress the leakage current between elements of different HBTs and FETs to a low level. In addition, as a method for forming a high resistance layer widely and uniformly in the depth direction, there is a multi-stage implantation method in which implantation is performed with several types of ion implantation energy. However, this method increases the manufacturing variation and significantly increases the processing time of the ion implantation process, which causes a significant cost increase. Furthermore, since the active layer is not removed in the high resistance region by ion implantation, the inter-element leakage current is larger than when the active layer is removed. For this reason, an interval between the elements is required so that the remaining leakage current does not affect the characteristics, and the area of the element isolation region is increased.

  On the other hand, when the element isolation region is formed by removing the active layer by wet etching, the element isolation region must be formed by wet etching before the gate forming step of the FET due to process restrictions. Therefore, since the total step of the semiconductor device itself including the HBT and FET is very large at the time of the gate formation process of the FET, the resist film thickness and resolution covering the step are restricted, and as a result, the gate dimension is reduced. Refinement becomes difficult. In addition, since wet etching is isotropic etching, side etching is performed by the same dimension as the dimension in the depth direction to be etched in a certain plane orientation, and element isolation is performed in consideration of the amount of side etching. It is necessary to set a wide area. In addition, depending on the plane orientation, the etched mesa end face has a reverse mesa shape, so that the wiring straddling that portion cannot be formed from the upper part by vapor deposition, which increases layout constraints and increases the chip area. It also leads to an increase.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that achieves both improvement in characteristics of a semiconductor device that operates in a high frequency band and reduction in manufacturing cost, and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a plurality of semiconductor elements are arranged using a plurality of semiconductor layers stacked on the same semiconductor substrate, The semiconductor layer is a first region that is a part of the plurality of semiconductor layers, a first region, and a second region that is adjacent to the surface direction of the semiconductor substrate and is a part of the plurality of semiconductor layers. The semiconductor device includes a field effect transistor formed using the first region, a first semiconductor element formed using the second region, and the first region. A first separation groove provided on a first boundary that is a boundary with the second region, and separating the first region and the second region; and the first separation groove includes: A conductive metal layer having a ground potential is formed on the inner wall surface and the end of the inner wall surface. And wherein the Rukoto.

  As a result, a grounded isolation groove is formed in the element isolation region between the FET and the semiconductor element adjacent to the FET, so that high frequency noise is shielded and the high frequency switching characteristics of the FET can be improved. It becomes. In addition, since the grounded conductive metal layer is formed on the inner wall of the separation groove, electrical suppression of the leakage current between elements is enhanced, so that it is not necessary to secure the width of the separation groove more than necessary. Therefore, improvement in high frequency characteristics and reduction in manufacturing cost due to area saving can be realized.

  The first separation groove is preferably formed by dry etching the first boundary into which ions have been previously implanted.

  As a result, it is not necessary to employ wet etching that restricts the process and the resist to be used, so that the device processing accuracy is improved and the width of the separation groove need not be set more than necessary. Therefore, it is possible to realize a reduction in manufacturing cost due to a reduction in variation in characteristics between elements and a reduction in area.

  Further, by using dry etching instead of wet etching for forming the separation groove, the separation groove can be formed after the FET is formed. Therefore, after confirming the high-frequency signal switching characteristics of the FET, it is possible to optimize the arrangement location, such as effectively arranging the separation groove only in the portion adjacent to the HBT around the FET. Therefore, layout restrictions such as wiring and other elements can be reduced.

  Further, it is preferable that the semiconductor device further includes a via hole penetrating the semiconductor substrate and the plurality of semiconductor layers, and the first separation groove and the via hole are connected by wiring.

  Thereby, in the case of a semiconductor device including a via hole, the via hole forming hole and the separating groove can be simultaneously formed by optimizing the width of the separating groove structure. Therefore, the manufacturing cost can be reduced by simplifying the manufacturing process.

  Further, the first semiconductor element is a heterojunction bipolar transistor, and the plurality of semiconductor layers are further adjacent to the second region in the plane direction of the semiconductor substrate, and one of the plurality of semiconductor layers. The semiconductor device further includes a second semiconductor element formed using the third region, and a boundary between the second region and the third region And a second separation groove that separates the second region and the third region, and the second separation groove includes an inner wall surface and an inner wall surface of the inner wall surface. It is preferable that a conductive metal layer having a ground potential is formed at the end.

  As a result, since a grounded isolation groove is formed in the element isolation region between the HBT and the semiconductor element adjacent to the HBT, the high frequency noise generated from the high frequency amplified signal in the HBT is shielded, and the adjacent FET In addition, the characteristics of the semiconductor element can be improved. In addition, since the grounded conductive metal layer is formed on the inner wall of the separation groove, it is not necessary to secure the width of the separation groove more than necessary. Therefore, improvement in high frequency characteristics and reduction in manufacturing cost due to area saving can be realized.

  The second separation groove is preferably formed by dry-etching the second boundary into which ions have been previously implanted.

  As a result, it is not necessary to employ wet etching that restricts the process and the resist to be used, so that the device processing accuracy is improved and the width of the separation groove need not be set more than necessary. Therefore, it is possible to realize a reduction in manufacturing cost due to a reduction in variation in characteristics between elements and a reduction in area.

  The semiconductor device further includes a via hole penetrating the semiconductor substrate and the plurality of semiconductor layers, and the first separation groove, the second separation groove, and the via hole are connected by wiring. Preferably it is.

  As a result, in addition to the HBT and the FET, in the case of a semiconductor device including a via hole, it is possible to simultaneously form the via hole forming hole and the separating groove by optimizing the width of the separating groove structure. it can. Therefore, the manufacturing cost can be reduced by simplifying the manufacturing process.

  In addition, the first separation groove is longer in the surface direction of the semiconductor substrate than at least finger portions of the source electrode and the drain electrode of the field effect transistor, and is closest to the field effect transistor and the field effect transistor. It is preferable that at least a part of the first separation groove exists between the semiconductor element.

  This suppresses the interaction between the drain current of the FET and other semiconductor elements without leakage, and particularly suppresses the leakage current with the closest semiconductor element having the strongest interaction. Can be reliably suppressed. Therefore, the high frequency switching characteristics of the FET can be improved.

  Further, the present invention can be realized not only as a semiconductor device provided with such characteristic means, but also as a method for manufacturing a semiconductor device using the characteristic means included in the semiconductor device as a step. .

  According to the semiconductor device of the present invention, the FET having a high-frequency switching function and the HBT having a high-frequency signal amplification function are formed on the same semiconductor substrate, and a grounded separation groove is provided between the FET and the HBT or another element. Is formed. Therefore, it is possible to suppress the leakage current between the elements with the FET, and it is necessary to secure the width of the separation groove more than necessary by forming the conductive metal layer having the ground potential on the inner wall of the separation groove. Absent. Therefore, the manufacturing cost can be reduced due to the area saving while improving the high frequency characteristics.

(Embodiment 1)
The semiconductor device in this embodiment includes a field effect transistor (Field Effect Transistor) formed on a semi-insulating semiconductor substrate using a carrier traveling layer, an AlGaAs barrier layer, an InGaAs channel layer, and a cap layer. (Hereinafter referred to as FET), and a heterojunction bipolar transistor (Heterojunction Bipolar Transistor: hereinafter referred to as HBT) formed using a subcollector layer, collector layer, base layer, and emitter layer, and contact with each carrier traveling layer Each electrode includes a metal wiring layer electrically connected to each electrode, an element isolation region, and an isolation groove having a ground potential formed in the element isolation region. Thereby, both improvement in characteristics of a semiconductor device operating in a high frequency band and reduction in manufacturing cost can be achieved.

  Hereinafter, Embodiment 1 of the present invention will be described in detail with reference to the drawings.

  FIG. 1A is a plan view of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line A-A ′ of the semiconductor device according to the first embodiment of the present invention. The semiconductor device 100 in the figure includes a semi-insulating GaAs substrate 1, a drain electrode 11, a source electrode 12, a gate electrode 13, a collector electrode 14, a base electrode 15, an emitter electrode 16, and a first wiring layer. 17, a second wiring layer 18, an HBT region 22, an FET region 23, an element isolation region 24, and an isolation groove 25.

  The semi-insulating GaAs substrate 1 functions as a semiconductor substrate on which a plurality of semiconductor elements are formed.

  The HBT region 22 functions as a second region adjacent to the FET region 23. In order from the surface of the AlGaAs barrier layer 3, the GaAs subcollector / cap layer 5, the GaAs collector layer 6, the GaAs base layer 7, and the InGaP An emitter layer 8, a GaAs emitter cap layer 9, and an InGaAs emitter contact layer 10 are provided.

  The GaAs base layer 7 and the InGaP emitter layer 8 form an InGaP / GaAs heterojunction.

  The FET region 23 functions as a first region of a plurality of semiconductor layers, and in order from the surface of the semi-insulating GaAs substrate 1 into the GaAs / AlGaAs superlattice layer 2, the AlGaAs barrier layer 3, and the AlGaAs barrier layer 3. The InGaAs channel layer 4 and the GaAs subcollector / cap layer 5 are provided.

  The voltage applied to the gate electrode 13 affects the carriers traveling through the InGaAs channel layer 4, whereby the current flowing between the drain electrode 11 and the source electrode 12 is controlled.

  The GaAs / AlGaAs superlattice layer 2, the AlGaAs barrier layer 3, the InGaAs channel layer 4, the GaAs subcollector / cap layer 5, the GaAs collector layer 6, the GaAs base layer 7, the InGaP emitter layer 8, The GaAs emitter cap layer 9 and the InGaAs emitter contact layer 10 are a plurality of semiconductor layers stacked on a semiconductor substrate and function as active layers.

  The element isolation region 24 is formed at the boundary between the HBT region 22 and the FET region 23 and is ion-implanted over a plurality of semiconductor layers.

  In the isolation trench 25, the ion-isolated element isolation region 24 is dry-etched, and a conductive metal layer having a ground potential is formed on the etched inner wall surface and its end.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. FIG. 2 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

  First, a GaAs / AlGaAs superlattice layer 2, an AlGaAs barrier layer 3, an InGaAs channel layer 4 disposed in the AlGaAs barrier layer 3, and a GaAs subcollector serving as a GaAs / AlGaAs superlattice layer 2 in this order from the lower layer on the semi-insulating GaAs substrate 1. The cap layer 5, the GaAs collector layer 6, the GaAs base layer 7, the InGaP emitter layer 8, the GaAs emitter cap layer 9, and the InGaAs emitter contact layer 10 are epitaxially grown to form a plurality of semiconductor layers (FIG. 2 ( a)).

  Next, a resist is patterned on a plurality of semiconductor layers by a photolithography method, and an emitter mesa region 19 is formed by etching the resist opening by a dry etching method. Subsequently, the base mesa region 20 is formed by the same method (FIG. 2B).

Next, the part other than the place where the element isolation is performed is protected with a resist, and an element isolation region 24 having a high resistance is formed by implanting He ⁺ ions, and the HBT region 22 and the FET region 23 are partitioned (FIG. 2 ( c)).

  Next, after forming the insulating film, the portion of the insulating film where the emitter, base and collector electrodes are formed and the portion of the InGaP emitter layer 8 where the base electrode 15 is formed are removed and contacted with the InGaAs emitter contact layer 10. An emitter electrode 16 made of Ti / Pt / Au, etc., a base electrode 15 made of Ti / Pt / Au etc. in contact with the GaAs base layer 7, a collector made of AuGe / Ni / Au etc. in contact with the GaAs subcollector / cap layer 5 The electrodes 14 are formed sequentially.

  Next, the insulating film in the portion where the drain and source electrodes are formed is removed, and the drain electrode 11 and the source electrode 12 made of AuGe / Ni / Au or the like that are in contact with the GaAs subcollector / cap layer 5 are formed. Further, the portion of the insulating film where the gate electrode is to be formed is removed, the portion of the GaAs subcollector / cap layer 5 is removed to form the gate digging region 21, and then the Ti / Al / contact with the AlGaAs barrier layer 3 is contacted. A gate electrode 13 made of Ti or the like is formed.

  Next, after forming an insulating film, the contact portion to each electrode being formed is opened, and the first wiring layer 17 is formed thereon. (FIG. 2 (d)).

  Next, after the insulating film is formed, all the insulating film in the element isolation region 24 where the isolation groove is to be disposed is removed, and the isolation groove 25 is formed in that place by a dry etching method with a width of about 2 to 5 μm. And a dimension having a depth of about 5 to 10 μm (FIG. 2E).

  In this manufacturing process, the depth of the separation groove 25 to be formed is optimized to a depth that does not cause wafer cracking during polishing in the component processing process after the diffusion process.

  Further, in order to further suppress the inter-element leakage current between the HBT and other elements, it is preferable that this separation groove 25 is also arranged around the HBT.

  Next, the insulating film at the place where the first wiring layer 17 and the second wiring layer 18 are contacted is removed, and the second wiring layer 18 is plated on the portion to be connected to the first wiring layer 17 and the separation groove 25 portion. Etc. (FIG. 2F).

  Finally, a final protective film is formed, and the protective film on each pad and scribe line portion is removed to complete the process.

  According to the method of manufacturing a semiconductor device according to the embodiment of the present invention, the step of forming the isolation trench 25 can be performed after forming each electrode such as an HBT and an FET, so that the active layer is removed by wet etching. As compared with the case where the element isolation region is formed, the global step at the time of forming the gate of the FET is small, and the influence on the miniaturization of the gate dimension is small.

  In the present embodiment, the place where the separation groove 25 shown in FIG. 2E is formed is optimized in consideration of the characteristics such as the switching operation of the high-frequency signal. Furthermore, it is desirable that the separation groove 25 arranged around the FET is longer than the finger lengths of the source electrode and the drain electrode of the adjacent FET in order to reliably reduce the inter-element leakage current. Here, the finger length is the length of the portion where the source electrode and the drain electrode face each other in the layout on the substrate plane, and is L in the layout of the FET portion shown in FIG.

  Further, in the present embodiment, the step of forming the base electrode 15 shown in FIG. 2D adopts an InGaP emitter by adopting a material that diffuses into a semiconductor layer such as Pt as the lowermost layer of the base electrode 15. The base electrode 15 may be formed on the InGaP8 layer without removing the layer 8.

  In the present embodiment, the step of forming the collector electrode 14, the source electrode 12 and the drain electrode 11 shown in FIG. 2D includes one mask including the step of removing the interlayer film where the electrodes are to be formed. May be performed simultaneously.

  FIG. 3 is a comparison diagram of inter-element leakage currents between the semiconductor device according to the first embodiment of the present invention and the conventional semiconductor device. The horizontal axis represents a conventional semiconductor device in which element isolation is performed only by ion implantation (denoted as only ion implantation in the figure), and a conventional semiconductor device in which element isolation is performed only by wet etching (only wet etching is illustrated in the figure). ), And a semiconductor device according to the first embodiment of the present invention (in the drawing, described as a separation groove structure of the present invention). The vertical axis indicates the leakage current between the elements when the separation groove is arranged around the FET and when the separation groove is arranged around the HBT.

  From the results shown in FIG. 3, the semiconductor device according to the first embodiment of the present invention includes the isolation trench 25 that is grounded in the element isolation region 24, thereby reducing the inter-element leakage current of the FET by wet etching. It is equivalent to the one in which the active layer is removed to form the element isolation region, and the leakage level is suppressed to a favorable level.

  In addition, the size of the gate electrode is also reduced compared to the size of the gate electrode of the conventional semiconductor device by wet etching. Furthermore, since the semiconductor device according to this embodiment has the active layer removed in the isolation trench portion and has the ground potential, the leakage current can be reliably reduced, so that the element isolation region is obtained by ion implantation. Compared to a conventional semiconductor device using a high resistance region, the distance between the elements can be reduced with the isolation groove interposed therebetween, so that the area of the element isolation region can be reduced.

  From the above, the semiconductor device according to the first embodiment of the present invention realizes improvement in high frequency characteristics by suppressing inter-element leakage current and reduction in manufacturing cost due to area saving.

  Furthermore, in the manufacturing process of the semiconductor device of the present embodiment, the process of forming the isolation groove 25 is the process described in FIG. Therefore, before the process (when the process of FIG. 2D is completed), the FET and HBT electrodes are formed, so that the electrical characteristics of the FET and HBT can be measured. As a result, the semiconductor device according to the present embodiment can optimize the location of the separation groove in consideration of various characteristics including high-frequency signal switching operation. Has few constraints.

(Embodiment 2)
The semiconductor device according to the second embodiment includes a via hole in addition to the HBT and the FET. The semiconductor device manufacturing method simultaneously forms the via hole forming hole and the separation groove by optimizing the width of the separation groove from the relationship between the pattern width and the etching depth. As a result, the leakage current between the elements of the FET can be suppressed without adding any manufacturing process, so that the characteristics can be improved without increasing the cost.

  Hereinafter, Embodiment 2 of the present invention will be described in detail with reference to the drawings.

  FIG. 4A is a plan view of the semiconductor device according to the second embodiment of the present invention. FIG. 4B is a cross-sectional view taken along the B-B ′ portion of the semiconductor device according to the second embodiment of the present invention. The semiconductor device 200 in the figure includes a semi-insulating GaAs substrate 1, a drain electrode 11, a source electrode 12, a gate electrode 13, a collector electrode 14, a base electrode 15, an emitter electrode 16, and a first wiring layer. 17, an HBT region 22, an FET region 23, an element isolation region 24, a grounded isolation groove 25, a surface via hole 26, a back metal layer 27, and a second wiring layer 28. The semiconductor device shown in FIG. 4 differs from the semiconductor device shown in FIG. 1 only in that it includes a front via hole 26 and a back metal layer 27 and in the layout of the second wiring layer 28. Description of the same points as those of the semiconductor device shown in FIG. 1 will be omitted, and only different points will be described below.

  The second wiring layer 28 has a function of electrically connecting the inner wall surface of the separation groove 25 and the inner wall surface of the surface via hole 26. In addition, since the second wiring layer 28, the separation groove 25, the front surface via hole 26, and the back surface metal layer 27 are grounded, leakage current between elements is suppressed, and high frequency switching characteristics of the FET and high frequency signal amplification characteristics of the HBT are improved. To do.

  Next, a method for manufacturing the semiconductor device shown in FIG. 4 will be described. FIG. 5 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

  First, a GaAs / AlGaAs superlattice layer 2, an AlGaAs barrier layer 3, an InGaAs channel layer 4 disposed in the AlGaAs barrier layer 3, and a GaAs subcollector serving as a GaAs / AlGaAs superlattice layer 2 in this order from the lower layer on the semi-insulating GaAs substrate 1. A cap layer 5, a GaAs collector layer 6, a GaAs base layer 7, an InGaP emitter layer 8, a GaAs emitter cap layer 9, and an InGaAs emitter contact layer 10 are epitaxially grown to form a plurality of semiconductor layers (FIG. 5 ( a)).

  Next, a resist is patterned on a plurality of semiconductor layers by a photolithography method, and an emitter mesa region 19 is formed by etching the resist opening by a dry etching method. Subsequently, the base mesa region 20 is formed by the same method (FIG. 5B).

Next, the part other than the place where the element isolation is performed is protected with a resist, and an element isolation region 24 having a high resistance is formed by implanting He ⁺ ions, and the HBT region 22 and the FET region 23 are partitioned (FIG. 5 ( c)).

  Next, after forming the insulating film, the portion of the insulating film where the emitter, base and collector electrodes are formed and the portion of the InGaP emitter layer 8 where the base electrode 15 is formed are removed and contacted with the InGaAs emitter contact layer 10. An emitter electrode 16 made of Ti / Pt / Au, etc., a base electrode 15 made of Ti / Pt / Au etc. in contact with the GaAs base layer 7, a collector made of AuGe / Ni / Au etc. in contact with the GaAs subcollector / cap layer 5 The electrodes 14 are sequentially formed.

  Next, the insulating film in the portion where the drain and source electrodes are formed is removed, and the drain electrode 11 and the source electrode 12 made of AuGe / Ni / Au or the like that are in contact with the GaAs subcollector / cap layer 5 are formed. Further, the portion of the insulating film where the gate electrode is to be formed is removed, the portion of the GaAs subcollector / cap layer 5 is removed to form the gate digging region 21, and then the Ti / Al / contact with the AlGaAs barrier layer 3 is contacted. A gate electrode 13 made of Ti or the like is formed.

  Next, after forming an insulating film, the contact portion to each electrode being formed is opened, and the first wiring layer 17 is formed thereon. (FIG. 5D).

  Next, after the insulating film is formed, all of the insulating film in the element isolation region 24 where the isolation groove 25 and the surface via hole 26 are to be disposed is removed, and further, the isolation groove 25 is formed there by dry etching. 5 to 10 μm in depth, and a hole 29 for forming a surface via hole is simultaneously formed in a dimension of about 50 μm in diameter and 120 to 160 μm in depth (FIG. 5E).

  In this manufacturing process, the depth of the separation groove 25 to be formed is optimized to a depth that does not cause wafer cracking during polishing in the component processing process after the diffusion process.

  Further, in order to further suppress the inter-element leakage current between the HBT and other elements, it is preferable that this separation groove 25 is also arranged around the HBT.

  Next, the insulating film where the first wiring layer 17 and the second wiring layer 28 are brought into contact with each other is removed, a portion to be connected to the first wiring layer 17, a separation groove 25 portion, a hole 29 for forming a surface via hole, etc. The second wiring layer 28 is formed by plating or the like.

  Next, after forming a final protective film, removing the protective film of each pad and scribe line portion and completing the diffusion process, an on-wafer DC inspection is performed, and the wafer thickness is increased from the back side of the semi-insulating GaAs substrate 1. Polish until final chip thickness is reached. Thereafter, a back metal layer 27 made of AuSn or the like for die bonding is deposited on the back surface to complete the semiconductor device of the second embodiment (FIG. 5F).

  In the present embodiment, the pattern width of the separation groove 25 to be formed is optimized by the relationship between the pattern width and the etching depth under the same conditions illustrated in FIG.

  FIG. 6 is a graph showing the relationship between the pattern width and the etching depth under the same etching conditions. The horizontal axis represents the pattern width of the etched portion, and the vertical axis represents the etching depth. This graph shows that simultaneous etching is possible if it is on a curve connecting the plotted points. In the manufacturing process of the semiconductor device according to the present embodiment, since the dimension of the separation groove 25 and the dimension of the surface via hole forming hole 29 can be selected on the curve, in the etching process described above (FIG. 5E). ), Simultaneous etching is realized. In the manufacturing process of the semiconductor device according to the present embodiment, the pattern width is optimized so that the etching depth of the separation groove 25 is about 5 to 10 μm.

  In the present embodiment, the place where the separation groove 25 shown in FIG. 5E is formed is optimized in consideration of characteristics such as the switching operation of the high-frequency signal. Further, it is desirable that the separation groove 25 arranged around the FET is longer than the finger length L of the adjacent source electrode and drain electrode of the FET in order to reliably reduce the leakage current between the elements.

  In the semiconductor device according to the present embodiment formed as described above, the formation of the isolation trench 25 having the ground potential and the surface via hole 26 is performed at the same time. Current suppression is achieved.

  As for the suppression result of the inter-element leakage current, the same result as the result described in FIG. 3 was obtained also in the present embodiment. Therefore, in the semiconductor device according to the second embodiment of the present invention, as in the semiconductor device according to the first embodiment, the element isolation region is formed by removing the active layer from the FET inter-element leakage current by wet etching. It is equivalent to the one and is suppressed to a good leak level.

  In addition, the size of the gate electrode is also reduced compared to the size of the gate electrode of the conventional semiconductor device by wet etching. Furthermore, since the semiconductor device according to this embodiment has the active layer removed in the isolation trench portion and has the ground potential, the leakage current can be reliably reduced, so that the element isolation region is obtained by ion implantation. Compared to a conventional semiconductor device using a high resistance region, the distance between the elements can be reduced with the isolation groove interposed therebetween, so that the area of the element isolation region can be reduced.

  From the above, in the semiconductor device according to the second embodiment of the present invention, the high-frequency characteristics are improved by suppressing the leakage current between elements, and the manufacturing cost is reduced due to the area saving and the sharing of the manufacturing process.

  Further, in the manufacturing process of the semiconductor device of the present embodiment, the process of forming the isolation groove is the process described in FIG. 5E, as in the manufacturing process of the semiconductor device of the first embodiment. Therefore, since the FET and HBT electrodes are formed before the process (when the process of FIG. 5D is completed), the electrical characteristics of the FET and HBT can be measured in advance.

  As a result, in the semiconductor device of the present embodiment, the location of the separation groove can be optimized in consideration of various characteristics including the switching operation of the high frequency signal. There are almost no restrictions.

  Note that the front surface via hole 26 described in FIG. 4 may be a back surface via hole. The step of forming the back via hole is different from the step of FIG. 5E and FIG. 5F described in the second embodiment. In the case of forming the back via hole, the via hole forming hole is not formed at the same time when the isolation groove 25 is formed by the dry etching method after the element forming process up to FIG. After the separation groove 25 is formed, polishing is performed from the back surface side of the semi-insulating GaAs substrate 1 until the wafer thickness reaches the final chip thickness, and then a through hole for forming a via hole is formed by etching from the back surface side. Then, an inner wall surface of the through hole for forming the via hole and a wiring layer necessary for grounding thereof are formed by a plating method or the like.

  Even in this case, the separation groove is connected to a grounded via hole, thereby providing an effect of enhancing the suppression of leakage current between elements.

  The semiconductor device and the manufacturing method thereof according to the present invention have been described based on the embodiments. However, the present invention is not limited to these embodiments. Unless it deviates from the meaning of the present invention, various modifications conceived by those skilled in the art have been made in the present embodiment, and forms constructed by arbitrarily combining components in different embodiments are also within the scope of the present invention. included.

  INDUSTRIAL APPLICABILITY The present invention is useful for a semiconductor device that operates in a high frequency band and a manufacturing method thereof, and is particularly suitable as a semiconductor device using a field effect transistor as a switching element.

(A) It is a top view of the semiconductor device which concerns on Embodiment 1 of this invention. (B) It is sectional drawing in the A-A 'part of the semiconductor device which concerns on Embodiment 1 of this invention. It is a manufacturing process figure of the semiconductor device concerning Embodiment 1 of the present invention. It is a comparison figure of the leak current between elements of the semiconductor device concerning Embodiment 1 of the present invention, and the conventional semiconductor device. (A) It is a top view of the semiconductor device which concerns on Embodiment 2 of this invention. (B) It is sectional drawing in the B-B 'part of the semiconductor device which concerns on Embodiment 2 of this invention. It is a manufacturing process figure of the semiconductor device concerning Embodiment 2 of the present invention. It is a graph which shows the relationship between the pattern width and etching depth on the same etching conditions. (A) It is a top view of the semiconductor device using the conventional Bi-FET process. (B) It is sectional drawing in the C-C 'part of the semiconductor device using the conventional Bi-FET process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,701 Semi-insulating GaAs substrate 2,702 GaAs / AlGaAs superlattice layer 3,703 AlGaAs barrier layer 4,704 InGaAs channel layer 5,705 GaAs subcollector / cap layer 6,706 GaAs collector layer 7,707 GaAs base layer 8, 708 InGaP emitter layer 9, 709 GaAs emitter cap layer 10, 710 InGaAs emitter contact layer 11, 711 Drain electrode 12, 712 Source electrode 13, 713 Gate electrode 14, 714 Collector electrode 15, 715 Base electrode 16, 716 Emitter electrode 17, 717 First wiring layer 18, 28, 718 Second wiring layer 19, 719 Emitter mesa region 20, 720 Base mesa region 21, 721 Gate digging region 22, 722 HBT region 23, 23 FET region 24,724 isolation region 25 separating groove 26 surface via-hole 27 back metal layer 29 surface via hole formed holes 100,200,700 semiconductor device for

Claims (13)

A semiconductor device in which a plurality of semiconductor elements are arranged using a plurality of semiconductor layers stacked on the same semiconductor substrate,
The plurality of semiconductor layers are:
A first region that is part of the plurality of semiconductor layers;
The first region, and a second region adjacent to the surface direction of the semiconductor substrate and being a part of the plurality of semiconductor layers,
The semiconductor device includes:
A field effect transistor formed using the first region;
A first semiconductor element formed using the second region;
A first separation groove provided on a first boundary which is a boundary between the first region and the second region, and separating the first region and the second region;
The semiconductor device, wherein the first separation groove is formed with an inner wall surface and a conductive metal layer having a ground potential at an end portion of the inner wall surface. The semiconductor device according to claim 1, wherein the first separation groove is formed by dry etching the first boundary into which ions have been previously implanted. The semiconductor device further includes:
A via hole penetrating the semiconductor substrate and the plurality of semiconductor layers;
The semiconductor device according to claim 1, wherein the first separation groove and the via hole are connected by wiring. The first semiconductor element is a heterojunction bipolar transistor;
The plurality of semiconductor layers further includes:
The second region, and a third region adjacent to the surface direction of the semiconductor substrate and being a part of the plurality of semiconductor layers,
The semiconductor device further includes:
A second semiconductor element formed using the third region;
A second separation groove provided at a second boundary which is a boundary between the second region and the third region, and separating the second region and the third region;
The semiconductor device according to claim 1, wherein the second separation groove is formed with an inner wall surface and a conductive metal layer having a ground potential at an end of the inner wall surface. The semiconductor device according to claim 4, wherein the second separation groove is formed by dry etching the second boundary into which ions have been previously implanted. The semiconductor device further includes:
A via hole penetrating the semiconductor substrate and the plurality of semiconductor layers;
The semiconductor device according to claim 4, wherein the first separation groove, the second separation groove, and the via hole are connected by wiring. The first separation groove is longer in the surface direction of the semiconductor substrate than at least finger portions of the source electrode and the drain electrode of the field effect transistor,
7. The device according to claim 1, wherein at least a part of the first separation groove exists between the field effect transistor and a semiconductor element closest to the field effect transistor. A semiconductor device according to 1. A method of manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on the same semiconductor substrate,
A semiconductor layer stacking step of sequentially stacking a plurality of semiconductor layers on the surface of the semiconductor substrate;
An FET forming step of forming a field effect transistor using a first region that is part of the plurality of semiconductor layers;
An FET adjacent element forming step of forming a first semiconductor element by using the first region and a second region adjacent to the surface direction of the semiconductor substrate and being a part of the plurality of semiconductor layers;
After the FET formation step and the FET adjacent element formation step, the first region and the second region are separated into a first boundary which is a boundary between the first region and the second region. A separation groove forming step for forming a first separation groove;
And a metal layer forming step of forming a grounded conductive metal layer on an inner wall surface of the first separation groove and an end of the inner wall surface. The method for manufacturing the semiconductor device further includes:
An ion implantation step for implanting ions into the first boundary before the separation groove forming step;
In the separation groove forming step,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the first separation groove is formed by dry etching the ion-implanted first boundary. In the separation groove forming step,
At the same time as forming the first separation groove, a hole for forming a via hole is formed,
In the metal layer forming step,
The grounded conductive metal layer is simultaneously formed on an inner wall surface of the first separation groove and an end portion of the inner wall surface, and an inner wall surface of the hole for forming the via hole and an end portion of the inner wall surface. 10. A method of manufacturing a semiconductor device according to claim 8, wherein The first semiconductor element is a heterojunction bipolar transistor;
The method for manufacturing the semiconductor device further includes:
Prior to the separation groove forming step, a second semiconductor element is formed using the second region and a third region adjacent to the surface direction of the semiconductor substrate and being a part of the plurality of semiconductor layers. Including an HBT adjacent element forming step,
In the separation groove forming step,
Secondly, the second region and the third region are separated into a second boundary which is a boundary between the second region and the third region at the same time when the first separation groove is formed. Forming a separation groove,
In the metal layer forming step,
A grounded conductive metal layer is simultaneously formed on the inner wall surface of the first separation groove and the end portion of the inner wall surface, and on the inner wall surface of the second separation groove and the end portion of the inner wall surface; 10. A method of manufacturing a semiconductor device according to claim 8, wherein the method is a semiconductor device manufacturing method. In the ion implantation step,
Ion implantation for the first boundary and the second boundary;
In the separation groove forming step,
The first separation groove and the second separation groove are simultaneously formed by simultaneously performing dry etching on the first and second boundaries into which ions are implanted. A manufacturing method of the semiconductor device described. In the separation groove forming step,
Forming the first and second separation grooves, and simultaneously forming a hole for forming a via hole;
In the metal layer forming step,
The grounded conductive metal on the inner wall surface of each of the first and second separation grooves and the end portion of the inner wall surface, and on the inner wall surface of the via hole forming hole and the end portion of the inner wall surface The method for manufacturing a semiconductor device according to claim 11, wherein the layers are formed simultaneously.

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