JP2009239189A - Semiconductor storage device, and device using the semiconductor storage device - Google Patents

Abstract

A semiconductor memory device capable of performing a high-speed writing operation and erasing operation at a relatively low voltage and rewriting without a body contact and reducing a circuit area.
In this semiconductor memory device, under the control of a control unit 111, the output of the even-numbered bit line voltage generation circuit 108 is set to 12V, the output of the odd-numbered bit line voltage generation circuit 109 is set to 0V, and The row decoder 102 applies 15V higher than 0V to the word line WL0. Next, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 0V, sets the output of the odd-numbered bit line voltage generation circuit 109 to 12V, and the row decoder 102 applies 0V to the word line WL0. High 15V is applied. Thereby, the semiconductor memory element MC0 can be erased with a relatively small voltage.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device and an apparatus using the semiconductor memory device. More specifically, a semiconductor memory device having a semiconductor memory element that accumulates charges in an insulator having a level for trapping charges, and a device including the semiconductor memory device (for example, a display device, a liquid crystal display device, and a receiver) About.

  A semiconductor memory element is generally formed using a semiconductor substrate. On the other hand, in a device using an insulating substrate such as glass such as a liquid crystal display device, a semiconductor layer is formed on the insulating substrate, and a thin film transistor (TFT) is formed using the semiconductor layer. This TFT constitutes a signal processing circuit and a device driving circuit. In addition, it is desired that the semiconductor memory element is formed on the insulating substrate together with the TFTs constituting these circuits.

  For example, Non-Patent Document 1 (Hung-Tse Chen et al., “SID 05 Digest”, p1152-1155, 2005) discloses a nonvolatile memory element using a silicon nitride film formed on an insulating substrate such as a glass substrate. is doing.

  As described in Non-Patent Document 1, in the technology for forming a nonvolatile memory on an insulating substrate made of glass, FN (Fowler) is used to inject and extract electrons from / to a charge trap insulating film during writing and erasing.・ Nordheim) Tunnel current is used. Therefore, there is a problem that a high voltage is required for the write operation and the erase operation.

  In the nonvolatile memory described in Non-Patent Document 1, a high voltage of 20 V is applied during a write operation and -40 V is applied during an erase operation. For this reason, a power supply or a booster circuit for supplying these high voltages is necessary to perform the write operation and the erase operation, which increases the manufacturing cost. Further, in order to flow and erase the FN current, the channel needs to be a storage layer.

On the other hand, if the applied voltage at the write operation and the applied voltage at the erase operation are lowered, the efficiency of the FN tunnel is drastically lowered, and the write speed and the erase speed are remarkably lowered. You can't get it.
Hung-Tse Chen et al., “SID 05 Digest”, p1152-1155, 2005

  Accordingly, an object of the present invention is that a high-speed write operation and erase operation can be performed at a relatively low voltage, so that a power supply or a boost circuit for supplying a high voltage is not necessary, and a semiconductor memory device that can be manufactured at low cost, and An object of the present invention is to provide a device (for example, a display device, a liquid crystal display device, and a receiver) provided with such a semiconductor memory device.

In order to solve the above problems, a semiconductor memory device of the present invention includes a semiconductor layer formed on a substrate having an insulating surface,
A first diffusion layer formed in the semiconductor layer;
A second diffusion layer formed in the semiconductor layer;
A charge storage film that covers at least a channel region between the first diffusion layer and the second diffusion layer in the semiconductor layer and into which charges are injected from the channel region;
A gate electrode located on the opposite side of the channel region across the charge storage film;
A semiconductor memory device having
A word line connected to the gate electrode;
A first bit line connected to the first diffusion layer of the semiconductor memory element;
A second bit line connected to the second diffusion layer of the semiconductor memory element;
A first bit line voltage generating circuit connected to the first bit line;
And a second bit line voltage generation circuit connected to the second bit line.

  According to the semiconductor memory device of the present invention, when the semiconductor memory element is a P-type semiconductor memory element, the second bit line voltage generating circuit is changed to the second bit line by the first bit line voltage generating circuit. From the first bit line, a voltage higher than the voltage applied to the second diffusion layer can be applied to the first diffusion layer. In this voltage application state, the erase operation can be performed with a relatively small voltage by applying a voltage higher than the voltage applied to the second diffusion layer to the gate electrode. On the other hand, by applying a voltage lower than the voltage applied to the second diffusion layer to the gate electrode in a voltage application state in which a voltage higher than that of the second diffusion layer is applied to the first diffusion layer. The write operation can be performed with a relatively small voltage. On a glass substrate, a P-type semiconductor memory element is more preferable than an N-type semiconductor memory element because rewriting is stable. An SOI (silicon-on-insulator) substrate may be an N-type semiconductor memory element or a P-type semiconductor memory element.

  On the other hand, when the semiconductor memory element is an N-type semiconductor memory element, the second bit line voltage generating circuit is transferred from the second bit line to the second diffusion layer by the first bit line voltage generating circuit. A voltage lower than the applied voltage can be applied to the first diffusion layer from the first bit line. In this voltage application state, by applying a voltage lower than the voltage applied to the second diffusion layer to the gate electrode, the erase operation can be performed with a relatively small voltage. On the other hand, by applying a voltage higher than the voltage applied to the second diffusion layer to the gate electrode in a voltage application state in which a voltage lower than that of the second diffusion layer is applied to the first diffusion layer. The write operation can be performed with a relatively small voltage.

  Therefore, according to the semiconductor memory device of the present invention, high-speed writing operation and erasing operation can be performed at a relatively low voltage, and it can be manufactured at low cost, and the memory window is large and high reliability can be achieved. In addition, the ability to reduce the circuit area is advantageous for cost reduction.

In one embodiment, the first and second diffusion layers have a P-type conductivity type, and the semiconductor memory element is a P-type semiconductor memory element.
A voltage higher than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode After performing a first voltage application that applies a voltage higher than a voltage applied to the second diffusion layer, a voltage higher than a voltage applied to the first diffusion layer from the first bit line is applied. A second voltage is applied from the second bit line to the second diffusion layer and a voltage higher than the voltage applied to the first diffusion layer from the word line to the gate electrode. And a controller for controlling the first and second bit line voltage generating circuits and the word line voltage generating circuit connected to the word lines to erase the P-type semiconductor memory element.

  According to this embodiment, the first and second bit line voltage generation circuits and the word line voltage generation circuit are controlled by the control unit, so that the P-type semiconductor memory element is in a state in which the first voltage is applied. After that, the erase operation can be performed at a relatively low voltage by setting the second voltage application state.

  Note that in the first voltage application, it is desirable to apply a voltage higher than the voltage applied to the first diffusion layer to the gate electrode. In addition, in the second voltage application, it is desirable to apply a voltage higher than the voltage applied to the second diffusion layer to the gate electrode.

In the semiconductor memory device of one embodiment, the control unit is
After applying the first voltage, after applying the second voltage, a voltage higher than the voltage applied from the second bit line to the second diffusion layer is applied. The third voltage application is performed such that a third voltage application is applied from the bit line to the first diffusion layer and a voltage higher than the voltage applied to the second diffusion layer from the word line to the gate electrode. The P-type semiconductor memory element is erased by controlling the first and second bit line voltage generation circuits and the word line voltage generation circuit connected to the word lines.

  According to the semiconductor memory device of this embodiment, the first voltage is applied, the second voltage is applied, and the third voltage is further applied, whereby the P-type semiconductor is applied. The memory element can be erased more reliably.

  In the third voltage application, it is desirable to apply a voltage higher than the voltage applied to the first diffusion layer to the gate electrode.

In the semiconductor memory device of one embodiment, the control unit is
After applying the first, second, and third voltages in order, a voltage higher than the voltage applied from the first bit line to the first diffusion layer is applied from the second bit line. The first and second voltages are applied so that a fourth voltage is applied to the second diffusion layer and a voltage higher than the voltage applied to the first diffusion layer from the word line to the gate electrode. The bit line voltage generation circuit and the word line voltage generation circuit connected to the word line are controlled to erase the P-type semiconductor memory element.

  According to the semiconductor memory device of this embodiment, the first, second, and third voltage applications are sequentially performed, and then the fourth voltage application is further performed. It can be erased more reliably.

  In the fourth voltage application, it is desirable to apply a voltage higher than the voltage applied to the second diffusion layer to the gate electrode.

In one embodiment, the first and second diffusion layers have an N-type conductivity type, and the semiconductor memory element is an N-type semiconductor memory element.
A voltage lower than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode After performing a first voltage application that applies a voltage lower than the voltage applied to the second diffusion layer, a voltage lower than the voltage applied to the first diffusion layer from the first bit line is applied. A second voltage is applied from the second bit line to the second diffusion layer and a voltage lower than a voltage applied to the first diffusion layer from the word line to the gate electrode. And a controller for erasing the N-type semiconductor memory element by controlling the first and second bit line voltage generating circuits and the word line voltage generating circuit connected to the word lines.

  According to this embodiment, the first and second bit line voltage generation circuits and the word line voltage generation circuit are controlled by the control unit, so that the N-type semiconductor memory element is in a state in which the first voltage is applied. After that, the erase operation can be performed at a relatively low voltage by setting the second voltage application state.

  Note that in the first voltage application, it is desirable to apply a voltage lower than the voltage applied to the first diffusion layer to the gate electrode. In addition, in the second voltage application, it is desirable to apply a voltage lower than the voltage applied to the second diffusion layer to the gate electrode.

In the semiconductor memory device of one embodiment, the control unit is
After applying the first voltage, after applying the second voltage, a voltage lower than the voltage applied from the second bit line to the second diffusion layer is applied. The third voltage application is performed such that a third voltage is applied from the bit line to the first diffusion layer and a voltage lower than the voltage applied to the second diffusion layer from the word line to the gate electrode. The N-type semiconductor memory element is erased by controlling the first and second bit line voltage generation circuits and the word line voltage generation circuit connected to the word lines.

  According to the semiconductor memory device of this embodiment, the first voltage is applied, the second voltage is applied, and the third voltage is further applied, whereby the N-type semiconductor is applied. The memory element can be erased more reliably.

  In the third voltage application, it is desirable to apply a voltage lower than the voltage applied to the first diffusion layer to the gate electrode.

In the semiconductor memory device of one embodiment, the control unit is
After the first, second, and third voltage applications are sequentially performed, a voltage lower than the voltage applied from the first bit line to the first diffusion layer is applied from the second bit line. The first and second voltages are applied so that a fourth voltage is applied to the second diffusion layer and a voltage lower than the voltage applied to the first diffusion layer from the word line to the gate electrode. The bit line voltage generating circuit and the word line voltage generating circuit connected to the word line are controlled to erase the N-type semiconductor memory element.

  According to the semiconductor memory device of this embodiment, the first voltage, the second voltage, and the third voltage are sequentially applied, and then the fourth voltage is further applied. It can be erased more reliably.

  In one embodiment, the control unit erases the semiconductor memory element by repeating voltage application control for applying the second voltage after applying the first voltage a plurality of times.

  According to the semiconductor memory device of this embodiment, the semiconductor memory element can be erased with certainty.

In one embodiment of the semiconductor memory device, the word line having the semiconductor element and connected to the gate electrode;
A first bit line connected to the first diffusion layer of the semiconductor memory element;
A second bit line connected to the second diffusion layer of the semiconductor memory element and connected to the ground;
And a bit line voltage generation circuit connected to the first bit line.

  According to this embodiment, when the semiconductor element is a P-type semiconductor element, it is higher than the ground potential applied from the second bit line to the second diffusion layer by the bit line voltage generation circuit. A voltage can be applied from the first bit line to the first diffusion layer. In this voltage application state, an erase operation can be performed with a relatively small voltage by applying a voltage higher than the ground potential to the gate electrode. On the other hand, in a state where a voltage higher than the ground potential is applied to the first diffusion layer, a write operation is performed at a relatively low voltage by applying a voltage lower than the ground potential to the gate electrode. Can do.

  On the other hand, when the semiconductor element is an N-type semiconductor element, the bit line voltage generation circuit applies a voltage lower than the ground potential applied from the second bit line to the second diffusion layer. One bit line can be applied to the first diffusion layer. In this voltage application state, an erase operation can be performed at a relatively low voltage by applying a voltage lower than the ground potential to the gate electrode. On the other hand, in a state where a voltage lower than the ground potential is applied to the first diffusion layer, a write operation is performed at a relatively low voltage by applying a voltage higher than the ground potential to the gate electrode. Can do.

  Therefore, according to the semiconductor memory device of this embodiment, high-speed writing operation and erasing operation can be performed with a relatively small voltage, and it can be manufactured at a low cost, and the memory window is large and high reliability can be achieved. In addition, since writing, erasing or reading can be performed by one bit line voltage generation circuit, the circuit area can be reduced, which is advantageous for cost reduction.

In one embodiment, the first and second diffusion layers have a P-type conductivity type, and the semiconductor memory element is a P-type semiconductor memory element.
A voltage higher than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode The bit line voltage generation circuit and the word line voltage generation circuit connected to the word line are controlled so as to apply a voltage higher than the voltage applied to the second diffusion layer to erase the P-type semiconductor memory element A control unit is provided.

  According to the semiconductor memory device of this embodiment, the control unit controls the bit line voltage generation circuit and the word line voltage generation circuit, and the voltage is higher than the voltage applied to the second diffusion layer. Is applied to the first diffusion layer, and a voltage higher than the voltage applied to the second diffusion layer is applied to the gate electrode, so that the erase operation can be performed at a relatively low voltage. it can. On the other hand, by applying a voltage lower than the voltage applied to the second diffusion layer to the gate electrode in a voltage application state in which a voltage higher than that of the second diffusion layer is applied to the first diffusion layer. The writing operation can be performed at a relatively low voltage.

  Therefore, according to the semiconductor memory device of this embodiment, high-speed write operation and erase operation can be performed at a relatively low voltage, and it can be manufactured at low cost, and the memory window is large and high reliability can be achieved.

In one embodiment, the first and second diffusion layers have an N-type conductivity type, and the semiconductor memory element is an N-type semiconductor memory element.
A voltage lower than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode The bit line voltage generation circuit and the word line voltage generation circuit connected to the word line are controlled so as to apply a voltage lower than the voltage applied to the second diffusion layer to erase the N-type semiconductor memory element A control unit is provided.

  According to the semiconductor memory device of this embodiment, the control unit controls the bit line voltage generation circuit and the word line voltage generation circuit, so that the voltage is lower than the voltage applied to the second diffusion layer. Is applied to the first diffusion layer, and a voltage lower than the voltage applied to the second diffusion layer is applied to the gate electrode, the erase operation can be performed at a relatively low voltage. it can. On the other hand, by applying a voltage higher than the voltage applied to the second diffusion layer to the gate electrode in a voltage application state in which a voltage lower than that of the second diffusion layer is applied to the first diffusion layer. The writing operation can be performed at a relatively low voltage.

  Therefore, according to the semiconductor memory device of this embodiment, high-speed write and erase operations can be performed at a relatively low voltage, and rewriting can be performed without body contact, thereby reducing the circuit area. In addition, the memory window is large and high reliability can be achieved.

  In one embodiment, the channel length of the semiconductor memory element is 0.1 μm or more and 5.0 μm or less.

  According to the semiconductor memory device of this embodiment, a high-speed erase operation can be performed at a relatively low voltage.

A liquid crystal display device according to an embodiment includes the semiconductor memory device described above, and an area surrounded by scanning lines and signal lines arranged vertically and horizontally on a panel substrate is one pixel and a pixel electrode corresponding to the one pixel. A liquid crystal display device having a drive circuit for selectively driving the liquid crystal and interposing a liquid crystal between the pixel electrode and the counter electrode,
In the semiconductor memory device, the correlation data defining the correlation between the digital gradation data and the voltage of the analog gradation signal is stored,
A DA converter that converts the digital gradation data into the analog gradation signal based on the correlation data input from the semiconductor memory device;
A voltage output circuit that outputs a voltage determined by the analog gradation signal input from the DA converter to the counter electrode;
The semiconductor memory device and the voltage output circuit are formed on the panel substrate.

  According to the liquid crystal display device of this embodiment, the DA converter converts the digital gradation data into the analog gradation signal based on the correlation data stored in the small and highly reliable semiconductor storage device. Can be converted. Further, according to the liquid crystal display device of this embodiment, since the semiconductor memory device is formed on the panel substrate of the liquid crystal display device, it is possible to reduce the cost of the external component itself and the mounting cost of the external component. it can. In addition, since the adjustment of the correlation data for converting the digital gradation data into the analog gradation signal can be easily automated, the inspection cost can be reduced.

A receiver according to an embodiment includes a memory circuit including the semiconductor memory device,
A display device;
A receiving circuit for receiving an image signal;
An image signal circuit for supplying the image signal received by the receiving circuit to the display device,
The storage circuit, the reception circuit, and the image reception circuit are formed on the panel substrate of the display device, and store data necessary for generating the image signal in the storage circuit.

  According to the receiver of this embodiment, the data necessary for generating the image signal is stored in the storage circuit including the semiconductor storage device with low cost and high reliability. Can be realized.

  According to the semiconductor memory device of the present invention, high-speed write and erase operations can be performed at a relatively low voltage, and rewriting can be performed without a body contact, so that the circuit area can be reduced and the memory can be reduced. Large windows and high reliability can be achieved. In addition, the ability to reduce the circuit area is advantageous for cost reduction.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. In the following description, two states (so-called write state and erase state) linked to information storage are defined as follows. That is, the case where majority carriers in the conductivity type of the first and second diffusion layer regions are mainly accumulated in the gate insulating film having a function of accumulating charges is defined as a written state. On the other hand, a case where carriers having a conductivity type opposite to the majority carriers are mainly accumulated in the gate insulating film or a case where the accumulated charge is effectively small is defined as an erased state. This erased state includes a case where holes and electrons are accumulated together to cancel each other's potential and the accumulated charge is effectively small.

(First embodiment)
FIG. 1 shows a semiconductor memory device according to the first embodiment of the present invention.

  The semiconductor memory device according to the first embodiment includes a semiconductor memory element array 100 in which a plurality of nonvolatile P-type semiconductor memory elements MC0, MC1,. In the row direction of the semiconductor memory element array 100, a plurality of word lines WL0 to WLn connected to the control gates of the semiconductor memory elements MC0, MC1,.

  The semiconductor memory device according to the first embodiment includes a plurality of bit lines BL0, BL1, BL2, BL3,... Extending in the column direction of the semiconductor memory element array 100. The plurality of bit lines BL0, BL1, BL2, BL3,... Connect one input / output terminals of the plurality of semiconductor memory elements arranged in the same column to each other. For example, even-numbered bit lines BL0, BL2,... Are connected to the sources of the respective semiconductor memory elements, and odd-numbered bit lines BL1, BL3,.

  The word lines WL0 to WLm are connected to a row decoder 102 that selects an arbitrary word line. The row decoder 102 forms a word line voltage generation circuit. The bit lines BL0, BL1, BL2, BL3,... Are connected to transistors Tr0 to Tr4, respectively. The bit lines BL 0, BL 1, BL 2, BL 3,... Are odd-numbered bit line voltage generation circuit 109 or even-numbered bit lines by transistors Tr 0 to Tr 4 selected by output signals SEL 0 to SEL 4 output from the bit line selection circuit 103. The voltage generation circuit 108 is connected. The bit lines BL0, BL1, BL2, BL3,... Are connected to the sense amplifier 101.

  Here, for each semiconductor memory element in the column of the nonvolatile P-type semiconductor memory elements MC0, the bit line BL0 forms a first bit line, while the bit line BL1 forms a second bit line. Further, for each semiconductor memory element in the column of the nonvolatile P-type semiconductor memory element MC0, the even-numbered bit line voltage generation circuit 108 to which the bit line BL0 forming the first bit line is connected has the first bit. While forming the line voltage generating circuit, the odd-numbered bit line voltage generating circuit 109 to which the bit line BL1 forming the second bit line is connected forms the second bit line voltage generating circuit.

  For each semiconductor memory element in the column of the nonvolatile P-type semiconductor memory element MC1, the bit line BL1 forms a first bit line, and the bit line BL2 forms a second bit line. Therefore, for each semiconductor memory element in the column of the P-type semiconductor memory element MC1, the odd-numbered bit line voltage generation circuit 109 to which the bit line BL1 forming the first bit line is connected generates the first bit line voltage. While forming a circuit, the even-numbered bit line voltage generation circuit 108 to which the bit line BL2 forming the second bit line is connected forms the second bit line voltage generation circuit.

  For each semiconductor memory element in the column of the nonvolatile P-type semiconductor memory elements MC2, the bit line BL2 forms a first bit line, while the bit line BL3 forms a second bit line. Therefore, for each semiconductor memory element in the column of the P-type semiconductor memory element MC2, the even-numbered bit line voltage generation circuit 108 to which the bit line BL2 forming the first bit line is connected generates the first bit line voltage. While forming a circuit, an odd-numbered bit line voltage generation circuit 109 to which a bit line BL3 forming a second bit line is connected forms a second bit line voltage generation circuit.

  For each semiconductor memory element in the column of the nonvolatile P-type semiconductor memory elements MC3, the bit line BL3 forms a first bit line, while the bit line BL4 forms a second bit line. Therefore, for each semiconductor memory element in the column of the P-type semiconductor memory element MC3, the odd-numbered bit line voltage generation circuit 109 connected to the bit line BL3 forming the first bit line generates the first bit line voltage. While forming a circuit, the even-numbered bit line voltage generation circuit 108 to which the bit line BL4 forming the second bit line is connected forms the first bit line voltage generation circuit.

  In addition, the semiconductor memory device of this embodiment includes a control unit 111 shown in FIG. The control unit 111 controls operations of the row decoder 102, the bit line selection circuit 103, the even-numbered bit line voltage generation circuit 108, and the odd-numbered bit line voltage generation circuit 109.

  Each of the nonvolatile P-type semiconductor memory elements MC0, MC1,... Provided in the semiconductor memory device of this embodiment is composed of the semiconductor memory element 200 shown in FIG. The semiconductor memory element 200 includes an insulating substrate 201 and a silicon body 207 as a semiconductor layer provided on the insulating substrate 201. P-type well regions 203 and 204 are formed at both ends of the silicon body 207. The P-type well region 203 forms a first diffusion layer, while the P-type well region 204 forms a second diffusion layer.

  A tunnel insulating film 208 and a charge storage film 201 are sequentially formed on the P-type well regions 203 and 204, and a gate electrode 202 is formed on the charge storage film 201 via a gate insulating film 205. The charge storage film 201 is a part where charges are actually stored by a rewrite operation.

  Regarding the channel length, if the channel length is too long, there is a problem that the erase voltage becomes very high. On the other hand, if the channel length is shorter than 0.1 μm, the influence of the short channel effect increases and the variation between semiconductor elements also increases. Therefore, the channel length is preferably 0.1 μm or more.

  Next, the erasing operation in this embodiment will be described with reference to FIG.

  Here, as an example, a case where the semiconductor memory element MC0 is erased will be described. First, in order to apply the first voltage to the semiconductor memory element MC0, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 12V and the odd-numbered bit line voltage generation circuit 109. Set the output to 0V. Further, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 12V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. As a result, a voltage of 12V is applied to the bit line BL0, and a voltage of 0V is applied to the bit line BL1. In this state, the row decoder 102 applies an appropriate voltage (for example, 15V) higher than the output 0V of the odd-numbered bit line voltage generation circuit 109 to the word line WL0.

  As a result, a voltage of 12V from the bit line BL0 is applied to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and a voltage of 0V from the bit line BL1 is applied to the P-type well 204 forming the second diffusion layer. The voltage of 15 V is applied to the gate electrode 202. This voltage application state is the first voltage application.

  Thereafter, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 0V and sets the output of the odd-numbered bit line voltage generation circuit 109 to 12V. Further, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 0V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. As a result, a voltage of 0V is applied to the bit line BL0, and a voltage of 12V is applied to the bit line BL1. In this state, the row decoder 102 applies an appropriate voltage (for example, 15V) higher than the output 0V of the even-numbered bit line voltage generation circuit 108 to the word line WL0. As a result, a voltage of 0V from the bit line BL0 is applied to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and a voltage of 12V from the bit line BL1 is applied to the P-type well 204 forming the second diffusion layer. The voltage of 15 V is applied from the word line WL0 to the gate electrode 202. This voltage application state is the second voltage application.

  Thus, the semiconductor memory element MC0 can be erased by applying the second voltage after the application of the first voltage.

  Next, the write operation in this embodiment will be described with reference to FIG.

  Here, as an example, a case where data is written to the semiconductor memory element MC0 will be described. First, the control unit 111 sets the output of the even bit line voltage generation circuit 108 to 12V and sets the output of the odd number bit line voltage generation circuit 109 to 0V. Further, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 12V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. As a result, a voltage of 12V is applied to the bit line BL0, and a voltage of 0V is applied to the bit line BL1. Next, the row decoder 102 applies a voltage of −3 V to the word line WL0. As a result, in only the semiconductor memory element MC0, a voltage of 12V is applied from the bit line BL0 to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and the bit is applied to the P-type well 204 forming the second diffusion layer. A voltage of 0V is applied from the line BL1, and a voltage of -3V is applied from the word line WL0 to the gate electrode 202. That is, the gate voltage −3 V, the source voltage 12 V, and the drain voltage 0 V are applied only to the semiconductor memory element MC0. By applying this voltage, data can be written in the semiconductor memory element MC0.

  Next, the read operation in this embodiment will be described with reference to FIG.

  Here, as an example, an operation of reading information from the semiconductor memory element MC0 will be described.

  First, the control unit 111 sets the outputs of both the even-numbered bit line voltage generation circuit 108 and the odd-numbered bit line voltage generation circuit 109 to 4V. Further, the output signal SEL0 of the bit line selection circuit 103 is set to 0V, and the outputs of the output signals SEL1 to SEL4 are set to 4V. As a result, the transistor Tr0 controlled by the output signal SEL0 is turned off and the transistors Tr1 to Tr4 controlled by the output signals SEL1 to SEL4 are turned on. Further, the output WL0 of the row decoder 102 is set to 0V. At this time, the gate voltage 0V, the source voltage 0V, and the drain voltage 4V are applied only to the semiconductor memory element MC0, a current flows from the drain to the source in the semiconductor memory element MC0, and the bit line BL0 is charged. Then, after a certain period of time has elapsed, when the voltage of the word line WL0 is set to 4 V by the row decoder 102, the charging of the bit line BL0 is completed.

  In the above-described operation, when the semiconductor memory element MC0 is in the erased state, the current drive capability of the semiconductor memory element MC0 is large, so that the voltage of the charged bit line BL0 becomes high. On the other hand, when the semiconductor memory element MC0 is in the write state, the current drive capability of the semiconductor memory element MC0 is small, and thus the voltage of the bit line BL0 after charging is low. Accordingly, after the voltage of the word line WL0 is set to 0 V, the stored information of the semiconductor memory element MC0 can be read by comparing the voltage of the bit line BL0 with the reference voltage by the sense amplifier 101.

Next, the drain current-gate voltage characteristic (Id-Vg characteristic) of the semiconductor memory element MC0 of the semiconductor memory device of this embodiment will be described with reference to FIG. In FIG. 3, the vertical axis represents the drain current Id (A), and the horizontal axis represents the gate voltage Vg (V). In the above vertical axis, for example, “4E-06” represents “4 × 10 ⁻⁶ ” and “1.E-05” represents “1 × 10 ⁻⁵ ”.

  In FIG. 3, an initial characteristic K0 represents a drain current-gate voltage characteristic before the erase operation of the semiconductor memory element MC0. The first characteristic K1 represents the drain current-gate voltage characteristic of the semiconductor memory element MC0 after the application of the first voltage in the erase operation. The second characteristic K2 represents the drain current-gate voltage characteristic of the semiconductor memory element MC0 after applying the second voltage after applying the first voltage in the erasing operation.

  The element parameters of the semiconductor memory element MC0 in the characteristics shown in FIG. 3 are as follows. In the semiconductor memory element 200 shown in FIG. 2, the thickness of the gate insulating film 205 is 10 nm, and the thickness of the tunnel oxide film 208 is 10 nm. The thickness of the nitride film constituting the charge storage film 201 was 25 nm, the channel length was 0.7 μm, and the channel width was 2.5 μm.

  As described above, the channel length is preferably 5.0 μm or less, and more preferably 1.0 μm or less because a high-performance semiconductor device capable of high-speed erasing with a low voltage can be obtained. On the other hand, when the channel length is shorter than 0.1 μm, the influence of the short channel effect is increased, and the variation between the semiconductor elements is increased. Therefore, the channel length is preferably 0.1 μm or more. Appropriate erase conditions differ depending on the channel length, and the shorter the channel length, the lower the erase voltage.

  Further, as conditions for the erase operation, when the first voltage is applied, 12V is applied to the first diffusion layer (P-type well 203), 0V is applied to the second diffusion layer (P-type well 204), and 15V is applied to the gate electrode 202. After a voltage is applied for 1 second, a second voltage is applied to apply a voltage of 0V to the first diffusion layer (P-type well 203), 12V to the second diffusion layer (P-type well 204), and 15V to the gate electrode. Applied for 1 second.

  As a result of the erase operation, as shown in FIG. 3, the drain current-gate voltage characteristic of the semiconductor memory element MC0 is changed from the initial characteristic K0 to the second characteristic K2, and the threshold value is shifted by approximately 9V.

  FIG. 4 shows the result of rewriting by the erase operation and the write operation in this embodiment. In FIG. 4, the horizontal axis indicates the number of rewrites, and the vertical axis indicates the threshold value. In FIG. 4, the threshold value after writing is shown in the region R1, and the threshold value after erasing is shown in the region R2. As shown in FIG. 4, approximately 11 V is achieved as the threshold window after 10 rewrites.

  In the above-described embodiment, the P-type semiconductor memory element is more preferable than the N-type semiconductor memory element because the rewriting is more stable and particularly preferable on the glass substrate. Therefore, the semiconductor memory elements MC0, MC1,. However, the present invention can also be applied to a semiconductor memory device having an N-type semiconductor memory element. When an SOI substrate is used, an N-type semiconductor memory element or a P-type semiconductor memory element may be used.

  In the case of a semiconductor memory device having an N-type semiconductor memory element, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 3 V and the output of the odd-numbered bit line voltage generation circuit 109 during the erase operation. The row decoder 102 applies an appropriate voltage (for example, 0 V) lower than the output 15 V of the odd-numbered bit line voltage generation circuit 109 to the word line WL0. This voltage application state is the first voltage application. Thereafter, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 15V, sets the output of the odd-numbered bit line voltage generation circuit 109 to 3V, and the row decoder 102 applies the even-numbered bit to the word line WL0. An appropriate voltage (for example, 0 V) lower than the output 15 V of the line voltage generation circuit 108 is applied.

  Further, as the substrate of the semiconductor memory element, SOI (silicon-on-oxide) such as SIMOX (silicon-implanted oxide), Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.), etc. It is also possible to use a single crystal semiconductor thin film as an active layer using an insulator substrate.

(Second embodiment)
Next explained is a second embodiment of the semiconductor memory device according to the invention. The second embodiment is different from the first embodiment in the contents of the erase operation by the control unit 11 and the channel length of the element parameters of the semiconductor memory element MC0. Since this is the same as that of the first embodiment described above, differences from the first embodiment will be mainly described.

  With reference to FIG. 1, the erasing operation in the second embodiment will be described.

  Here, as an example, in order to apply the first voltage to the semiconductor memory element MC0, the output of the even-numbered bit line voltage generation circuit 108 is set to 12V, and the odd-numbered bit line voltage generation circuit 109 is set to 0V. To do. Further, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 12V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. As a result, a voltage of 12V is applied to the bit line BL0, and a voltage of 0V is applied to the bit line BL1. In this state, the row decoder 102 applies an appropriate voltage (for example, 15V) higher than the output 0V of the odd-numbered bit line voltage generation circuit 109 to the word line WL0.

  As a result, a voltage of 12V from the bit line BL0 is applied to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and a voltage of 0V from the bit line BL1 is applied to the P-type well 204 forming the second diffusion layer. The voltage of 15 V is applied to the gate electrode 202. This voltage application state is the first voltage application.

  Thereafter, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 0V and sets the output of the odd-numbered bit line voltage generation circuit 109 to 12V. Further, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 12V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. As a result, a voltage of 0V is applied to the bit line BL0, and a voltage of 12V is applied to the bit line BL1. In this state, the row decoder 102 applies an appropriate voltage (for example, 15V) higher than the output 0V of the even-numbered bit line voltage generation circuit 108 to the word line WL0. As a result, a voltage of 0V from the bit line BL0 is applied to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and a voltage of 12V from the bit line BL1 is applied to the P-type well 204 forming the second diffusion layer. The voltage of 15 V is applied from the word line WL0 to the gate electrode 202. This voltage application state is the second voltage application.

  Thereafter, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 12V and sets the output of the odd-numbered bit line voltage generation circuit 109 to 0V. In this state, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 12V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. In this state, the row decoder 102 applies an appropriate voltage (for example, 15V) higher than the output 0V of the odd-numbered bit line voltage generation circuit 109 to the word line WL0. As a result, a voltage of 12V from the bit line BL0 is applied to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and a voltage of 0V from the bit line BL1 is applied to the P-type well 204 forming the second diffusion layer. The voltage of 15 V is applied from the word line WL0 to the gate electrode 202. This voltage application state is the third voltage application.

  Thereafter, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 0V and sets the odd-numbered bit line voltage generation circuit 109 to 12V. In this state, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 12V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. In this state, the row decoder 102 applies an appropriate voltage (for example, 15V) higher than the output 0V of the even-numbered bit line voltage generation circuit 108 to the word line WL0. As a result, a voltage of 0V from the bit line BL0 is applied to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and a voltage of 12V from the bit line BL1 is applied to the P-type well 204 forming the second diffusion layer. The voltage of 15 V is applied from the word line WL0 to the gate electrode 202. This voltage application state is the fourth voltage application.

  Thus, the semiconductor memory element MC0 can be erased by sequentially applying the first, second, third and fourth voltages.

  Note that the write operation and read operation of the second embodiment are the same as those of the first embodiment.

Next, the drain current-gate voltage characteristic (Id-Vg characteristic) of the semiconductor memory element MC0 of the semiconductor memory device of this embodiment will be described with reference to FIG. In FIG. 5, the vertical axis represents the drain current Id (A), and the horizontal axis represents the gate voltage Vg (V). In the above vertical axis, for example, “4E-06” represents “4 × 10 ⁻⁶ ” and “1.E-05” represents “1 × 10 ⁻⁵ ”.

  The element parameters of the semiconductor memory element MC0 in the characteristics shown in FIG. 5 are as follows. In the semiconductor memory element 200 shown in FIG. 2, the thickness of the gate insulating film 205 is 10 nm, and the thickness of the tunnel oxide film 208 is 10 nm. The thickness of the nitride film constituting the charge storage film 201 was 25 nm, the channel length was 1.2 μm, and the channel width was 2.5 μm.

  In FIG. 5, an initial characteristic J0 represents a drain current-gate voltage characteristic before writing of the semiconductor memory element MC0. A characteristic J1 represents a drain current-gate voltage characteristic after writing in the semiconductor memory element MC0. A characteristic J2 represents a drain current-gate voltage characteristic after the first voltage is applied to the semiconductor memory element MC0 after writing. A characteristic J3 represents a drain current-gate voltage characteristic of the semiconductor memory element MC0 after the application of the first and second voltages in the erasing operation. A characteristic J4 represents a drain current-gate voltage characteristic of the semiconductor memory element MC0 after applying the third voltage after applying the first and second voltages in the erasing operation. A characteristic J5 represents a drain current-gate voltage characteristic of the semiconductor memory element MC0 after applying the third and fourth voltages after applying the first and second voltages in the erasing operation.

  In the above writing, a voltage of 12 V is applied to the first diffusion layer (P-type well 203), 0 V is applied to the second diffusion layer (P-type well 204), and -3 V is applied to the gate electrode 202 for 1 second. The erase operation is performed under the condition that the first voltage is applied, the first diffusion layer (P-type well 203) is 12V, the second diffusion layer (P-type well 204) is 0V, and the gate electrode 202 is 15V. Is applied for 1 second, and then the second voltage is applied to the first diffusion layer (P-type well 203) at 0V, the second diffusion layer (P-type well 204) at 12V, and the gate electrode at 15V. Was applied for 1 second. Thereafter, in the third voltage application, a voltage of 12 V is applied to the first diffusion layer, a voltage of 0 V is applied to the second diffusion layer, and a voltage of 15 V is applied to the gate electrode 202 for 1 second. A voltage of 0 V was applied to the first diffusion layer, 12 V was applied to the second diffusion layer, and 15 V was applied to the gate electrode 202 for 1 second.

  In the second embodiment, the channel length, which is an element parameter of the semiconductor memory element MC0, is 1.2 μm, and the channel length is longer than the channel length of 0.7 μm of the semiconductor memory element MC0 in the first embodiment described above. For this reason, as shown in the drain current-gate voltage characteristic J3 of the semiconductor memory element MC0, sufficient erasing cannot be performed only by applying the first and second voltages in the erasing operation. That is, after applying a voltage of 12V to the first diffusion layer, 0V to the second diffusion layer, and 15V to the gate electrode for 1 second, 0V to the first diffusion layer, 12V to the second diffusion layer, and to the gate electrode Even if a voltage of 15 V is applied for 1 second, sufficient erasing cannot be performed. On the other hand, after applying the first and second voltages, the characteristic J4 after applying the third voltage, and after applying the first and second voltages, the third and fourth voltages are applied. According to the characteristic J5 after the application, sufficient erasure can be performed.

  According to the present embodiment, erasing can be effectively performed even for an element having a large channel length, and the channel length may be 5.0 μm or more. In order to perform high-speed erasing at a relatively low voltage, The channel length is preferably 2.0 μm or less. Appropriate erasing conditions differ depending on the channel length, and the smaller the channel length, the lower the erasing voltage can be set. Therefore, the channel length is more preferably 1.5 μm or less.

  In the second embodiment, the P-type semiconductor memory element is more preferable than the N-type semiconductor memory element on the glass substrate because the rewriting is stable and particularly preferable. Therefore, the semiconductor memory elements MC0, MC1,. Although an example of a semiconductor memory element has been described, the present invention can also be applied to a semiconductor memory device having an N-type semiconductor memory element. When an SOI substrate is used, an N-type semiconductor memory element or a P-type semiconductor memory element may be used.

  In the case of a semiconductor memory device having an N-type semiconductor memory element, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 3 V and the output of the odd-numbered bit line voltage generation circuit 109 during the erase operation. The row decoder 102 applies an appropriate voltage (for example, 0 V) lower than the output 15 V of the odd-numbered bit line voltage generation circuit 109 to the word line WL0. This voltage application state is the first voltage application. Thereafter, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 15V, sets the output of the odd-numbered bit line voltage generation circuit 109 to 3V, and the row decoder 102 applies the even-numbered bit to the word line WL0. An appropriate voltage (for example, 0 V) lower than the output 15 V of the line voltage generation circuit 108 is applied. This voltage application state is the second voltage application. After that, the control unit 111 further sets the output of the even-numbered bit line voltage generation circuit 108 to 3V, sets the output of the odd-numbered bit line voltage generation circuit 109 to 15V, and the row decoder 102 selects the word line WL0. A suitable voltage (for example, 0 V) lower than the output 15 V of the odd-numbered bit line voltage generation circuit 109 is applied to the first bit line. This voltage application state is the third voltage application. Thereafter, the control unit 111 further sets the output of the even-numbered bit line voltage generation circuit 108 to 15 V, sets the output of the odd-numbered bit line voltage generation circuit 109 to 3 V, and the row decoder 102 applies an even number to the word line WL0. An appropriate voltage (for example, 0V) lower than the output 15V of the number bit line voltage generation circuit 108 is applied. This voltage application state is the fourth voltage application.

(Third embodiment)
Next, FIG. 6 shows a third embodiment of the semiconductor memory device of the present invention. In the third embodiment, the odd-numbered bit line voltage generation circuit 109 in the first embodiment is deleted and the odd-numbered bit lines BL1 and BL3 are connected to the ground, and the contents of the erase operation by the control unit 111 are as follows. Is different from the first embodiment. Therefore, in the third embodiment, differences from the first embodiment will be mainly described.

  With reference to FIG. 6, the erasing operation in the third embodiment will be described. Here, as an example, a case where the semiconductor memory element MC0 is erased will be described. First, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to 12V. Further, the output signals SEL0 and SEL1 of the bit line selection circuit 103 are set to 12V, and the transistors Tr0 and Tr1 controlled by the output signals SEL0 and SEL1 are turned on. As a result, a voltage of 12V is applied to the bit line BL0, and a ground potential (0V) is applied to the bit line BL1. In this state, the row decoder 102 applies an appropriate voltage (as an example, 15 V) higher than the ground potential (0 V) to the word line WL0. As a result, a voltage of 12V from the bit line BL0 is applied to the P-type well 203 forming the first diffusion layer shown in FIG. 2, and a voltage of 0V from the bit line BL1 is applied to the P-type well 204 forming the second diffusion layer. The voltage of 15 V is applied to the gate electrode 202.

  In the third embodiment, the semiconductor memory element MC0 is erased by the voltage application.

  Note that the write operation in the third embodiment is the same as the write operation in the first embodiment described above except that the control unit 111 does not control the odd-numbered bit line voltage generation circuit 109. The read operation in the third embodiment is the same as the read operation in the first embodiment described above, except that the control unit 111 has no operation to control the odd-numbered bit line voltage generation circuit 109.

Next, with reference to FIG. 7, the drain current-gate voltage characteristic (Id-Vg characteristic) of the semiconductor memory element MC0 of the semiconductor memory device of this embodiment will be described. In FIG. 7, the vertical axis represents the drain current Id (A), and the horizontal axis represents the gate voltage Vg (V). In the above vertical axis, for example, “4E-06” represents “4 × 10 ⁻⁶ ” and “1.E-05” represents “1 × 10 ⁻⁵ ”.

  In FIG. 7, an initial characteristic H0 represents a drain current-gate voltage characteristic before the erase operation of the semiconductor memory element MC0. A characteristic H1 represents a drain current-gate voltage characteristic of the semiconductor memory element MC0 after the erase operation.

  The element parameters of the semiconductor memory element MC0 in the characteristics shown in FIG. 7 are as follows. In the semiconductor memory element 200 shown in FIG. 2, the thickness of the gate insulating film 205 is 10 nm and the thickness of the tunnel oxide film 208 is 10 nm. The thickness of the nitride film constituting the charge storage film 201 was 25 nm, the channel length was 0.7 μm, and the channel width was 2.5 μm.

  As conditions for the erasing operation, a voltage of 12V is applied to the first diffusion layer (P-type well 203), 0V is applied to the second diffusion layer (P-type well 204), and 15V is applied to the gate electrode 202 by applying the voltage. Applied for 1 second.

  As shown in FIG. 7, a threshold shift of about 2 V was obtained by applying the voltage by the erase operation.

  In the third embodiment, an example in which the semiconductor memory elements MC0, MC1,... Are P-type semiconductor memory elements has been described. However, the present invention can also be applied to a semiconductor memory device having N-type semiconductor memory elements. In this case, during the erase operation, the control unit 111 sets the output of the even-numbered bit line voltage generation circuit 108 to −12V, and the row decoder 102 applies an appropriate voltage lower than the ground potential (0V) to the word line WL0. (For example, -15V) is applied.

(Fourth embodiment)
Next, with reference to FIG. 8A and FIG. 8B, the liquid crystal display device as 4th Embodiment of this invention is demonstrated. In this liquid crystal display device, as shown in FIG. 8A, a region surrounded by scanning lines 312 and signal lines 313 arranged vertically and horizontally on a panel substrate 301 is defined as one pixel 302. As shown in FIG. 8B, this liquid crystal display device has a pixel TFT (thin film transistor) 311 which forms a drive circuit for selectively driving the pixel electrode 314 corresponding to the one pixel 302. The gate of the pixel TFT 311 is connected to the scanning line 312, one diffusion region (for example, source) is connected to the signal line 313, and the other diffusion region (for example, drain) is connected to the pixel electrode 314. A liquid crystal 316 is interposed between the pixel electrode 314 and the common electrode 315 common to the panel. A predetermined voltage generated by the voltage generation circuit 322 is applied to the counter electrode 315.

  This liquid crystal display device has the semiconductor memory device of any of the first to third embodiments described above as the memory unit 321 on the panel substrate 301. The memory cell portion 321 is used as an element for storing image information to be provided to the voltage generation circuit 322 that applies a voltage to the counter electrode 315 of the liquid crystal display device. More specifically, the voltage generated by the voltage generation circuit 322 is determined based on image information stored in the memory unit 321. The voltage generated by the voltage generation circuit 322 is applied to the counter electrode 315 in order to suppress screen flickering. The generated voltage value should be adjusted for each panel.

  In this embodiment, since the generated voltage value is determined based on the image information stored in the memory unit 321, in a general case where voltage adjustment is performed by adjusting a variable resistor externally attached to the panel. Compared with this, it is possible to reduce the cost of the external component itself and the mounting cost of the external component. In addition, since the voltage adjustment can be automated, the inspection cost can be reduced. Furthermore, since the semiconductor memory device of this embodiment has a simple gate insulating film structure and requires a small number of processes, it is advantageous for cost reduction.

(Fifth embodiment)
Next, a display device as a fifth embodiment of the present invention will be described with reference to FIG. This display device is, for example, a liquid crystal panel or an organic EL panel.

  The display device includes the panel substrate 301, the scanning line 312, the signal line 313, the pixel 302, the pixel electrode 314, the counter electrode 315, and the liquid crystal 316 as described in the fourth embodiment as the display unit 415. The display device also includes a DA converter 412 that receives digital gradation data (digital information) from the display data generation circuit 413 and converts the digital gradation data into an analog gradation signal. The display device also includes a memory unit 411 that stores data defining the correlation between the digital gradation data and the voltage of the analog gradation signal. The memory unit 411 is configured by any one of the semiconductor memory devices of the first to third embodiments described above.

  The DA converter 412 converts the digital gradation data into an analog gradation signal based on the data stored in the memory unit 411 and outputs the analog gradation signal to the voltage output circuit 414. The voltage output circuit 414 outputs a signal voltage based on the analog gradation signal to the display unit 415. The voltage output circuit 414, the DA converter 412 and the memory unit 411 are formed on the panel substrate 301.

  According to the display device of this embodiment, the DA converter 412 is configured so that the color of the image displayed on the display unit 415 is naturally reproduced based on the data stored in the memory unit 411. The gradation data is converted into an analog gradation signal. The correlation between the digital gradation data and the analog gradation signal should be adjusted for each panel.

  According to this embodiment, since the conversion is performed based on the data stored in the memory unit 411, the voltage is adjusted by adjusting a variable resistor externally attached to the panel. The cost of the external parts themselves and the cost of attaching the external parts can be reduced. In addition, since the voltage adjustment can be automated, the inspection cost can be reduced. Furthermore, since the semiconductor memory device of this embodiment has a simple gate insulating film structure and requires a small number of processes, it is advantageous for cost reduction.

(Sixth embodiment)
Next, a receiver as a sixth embodiment of the invention will be described with reference to FIG. The receiver 500 includes a tuner 512 to which a reception signal is input from an antenna terminal 515, a control unit 514 that controls a tuning operation of the reception signal by the tuner 512, and a speaker 513 to which an audio signal selected by the tuner 512 is input. And a display device 511 including a liquid crystal display panel to which the image signal selected by the tuner 512 is input.

  In addition, the receiver 500 receives on the panel substrate of the display device 511 a reception circuit 505 that receives an image signal from the tuner 512 and performs signal processing on the image signal received by the reception circuit 505 and then performs liquid crystal processing. It has an image signal circuit 506 supplied to the display portion, and a storage circuit 510 for storing data necessary for performing signal processing of the image signal. In this embodiment, the memory circuit 510 is constituted by any one of the semiconductor memory devices of the first to third embodiments described above.

  The nonvolatile memory included in the memory circuit 510 included in the display device 511 includes information for determining a voltage value to be applied to the counter electrode of the liquid crystal display panel as described in the fourth embodiment, The data representing the correlation between the digital gradation data and the voltage of the analog gradation signal as described in the fifth embodiment can be stored.

  Furthermore, in this receiver 500, the encrypted signal is sent to the display device 511 via the tuner 512, and the image signal circuit 506 of the liquid crystal display panel decrypts the code, thereby enhancing information security. However, the encryption key at this time can be stored in the storage circuit 510 provided in the liquid crystal display panel. By providing such a display device 511, a high-performance receiver 500 can be realized at low cost.

  Note that FIG. 10 illustrates a configuration in which the receiver receives a wireless signal with an antenna. However, when receiving a signal with a wire, the tuner 512 includes a cable connection terminal instead of the antenna terminal 515. Instead, a signal receiving unit is provided.

1 is a schematic diagram showing a semiconductor memory device according to a first embodiment of the present invention. 1 is a schematic view of a P-type semiconductor memory element according to a first embodiment of the present invention. It is a characteristic view explaining the drain current-gate voltage characteristic (Id-Vg characteristic) of semiconductor memory element MC0 of 1st Embodiment of this invention. It is a graph which shows the threshold value window of the semiconductor memory element rewritten by the erasing method and writing method of 1st Embodiment of this invention. It is a characteristic view which shows the Id-Vg characteristic of the semiconductor memory element rewritten by the erasing method and writing method of 2nd Embodiment of this invention. It is the schematic which shows the semiconductor memory device of 3rd Embodiment of this invention. It is a characteristic view which shows the Id-Vg characteristic of the semiconductor memory element erase | eliminated by the erase method of 3rd Embodiment of this invention. It is a schematic diagram which shows the panel substrate 301 of the liquid crystal display device of 4th Embodiment of this invention. It is a typical circuit block diagram of the liquid crystal display device of the said 4th Embodiment. It is a circuit block diagram of the display apparatus of 5th Embodiment of this invention. It is a block diagram of the receiver of 6th Embodiment of this invention.

Explanation of symbols

100 storage element array 101 sense amplifier 102 row decoder 103 bit line selection circuit 108 even number bit line voltage generation circuit 109 odd number bit line voltage generation circuit 111 control unit 200 semiconductor storage element 201 charge storage film 202 gate electrode 203 first diffusion Layer 204 second diffusion layer 205 gate insulating film 206 insulating substrate 207 silicon body 208 tunnel insulating film 311 pixel electrode 312 scanning line 313 signal line 314 pixel electrode 315 counter electrode 316 liquid crystal 321 memory unit 322 voltage generation circuit 411 memory unit 412 DA Converter 414 Output circuit 415 Display unit 500 Receiver 505 Reception circuit 506 Image signal circuit 510 Storage circuit 511 Display device (liquid crystal display panel)
512 Tuner 513 Speaker 514 Control Unit

Claims (14)

A semiconductor layer formed over a substrate having an insulating surface;
A first diffusion layer formed in the semiconductor layer;
A second diffusion layer formed in the semiconductor layer;
A charge storage film that covers at least a channel region between the first diffusion layer and the second diffusion layer in the semiconductor layer and into which charges are injected from the channel region;
A semiconductor memory element having a gate electrode located on the opposite side of the channel region across the charge storage film;
A word line connected to the gate electrode;
A first bit line connected to the first diffusion layer of the semiconductor memory element;
A second bit line connected to the second diffusion layer of the semiconductor memory element;
A first bit line voltage generating circuit connected to the first bit line;
A semiconductor memory device comprising: a second bit line voltage generation circuit connected to the second bit line. The semiconductor memory device according to claim 1,
The first and second diffusion layers have a P-type conductivity type, and the semiconductor memory element is a P-type semiconductor memory element,
A voltage higher than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode After performing a first voltage application that applies a voltage higher than a voltage applied to the second diffusion layer, a voltage higher than a voltage applied to the first diffusion layer from the first bit line is applied. A second voltage is applied from the second bit line to the second diffusion layer and a voltage higher than the voltage applied to the first diffusion layer from the word line to the gate electrode. And a control unit for controlling the first and second bit line voltage generation circuits and the word line voltage generation circuit connected to the word lines to erase the P-type semiconductor memory element. Semiconductor memory device. The semiconductor memory device according to claim 2,
The control unit
After applying the first voltage, after applying the second voltage, a voltage higher than the voltage applied from the second bit line to the second diffusion layer is applied. The third voltage application is performed such that a third voltage application is applied from the bit line to the first diffusion layer and a voltage higher than the voltage applied to the second diffusion layer from the word line to the gate electrode. A semiconductor memory device, wherein the P-type semiconductor memory element is erased by controlling the first and second bit line voltage generating circuits and the word line voltage generating circuit connected to the word lines. The semiconductor memory device according to claim 3.
The control unit
After applying the first, second, and third voltages in order, a voltage higher than the voltage applied from the first bit line to the first diffusion layer is applied from the second bit line. The first and second voltages are applied so that a fourth voltage is applied to the second diffusion layer and a voltage higher than the voltage applied to the first diffusion layer from the word line to the gate electrode. A semiconductor memory device, wherein the bit line voltage generating circuit and the word line voltage generating circuit connected to the word line are controlled to erase the P-type semiconductor memory element. The semiconductor memory device according to claim 1,
The first and second diffusion layers have an N-type conductivity type, and the semiconductor memory element is an N-type semiconductor memory element,
A voltage lower than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode After performing a first voltage application that applies a voltage lower than the voltage applied to the second diffusion layer, a voltage lower than the voltage applied to the first diffusion layer from the first bit line is applied. A second voltage is applied from the second bit line to the second diffusion layer and a voltage lower than a voltage applied to the first diffusion layer from the word line to the gate electrode. And a controller for controlling the first and second bit line voltage generating circuits and the word line voltage generating circuit connected to the word lines to erase the N-type semiconductor memory element. Semiconductor memory device. The semiconductor memory device according to claim 5.
The control unit
After applying the first voltage, after applying the second voltage, a voltage lower than the voltage applied from the second bit line to the second diffusion layer is applied. The third voltage application is performed such that a third voltage is applied from the bit line to the first diffusion layer and a voltage lower than the voltage applied to the second diffusion layer from the word line to the gate electrode. A semiconductor memory device, wherein the N-type semiconductor memory element is erased by controlling the first and second bit line voltage generating circuits and the word line voltage generating circuit connected to the word lines. The semiconductor memory device according to claim 6.
The control unit
After the first, second, and third voltage applications are sequentially performed, a voltage lower than the voltage applied from the first bit line to the first diffusion layer is applied from the second bit line. The first and second voltages are applied so that a fourth voltage is applied to the second diffusion layer and a voltage lower than the voltage applied to the first diffusion layer from the word line to the gate electrode. And erasing the N-type semiconductor memory element by controlling the bit line voltage generating circuit and the word line voltage generating circuit connected to the word line. 6. The semiconductor memory device according to claim 2, wherein
The control unit
A semiconductor memory device comprising: erasing the semiconductor memory element by repeating voltage application control for applying the second voltage after performing the first voltage application a plurality of times. The semiconductor memory element according to claim 1,
A word line connected to the gate electrode;
A first bit line connected to the first diffusion layer of the semiconductor memory element;
A second bit line connected to the second diffusion layer of the semiconductor memory element and connected to the ground;
A semiconductor memory device comprising: a bit line voltage generation circuit connected to the first bit line. The semiconductor memory device according to claim 1 or 9,
The first and second diffusion layers have a P-type conductivity type, and the semiconductor memory element is a P-type semiconductor memory element,
A voltage higher than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode The bit line voltage generation circuit and the word line voltage generation circuit connected to the word line are controlled so as to apply a voltage higher than the voltage applied to the second diffusion layer to erase the P-type semiconductor memory element A semiconductor memory device comprising a control unit for performing the above operation. The semiconductor memory device according to claim 1 or 9,
The first and second diffusion layers have an N-type conductivity type, and the semiconductor memory element is an N-type semiconductor memory element,
A voltage lower than the voltage applied from the second bit line to the second diffusion layer is applied from the first bit line to the first diffusion layer, and the word line to the gate electrode The bit line voltage generation circuit and the word line voltage generation circuit connected to the word line are controlled so as to apply a voltage lower than the voltage applied to the second diffusion layer to erase the N-type semiconductor memory element A semiconductor memory device comprising a control unit for performing the above operation. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein a channel length of the semiconductor memory element is 0.1 μm or more and 5.0 μm or less. A semiconductor memory device according to any one of claims 1 to 11, comprising:
A region surrounded by scanning lines and signal lines arranged vertically and horizontally on a panel substrate is set as one pixel, and a driving circuit for selectively driving a pixel electrode corresponding to the one pixel is provided. A liquid crystal display device with liquid crystal interposed between,
In the semiconductor memory device, the correlation data defining the correlation between the digital gradation data and the voltage of the analog gradation signal is stored,
A DA converter that converts the digital gradation data into the analog gradation signal based on the correlation data input from the semiconductor memory device;
A voltage output circuit that outputs a voltage determined by the analog gradation signal input from the DA converter to the counter electrode;
The liquid crystal display device, wherein the semiconductor memory device and the voltage output circuit are formed on the panel substrate. A memory circuit including the semiconductor memory device according to claim 1;
A display device;
A receiving circuit for receiving an image signal;
An image signal circuit for supplying the image signal received by the receiving circuit to the display device,
The storage circuit, the reception circuit, and the image reception circuit are formed on the panel substrate of the display device, and the storage circuit stores data necessary for generating the image signal. .

Images