JP2009238778A - Method of manufacturing light emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve ESD (Electro Static Discharge) breakdown voltage in a method of manufacturing a light emitting element. <P>SOLUTION: A method of manufacturing a light emitting element includes a step of forming an MQW (Multi Quantum Well) active layer 24 that includes: the steps of forming a well layer 21 made of a nitride semiconductor; and forming a barrier layer 23 made of a nitride semiconductor on the well layer 21 at a growth temperature which is 130 to 150°C higher than the growth temperature of the well layer 21. The ESD breakdown voltage is improved by setting the difference in growth temperature between the barrier layer 23 and well layer 21 to not less than 130°C. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a method for manufacturing a light emitting device, and more particularly to a method for manufacturing a light emitting device having a nitride semiconductor layer.

  An LED having a nitride semiconductor layer is used as a light emitting element such as a white LED (Light Emitting Diode). In such an LED, an active layer having an MQW (Multi Quantum Well) structure is used. Patent Document 1 discloses an LED manufactured by forming the MQW active layer by increasing the growth temperature of the GaN barrier layer between 150 ° C. and 220 ° C. as compared to the growth temperature of the InGaN well layer.

Japanese Patent Laid-Open No. 2007-036133

  In an LED having a nitride semiconductor layer, there is a problem that an electrostatic discharge (ESD) breakdown voltage is low.

  An object of the present invention is to improve the ESD withstand voltage.

  The present invention includes a step of forming a well layer made of a nitride semiconductor, and a barrier layer made of a nitride semiconductor is formed on the well layer at a growth temperature that is 130 ° C. or more and less than 150 ° C. higher than the growth temperature of the well layer. And a step of forming an MQW active layer including the step of: a method of manufacturing a light emitting device. According to the present invention, the ESD withstand voltage can be improved by setting the difference in growth temperature between the barrier layer and the well layer to 130 ° C. or more. Moreover, the fall of luminous efficiency can be suppressed by making the difference of the growth temperature of a barrier layer and a well layer into less than 150 degreeC.

  The said structure WHEREIN: The growth temperature of the said barrier layer can be made into the structure 140 to 150 degreeC higher than the growth temperature of the said well layer. In the above configuration, the well layer / barrier layer may be configured of any one of InGaN / GaN, InGaN / InGaN, and AlInGaN / AlInGaN. Furthermore, the said structure WHEREIN: The said board | substrate can be set as the structure which is either Si, SiC, GaN, and sapphire. Further, in the above structure, the active layer can be formed using a MOCVD method. Further, in the above structure, the growth temperature of the barrier layer may be 870 ° C. or lower.

  According to the present invention, the ESD withstand voltage can be improved.

  As in Patent Document 1, it has been conventionally known that the barrier layer is preferably grown at a growth temperature higher by 160 to 200 ° C. than the well layer. The inventor has found that the difference in growth temperature between the barrier layer and the well layer also affects the ESD withstand voltage. Examples of the present invention will be described below.

  A method for manufacturing a light-emitting element according to an example will be described with reference to FIGS. Referring to FIG. 1, an AlN buffer layer 12, a Si-doped GaN buffer layer 14, an undoped GaN buffer layer 16, an n-type GaN buffer layer 16, and an n-doped GaN buffer layer 16 are formed on a sapphire substrate 10 having (0001) as a main surface by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. The n-type GaN intermediate layer 18, the n-type GaN contact layer 20, the n-type GaN layer 22, the MQW active layer 24, and the p-type GaN layer 26 are grown in this order.

The growth conditions for each layer are as follows.
Growth conditions for AlN buffer layer 12 Film thickness: 580 nm
Dope concentration: undoped Source gas: TMA (trimethylaluminum), NH ₃
Carrier gas: Hydrogen Pressure: 50 Torr
Growth temperature: 1040 ° C. (growth 1), 1140 ° C. (growth 2)
The growth temperature is changed from growth 1 to growth 2 during the growth.

Growth conditions for Si-doped GaN buffer layer 14 Film thickness: 60 nm
Si doping concentration: 1.5 × 10 ¹⁹ cm ⁻³
Source gas: TMG (trimethyl gallium), NH ₃ , SiH ₄
Carrier gas: Hydrogen Pressure: 200 Torr
Growth temperature: 1040 ° C

Growth condition of undoped GaN buffer layer 16 Film thickness: 1330 nm
Dope concentration: undoped Source gas: TMG, NH ₃
Carrier gas: Hydrogen Pressure: 200 Torr
Growth temperature: 1040 ° C

Growth conditions for n-type GaN intermediate layer 18 Film thickness: 1380 nm
Si doping concentration: 1.5 × 10 ¹⁹ cm ⁻³
Source gas: TMG, NH ₃ , SiH ₄
Carrier gas: Hydrogen Pressure: 100 Torr
Growth temperature: 1040 ° C

Growth conditions for n-type InGaNIn contact layer 20 Film thickness: 500 nm
Source gas: TMG, TMI (trimethylindium), NH ₃ , SiH ₄
Si doping concentration: 1.5 × 10 ¹⁹ cm ⁻³
Carrier gas: Nitrogen Pressure: 300 Torr
Growth temperature: 830 ° C

Growth conditions for n-type GaN layer 22 Film thickness: 170 nm
Si doping concentration: 1.5 × 10 ¹⁹ cm ⁻³
Source gas: TMG, NH ₃ , SiH ₄
Carrier gas: Hydrogen Pressure: 100 Torr
Growth temperature: 1040 ° C

Growth conditions for MQW active layer 24 Film thickness: 83 nm
Number of layers: 5 well layers, 7 barrier layers Well layer 21: In _0.16 Ga _0.84 N
Film thickness: 2.2nm
Dope concentration: undoped Source gas: TEG (triethylgallium), TMI, NH ₃
Carrier gas: Nitrogen Pressure: 300 Torr
Growth temperature: T2 (described later)
Barrier layer 23: GaN
Film thickness: 12nm
Si doping concentration: 5 × 10 ¹⁷ cm ⁻³
Source gas: TEG, NH ₃
Carrier gas: Nitrogen Pressure: 300 Torr
Growth temperature: T1 (described later).
In the growth from the barrier layer 23 to the well layer 21, the supply of the source gas into the growth furnace is stopped after the barrier layer 23 is grown. After that, while supplying the carrier gas into the growth furnace, the process waits without supplying the source gas until the growth temperature of the well layer 21 is reached.

Growth conditions of p-type GaN layer 26 Film thickness: 200 nm
Mg doping concentration: 4 × 10 ¹⁹ cm ⁻³
Source gas: TMG, NH ₃ , Cp ₂ Mg (biscyclopentadienyl magnesium)
Carrier gas: Hydrogen Pressure: 200 Torr
Growth temperature: 975 ° C

  As shown in FIG. 2, a region for forming the n-type electrode 30 is selectively dry-etched up to the n-type InGaN contact layer 20 to form a groove. A p-type electrode 28 made of NiAu is formed on a part of the p-type GaN layer 26 using a vapor deposition method so as to be electrically connected to the p-type GaN layer 26. Annealing is performed at 500 ° C. in the atmosphere to form an alloy with the p-type GaN layer 26. An n-type electrode 30 made of Ta / Al / Pt is formed from below on a part of the bottom surface of the groove so as to be electrically connected to the n-type InGaN contact layer 20 by vapor deposition. Annealing is performed at 500 ° C. in the atmosphere to form an alloy with the n-type InGaN contact layer 20. Thus, the configuration of FIG. 2 is completed. Thereafter, a protective film (not shown) made of silicon oxide and an electrode pad (not shown) connected to the p-type electrode 28 and the n-type electrode 30 are formed by a known method.

  The substrate 10 is ground to a thickness of 100 μm. Using the scribe method, the wafer is divided from the back surface of the substrate 10 and divided into chips of, for example, about 350 μm × 350 μm. After that, it is mounted on the package. Thus, the LED according to the example is completed. The p-type electrode 28 and the n-type electrode 30 may be made of ITO (indium tin oxide) or the like.

  FIG. 3 is a diagram showing the growth temperatures of the n-type GaN layer 22, the active layer 24, and the p-type GaN layer 26 with respect to time. The number of barrier layers 23 and well layers 21 in the active layer 24 is omitted from the total number described above. As shown in FIG. 3, when forming the MQW active layer 24, after forming the well layer 21, the barrier layer 23 is formed on the well layer 21 at a growth temperature T1 higher than the growth temperature T2 of the well layer 21. .

Table 1 is a table showing the growth temperature T1 of the barrier layer 23, the growth temperature T2 of the well layer 21, and T1-T2 of the samples 1 to 5 that were prototyped.

  With respect to the LEDs according to Sample 1 to Sample 5, the ESD withstand voltage in the reverse direction was evaluated. For the ESD application, a human body model to which a resistance of 1.5 kΩ and a capacity of 100 pF were added was used to determine whether or not the LED was destroyed after being applied five times. That is, it is determined whether the LED is broken before and after application of the reverse voltage (implemented five times). If the LED is not broken, the reverse voltage is increased. When the LED was destroyed, the voltage was taken as the ESD withstand voltage. In addition, determination of destruction of LED was performed by the fluctuation | variation of the voltage value at the time of confirmation of light emission of LED, and forward direction electricity supply. Table 1 shows the ESD withstand voltage of each sample.

  FIG. 4 is a diagram showing an ESD breakdown voltage with respect to a difference T1-T2 between the growth temperature T1 of the barrier layer 23 and the growth temperature T2 of the well layer 21. In FIG.

  As shown in FIG. 4, when T1-T2 is 130 ° C. or higher, the ESD withstand voltage increases. This is presumably because the crystallinity of the InGaN well layer 21 deteriorates at temperatures below 130 ° C. On the other hand, if T1-T2 is 130 ° C. or higher, the ESD withstand voltage is improved. However, when the growth temperature difference between the well layer 21 and the barrier layer 23 is large, the growth switching time (the standby time from the growth temperature of the well layer 21 to the growth temperature of the barrier layer 23) becomes long. The shorter the switching period of the well layer 21 / barrier layer 23, the more damage caused by the well layer 21 being exposed to the atmosphere in the growth furnace (generally a nitrogen atmosphere) during the switching period (for example, In from the In-containing layer). Detachment) can be reduced. Referring to FIG. 4, the ESD withstand voltage improvement effect is temporarily reduced with T1−T2 peaking at 150 ° C. From this, it is preferable that T1-T2 is less than 150 degreeC from a viewpoint of shortening of a switching period. As mentioned above, the preferable range of T1-T2 is 130 degreeC or more and less than 150 degreeC. Also, referring to FIG. 4, from the viewpoint of ESD withstand voltage, T1-T2 is more preferably 140 ° C. or higher. The growth temperature of the barrier layer 23 is preferably 870 ° C. or less from the viewpoint of avoiding damage caused by heat applied to the well layer 21.

  In the embodiment, the example using the sapphire substrate 10 has been described, but a Si substrate, a SiC substrate, or a GaN substrate may be used. The n-type GaN layer 22 and the p-type GaN layer 26 may be nitride semiconductor layers other than GaN as long as they have a higher refractive index than the active layer 24 and function as a cladding layer. Furthermore, the well layer 21 and the barrier layer 23 may be nitride semiconductor layers other than InGaN and GaN as long as the active layer 24 functions as a light emitting layer. For example, as the combination of the well layer 21 / barrier layer 23, InGaN / GaN, InGaN / InGaN, AlInGaN / AlInGaN, or the like can be employed.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

FIG. 1 is a cross-sectional view illustrating a method for manufacturing an LED according to an embodiment. FIG. 2 is a cross-sectional view of the LED according to the example. FIG. 3 is a diagram showing the growth temperature of the example. FIG. 4 is a diagram showing the ESD withstand voltage of each sample.

Explanation of symbols

10 substrate 12 AlN buffer layer 14 Si doped GaN buffer layer 16 undoped GaN buffer layer 18 n-type GaN intermediate layer 20 n-type InGaN contact layer 21 well layer 22 n-type GaN layer 23 barrier layer 24 active layer 26 p-type GaN layer 28 p Type electrode 30 n-type electrode

Claims (6)

  A step of forming a well layer made of a nitride semiconductor, and a step of forming a barrier layer made of a nitride semiconductor on the well layer at a growth temperature that is 130 ° C. or more and less than 150 ° C. higher than the growth temperature of the well layer; A method for manufacturing a light-emitting element, comprising the step of forming an MQW active layer containing:   2. The method of manufacturing a light emitting device according to claim 1, wherein the growth temperature of the barrier layer is 140 ° C. or more and less than 150 ° C. higher than the growth temperature of the well layer.   2. The method of manufacturing a light emitting device according to claim 1, wherein the well layer / the barrier layer is made of any one of InGaN / GaN, InGaN / InGaN, and AlInGaN / AlInGaN.   The method for manufacturing a light emitting element according to claim 1, wherein the substrate is one of Si, SiC, GaN, and sapphire.   2. The method of manufacturing a light emitting device according to claim 1, wherein the active layer is formed by MOCVD. The method for manufacturing a light emitting device according to claim 1, wherein the growth temperature of the barrier layer is 870 ° C. or less.

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