JP2009238132A - Data processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance a reliability of memory copy processing without degrading performance. <P>SOLUTION: In a processor 102 equipped with an instruction execution unit 102-1 to 102-N which can process multiple instructions simultaneously, memory readout processing is duplicated according to a logic of a software which operates on the processor 102, and determination is made whether both the data is in agreement on the processor 102. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory copy register file, a data processing apparatus, a memory copy method, and a program for executing the method.

  Memory copy processing is widely performed in general data processing apparatuses.

  The memory copy process is a process of transferring target data from a memory copy source to a memory copy destination via a processor. In particular, in an input / output processing device having a high specific gravity for data transfer processing, most of the processing is this memory copy processing, and it is extremely important to improve the reliability of this memory copy processing.

  As an example of an apparatus for improving the reliability of the memory copy process, there is a duplex memory system described in Japanese Patent Laid-Open No. 8-16484 (Patent Document 1).

  This dual memory system includes a dual CPU bus, system bus control device, system bus and memory device, and each of the CPU bus, system bus control device, system bus and memory device has a data comparison circuit. I have. In each of these comparison circuits, a check is made as to whether or not the duplicated data match each other.

  Japanese Patent Laid-Open No. 56-9828 (Patent Document 2) discloses that when data is transferred from the keyboard to the keyboard control device, the same data is transferred from the keyboard to the keyboard control device at least twice, and the two transferred data are transferred. We have proposed a data transfer reading method that makes data valid when the data match.

JP-A-8-328888 (Patent Document 3) executes a processing program in the first processing apparatus, then executes a processing program for performing the same processing in the second processing apparatus, and outputs both output data. In comparison, a software duplication processing device that outputs output data via an output device only when they match is proposed.
JP-A-8-16484 Japanese Patent Laid-Open No. 56-9828 JP-A-8-328888

  In the duplex memory system described in JP-A-8-16484 (Patent Document 1), it is necessary to perform duplex processing in each of the CPU bus, the system bus control device, the system bus, and the memory device. There was a problem that the amount of hardware would become very large.

  The data transfer reading method described in Japanese Patent Application Laid-Open No. 56-9828 (Patent Document 2) relates only to reading of data from the keyboard to the keyboard control device. There is a problem that it is difficult to apply to memory copy processing. In addition, there is a problem that the performance is greatly reduced.

  In addition, according to the software duplex processing apparatus described in Japanese Patent Laid-Open No. 8-328888 (Patent Document 3), the same processing by software must be repeated twice, so that the data processing amount increases. There was a problem that could not be avoided. In addition, there is a problem that the performance is greatly reduced.

  It is an object of the present invention to provide a memory copy register file, a data processing apparatus, a memory copy method, and a program for executing the method that solve the above-described problems.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided a memory copy register file for copying data stored in a copy source from the copy source to a copy destination. A first register and a second register for storing addresses, a third register for storing the copy destination address, a fourth register for storing the number of data transfer cycles, and one cycle of the data The fifth register for storing the transfer data length in the first register, the sixth register for storing the data read via the address stored in the first register, and the second register. A seventh register for storing data read via the address; data stored in the sixth register; and the seventh register. And an eighth register for storing an exclusive OR with the data stored in the data, and a logical sum of the exclusive OR stored in the eighth register and the value stored in the register. And a register file comprising a ninth register.

  Furthermore, the present invention provides, as a second aspect, a processor connected to the register file, including the register file described above, and at least two instruction execution units each capable of executing instructions simultaneously, and the processor And a memory connected to the data processing device.

  Furthermore, the present invention provides, as a third aspect, in the above register file, using the addresses stored in the first register and the second register, the sixth register and the seventh register. The first process of executing two memory loads for storing the data read from the copy source in the register, and the exclusive of the data stored in the sixth register and the data stored in the seventh register A second step of storing a logical sum in the eighth register; and a logical sum of the exclusive logical sum stored in the eighth register and the value stored in the ninth register. A third process for storing in the register and a memory store for storing the data stored in the sixth register in the copy destination using the address stored in the third register. It provides a way to copy the steps of the data stored in the copy source comprising the copy destination from the copy source.

  Furthermore, the present invention provides, as a fourth aspect, a program for causing a computer to execute a method of copying data stored in a copy source from the copy source to the copy destination in the register file. The processing performed by the program uses the addresses stored in the first register and the second register to store the data read from the copy source in the sixth register and the seventh register. A first process for executing the two memory loads, and an exclusive OR of the data stored in the sixth register and the data stored in the seventh register is stored in the eighth register. And the logical sum of the exclusive OR stored in the eighth register and the value stored in the ninth register is stored in the ninth register. And a fourth process for executing a memory store for storing the data stored in the sixth register in the copy destination using the address stored in the third register. Provide a program that consists of

  The present invention has the following effects.

  The first effect is that, in the memory copy process, memory reading is duplicated and it is determined whether or not both data match on the processor, so that data corruption is prevented and the reliability of the memory copy process is improved. It is possible to improve.

  The second effect is that, in the memory copy process, the memory copy source address management register (first register and second register) and the memory copy destination address management register (third register) are terminated. Since it is determined whether or not the stored value matches the final address calculated in advance, address corruption during the memory copy process can be prevented, and the reliability of the memory copy process can be improved. .

  The third effect is that the memory copy process is executed by software on a processor capable of processing a plurality of instructions at the same time. Therefore, special hardware for executing the memory copy process is not required, and the memory copy process is inexpensive. The process can be realized.

  The fourth effect is that the memory copy process is executed by software on a processor capable of simultaneously processing a plurality of instructions. Therefore, the memory copy process by other means, for example, the same process is executed twice in series. Compared with the memory copy process for confirming the coincidence of results, there is no performance degradation.

  As described above, according to the present invention, in a processor having an instruction execution unit capable of simultaneously processing a plurality of instructions, memory read processing is duplexed according to the logic of software operating on the processor, and both of the processors are executed on the processor. By determining whether or not the data match, it is possible to improve the reliability of the memory copy process without degrading the performance.

(First embodiment)
FIG. 1 is a block diagram showing a hardware configuration of a data processing apparatus 100 including a register file 101 according to the first embodiment of the present invention.

  A data processing device 100 shown in FIG. 1 includes a register file 101 according to the first embodiment of the present invention, a processor 102 connected to the register file 101, a memory 103 connected to the processor 102, It is composed of

  The memory 103 is a memory that functions as a main storage device in the data processing apparatus 100.

  The processor 102 includes N (N is an integer of 2 or more) instruction execution units 102-1 to 102-N, each of which can execute instructions simultaneously.

  The processor 102 executes an instruction specified by a software program in the data processing apparatus 100.

  FIG. 2 is a block diagram showing the structure of the register file 101 according to the first embodiment of the present invention.

  The register file 101 includes various registers. Examples of the register types include general-purpose registers, floating point registers, control registers, and instruction pointers.

  As shown in FIG. 2, the register file 101 includes a first register (master side register) 201 that manages the memory copy source address and a second register (slave side register) that manages the memory copy source address. 202, a third register 203 that manages the address of the memory copy destination, a fourth register 204 that manages the number of cycles in the execution process of the memory copy, and manages the data length per cycle, that is, one cycle The fifth register 205 for storing the byte length to be copied in step 6, the sixth register (master side register) for storing the memory copy data, and the seventh register (slave side register) for storing the memory copy data ), An eighth register 208 for storing an exclusive OR operation result, and an OR operation result A ninth register 209 to pay, and a.

  The register file 101 has two registers for managing the memory copy source address, ie, the first register 201 as the master-side register and the second register as the slave-side register, in order to duplicate the memory reading. 202.

  As will be described later, “1” or “8” is stored in the fifth register 205.

  Similar to the case of the first register 201 and the second register 202, the register file 101 has two registers as the registers for storing the memory copy data, that is, as the master side register in order to duplicate the reading of the memory. The sixth register 206 and a seventh register 207 as a slave side register are provided.

  The eighth register 208 and the ninth register 209 are used for duplex checking of data read from the memory.

  FIG. 3 is a flowchart of a memory copy start process in the data processing apparatus 100 including the register file 101 according to the present embodiment.

  Hereinafter, a memory copy start process in the data processing apparatus 100 will be described with reference to FIG.

  First, the first address of the memory copy source is stored in the first register 201 (step S301).

  Next, the start address of the memory copy source is stored in the second register 202 (step S302).

  Next, the start address of the memory copy destination is stored in the third register 203 (step S303).

  Next, the number of memory copy cycles is stored in the fourth register 204 (step S304).

  Next, the data length of one cycle of memory copy is stored in the fifth register 205 (step S305).

  Next, zero is stored in the ninth register 209 (step S306). That is, the error display is cleared.

  FIG. 4 is a flowchart of the memory copy execution process in the data processing apparatus 100 including the register file 101 according to the present embodiment.

  Each step shown in FIG. 4 is executed after the step shown in FIG.

  Hereinafter, a memory copy execution process in the data processing apparatus 100 will be described with reference to FIG.

  First, the memory data designated by the address stored in the first register 201 is read, and the read memory data is stored in the sixth register 206 (step S401).

  The memory data designated by the address stored in the second register 202 is read, and the read memory data is stored in the seventh register 207 (step S402).

  Reading of memory data designated by the address stored in the first register 201 (step S401), reading of memory data designated by the address stored in the second register 202 (step S402), Are done in parallel. That is, these two steps S401 and S402 may be executed in succession or simultaneously.

  The addresses stored in the first register 201 and the second register 202 are both the top addresses of the memory copy source (steps S301 and S302 in FIG. 3), and are the same address. Therefore, the memory data stored in the sixth register 206 and the seventh register 207 is the same unless a hardware failure occurs.

  Next, an exclusive OR operation of the memory data stored in the sixth register 206 and the memory data stored in the seventh register 207 is performed, and the calculation result is stored in the eighth register 208 (step S403).

  If the data stored in the sixth register 206 and the contents of the data stored in the seventh register 207 match, the operation result of the exclusive OR operation is zero. The result is non-zero.

  Next, an OR operation is performed on the operation result stored in the eighth register 208 and the data stored in the ninth register 209 (zero in the first stage), and the operation result is stored in the ninth register 209. (Step S404).

  Therefore, in the memory copy execution process, if there is even a mismatch between the contents of the data stored in the sixth register 206 and the data stored in the seventh register 207, the ninth The content of the register 209 is non-zero.

  On the other hand, if there has never been a mismatch between the contents of the data stored in the sixth register 206 and the data stored in the seventh register, the contents of the ninth register 209 are zero at the end of the memory copy. It becomes.

  Next, the memory data stored in the sixth register 206 is stored in the memory area designated by the address stored in the third register 203 (step S405).

  Next, the data length of one cycle of the memory copy stored in the fifth register 205 is added to the addresses stored in the first register 201, the second register 202, and the third register 203, respectively. The addition result is stored again in the first register 201, the second register 202, and the third register 203 (step S406).

  In the present embodiment, the value stored in the fifth register 205 is set to “1” or “8”. When the value stored in the fifth register 205 is “1”, the corresponding memory copy is processed by 1 byte per cycle, and the value stored in the fifth register 205 is “8”. In some cases, the corresponding memory copy is 8 bytes per cycle.

  Furthermore, “1” is subtracted from the number of memory copy cycles stored in the fourth register 204, and the subtraction result is stored again in the fourth register 204 (step S406).

  Next, it is confirmed whether or not the number of memory copy cycles stored in the fourth register 204 is zero (step S407).

  If the number of memory copy cycles is zero (YES in step S407), the memory copy execution process ends, and the process proceeds to a memory copy end process described later (FIG. 5).

  If the memory copy cycle number is non-zero (NO in step S407), the memory copy execution process is continued. That is, the processes in steps S401 and S402 to S407 are executed again.

  FIG. 5 is a flowchart of a memory copy end process in the data processing apparatus 100 including the register file 101 according to the present embodiment.

  Each step shown in FIG. 5 is executed after the step shown in FIG.

  Hereinafter, the memory copy end process in the data processing apparatus 100 will be described with reference to FIG.

  As will be described below, the end process of the memory copy process is started when the number of cycles stored in the fourth register 204 becomes zero, and the last value stored in the ninth register 209 is zero. If it is not zero, an error is detected.

  First, it is determined whether or not the content stored in the first register 201 matches the content stored in the second register 202 (step S501).

  If the contents stored in the first register 201 and the contents stored in the second register 202 do not match (NO in step S501), a hardware failure has occurred and the memory copy has occurred. Indicates that the process is not reliable. For this reason, failure processing is performed (step S505).

  If the content stored in the first register 201 matches the content stored in the second register 202 (YES in step S501), the content stored in the ninth register 209 Whether or not is zero is determined (step S504).

  If the content stored in the ninth register 209 is not zero (NO in step S504), it indicates that a hardware failure has occurred in the memory read redundancy check. For this reason, failure processing is performed (step S505).

  If the content stored in the ninth register 209 is zero (YES in step S504), the memory copy process ends normally.

  FIG. 6 is a time chart when a memory copy pipeline process is performed in the data processing apparatus 100 including the register file 101 according to the present embodiment.

  The time chart shown in FIG. 6 includes items 601 to 607.

  An item 601 indicates a machine cycle. In FIG. 6, machine cycles 1 to 10 are shown, and machine cycles 11 and after are omitted.

  Item 602 indicates the update status of the contents of the fourth register 204 executed in step S406 (FIG. 4).

  In the present embodiment, the initial value is set to “7”. That is, in the memory copy execution process shown in FIG. 4, a process of 7 cycles is performed.

  An item 603 indicates the number of executions of the memory load (master side) executed in step S401 (FIG. 4).

  An item 604 indicates the number of executions of the memory load (slave side) executed in step S402 (FIG. 4).

  As is clear from the comparison between the item 603 and the item 604, the same number of executions of memory loads are performed in the same machine cycle.

  An item 605 indicates the number of executions of the exclusive OR operation executed in step S403 (FIG. 4).

  An item 606 indicates the number of executions of the logical sum operation executed in step S404 (FIG. 4).

  An item 607 indicates the number of memory stores executed in step S405 (FIG. 4).

  In the flowchart shown in FIG. 4, the actual execution order is changed for easy understanding logically. In the case of corresponding to the machine cycle, in the execution process of the memory copy, pipeline processing is performed as shown in the time chart shown in FIG.

  In items 603 to 607, the same number of execution times corresponds to the same memory data.

  For example, when focusing on the first execution number, “first time” corresponds to items 603 and 604 corresponding to the machine cycle “1”, items 605 and 607 corresponding to the machine cycle “7”, and machine cycle “8”. This is shown in item 606. That is, in the items 603 and 604 corresponding to the machine cycle “1”, the data read from the memory by the first memory load is the first exclusive OR operation of the item 605 corresponding to the machine cycle “7”. In the first OR operation of the item 606 corresponding to the machine cycle “8” and used in the first memory store of the item 607, the first exclusive OR of the item 605 corresponding to the machine cycle “7” is used. The result of the operation is used.

  Similarly, paying attention to the second execution number, “second” corresponds to items 603 and 604 corresponding to machine cycle “2”, items 605 and 607 corresponding to machine cycle “8”, and machine cycle “9”. A corresponding item 606 is shown. That is, in the items 603 and 604 corresponding to the machine cycle “2”, the data read from the memory by the second memory load is the second exclusive OR operation of the item 605 corresponding to the machine cycle “8”. In the second OR operation of the item 606 corresponding to the machine cycle “9” used in the second memory store of the item 607, the second exclusive OR of the item 605 corresponding to the machine cycle “8” is used. The result of the operation is used.

  The same applies to the “third” to “seventh” execution times.

  As described above, the number of executions of memory load (master side), the number of executions of memory load (slave side), the number of executions of exclusive OR operations, the number of executions of OR operations, and the number of memory stores are machine cycle numbers. It is implemented corresponding to.

  In this way, by utilizing the N instruction execution units 102-1 to 102-N, each capable of executing instructions simultaneously, it is possible to perform pipeline processing of memory copy as shown in FIG. Become.

  In the execution process of the memory copy process, items 602 to 607 are processed in parallel by different instruction execution units.

  FIG. 7 is a flowchart when performing memory copy processing classification.

  In general, there is no limitation on the data length of the memory copy, the memory copy source address, and the memory copy destination address. Therefore, if the data length of one cycle is set to 1 byte and a memory copy process in units of 1 byte is executed, no logical contradiction occurs. However, if a memory copy process in units of 1 byte is executed in all cases, performance is improved. Is expected to occur.

  In order to avoid such performance problems, the memory copy processing is classified according to the flowchart shown in FIG.

  First, it is determined whether or not the data length of the memory copy is 8 bytes or more (step S701).

  When the memory copy data length is less than 8 bytes (NO in step S701), the memory copy cycle number is set as the memory copy data length (step S702).

  Next, the data length of one cycle of memory copy is set to 1 byte (step S703).

  Next, a memory copy process in units of 1 byte is executed (step S704).

  Thereby, the memory copy process ends.

  If the data length of the memory copy is 8 bytes or more (YES in step S701), the memory copy cycle number is the quotient of equation (1), and the data length of the next memory copy is the remainder of equation (1). (Step S705).

  Memory copy data length ÷ 8 (1)

  Next, the data length of one cycle of memory copy is set to 8 bytes (step S706).

  Next, a memory copy process in units of 8 bytes is executed (step S707).

  Next, it is determined whether or not the data length (step S705) of the next memory copy set as the remainder of the equation (1) is zero (step S708).

  If the data length of the next memory copy is zero (YES in step S708), the memory copy process ends.

  If the data length of the next memory copy is not zero (NO in step S708), the memory copy cycle number is set as the data length of the next memory copy (step S709).

  Next, the data length of one cycle of memory copy is set to 1 byte (step S710).

  Next, a memory copy process in units of 1 byte is executed (step S711).

  Thereby, the memory copy process ends.

  Specifically, the one-byte unit memory copy process (step S704) is executed according to the flowcharts shown in FIGS.

  Further, the memory copy process in units of 8 bytes (step S707) is specifically executed according to the flowcharts shown in FIGS.

  Further, the memory copy processing in units of 1 byte (step S711) is specifically executed according to the flowcharts shown in FIGS.

  The number of memory copy cycles (step S304 in FIG. 3) and the data length of one cycle of memory copy (step S305 in FIG. 3) are determined by the steps shown in the flowchart of FIG.

  As described above, according to the data processing apparatus 100 including the register file 101 according to the present embodiment, in memory copy processing, memory reading is duplicated, and whether these two data match on the processor 102 or not. Therefore, it is possible to prevent data corruption and to improve the reliability of the memory copy process.

(Modification of the first embodiment)
FIG. 8 is a block diagram of a data processing device 150 that is a modification of the data processing device 100 including the register file 101 according to the first embodiment of the present invention.

  The data processing device 150 according to this modification additionally includes a cache memory 104 as compared with the data processing device 100 according to the first embodiment.

  The cache memory 104 is connected between the processor 102 and the memory 103.

  The cache memory 104 temporarily stores a part of the data stored in the memory 103. Thereby, the access performance from the processor 102 to the memory 103 can be improved.

(Second embodiment)
FIG. 9 is a block diagram showing the structure of the register file 200 according to the second embodiment of the present invention.

  As shown in FIG. 9, the register file 200 according to the present embodiment includes a first register in addition to the first to ninth registers 201 to 209 constituting the register file 101 according to the first embodiment. The tenth register 210 that verifies the address calculation in the 201 and the second register 202 and the eleventh register 211 that verifies the address calculation in the third register 203 are provided.

  The tenth register 210 and the eleventh register 211 are used to verify whether the address calculation in the first register 201, the second register 202, and the third register 203 has been performed correctly.

  The register file 200 according to this embodiment has the same structure as that of the register file 101 according to the first embodiment except that a tenth register 210 and an eleventh register 211 are additionally provided. In addition, the data processing apparatus including the register file 200 according to the present embodiment has the same structure as the data processing apparatus 100 including the register file 101 according to the first embodiment. For this reason, the same reference numerals as those in the first embodiment are used for the same components as those in the first embodiment.

  FIG. 10 is a flowchart of the memory copy start process in the data processing apparatus including the register file 200 according to the present embodiment.

  Hereinafter, a memory copy start process in the data processing apparatus including the register file 200 according to the present embodiment will be described with reference to FIG.

  Each step from step S301 to step S306 is performed in the same manner as in the first embodiment.

  Subsequent to step S306, the memory copy source address at the end of the memory copy is stored in the tenth register 210 (step S307).

  Specifically, as shown in Expression (2), the product of the data stored in the fourth register 204 and the data stored in the fifth register 205 and the first register 201 The sum with the stored data is stored in the tenth register 210.

[Tenth register] =
[First register] + [fourth register] × [fifth register] (2)

  Next, the memory copy destination address at the end of the memory copy is stored in the eleventh register 211 (step S308).

  Specifically, as shown in Expression (3), the product of the data stored in the fourth register 204 and the data stored in the fifth register 205 and the third register 203 are stored. The sum with the stored data is stored in the eleventh register 211.

[Eleventh register] =
[Third register] + [fourth register] × [fifth register] (3)

  The tenth register 210 and the eleventh register 211 are used for checking whether or not the address update is correctly performed at the end of the memory copy.

  FIG. 11 is a flowchart of the memory copy end process in the data processing apparatus including the register file 200 according to the present embodiment.

  Each step shown in FIG. 11 is executed after the step shown in FIG.

  Hereinafter, with reference to FIG. 11, a memory copy end process in the data processing apparatus including the register file 200 according to the present embodiment will be described.

  First, it is determined whether or not the content stored in the first register 201 matches the content stored in the second register 202 (step S501).

  If the contents stored in the first register 201 and the contents stored in the second register 202 do not match (NO in step S501), a hardware failure has occurred and the memory copy has occurred. Indicates that the process is not reliable. For this reason, failure processing is performed (step S505).

  If the content stored in the first register 201 matches the content stored in the second register 202 (YES in step S501), the content stored in the second register 202 And whether the content stored in the tenth register 210 matches (step S502).

  If the contents stored in the second register 202 do not match the contents stored in the tenth register 210 (NO in step S502), a hardware failure has occurred and the memory copy has occurred. Indicates that the process is not reliable. For this reason, failure processing is performed (step S505).

  If the content stored in the second register 202 matches the content stored in the tenth register 210 (YES in step S502), the content stored in the third register 203 And whether or not the contents stored in the eleventh register 211 match (step S503).

  If the contents stored in the third register 203 and the contents stored in the eleventh register 211 do not match (NO in step S503), a hardware failure has occurred and the memory copy has occurred. Indicates that the process is not reliable. For this reason, failure processing is performed (step S505).

  When the content stored in the third register 203 matches the content stored in the eleventh register 211 (YES in step S503), the content stored in the ninth register 209 Whether or not is zero is determined (step S504).

  If the content stored in the ninth register 209 is not zero (NO in step S504), it indicates that a hardware failure has occurred in the memory read redundancy check. For this reason, failure processing is performed (step S505).

  If the content stored in the ninth register 209 is zero (YES in step S504), the memory copy process ends normally.

  As described above, according to the register file 200 according to this embodiment, the tenth register 210 and the eleventh register that verify the address calculation in the first register 201, the second register 202, and the third register 203. Therefore, the reliability of the memory copy process can be improved.

It is a block diagram which shows the hardware constitutions of the data processor provided with the register file which concerns on 1st embodiment of this invention. It is a block diagram which shows the structure of the register file which concerns on 1st embodiment of this invention. It is a flowchart of the memory copy start process in a data processor provided with the register file which concerns on 1st embodiment of this invention. It is a flowchart of the execution process of memory copy in a data processor provided with the register file which concerns on 1st embodiment of this invention. 4 is a flowchart of a memory copy end process in the data processing apparatus including the register file according to the first embodiment of the present invention. It is a time chart in the case of performing a memory copy pipeline process in the data processing apparatus including the register file according to the first embodiment of the present invention. It is a flowchart at the time of performing the processing classification of a memory copy in a data processor provided with a register file concerning a first embodiment of the present invention. It is a block diagram of a data processor which is a modification of a data processor provided with a register file concerning a first embodiment of the present invention. It is a block diagram which shows the structure of the register file which concerns on 2nd embodiment of this invention. It is a flowchart of the memory copy start process in a data processing apparatus provided with the register file which concerns on 2nd embodiment of this invention. It is a flowchart of the end process of memory copy in a data processor provided with the register file which concerns on 2nd embodiment of this invention.

Explanation of symbols

100 Data processing apparatus 101 including register file according to first embodiment Register file 102 according to first embodiment Processor 102-1 to 102-N Instruction execution unit 103 Memory 104 Cache memory 150 Data according to modification Processing device 200 Register file according to second embodiment

Claims (16)

A memory copy register file for copying data stored in a copy source from the copy source to a copy destination,
A first register and a second register for respectively storing the copy source addresses;
A third register for storing the address of the copy destination;
A fourth register for storing the number of data transfer cycles;
A fifth register for storing a transfer data length in one cycle of the data;
A sixth register for storing data read via the address stored in the first register;
A seventh register for storing data read via the address stored in the second register;
An eighth register for storing an exclusive OR of the data stored in the sixth register and the data stored in the seventh register;
A ninth register for storing a logical sum of the exclusive OR stored in the eighth register and the value stored in the register;
A register file with The register file according to claim 1, further comprising a tenth register for verifying whether address calculation in the first register and the second register is correctly performed. 3. The register file according to claim 1, further comprising an eleventh register for verifying whether the address calculation in the third register is correctly performed. A register file as claimed in any one of claims 1 to 3;
A processor comprising at least two instruction execution units each capable of executing instructions simultaneously and connected to the register file;
A memory connected to the processor;
A data processing apparatus comprising: The data processing apparatus according to claim 4, further comprising a cache memory connected between the processor and the memory and temporarily storing a part of data stored in the memory. Number of executions of memory load in the first register, number of executions of memory load in the second register, number of executions of exclusive OR operation in the eighth register, and execution of OR operation in the ninth register 6. The data processing apparatus according to claim 4, wherein the number of times is executed corresponding to a machine cycle number. In the register file according to any one of claims 1 to 3,
Two memory loads for storing data read from the copy source in the sixth register and the seventh register are executed using the addresses stored in the first register and the second register. The first process and
A second step of storing an exclusive OR of the data stored in the sixth register and the data stored in the seventh register in the eighth register;
A third step of storing a logical sum of the exclusive OR stored in the eighth register and a value stored in the ninth register in the ninth register;
A fourth step of executing a memory store for storing the data stored in the sixth register in the copy destination using the address stored in the third register;
A method of copying data stored in a copy source comprising the copy source to the copy destination. The addresses stored in the first register, the second register, and the third register are added by the data length stored in the copy destination in one cycle of the first process to the fourth process. And the fifth process
A sixth step of subtracting 1 from the number of cycles stored in the fourth register;
A seventh process of repeating the first to sixth processes until the number of cycles stored in the fourth register becomes zero by subtraction in the sixth process;
Further comprising
The method according to claim 7, wherein the fifth to seventh processes are performed after the fourth process. An eighth step of storing the first address of the memory copy source in the first register;
A ninth step of storing the start address of the memory copy source in the second register;
A tenth step of storing the start address of the memory copy destination in the third register;
An eleventh step of storing the data length of one cycle of memory copy in the fifth register;
A twelfth process of storing zero in the ninth register;
Further comprising
The method according to claim 7 or 8, wherein the ninth to twelfth processes are performed before the first process. A thirteenth process of storing the number of memory copy cycles in the fourth register, wherein the thirteenth process is executed between the tenth process and the eleventh process; The method according to claim 9. The method according to any one of claims 7 to 10, further comprising verifying whether the address calculation in the first register and the second register is correctly performed. 12. The method according to claim 7, further comprising verifying whether the address calculation in the third register is correctly performed. The data length is
Determining whether or not the data length of the memory copy is greater than or equal to N bytes, which is a predetermined number of bytes;
When the memory copy data length is less than N bytes, the process of setting the memory copy cycle number to the memory copy data length;
The process of setting the data length of one cycle of memory copy to 1 byte;
The method according to claim 9, wherein the method is defined by: The data length is
Determining whether or not the data length of the memory copy is greater than or equal to N bytes, which is a predetermined number of bytes;
When the data length of the memory copy is N bytes or more, the process of setting the number of memory copy cycles as the quotient of equation (1) and the data length of the next memory copy as the remainder of equation (1);
Memory copy data length ÷ N (1)
Setting the data length of one cycle of memory copy to N bytes;
Is defined by
A process of executing a memory copy process in units of N bytes;
Determining whether the data length of the next memory copy is zero,
The process of ending the memory copy process when the data length of the next memory copy is zero,
The method according to claim 7, further comprising: The data length is
Determining whether or not the data length of the memory copy is greater than or equal to N bytes, which is a predetermined number of bytes;
When the data length of the memory copy is N bytes or more, the process of setting the number of memory copy cycles as the quotient of equation (1) and the data length of the next memory copy as the remainder of equation (1);
Memory copy data length ÷ N (1)
Setting the data length of one cycle of memory copy to N bytes;
A process of executing a memory copy process in units of N bytes;
Determining whether the data length of the next memory copy is zero,
When the data length of the next memory copy is not zero, the process of setting the number of memory copy cycles to the data length of the next memory copy,
The process of setting the data length of one cycle of memory copy to 1 byte;
The method according to claim 7, wherein the method is defined by: A program for causing a computer to execute a method of copying data stored in a copy source from the copy source to the copy destination in the register file according to any one of claims 1 to 3. ,
The processing performed by the program is as follows:
Two memory loads for storing data read from the copy source in the sixth register and the seventh register are executed using the addresses stored in the first register and the second register. The first process,
A second process of storing an exclusive OR of the data stored in the sixth register and the data stored in the seventh register in the eighth register;
A third process of storing a logical sum of the exclusive OR stored in the eighth register and a value stored in the ninth register in the ninth register;
A fourth process for executing a memory store for storing the data stored in the sixth register in the copy destination using the address stored in the third register;
A program that consists of:

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