JP2009223968A - Nonvolatile semiconductor storage device - Google Patents

Abstract

The present invention provides means for preventing re-writing to a storage element in which storage information “0” is once written to prevent erroneous reading in a reading operation.
In a non-volatile semiconductor memory device having two memory elements in which a first silicon oxide film, a charge storage nitride film, and a second silicon oxide film are stacked on both sides of a gate electrode, the charge storage nitridation is performed. When the charge is injected into the film divided into a plurality of times, the write voltage is set so as to increase stepwise from the initial write voltage to the set write voltage. The target current for confirming the holding state is set to increase stepwise from the initial target current to the set target current with a slope larger than the slope at which the cell current increases due to the change in the charge holding state. When injecting charge into the storage element, if the cell current exceeds the target current, the charge is injected into the storage element at the write voltage, and if the cell current is below the target current, the charge is injected into the storage element. I will not do it To.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory device having memory elements using charge storage nitride films on both sides of a gate electrode.

  As a conventional nonvolatile semiconductor memory device, a MONOS (Metal Oxide Nitride Oxide Substrate) type memory cell includes a gate electrode disposed opposite to a semiconductor substrate across a gate insulating film formed on a P-type semiconductor substrate, Two memory elements formed by laminating a first silicon oxide film, a charge storage nitride film, and a second silicon oxide film on both side surfaces of the gate electrode, and a semiconductor substrate under these two memory elements And a source layer and a drain layer, each of which is an N-type high-concentration diffusion layer, formed on a semiconductor substrate opposite to the gate electrode of the LDD layer, respectively, and an LDD (Lightly Doped Drain) layer formed therein. When memory information “0” is written in an element, for example, a memory element on the drain side, a gate electrode and a drain layer A positive voltage is applied, the source layer is set to the ground voltage, hot electrons generated in the drain side LDD layer are injected into the charge storage nitride film of the drain side memory element, and writing to the drain side memory element is performed. When reading storage information of the storage element on the side, a positive voltage is applied to the gate electrode and the source layer, and the drain layer is set to the ground voltage, and the storage element under the storage element by electrons held in the charge storage nitride film of the storage element Utilizing the increase in resistance of the LDD layer, when the stored information is “1”, the cell current flowing between the source and the drain is relatively high, and when the stored information is “0”, the cell current is relatively low. Is used to read the memory information written in the memory element on the drain side (see, for example, Patent Document 1).

In addition, in a floating gate electrode type memory cell, when writing one of quaternary data to be written to the memory cell, for example, “10”, a memory cell that is easy to write among the memory cells is “10” by one writing. If the memory cell voltage has not reached the target threshold voltage by checking the voltage of the memory cell written after the initial gate voltage so that the target threshold voltage becomes “ In some cases, the programming is performed by increasing the number of times, and when the voltage of the confirmed memory cell reaches the target threshold voltage, the verification programming is performed to terminate the programming (see, for example, Patent Document 2).
Japanese Patent Laying-Open No. 2005-64295 (paragraphs 0019-0022 and 0029-0037, FIG. 1) JP 2006-172681 A (mainly paragraphs 0031-0032, FIGS. 4 and 5)

  In the above-described MONOS type memory cell, for example, when the storage information “0” is written in the storage element on the drain side, that is, when electrons are injected into the charge storage nitride film, theoretically, Although there should be no effect on the source-side storage element located on the opposite side across the gate electrode, the storage information of the source-side storage element is actually “1”, that is, electrons are injected into the charge storage nitride film. If this is not the case (hereinafter, this state is also referred to as “unwritten”), electrons are present in the charge storage nitride film of the source storage element under the influence of the electrons injected into the drain storage element. Thus, there is a phenomenon that the cell current when reading the storage information of the storage element on the source side decreases, and as a result, the separation width W becomes narrow.

  However, in the technique of Patent Document 1, when the storage information “0” is written in the storage element on the drain side, a positive voltage is applied to the gate electrode and the drain layer, the source layer is grounded, and the injection is performed once. In the case where the memory element that injects electrons into the charge storage nitride film of the storage element on the drain side is written by one-bit completion type, the memory element that injects electrons due to manufacturing variation is an easily writable memory element. Indicates that the write gate voltage is relatively excessive, and there are a large number of electrons in the unwritten memory element located on the opposite side, and as shown as a bar graph with hatching in FIG. The separation width W between the distribution of the cell current on the write side where the information is “0” and the distribution of the cell current on the non-write side where the storage information is “1” is narrowed. That outbreak may occur There is a problem.

Here, the distribution of the initial state on the unwritten side shown as a white bar graph in FIG. 11 shows the manufacturing in the case where the writing process is not performed (immediately after manufacturing or the erased state of the storage elements of all the memory cells). It shows the cell current distribution of each memory element caused by the variation.
Further, the separation width W is assumed when the distribution form on the writing side and the non-writing side are assumed to be normal distributions, and the standard deviation obtained by multiplying the average value shown in the table in the figure by a predetermined magnification is added or subtracted. The current value of the difference between the lower limit value of the cell current on the unwritten side and the upper limit value of the cell current on the write side.

  Note that in a floating gate electrode type memory cell, only electrons for setting a threshold voltage (threshold voltage) indicating one of four memory states are injected into one memory cell. Therefore, as shown in Patent Document 2, even if the threshold voltage indicating one storage state varies among the memory cells, the memory element on one side, such as a MONOS type memory cell, may be used. A phenomenon in which the injected electrons affect the memory element on the other side does not occur.

In order to prevent a decrease in the separation width W between the cell current distributions on the write side where the stored information is “0” and the unwritten side where the stored information is “1”, at present, Patent Document 2 The same verify writing as that in the case of the floating gate electrode type memory cell shown in FIG. 2 is performed also in the MONOS type memory cell.
A MONOS type memory cell will be described below.

12 is an explanatory view showing a cross section of a conventional MONOS type memory cell, FIG. 13 is a circuit diagram showing a conventional memory cell array, FIG. 14 is a block diagram showing a conventional control system, and FIG. 15 is an equivalent of the conventional memory cell. It is a circuit diagram which shows a circuit.
In FIG. 12, reference numeral 1 denotes a MONOS type memory cell (hereinafter simply referred to as a memory cell) as a nonvolatile semiconductor memory device, which is a MOSFET (Metal Oxide Field Effect Transistor) type memory cell. nMOS (n-channel MOS) type.

Reference numeral 2 denotes a semiconductor substrate, which is a substrate made of single crystal silicon (Si) diffused with a relatively low concentration of P-type impurities.
Reference numeral 3 denotes a gate electrode, which is an electrode formed by laminating polysilicon on a gate insulating film 4 made of silicon oxide (SiO ₂ ) formed on the semiconductor substrate 2, with the gate insulating film 4 interposed therebetween. Opposed to the semiconductor substrate 2.

Reference numerals 5 and 6 denote high-concentration diffusion layers, which are diffusion layers formed by diffusing relatively high-concentration N-type impurities in the surface layer of the semiconductor substrate 2 spaced from the gate electrodes 3 on both sides of the gate electrode 3, On the semiconductor substrate 2 between the gate electrode 3, LDD layers are formed as low concentration diffusion layers in which N-type impurities are diffused at a relatively low concentration.
In the following description, for the sake of distinction, the high-concentration diffusion layer on the left side in FIG. 12 is referred to as the source layer 5 and the low-concentration diffusion layer is referred to as the LDD layer 5a. The high concentration diffusion layer is referred to as the drain layer 6, and the low concentration diffusion layer is referred to as the LDD layer 6a.

A channel region 7 is a region where a channel of the MOSFET is formed, and is a region on the gate electrode 3 side of the P-type semiconductor substrate 2 between the source layer 5 and the drain layer 6.
Reference numeral 8 denotes a first silicon oxide film which covers the side surface of the gate electrode 3 and the LDD layers 5a and 6a with an L-shaped cross-sectional shape and is made of silicon oxide reaching the end portions of the source layer 5 and the drain layer 6. It is a thin thin insulating film.

Reference numeral 9 denotes a charge storage nitride film (shown by hatching in FIG. 12; the same applies to other drawings), and L-shaped silicon nitride (Si ₃ N ₄ ) laminated on the first silicon oxide film 8. The insulating and dielectric thin film is made of and has a function of accumulating and holding injected charges (electrons in this description).
Reference numeral 10 denotes a second silicon oxide film, which is an insulating film made of sidewall-shaped silicon oxide laminated on the charge storage nitride film 9 and suppresses movement of electrons held in the charge storage nitride film 9. It has a function.

Here, the side wall shape means that the gate electrode 3 is formed when the cross-sectional shape of the second silicon oxide film 10 that is supposed to be rectangular is anisotropic etching or the like in the step of exposing the upper surface of the gate electrode 3. An upper corner portion on the opposite side is cut off, and one corner portion of the rectangle has a circular arc shape or a parabolic shape.
12a, 12b is a storage device, the first silicon oxide film 8 above, the charge storage nitride film 9, _SiO 2 _· Si ₃ formed by laminating a second silicon oxide film 10 in this order N 4 · SiO ₂ The storage element 12a is formed on the LDD layer 5a of the source layer 5 and the storage element 12b is formed on the LDD layer 6a of the drain layer 6, respectively. .

Reference numeral 14 denotes an intermediate insulating film, which is a thick insulating film made of silicon oxide formed on the semiconductor substrate 2 covering the gate electrode 3 and the storage elements 12a and 12b.
A contact plug 15 is formed by embedding a conductive material such as aluminum (Al) or tungsten (W) in a contact hole formed as a through hole reaching the source layer 5 and the drain layer 6 from the upper surface of the intermediate insulating film 14. The conductive plug has a function of electrically connecting the source layer 5 and the drain layer 6 to the bit line BL which is a wiring formed on the intermediate insulating film 14.

  In FIG. 12, the contact plug 15 is illustrated as being formed for each of the source layer 5 and the drain layer 6 of one memory cell 1, but actually, the source layer 5 and the drain layer 6 are formed. Are formed in common with the drain layer 6 and the source layer 5 of each other adjacent memory cell 1, and the contact plug 15 of the drain layer 6 is a source of the other adjacent memory cell 1 (right side in FIG. 12). The contact plug 15 of the source layer 5 also functions as a contact plug of the drain layer 6 of another adjacent memory cell 1 (left side in FIG. 12).

Reference numeral 17 denotes a gate contact, which is a conductive plug formed by embedding a conductive material similar to the contact plug 15 in a contact hole formed as a through hole reaching the gate electrode 3 from the upper surface of the intermediate insulating film 14. The electrode 3 has a function of electrically connecting the word line WL which is a wiring formed on the intermediate insulating film 14.
The memory cell 1 is manufactured as follows.

  That is, a gate insulating film 4 is formed in an active region on the semiconductor substrate 2 by a thermal oxidation method or the like, and a polysilicon film for forming a gate electrode 3 is deposited thereon by a CVD (Chemical Vapor Deposition) method, A gate electrode 3 facing the semiconductor substrate 2 is formed with the gate oxide film 4 sandwiched by photolithography and etching, and a first silicon oxide film 8 is formed on the gate electrode 3 and the like by a thermal oxidation method or a CVD method, and thereafter LDD layers 5 a and 6 a are formed on the semiconductor substrate 2 on both sides of the gate electrode 3 by injecting a low concentration N-type impurity into the upper surface of the semiconductor substrate 2 exposed between the adjacent gate electrodes 3.

  Next, a charge storage nitride film 9 is formed on the first silicon oxide film 8 by the CVD method, a second silicon oxide film 10 is formed thereon by the CVD method, and the second silicon oxide film 10 is formed by etching. After forming the sidewall shape, the source layer 5 connected to the LDD layers 5a and 6a by injecting high concentration N-type impurities into the semiconductor substrate 2 outside the second silicon oxide film 10 on both sides of the gate electrode 3, A drain layer 6 is formed.

  Then, after forming the source layer 5 and the drain layer 6, an intermediate insulating film 14 made of silicon oxide is formed by a CVD method on the semiconductor substrate 2 including the gate electrode 3 and the memory elements 12a and 12b, and by photolithography and etching, A source layer 5, a bit line BL connected to the drain layer 6 via a contact plug 15, and a word line WL connected to the gate electrode 3 via a gate contact 17 are formed on the intermediate insulating film 14.

In this way, a plurality of memory cells 1 are manufactured.
In FIG. 13, reference numeral 20 denotes a memory cell array, in which a plurality of memory cells 1 are arranged in a matrix in M rows and N columns (M and N are integers of 2 or more). Each gate electrode 3 is connected to one word line WL, and the source layer 5 of each column and the drain layer 6 of the adjacent memory cell 1 are connected to one bit line BL.

The memory cell array 20 shown in FIG. 13 is a matrix having a total number of rows M = 256 and a total number of columns N = 16, 256 word lines WL ₀ to WL ₂₅₅ and ₁₆ bit lines BL _{1 to} BL ₁₆ . Is formed.
A column selection circuit 22 is a selection circuit for selecting each bit line BL, and one selection transistor 23 is provided for each bit line BL. Gate SG is connected.

Four selector gates SG shown in FIG. 13 are provided, which are connected to the gates of the select transistors 23 provided for every four bit lines BL, and _four of SG _{1 to} SG 4 are formed. Yes.
In FIG. 14, reference numeral 24 denotes a row selection circuit, which is a selection circuit for selecting each word line WL, and is configured similarly to the column selection circuit.

A bit line power supply circuit 25 generates a voltage to be supplied to each bit line BL of the memory cell array 20.
Reference numeral 26 denotes a read circuit, and a current (cell current Ic) flowing between the source layer 5 and the drain layer 6 of each memory cell 1 in order to determine stored information written in the storage elements 12a and 12b of each memory cell 1. This is a circuit for detecting and reading out.

  A comparison circuit 27 compares the cell current Ic read by the read circuit 26 with the target current Iref generated by the target current generation circuit 28 when the storage information “0” is written in the memory cell array 20. In addition, a determination signal indicating whether the cell current Ic is equal to or less than the target current Iref or exceeds the target current Iref is generated on and off, and is transmitted to the control unit 29.

The target current generating circuit 28 is a circuit for generating a target current Iref to be compared with the cell current Ic read by the reading circuit 26 in the comparison circuit 27. In this description, a target current Iref = 14 μA is set. appear.
The control unit 29 is formed of a microprocessor or the like, and controls each unit by a program stored in its built-in memory to write storage information to the storage elements 12a and 12b of each memory cell 1 of the memory cell array 20, It has a function of executing a read operation, an erase operation, and the like.

  A nonvolatile semiconductor memory device having the above-described memory cell array 20, column selection circuit 22, row selection circuit 24, bit line power supply circuit 25, readout circuit 26, comparison circuit 27, target current generation circuit 28, and control unit 29 is provided. It is formed as a chip before being singulated on a semiconductor wafer together with a non-volatile semiconductor memory device having another similar configuration, and processing such as writing operation of storage information to each memory cell 1 This is performed in cooperation with a storage information writing device 30 as an external control device connected to a terminal (electrode pad) of a chip of each nonvolatile semiconductor device formed on a semiconductor wafer with a probe or the like.

A main control unit 31 of the storage information writing device 30 has a function of executing a writing process and the like in cooperation with the control unit 29 while controlling each unit of the storage information writing device 30.
Reference numeral 32 denotes a storage unit of the storage information writing device 30, which stores a program executed by the main control unit 31, various data such as a storage information table (described later) used therein, processing results by the main control unit 31, and the like.

Reference numeral 34 denotes a variable write voltage generator, and a write voltage as a write voltage applied to the gate electrode 3 of the memory cell 1 during a write operation in response to a write voltage generation command in which a set voltage is written from the main controller 31. The gate voltage Vgw is generated in a stepwise manner depending on the number of writings k.
A read voltage generator 36 generates a read gate voltage Vgr as a read voltage supplied to the gate electrode 3 of the memory cell 1 during a read operation.

In addition, the solid line shown in FIG. 14 shows an internal connection, and a broken line shows an external connection.
In the memory cell 1 described above, each LDD layer 5a, 6a has a resistance value corresponding to the retention state of electrons injected into the charge storage nitride film 9 of the storage elements 12a, 12b, as in the equivalent circuit shown in FIG. The cell current Ic flowing between the source layer 5 and the drain layer 6 is increased or decreased by a change in the resistance value of the resistance change portion (the resistance value increases when the amount of electrons held is large). To do.

Using the increase / decrease in the cell current Ic due to the change in resistance value according to the electron holding state, the storage information “0” (the charge storage nitride film 9 holds a predetermined amount of electrons) in the storage elements 12a and 12b. Storage state) or stored information “1” (empty state in which electrons are not held in the charge storage nitride film 9) can be read out.
Further, the 2-bit memory cell 1 having the storage elements 12a and 12b is one memory cell 1 and, as shown in FIG. 16, "1, 1" (FIG. 16 (a)), "1" , 0 ”(FIG. 16B),“ 0, 1 ”(FIG. 16C), and“ 0, 0 ”(FIG. 16D).

  In such a write operation for writing the storage information “0” to the storage element 12a or 12b, when the storage information “0” is written to the storage element 12b on the drain layer 6 side, as shown in FIG. In addition, a write gate voltage Vgw (= 10 V) is applied to the word line WL connected to the gate electrode 3, the bit line BL connected to the source layer 5 is set to 0 V, and 6 V is applied to the bit line BL connected to the drain layer 6. When applied, hot electrons (electrons) generated in the LDD layer 6a are injected into the charge storage nitride film 9 of the storage element 12b on the drain layer 6 side, and the stored information “0” is stored in the storage element 12b on the drain layer 6 side. Write.

  When the storage information “0” is written to the storage element 12a on the source layer 5 side, the write gate voltage Vgw (= 10 V) is applied to the word line WL connected to the gate electrode 3, as shown in FIG. The bit line BL connected to the drain layer 6 is set to 0V, and 6V is applied to the bit line BL connected to the source layer 5 to generate hot electrons (electrons) generated in the LDD layer 5a on the source layer 5 side. The storage information “0” is written into the storage element 12 a on the source layer 5 side by being injected into the charge storage nitride film 9 of the storage element 12 a.

  Further, in the read operation of reading the storage information from the storage element 12a or 12b, when reading the storage information from the storage element 12b on the drain layer 6 side, as shown in FIG. A read gate voltage Vgr (= 3 V) is applied to the word line WL, the bit line BL connected to the drain layer 6 is set to 0 V, and 1.7 V is applied to the bit line BL connected to the source layer 5 to generate the cell current Ic. When the detected cell current Ic exceeds the determination current set as the median value of the separation width W, the storage information of the storage element 12b on the drain layer 6 side is determined to be “1”, and when the cell current Ic is equal to or less than the determination current The storage information is determined to be “0”, and the storage information of the storage element 12b on the drain layer 6 side is read.

  When reading storage information from the storage element 12a on the source layer 5 side, as shown in FIG. 18B, a read gate voltage Vgr (= 3V) is applied to the word line WL connected to the gate electrode 3, and the source The bit line BL connected to the layer 5 is set to 0 V, and 1.7 V is applied to the bit line BL connected to the drain layer 6 to detect the cell current Ic. When the cell current Ic exceeds the determination current, the source layer The storage information of the storage element 12a on the 5th side is determined as “1”, and the storage information is determined as “0” when the current is less than the determination current, and the storage information of the storage element 12a on the side of the source layer 5 is read.

  Further, in the erasing operation for erasing the stored information “0” in the memory elements 12 a and 12, an erasing gate voltage Vg (= −6 V) is applied to the word line WL connected to the gate electrode 3 as shown in FIG. 6V is applied to each of the bit lines BL connected to the source layer 5 and the drain layer 6 to cause hot holes (holes) generated in the respective LDD layers 5a and 6a to be charged in the respective storage elements 12a and 12b. The electrons are injected into the storage nitride film 9 to neutralize the electrons held in the charge storage nitride film 9 of the storage elements 12a and 12b, and the stored information written in the storage elements 12a and 12b is erased, that is, the storage elements The storage information of 12a and 12b is set to “1”.

When the memory elements 12a and 12b of all the chips are set in the erased state at the wafer level, a heat treatment at 350 ° C. for 4 hours is performed on the semiconductor wafer on which the chips of the plurality of nonvolatile semiconductor memory devices are formed after the erase operation. By applying the above, it is possible to improve the erasure of the stored information written in the storage elements 12a and 12b.
Further, when erasing the stored information “0” of either one of the memory elements 12a and 12b, the erase gate voltage Vg (= −6 V) is applied to the word line WL connected to the gate electrode 3 to erase the data. The erase operation may be performed by applying 6 V to the bit line BL and setting the bit line BL on the other side to a floating state.

Hereinafter, conventional verify writing in a MONOS type memory cell will be described.
As shown in FIG. 20, the conventional verify writing process has the storage element 12 read by the read operation when the storage information “0” is written to the storage element 12 of the memory cell 1 to be written. The target current Iref for confirming that the storage information “0” is written in the storage element 12 by the cell current Ic of the memory cell 1, that is, the holding state of the electrons held in the storage element 12 is constant. As a value, the write gate voltage Vgw applied to the gate electrode 3 of the memory cell 1 when electrons are injected into the charge storage nitride film 9 of the memory element 12 is the voltage at the time of the first electron injection. Even if the memory element 12 is difficult to write from the initial write voltage Vgws, the set write voltage V that can reliably set the cell current Ic of the memory element 12 to the target current Iref. Up to wset, it is divided into a plurality of times and set to increase stepwise with the write voltage width ΔVw. When electrons are injected in a plurality of times, the cell current Ic of the storage element 12 is When the cell current Ic exceeds the target current Iref when confirmed, electrons are injected into the memory element 12 at the write gate voltage Vgw set in a stepwise manner according to the write count k. When the cell current Ic is less than or equal to the target current Iref, the process is executed by not injecting electrons.

In this description, the initial write voltage Vgws is set to 7.9 V, the set write voltage Vgwset is set to 10 V, the write voltage width ΔVw is set to 0.3 V, the write gate from the initial write voltage Vgws to the set write voltage Vgwset The voltage Vgw is set to increase in 8 steps.
Such a verify writing process is executed in cooperation with the main control unit 31 and the control unit 29 of the stored information writing device 30, and the main control unit 31 mainly counts the number of times of writing k (k ≧ 0). The supply of the write gate voltage Vgw and the contents of the storage information to be written to the memory element 12 at the row address m and the column address n (m, n ≧ 0) of the memory cell array 20 of M rows and N columns (“1 ”Or“ 0 ”) to the control unit 29, and other processes are mainly handled by the control unit 29. Programs for executing these processes are stored in the storage unit 32 and the control unit 29. Each function means as hardware in the verify writing process is formed by program steps stored in advance in the built-in memory and executed by the main control unit 31 and the control unit 29.

Therefore, the storage unit 32 of the storage information writing device 30 stores a storage information table in which storage information to be written to the storage element 12 at each (m, n) address and the total number of times of writing K are stored. In addition, a count count area for counting the number of times of writing k is secured.
The built-in memory of the control unit 29 has a row count area and a column count area for counting the row address n and the column address m.

Hereinafter, a conventional verify write process will be described with reference to a flowchart shown in FIG.
The step name is represented by SSZ for the main control unit 31 of the storage information writing device 30 and SZ for the control unit 29.
(SSZ1) When the main control unit 31 of the stored information writing device 30 starts the verify writing process, the main writing unit Vgw is set to the initial writing voltage Vgws, and the initial writing gate voltage Vgw is set.

(SSZ2) The main control unit 31 having set the write gate voltage Vgw initializes the write count k in the count count area of the storage unit 32 as “1”.
(SSZ3) The main controller 31 generates the set write gate voltage Vgw by the variable write voltage generator 34 and supplies it to the row selection circuit 24, and also supplies the read gate voltage Vgr (3V constant in this description). Generated by the read voltage generator 36 and supplied to the row selection circuit 24.

(SSZ4) In parallel with this, the main control unit 31 transmits a write start notification for notifying the start of the verify write process to the control unit 29 (step SZ1).
(SZ1) On the other hand, the control unit 29 waiting for the arrival of the write start notification from the main control unit 31 proceeds to step SZ2 when receiving the write start notification. If the writing start notification is not received, the standby is continued.

(SZ2) Upon receiving the write start notification, the control unit 29 initializes the row address m in the row count area of the built-in memory to “0”.
(SZ3) The control unit 29 that has initialized the row address m initializes the column address n of the column count area of the built-in memory as “1”.
(SZ4) After the initialization, the control unit 29 performs the write operation in order to acquire the storage information to be written at the address (m, n) (address (0, 1) in this step) that executes the write operation. The storage information transmission request in which the address to execute is transmitted is transmitted to the main control unit 31 (step SSZ5).

(SSZ5) After transmitting the write start notification, the main control unit 31 waits for an incoming storage information transmission request from the control unit 29, and stores the storage information in the storage unit 32 when receiving the storage information transmission request. The storage information to be written at the address (m, n) is read from the table, and the read storage information is transmitted to the control unit 29 (step SZ5).
(SZ5) After transmitting the storage information transmission request, the control unit 29 waits for the arrival of storage information from the main control unit 31, and when the storage information is received, the received storage information is stored in the storage information “1”. Is determined to be unnecessary to inject electrons into the memory element 12 at the address, and the process proceeds to step SZ9.

If the received storage information indicates the storage information “0”, it is determined that it is necessary to inject electrons into the storage element 12 at the address, and the process proceeds to step SZ6.
(SZ6) The control unit 29 that determines that the electron injection into the storage element 12 at the address (from step SZ8 to step SZ8 is described as the storage element 12b) is necessary is the read voltage of the storage information writing device 30. The read gate voltage Vgr supplied from the generator 36 is selected, and the row selection circuit 24 selects the word line WL connected to the gate electrode 3 of the memory cell 1 having the memory element 12b at the address, and the word line A read gate voltage Vgr is supplied to WL, and 0 V generated by the bit line power supply circuit 25 is connected to the source layer 5 to the bit line BL connected to the drain layer 6 of the memory cell 1 by the column selection circuit 22. 1.7 V is supplied to the bit line BL, the cell current Ic at that time is read by the read circuit 26, and the read cell current Ic is read as the target current generating circuit 2 In the target current Iref is generated (= 14 .mu.A) and compared in the comparator circuit 27 receives the determination signal of the comparison result.

(SZ7) Upon receiving the determination signal from the comparison circuit 27, the control unit 29, when the determination signal indicates that the read cell current Ic exceeds the target current Iref, the electron to the storage element 12b It is determined that injection is necessary, and the process proceeds to step SZ8.
If the read cell current Ic is less than or equal to the target current Iref, it is determined that sufficient electrons have been injected into the storage element 12b and that no new electrons need to be injected, and the process proceeds to step SZ9.

  (SZ8) The control unit 29 that has determined that it is necessary to inject electrons into the storage element 12b selects the write gate voltage Vgw supplied from the variable write voltage generation unit 34 of the storage information writing device 30. The row selection circuit 24 selects the word line WL connected to the gate electrode 3 of the memory cell 1 having the memory element 12b, supplies the write gate voltage Vgw to the word line WL, and the column selection circuit 22 The bit line BL connected to the drain layer 6 of the memory cell 1 is supplied with 6V generated by the bit line power supply circuit 25, 0V is supplied to the bit line BL connected to the source layer 5, and the other bit lines BL are in a floating state. Then, electrons are injected into the charge storage nitride film 9 of the memory element 12b, and the process proceeds to step SZ9.

(SZ9) When the column address n in the column count area of the built-in memory is less than the total column number N, the control unit 29 determines that the write operation for the next column number n is performed, and proceeds to step SZ10. .
When the column address n is equal to or greater than the total column number N, the process proceeds to step SZ11.
(SZ10) The control unit 29 that has determined that the write operation for the next column number n is performed adds “1” to the column address n in the column count area, updates the column number n, and returns to step SZ4 to perform the same operation. Repeat the write operation to the new column of the row.

(SZ11) When the row address m in the row count area of the built-in memory is less than the total row number M, the control unit 29 determines that the write operation for the next row number m is performed, and proceeds to step SZ12. .
When the row address m is equal to or greater than the total number of rows M, the end of the write operation at the write count k (k = 1 in this step) is determined, and the process proceeds to step SZ13.

(SZ12) The control unit 29 that has determined that the write operation for the next row number m is performed adds “1” to the row address m in the row count area, updates the row number m, returns to step SZ3, and starts a new operation. Repeat the write operation to each column of the correct row.
(SZ13) The control unit 29 that has determined the end of the write operation at the write count k transmits a write operation end notification notifying the end of the current write operation to the main control unit 31 (step SSZ6). The process returns to step SZ1 through the connector Z, and waits for the arrival of the next write start notification from the main control unit 31.

(SSZ6) After transmitting the stored information, the main control unit 31 waits for the arrival of the write operation end notification from the control unit 29, and proceeds to step SSZ7 when the write operation end notification is received. . When the write operation end notification is not received, the standby is continued.
(SSZ7) When the write operation end notification is received, the main control unit 31 performs the next verify write processing when the write count k in the count count area of the storage unit 32 is less than the total write count K. It is determined that the process is to be performed and the process proceeds to step SSZ8.

When the number of writings k is equal to or greater than the total number of writings K, a series of verify writing processes is terminated.
(SSZ8) The control unit 29 that has determined that the next verify write processing is performed adds “1” to the write count k in the count count area, updates the write count k, and proceeds to step SSZ9. .
(SSZ9) The main control unit 31 that has updated the write count k sets the write gate voltage Vgw to the write gate voltage Vgw in order to set the current write gate voltage Vgw at the write count k (k = 2 in this step). A new write gate voltage Vgw is set by adding the width ΔVw.

(SSZ10) When the set write gate voltage Vgw exceeds the set write voltage Vgwset, the main control unit 31 having set a new write gate voltage Vgw proceeds to Step SSZ11.
When the set write gate voltage Vgw is equal to or lower than the set write voltage Vgwset, the process returns to step SSZ3, and the verify write process using the newly set write gate voltage Vgw is repeated.

  (SSZ11) The main control unit 31, which has determined that the set write gate voltage Vgw is higher than the set write voltage Vgwset, keeps the set write gate voltage Vgw constant at the set write voltage Vgwset. Then, the set write gate voltage Vgw is rewritten to the set write voltage Vgwset, and the process returns to step SSZ3 to repeat the verify write process using the newly set write gate voltage Vgw.

In the above description, writing and erasing in the wafer state is described as an example. However, the semiconductor wafer is diced and the nonvolatile semiconductor memory device is divided into chips, and then the memory cells of each chip are processed. Even in the case where processing such as writing is performed, it is possible to execute writing, erasing, and the like of desired storage information in the storage element by performing the same processing as described above.
Here, how the cell current Ic of the memory cell 1 having the memory element 12 in the conventional verify writing process changes will be described with reference to FIGS.

  As shown in FIG. 20, the write gate voltage Vgw supplied at the first (k = 1) write operation is 7.9 V, and the memory element 12 injected with electrons at the current write gate voltage Vgw As shown in FIG. 22, the cell current Ic of the memory cell 1 has about 19 μA, but exceeds the target current Iref (= 14 μA). Therefore, each memory information “0” stored in the memory cell array 20 is written. After completion of a series of write operations to the memory element 12, when the next time (k = 2) of the write gate voltage Vgw = 8.1 V, it is determined in step SZ7 that reinjection is necessary, and again Electrons are injected, and the cell current Ic becomes equal to or less than the target current Iref.

Further, when the storage information of the unwritten memory element 12 on the opposite side of the memory cell 1 is “1”, electrons are slightly injected into the memory element 12, and the unwritten memory element The 12 cell current Ic also decreases slightly.
In the subsequent write operation, as the number of times of writing k elapses, retention (electrons naturally leak from the storage element 12 via the first and second silicon oxide films 8 and 10, and the charge storage nitride film 9 ) And gate disturb (other unselected memory cells 1 that share the word line WL when electrons are injected into the storage element 12 of the selected memory cell 1). The electrons held in the storage element 12 of the non-selected memory cell 1 are removed or entered, and the amount of electrons held in the storage element 12 is reduced. Ic gradually increases.

When the cell current Ic exceeding the target current Iref is read in the read operation in step SZ6 due to the increase in the cell current Ic, reinjection is performed again in the determination in step SZ7 for the tenth time (k = 10) shown in FIG. In the meantime, the number of writings k is advanced, and the current writing gate voltage Vgw for the tenth time shown in FIG. 20 is 10 V, which is the same as the set writing voltage Vgwset. A write operation is performed at a high current write gate voltage Vgw (= 10 V) with respect to the easily writeable storage element 12 capable of writing the storage information “0” at the write gate voltage Vgw (= 8.1 V). Thereafter, the cell current Ic is reduced to about 2 μA and greatly reduced.
At this time, as shown in FIG. 22, when the storage information of the storage element 12 on the opposite side of the memory cell 1 is “1” (unwritten side), the storage element 12 has a high current write gate. Due to the influence of the voltage Vgw, more electrons are injected and a cell current Ic of about 33 μA flows.

  In the above-described conventional verify writing process, in the ideal case where rewriting is not performed on the storage element 12 in which the storage information [0] is once written, as shown in FIG. The standard deviation on the non-write side shown in the figure is equivalent to the standard deviation on the non-write side shown in the figure of FIG. 11, whereas the standard deviation on the write side is reduced. 11 is reduced to about ¼ of the standard deviation on the writing side in FIG. 11, and the separation width W is increased, thereby reducing the occurrence of erroneous reading when reading the storage information of each storage element 12.

  However, in the conventional verify writing process, as described with reference to FIG. 22 and the like, after storing the storage information “0” with the low write gate voltage Vgw into the easy-to-write memory element 12, the gate disturb or the like is performed. When the cell current Ic gradually increases and the cell current Ic exceeds the target current Iref, rewrite is performed by the write gate voltage Vgw that is increased with the lapse of the write count k. As a result of excessive writing and excessive electrons held in the memory element on the writing side, the cell current Ic is greatly reduced, so that the variation on the writing side increases and the standard deviation increases, and FIG. As shown in the table of FIG. 11, the standard deviation on the writing side is less than four times the standard deviation on the writing side of the table shown in FIG. 23 shown as an ideal case. 1 bit shown in Closer to the standard deviation in the case of a completion type, there is a problem that results in separation width W becomes narrow.

  The present invention has been made to solve the above-described problems, and provides a means for preventing erroneous reading in a reading operation by preventing rewriting to a storage element in which storage information “0” has been once written. The purpose is to provide.

  In order to solve the above problems, the present invention covers a semiconductor substrate, a gate electrode disposed opposite to the semiconductor substrate with a gate insulating film interposed therebetween, and both side surfaces of the gate electrode, and extends onto the semiconductor substrate. Two memories comprising an existing first silicon oxide film, a charge storage nitride film stacked on the first silicon oxide film, and a second silicon oxide film stacked on the charge storage nitride film A low-concentration diffusion layer formed on the semiconductor substrate under the two storage elements, and a high-concentration diffusion layer formed on the semiconductor substrate opposite to the gate electrode of the low-concentration diffusion layer In a non-volatile semiconductor memory device comprising: a write voltage applied to the gate electrode when a charge is injected into the charge storage nitride film of the memory element divided into a plurality of times; The voltage between the initial write voltage and the set write voltage is set to increase stepwise, and the charge injected at the write voltage is retained using the cell current flowing through the high-concentration diffusion layer. The target current for confirming the state is set so as to increase stepwise from the initial target current to the set target current at a slope larger than the slope at which the cell current increases due to the change in the charge holding state. In the case of injecting charges into the storage element, if the cell current exceeds the target current, the charge is injected into the storage element with the write voltage, and the cell current is equal to or less than the target current. In this case, charge is not injected into the memory element.

  As a result, the present invention assumes that for a memory element into which electrons have been injected so as to be less than or equal to the target current, the amount of electrons retained in the memory element decreases due to gate disturbance or the like, and the cell current gradually increases. In addition, it is possible to prevent the rewriting from being performed and to increase the separation width W between the writing side and the non-writing side to prevent erroneous reading in the reading operation.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a control system of the first embodiment, and FIG. 2 is a flowchart showing a writing process of the first embodiment.
In addition, the same part as the said prior art attaches | subjects the same code | symbol, and abbreviate | omits the description.
The configuration of the memory cell 1 and the memory cell array 20 as the nonvolatile semiconductor memory device of this embodiment is the same as that of the memory cell 1 and the memory cell array 20 shown in FIGS.

In FIG. 1, reference numeral 41 denotes a variable target current generating circuit that changes various settings according to control signals from the control unit 29 and generates a target current Iref to be compared with the cell current Ic read by the reading circuit 26. Thus, the target current Iref that is changed stepwise according to the number of times of writing k is generated.
The configuration of other control systems is the same as that in the case of FIG.

  The write processing of this embodiment is the same as the conventional verify write processing described with reference to FIG. 21, but when the storage information “0” is written to the storage element 12 of the memory cell 1 to be written. In addition, the memory information “0” is written in the memory element 12 by the cell current Ic of the memory cell 1 having the memory element 12 read by the read operation, that is, the electrons held in the memory element 12. The target current Iref is set differently when checking the holding state.

  That is, the target current Iref of this embodiment is surely written from the initial target current Irefs, which is the target current Iref at the time of reading the first cell current Ic, even if the memory element 12 that is difficult to write is written with the set write voltage Vgwset. The cell current Ic that can be written to is set up so as to increase in a stepwise manner with the current width ΔI, divided into a plurality of times until the set target current Irefset can be confirmed.

In the present embodiment, as shown in FIG. 3, the initial target current Irefs is set to 12.1 μA, the set target current Irefset is set to 14 μA, and the current width ΔI is set to 0.1 μA. From the initial target current Irefs to the set target current Irefset, The target current Iref is set to increase in 20 steps.
Further, the write gate voltage Vgw of this embodiment is set to increase in nine steps from the initial write voltage Vgws to the set write voltage Vgwset as in the conventional case.

The current width ΔI is preferably set to increase in the range of 0.1 μA or more and 0.2 μA or less.
When the current width ΔI is set to be larger than 0.2 μA, the initial target current Irefs is decreased by more than 4 μA with respect to the set target current Irefset, and the write gate that is increased with respect to one storage element 12 As a result of the write operation being performed many times at the voltage Vgw, excessive electrons are accumulated in the charge storage nitride film 9 of the storage element 12, and if the current width ΔI is set to less than 0.1 μA, the gate disturb For example, the number of electrons held in the charge storage nitride film 9 of the memory element 12 decreases and the cell current Ic becomes smaller than the increasing slope, and the read cell current Ic exceeds the target current Iref. This is because rewriting is performed.

For this reason, the slope of increase of the target current Iref (corresponding to the current width ΔI per one write operation) is larger than the slope of increase of the cell current Ic due to the change of the electron holding state in the memory element 12. Therefore, it is desirable to set so as to be as small as possible, that is, the current increase of the cell current Ic does not catch up.
In the writing process of this embodiment, when the storage information “0” is written in the storage element 12 to be written, the storage information “0” is written in the storage element 12 by the cell current Ic of the memory cell 1. 3 is set to the target current Iref that increases stepwise as shown in FIG. 3 described above, and the write gate voltage Vgw is set stepwise as in the prior art. When the cell current Ic of the memory element 12 is confirmed when electrons are injected in a plurality of times, the cell current Ic exceeds the target current Iref at that time. When the cell current Ic is equal to or lower than the target current Iref, electrons are injected at the write gate voltage Vgw that is set stepwise according to the number of times of writing k. By not It is the row.

  Such a writing process is executed in cooperation with the main control unit 31 and the control unit 29 of the stored information writing device 30, and the main control unit 31 performs a change in the target current Iref in addition to the same process as the conventional process. The other processes including the setting process of the current value of the target current Iref by the variable target current generation circuit 41 are mainly handled by the control unit 29, and a program for executing these processes is stored in the storage unit 32. Each function unit as hardware in the writing process of the present embodiment is formed by the steps of the program executed by the main control unit 31 and the control unit 29 in advance.

In addition, the storage unit 32 of the storage information writing device 30 stores a storage information table and a total number of times of writing K that are the same as the conventional one, and a number count area is secured.
Further, a row count area and a column count area similar to the conventional one are secured in the built-in memory of the control unit 29.
Hereinafter, the writing process of this embodiment will be described with reference to the flowchart shown in FIG.

The step name is represented by SSA for the main control unit 31 of the storage information writing device 30 and by SA for the control unit 29.
(SSA1) When starting the writing process, the main control unit 31 of the storage information writing device 30 sets the initial target current Iref using the target current Iref as the initial target current Irefs.
(SSA2) The main control unit 31 having set the target current Iref sets the write gate voltage Vgw to the initial write gate voltage Vgw in the same manner as in the conventional step SSZ1.

The subsequent operations of steps SSA3 and SSA4 of the main control unit 31 are the same as the operations of steps SSZ2 and SSZ3 of the conventional main control unit 31 described above, and thus the description thereof is omitted.
(SSA5) In parallel with the supply of the write gate voltage Vgw and the read gate voltage Vgr (constant 3 V in this embodiment), the main control unit 31 notifies the start of the write process with the set target current Iref attached The writing start notification to be transmitted is transmitted to the control unit 29 (step SA1).

(SA1) On the other hand, the control unit 29 waiting for the arrival of the write start notification from the main control unit 31 proceeds to step SA2 when receiving the write start notification. When the writing start notification is not received, the standby is continued.
(SA2) The control unit 29 that has received the write start notification controls the setting of the variable target current generation circuit 41 based on the target current Iref attached to the write start notification and sets the current write operation. The generated target current Iref is generated.

(SA3) The control unit 29 that has generated the target current Iref initializes the row address m in the same manner as in the conventional step SZ2.
The subsequent operations of steps SA4 to SA13 of the control unit 29 and step SSA6 of the main control unit 31 are the same as the operations of steps SZ3 to SZ12 of the conventional control unit 29 and step SSZ5 of the main control unit 31 described above. Therefore, the description is omitted.

In this case, the target current Iref generated by the variable target current generation circuit 41 is used as the target current Iref to be compared with the cell current Ic read by the comparison circuit 27 in step SA7.
(SA14) The control unit 29 that has determined the end of the write operation at the write count k transmits a write operation end notification notifying the end of the current write operation to the main control unit 31 (step SSA7), The process returns to step SA1 via the connector A, and waits for the arrival of the next write start notification from the main control unit 31.

(SSA7) After the storage information is transmitted, the main control unit 31 waits for the arrival of the write operation end notification from the control unit 29, and proceeds to step SSA8 when the write operation end notification is received. . When the write operation end notification is not received, the standby is continued.
(SSA8) When the write operation end notification is received, the main control unit 31 performs the next write process when the write count k in the count count area of the storage unit 32 is less than the total write count K. When this is determined, the process proceeds to step SSA9.

When the number of times of writing k is equal to or greater than the total number of times of writing K, the series of writing processing of this embodiment is terminated.
(SSA9) The controller 29 that has determined to perform the next writing process updates the writing count k in the same manner as in the conventional step SSZ8, and proceeds to step SSA10.
(SSA10) The main control unit 31 that has updated the write count k adds a current width ΔI to the target current Iref and sets a new target current Iref at the write count k (k = 2 in this step). A target current Iref is set.

(SSA11) The main control unit 31 having set a new target current Iref proceeds to step SSA12 when the set target current Iref exceeds the set target current Irefset.
When the set target current Iref is equal to or less than the set target current Irefset, the process proceeds to step SSA13.
(SSA12) The main control unit 31, which has determined that the set target current Iref is greater than the target current Irefset, sets the set target current Iref to be constant at the set target current Irefset. Iref is rewritten to the set target current Irefset, and the process proceeds to step SSA13.

In the present embodiment, as shown in FIG. 3, since the target current Iref is not set to be constant until the total number K of writing, this step is not executed.
(SSA13) The main control unit 31 having set a new target current Iref sets a new write gate voltage Vgw in the same manner as in the conventional step SSZ9.
(SSA14) When the new write gate voltage Vgw is set, the main control unit 31 proceeds to step SSA15 when the set write gate voltage Vgw exceeds the set write voltage Vgwset.

When the set write gate voltage Vgw is equal to or lower than the set write voltage Vgwset, the process returns to step SSA4 to perform the write process of the present embodiment using the newly set target current Iref and write gate voltage Vgw. Repeat.
(SSA15) The main control unit 31, which has determined that the set write gate voltage Vgw is higher than the set write voltage Vgwset, sets the set write gate voltage Vgw in the same way as the conventional step SSZ11. The write-in voltage Vgwset is rewritten, the process returns to step SSA4, and the write process of the present embodiment using the newly set target current Iref and write gate voltage Vgw is repeated.

A change in the cell current Ic of the memory cell 1 having the memory element 12 in the writing process of this embodiment will be described with reference to FIGS.
As shown in FIG. 3, the write gate voltage Vgw supplied during the first (k = 1) write operation is 7.9 V, and the memory element 12 injected with electrons at the current write gate voltage Vgw As shown in FIG. 4, the cell current Ic of the memory cell 1 has about 25 μA, but exceeds the target current Iref (= 12.2 μA), so that the storage information “0” of the memory cell array 20 is written. After a series of write operations to each storage element 12 to be inserted, when the next time (k = 2) write gate voltage Vgw = 8.1 V, it is determined in step SA8 that reinjection is necessary. Then, the electrons are injected again, and the cell current Ic decreases according to the holding state of the electrons stored in the charge storage nitride film 9, and in the example of FIG. 4, stepwise by the fifth injection (k = 5). Or less than the target current Iref that increases.

  In the subsequent write operation, even if the cell current Ic gradually increases due to a decrease in the amount of electrons retained in the memory element 12 due to gate disturbance or the like as the number of times of writing k has elapsed, as shown in FIG. In addition, since the target current Iref of the present embodiment is set to a slope larger than the slope of the increase in the cell current Ic, rewriting is performed on the memory element 12 into which electrons have been injected so as to be once less than the target current Iref. And the cell current Ic is not significantly reduced by the excessive write gate voltage Vgw. Therefore, as shown in FIG. 6, the standard deviation on the non-write side shown in FIG. 24, the standard deviation on the writing side is substantially equal to the standard deviation on the writing side in FIG. Reduced to about 65%, separation width There enlarged, it can be reduced that the erroneous reading occurs during the reading of the stored information from the storage element 12.

  As described above, in the writing process of this embodiment, the retention of electrons in the memory element 12 to be written is held using the target current Iref set to a slope larger than the slope of the increase in the cell current Ic due to gate disturb or the like. Since the writing operation is performed while checking the state, the rewriting is prevented from being performed on the storage element 12 in which the storage information “0” is once written, and the separation width W between the writing side and the non-writing side is prevented. Thus, erroneous reading in the reading operation can be prevented.

  As described above, in this embodiment, in a memory cell including two storage elements having electron storage nitride films formed on both sides of a gate electrode disposed opposite to a semiconductor substrate with a gate insulating film interposed therebetween, When the electrons are divided into a plurality of times and injected into the electron storage nitride film of the device, the write voltage applied to the gate electrode is set to increase stepwise from the initial write voltage to the set write voltage. At the same time, the target current for confirming the holding state of the electrons injected with the write voltage using the cell current flowing between the source layer and the drain layer is increased, and the cell current is increased by the change of the holding state of the electrons in the memory element. The cell current exceeds the target current when electrons are injected into the storage element by setting a stepwise increase from the initial target current to the set target current with a larger slope than When electrons are injected into the memory element at the write voltage, and electrons are not injected into the memory element when the cell current is equal to or lower than the target current, Even if the amount of electrons held in the storage element decreases due to gate disturbance, etc. due to gate disturbance, etc., the cell current gradually increases, preventing rewriting from being performed. The read-out separation width W can be increased to prevent erroneous reading in the reading operation.

FIG. 7 is a block diagram showing a control system of the second embodiment, and FIG. 8 is a flowchart showing a writing process of the second embodiment.
In addition, the same part as the said prior art attaches | subjects the same code | symbol, and abbreviate | omits the description.
The configuration of the memory cell 1 and the memory cell array 20 of this embodiment is the same as that of the memory cell 1 and the memory cell array 20 shown in FIGS.

In FIG. 7, reference numeral 45 denotes a variable read voltage generator, and the read gate voltage Vgr applied to the gate electrode 3 of the memory cell 1 at the time of a read operation in response to a read voltage generation command in which a set voltage is written from the main controller 31 It has a function of generating it by changing it stepwise according to the number of times of writing k.
The configuration of other control systems is the same as that in the case of FIG.

  The write processing of this embodiment is the same as the conventional verify write processing described with reference to FIG. 21, but when the storage information “0” is written to the storage element 12 of the memory cell 1 to be written. In the read operation, the memory cell 1 having the storage element 12 for confirming that the storage information “0” is written in the storage element 12, that is, the holding state of the electrons held in the storage element 12. The read gate voltage Vgr is set differently when reading the cell current Ic.

That is, the read gate voltage Vgr of the present embodiment is divided into a plurality of times and gradually decreased from the initial read voltage Vgrs, which is the read gate voltage Vgr at the time of reading the first cell current Ic, to the set read voltage Vgrset. Is set as follows.
In this embodiment, as shown in FIG. 9, the initial read voltage Vgrs is set to 3.62 V, the set read voltage Vgrset is set to 3.5 V, the read voltage width ΔVr is set to 0.03 V, and the set read voltage is set from the initial read voltage Vgrs. Until Vgrset, the read gate voltage Vgr is set to decrease in five steps, one step twice.

Further, the write gate voltage Vgw of the present embodiment is increased in 10 steps from the initial write voltage Vgws = 7.9 V to the set write voltage Vgwset = 10.6 V, with the write voltage width ΔVw being 0.3 V. Is set.
Note that the target current Iref of this embodiment is set to a constant value of 14 μA.
When the read gate voltage Vgr in the above read operation is decreased, the cell current Ic read from the same memory cell 1 is decreased, and the cell current Ic is decreased by 2 μA per 0.1 V of the read gate voltage Vgr.

Therefore, it is desirable to set the read voltage width ΔVr so as to decrease in the range of 0.01 V or more and 0.02 V or less.
If the read voltage width ΔVr is set to decrease within the range of 0.01 V or more and 0.02 V or less, the read cell current Ic decreases within the range of 0.1 μA or more and 0.2 μA or less. This is relatively equivalent to the case where the target current Iref is increased in the range of 0.1 μA or more and 0.2 μA or less in the first embodiment, and the charge accumulation of the memory element 12 is the same as described in the first embodiment. Excessive electrons are not accumulated in the nitride film 9, and the increase in the cell current Ic due to the decrease in the electrons held in the charge storage nitride film 9 of the memory element 12 by gate disturb or the like can be counteracted. This is because even if the current Iref is set to a constant value, the cell current Ic read from the memory cell 1 does not exceed the target current Iref as a result, and rewriting can be prevented. The

For this reason, the slope of decrease in the read gate voltage Vgr (corresponding to the read voltage width ΔVr per one write operation) is the slope in which the cell current Ic increases due to the change of the electron holding state in the memory element 12. It is desirable to set the state to be as small as possible with the inclination to cancel, that is, the state where the read cell current Ic does not increase.
In this embodiment, the read voltage width ΔVr is set to decrease by 0.03 V every second time, that is, by an average of 0.015 V per time, and the setting range of the read voltage width ΔVr described above is set. Thus, the inclination is set so as to cancel the inclination in which the cell current Ic increases due to the change in the electron holding state in the memory element 12.

  In the writing process of this embodiment, when the storage information “0” is written in the storage element 12 to be written, it is confirmed that the storage information “0” is written in the storage element 12. The read gate voltage Vgr when reading the cell current Ic of the memory cell 1 is set to the read gate voltage Vgr that decreases stepwise as shown in FIG. 9 as described above, and the target current Iref is set as in the prior art. When the write gate voltage Vgw is set to increase stepwise and electrons are injected in a plurality of times, the memory element 12 read at the set read gate voltage Vgr is used. If the cell current Ic exceeds the target current Iref when the cell current Ic is confirmed, the memory current is stored at the write gate voltage Vgw at that time stepwise set according to the number of times of writing k. Element 12 has electrons Injected, when the cell current Ic is less than the target current Iref is performed by not injecting electrons.

  Such a writing process is executed in cooperation with the main control unit 31 and the control unit 29 of the stored information writing device 30, and the main control unit 31 includes a variable read voltage generating unit in addition to the same process as the conventional one. 45 is in charge of the setting process of the read gate voltage Vgr by 45, and the other processes are mainly handled by the control unit 29. Programs for executing these processes are stored in advance in the storage unit 32 and the internal memory of the control unit 29. Thus, each function means as hardware in the writing process of the present embodiment is formed by the steps of the program executed by the main control unit 31 and the control unit 29.

In addition, the storage unit 32 of the storage information writing device 30 stores a storage information table and a total number of times of writing K that are the same as the conventional one, and a number count area is secured.
Further, a row count area and a column count area similar to the conventional one are secured in the built-in memory of the control unit 29.
Hereinafter, the writing process of this embodiment will be described with reference to the flowchart shown in FIG.

The step name is represented by SSB for the main control unit 31 of the storage information writing device 30 and SB for the control unit 29.
(SSB1) When the main control unit 31 of the stored information writing device 30 starts the writing process, the main gate 31 sets the first read gate voltage Vgr using the read gate voltage Vgr as the initial read voltage Vgrs.

(SSB2) The main control unit 31 having set the read gate voltage Vgr sets the write gate voltage Vgw to the initial write gate voltage Vgw in the same manner as in the conventional step SSZ1.
(SSB3) The main control unit 31 that has set the write gate voltage Vgw initializes the write count k in the same manner as in the conventional step SSZ2.
(SSB4) The main control unit 31 generates the set write gate voltage Vgw by the variable write voltage generation unit 34 and supplies it to the row selection circuit 24, and generates the set read gate voltage Vgr as a variable read voltage. Generated by the unit 45 and supplied to the row selection circuit 24.

(SSB5) In parallel with this, the main control unit 31 transmits a write start notification for notifying the start of the write process to the control unit 29 (step SB1).
Subsequent operations of steps SB1 to SB12 of the control unit 29 and step SSB6 of the main control unit 31 are the same as the operations of steps SZ1 to SZ12 of the conventional control unit 29 and step SSZ5 of the main control unit 31 described above. Therefore, the description is omitted.

In this case, in the read operation in step SB6, read gate voltage Vgr supplied from variable read voltage generating unit 45 of storage information writing device 30 is used.
(SB13) The control unit 29 that has determined the end of the write operation at the write count k transmits a write operation end notification for notifying the end of the current write operation to the main control unit 31 (step SSB7). The process returns to step SB1 via the connector B, and waits for the arrival of the next write start notification from the main control unit 31.

(SSB7) After the storage information is transmitted, the main control unit 31 waits for the arrival of the write operation end notification from the control unit 29, and when the write operation end notification is received, proceeds to step SSB8. To do. When the write operation end notification is not received, the standby is continued.
(SSB8) The main control unit 31 that has received the write operation end notification performs the next writing process when the write count k in the count count area of the storage unit 32 is less than the total write count K. And the process proceeds to step SSB9.

When the number of times of writing k is equal to or greater than the total number of times of writing K, the series of writing processing of this embodiment is terminated.
(SSB9) The control unit 29 that has determined to perform the next writing process updates the writing count k in the same manner as in the conventional step SSZ8, and proceeds to step SSB10.
(SSB10) The main control unit 31 that has updated the write count k sets a coefficient P to be multiplied by the read voltage width ΔVr to set the read gate voltage Vgr at the write count k (k = 2 in this step): Calculate with

P = INT ((k−1) / 2) (1)
The operation symbol INT () in this case indicates that the number after the decimal point in the parentheses is truncated and only the remaining integer is output. Since k = 2 in this step, P = INT (0.5) = 0 is calculated as the coefficient P.
As a result, the read gate voltage Vgr is set to decrease stepwise by setting one step twice.

(SSB11) The main control unit 31 that has calculated the coefficient P subtracts the value obtained by multiplying the read gate voltage Vgr by the read voltage width ΔVr and the coefficient P, and sets a new read gate voltage Vgr at the number of times of writing k.
(SSB12) The main control unit 31 having set a new read gate voltage Vgr proceeds to step SSB13 when the set read gate voltage Vgr is lower than the set read voltage Vgrset.

When the set read gate voltage Vgr is equal to or higher than the set read voltage Vgrset, the process proceeds to step SSB14.
(SSB13) The main control unit 31 that has determined that the set read gate voltage Vgr is lower than the read gate voltage Vgrset is set to keep the set read gate voltage Vgr constant at the set read voltage Vgrset. The read gate voltage Vgr is rewritten to the set read voltage Vgrset, and the process proceeds to step SSB14.

(SSB14) The main control unit 31 having set a new read gate voltage Vgr sets a new write gate voltage Vgw in the same manner as in the conventional step SSZ9.
(SSB15) When the set write gate voltage Vgw exceeds the set write voltage Vgwset, the main control unit 31 having set a new write gate voltage Vgw proceeds to Step SSB16.

When the set write gate voltage Vgw is less than or equal to the set write voltage Vgwset, the process returns to step SSB4, and the write process of this embodiment using the newly set read gate voltage Vgr and write gate voltage Vgw Repeat.
(SSB16) The main control unit 31, which has determined that the set write gate voltage Vgw is higher than the set write voltage Vgwset, sets the set write gate voltage Vgw in the same manner as in the conventional step SSZ11. The write-in voltage Vgwset is rewritten, the process returns to step SSB4, and the write process of the present embodiment using the newly set read gate voltage Vgr and write gate voltage Vgw is repeated.

  As shown in FIG. 5 of the first embodiment, the cell current Ic of the memory cell 1 having the storage element 12 in the writing process of the present embodiment is set as shown in FIG. 5 of the first embodiment, if the read gate voltage Vgr is constant. With the passage of the number of times of writing k, the amount of electrons retained in the storage element 12 decreases due to gate disturbance or the like, and the cell current Ic gradually increases. In this embodiment, however, the read gate voltage Vgr that decreases stepwise is gradually increased. The slope is set to a slope that cancels the slope of the increase in the cell current Ic, and the increase in the cell current Ic read from the storage element 12 is suppressed, so that electrons are once injected to be equal to or lower than the target current Iref. Since rewriting to the memory element 12 is prevented and the cell current Ic is not significantly reduced by the excessive writing gate voltage Vgw, as shown in FIG. 10, the non-writing shown in FIG. Side The quasi-deviation is almost the same as the standard deviation on the non-write side shown in FIG. 24 in the case of the conventional verify write process, whereas the standard deviation on the write side is the same as that shown in FIG. It is reduced to about 70% of the standard deviation on the insertion side, and the separation width W is expanded, so that it is possible to reduce the occurrence of erroneous reading when reading stored information from each storage element 12.

  As described above, in the writing process of this embodiment, the electrons of the memory element 12 to be written are used by using the read gate voltage Vgr set to a slope that cancels the slope of the increase in the cell current Ic due to gate disturb or the like. Since the writing operation is performed while confirming the holding state of the memory element, rewriting is prevented from being performed on the memory element 12 to which the memory information “0” has been once written, and the writing side and the non-writing side are separated. The width W can be increased to prevent erroneous reading in the reading operation.

  As described above, in this embodiment, in a memory cell including two storage elements having electron storage nitride films formed on both sides of a gate electrode disposed opposite to a semiconductor substrate with a gate insulating film interposed therebetween, When the electrons are divided into a plurality of times and injected into the electron storage nitride film of the device, the write voltage applied to the gate electrode is set to increase stepwise from the initial write voltage to the set write voltage. In addition, the read voltage applied to the gate electrode when confirming the holding state of the electrons injected by the writing voltage using the cell current flowing between the source layer and the drain layer is changed in the holding state of the electrons in the memory element. Is set to decrease in a stepwise manner from the initial read voltage to the set read voltage with a gradient that cancels the gradient in which the cell current increases, and is set when electrons are injected into the storage element. When the cell current read at the read voltage exceeds the target current for confirming the holding state of the electrons injected into the storage element, the cell current is injected into the storage element at the write voltage. When the current is lower than the target current, electrons are not injected into the memory element, so that the memory element into which the electrons are once injected to be lower than the target current is transferred to the memory element by gate disturb or the like. Even if the retention amount decreases and the cell current gradually increases, rewriting is prevented and the separation width W on the writing side and non-writing side is increased to prevent erroneous reading in the reading operation. be able to.

  In each of the above embodiments, the MONOS type memory cell as the nonvolatile semiconductor memory device has been described as the nMOS type. However, the same effect can be obtained even in the pMOS type. In this case, holes are injected into the charge storage nitride film of the memory element.

The block diagram which shows the control system of Example 1. Flow chart showing the writing process of the first embodiment The graph which shows the change of the write gate voltage of the write processing of Example 1, and a target current The graph which shows the change of the cell current at the time of the write-processing of Example 1 Part A enlarged view of FIG. Explanatory drawing which shows distribution of the cell current after the write-in process of Example 1. FIG. The block diagram which shows the control system of Example 2. Flow chart showing write processing of embodiment 2 The graph which shows the change of the write gate voltage of the write-in process of Example 2, and the read gate voltage Explanatory drawing which shows distribution of the cell current after the write-in process of Example 2. FIG. Explanatory diagram showing cell current distribution after conventional 1-bit complete write processing Explanatory drawing which shows the cross section of the conventional MONOS type memory cell Circuit diagram showing a conventional memory cell array Block diagram showing a conventional control system Circuit diagram showing equivalent circuit of conventional memory cell Explanatory diagram showing four storage states of a MONOS type memory cell Explanatory diagram showing a write operation of a MONOS type memory cell Explanatory diagram showing a read operation of a MONOS type memory cell Explanatory diagram showing erase operation of a MONOS type memory cell Graph showing change in write gate voltage in conventional verify write processing Flow chart showing conventional verify write processing Graph showing change in cell current during conventional verify write processing Explanatory drawing showing distribution of cell current after conventional ideal verify write processing Explanatory diagram showing cell current distribution after conventional verify write processing

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory cell 2 Semiconductor substrate 3 Gate electrode 4 Gate insulating film 5 High concentration diffusion layer (source layer)
5a, 6a LDD layer 6 High concentration diffusion layer (drain layer)
7 channel region 8 first silicon oxide film 9 charge storage nitride film 10 second silicon oxide film 12, 12a, 12b storage element 14 intermediate insulating film 15 contact plug 17 gate contact 20 memory cell array 22 column selection circuit 23 selection transistor 24 Row selection circuit 25 Bit line power supply circuit 26 Read circuit 27 Comparison circuit 28 Target current generation circuit 29 Control unit 30 Storage information writing device 31 Main control unit 32 Storage unit 34 Variable write voltage generation unit 36 Read voltage generation unit 41 Variable target Current generator 45 Variable read voltage generator

Claims (4)

A semiconductor substrate;
A gate electrode disposed opposite to the semiconductor substrate with a gate insulating film interposed therebetween;
A first silicon oxide film covering both side surfaces of the gate electrode and extending on the semiconductor substrate; a charge storage nitride film stacked on the first silicon oxide film; and the charge storage nitride film Two memory elements made of a second silicon oxide film stacked on
A low-concentration diffusion layer formed on each of the semiconductor substrates under the two storage elements;
A non-volatile semiconductor memory device comprising: a high-concentration diffusion layer formed on the semiconductor substrate opposite to the gate electrode of the low-concentration diffusion layer;
In the case where charges are injected into the charge storage nitride film of the memory element in a plurality of times, the write voltage applied to the gate electrode is changed from the initial write voltage which is the voltage at the first injection to the set write voltage. In between, set to increase gradually,
The target current for confirming the holding state of the charge injected at the write voltage using the cell current flowing through the high-concentration diffusion layer is greater than the slope at which the cell current increases due to the change in the holding state of the charge. Then, it is set to increase in steps between the initial target current and the set target current,
When injecting charge into the storage element, when the cell current exceeds the target current, charge is injected into the storage element with the write voltage, and when the cell current is equal to or less than the target current. A non-volatile semiconductor memory device characterized by not injecting charges into the memory element. In claim 1,
The non-volatile semiconductor memory device according to claim 1, wherein the inclination of the target current is set to increase in a range of 0.1 μA to 0.2 μA per time. A semiconductor substrate;
A gate electrode disposed opposite to the semiconductor substrate with a gate insulating film interposed therebetween;
A first silicon oxide film covering both side surfaces of the gate electrode and extending on the semiconductor substrate; a charge storage nitride film stacked on the first silicon oxide film; and the charge storage nitride film Two memory elements made of a second silicon oxide film stacked on
A low-concentration diffusion layer formed on each of the semiconductor substrates under the two storage elements;
A non-volatile semiconductor memory device comprising: a high-concentration diffusion layer formed on the semiconductor substrate opposite to the gate electrode of the low-concentration diffusion layer;
In the case where charges are injected into the charge storage nitride film of the memory element in a plurality of times, the write voltage applied to the gate electrode is changed from the initial write voltage which is the voltage at the first injection to the set write voltage. In between, set to increase gradually,
A read voltage applied to the gate electrode when confirming a holding state of the charge injected with the writing voltage using a cell current flowing through the high-concentration diffusion layer is changed according to a change in the holding state of the charge. Set the slope between the initial read voltage and the set read voltage to decrease step by step with a slope that cancels the increasing slope.
When injecting charge into the storage element, if the cell current read at the read voltage exceeds a target current for confirming the holding state of the charge injected into the storage element, the write A nonvolatile semiconductor memory device, wherein a charge is injected into the memory element with a voltage and no charge is injected into the memory element when the cell current is less than or equal to the target current. In claim 1,
The nonvolatile semiconductor memory device according to claim 1, wherein the slope of the read voltage is set to decrease in a range of 0.01 V or more and 0.02 V or less per time.

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