JP2009218390A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

A high-reliability and high-density semiconductor device is provided.
A lower semiconductor package 3 is directly mounted on a substrate 1 for electrical continuity, and an upper semiconductor package 2 is mounted on a substrate 1 via a first spacer 4 for electrical continuity. The upper semiconductor package 2 and the lower semiconductor package 3 are different from each other in height from the main surface of the substrate 1, and the first main surface of the substrate 1 and the first semiconductor package 3 are not in contact with each other. The second main surface opposite to the main surface is alternately arranged. Further, a part of the semiconductor element 7 constituting the lower semiconductor package 3 is arranged between the semiconductor element 7 constituting the upper semiconductor package 2 and the substrate 1, and the semiconductor element 7 constituting the lower semiconductor package 3 is arranged. A part of the first spacer 4 is disposed between the substrate 1 and the substrate 1.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device in which a plurality of semiconductor chips are mounted on a mounting substrate and a technique effective when applied to the manufacturing thereof.

  Various information devices such as large computers, personal computers, and portable devices have been improved in performance and miniaturization year by year. For this reason, while the semiconductor elements mounted on these devices have increased, the area of the substrate on which the semiconductor elements are mounted has been reduced, and there is a strong demand from the market to mount many large semiconductor elements on a limited substrate area. It has been. Techniques for meeting this market requirement include a technique for stacking a plurality of semiconductor elements on a semiconductor element mounted on a substrate, and a technique for mounting a plurality of semiconductor elements at different heights from the substrate. Has been developed.

  For example, in Japanese Patent Application Laid-Open No. 2002-176135 (Patent Document 1), a semiconductor module in which a semiconductor chip is mounted on one main surface of an insulating material and a plating film for heat dissipation is formed on the other main surface is manufactured. Disclosed is a technology for manufacturing a laminated semiconductor device having excellent heat dissipation characteristics by dropping a paste on a plating film and thermally connecting the plating film and a semiconductor chip when laminating this on an interposer. Has been.

  In Japanese Patent Laid-Open No. 8-236694 (Patent Document 2), an LSI chip is mounted on a carrier on which a wiring conductor is formed via fine bumps, a sealing resin is injected, and the LSI chip is thinned by polishing. After that, a three-dimensional stack module formed by connecting each carrier with a carrier connection bump through a through hole electrically connected to a wiring conductor is disclosed.

  Japanese Patent Laid-Open No. 2000-286380 (Patent Document 3) discloses that a stack assembly is formed by filling a resin between layers of solder-connected single carriers, and the stack assembly is solder-connected to a motherboard. A semiconductor mounting structure filled with a resin is disclosed.

  Japanese Patent Laying-Open No. 2004-335624 (Patent Document 4) discloses a semiconductor in which a first semiconductor package and a mounting substrate, and a first semiconductor package and a second semiconductor package are bonded with an adhesive layer made of an organic material. A module is disclosed.

  Japanese Patent Laying-Open No. 2006-278863 (Patent Document 5) describes a semiconductor device including a stacked semiconductor package configured by stacking a plurality of individual semiconductor packages and a base substrate on which the stacked semiconductor package is mounted. In the individual semiconductor package, at least the wiring of the wiring member fixed to the semiconductor element extends from only one side of the semiconductor element and is connected to the base.

  Japanese Patent Application Laid-Open No. 11-40745 (Patent Document 6) describes a plurality of semiconductor devices in which a plurality of leads protrude from a side surface of a package and are stacked on a wiring board. The protruding lengths of the leads of the semiconductor device are the same length, and at least the mounting end portions of the leads of one semiconductor device are arranged next to the mounting end portions of the leads of the other semiconductor devices in a state where they are overlapped with each other. It is configured.

Japanese Patent Application Laid-Open No. 2004-63777 (Patent Document 7) discloses a connection portion of a substrate on the outer side of the insulating film so that the insulating film which is a base member of the TCP type semiconductor device does not overlap with the connection portion of the substrate. It is stated that it is possible to ensure the life of the solder connection part of the electronic device by means of covering the lead part facing the semiconductor chip with a sealing resin, or by applying a resin to the lead under the semiconductor chip. ing.
JP 2002-176135 A JP-A-8-236694 JP 2000-286380 A JP 2004-335624 A JP 2006-278863 A Japanese Patent Laid-Open No. 11-40745 JP 2004-63777 A

  The present inventors are examining a method of alternately mounting adjacent semiconductor elements by changing the height from the substrate as a method of mounting many semiconductor elements on a limited substrate area. However, in the above method, the following problems are concerned when the thickness of the semiconductor element to be mounted is large. For example, the thermal expansion coefficient of a substrate made of glass epoxy resin (solidified by impregnating epoxy resin on a glass fiber cloth (glass cloth) stacked) is about 5 to 6 times that of a semiconductor element. Therefore, a thermal load caused by a thermal deformation difference between the substrate and the semiconductor element is generated in a solder connection portion that connects the two due to heat during use, changes in environmental temperature, and the like. The heat load increases as the semiconductor element is thicker and more rigid. Therefore, when the semiconductor element is thick, the reliability of the solder connection portion may be lowered. Furthermore, when the semiconductor element is thick, the height after mounting becomes high, so that mounting on a small device becomes difficult.

  In the above method, the following problems are concerned when the semiconductor element to be mounted is thin. For example, an external force may act on the semiconductor element when the semiconductor element is assembled or used. When an external force is applied to a thin semiconductor element, it is considered that the semiconductor element is cracked to cause a malfunction.

  An object of the present invention is to provide a semiconductor device with high reliability and high density.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  An embodiment of the invention disclosed in the present application will be briefly described as follows.

  In this embodiment, two upper semiconductor packages and three lower semiconductor packages are mounted on the first main surface of the substrate and the second main surface opposite to the first main surface, respectively. It is a semiconductor device. The lower semiconductor package is directly mounted on the substrate to establish electrical continuity, and the upper semiconductor package is mounted on the substrate via a spacer to provide electrical continuity. The semiconductor packages are arranged alternately on the main surface of the substrate without contacting each other with different heights from the main surface of the substrate. Further, a part of the semiconductor element constituting the lower semiconductor package is disposed between the semiconductor element constituting the upper semiconductor package and the substrate, and between the semiconductor element constituting the lower semiconductor package and the substrate, A part of the spacer is arranged.

  In this embodiment, two upper semiconductor packages and three lower semiconductor packages are mounted on the first main surface of the substrate and the second main surface opposite to the first main surface, respectively. A method for manufacturing a semiconductor device. First, after a spacer is arranged in a predetermined region of the main surface of the substrate, a predetermined region of the main surface of the substrate is arranged so that a part of the spacer is arranged between the semiconductor element constituting the lower semiconductor package and the substrate. The lower semiconductor package is disposed on the first semiconductor package, and then a part of the semiconductor element constituting the lower semiconductor package is disposed between the semiconductor element constituting the upper semiconductor package and the first surface of the spacer. An upper semiconductor package is disposed on the first surface. Thereafter, the substrate on which the lower and upper semiconductor packages are arranged is heated to a predetermined temperature and cooled to join the lower semiconductor package to the main surface of the substrate, and the upper semiconductor package is attached to the first surface of the spacer. Join.

  Among the inventions disclosed in the present application, the effects obtained by one embodiment will be briefly described as follows.

  Since the stress generated by the external force is reduced with respect to the semiconductor element constituting the semiconductor package, the semiconductor element can be prevented from cracking. Further, since a thin semiconductor element can be used, the height of the semiconductor device after the semiconductor package is mounted can be reduced. As a result, a highly reliable and high-density semiconductor device can be provided.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, the constituent elements (including element steps and the like) are not necessarily essential unless particularly specified and apparently essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings. In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1A is a top view of main parts of the semiconductor device according to the first embodiment, and FIG. 1B is a side view of main parts of the semiconductor device according to the first embodiment.

  In the first embodiment, two upper semiconductor packages 2 and three lower semiconductors are provided on the first main surface of the substrate 1 and the second main surface opposite to the first main surface, respectively. A semiconductor device in which the package 3 is mounted and a total of ten semiconductor packages are mounted on the main surface of the substrate 1 is illustrated.

  The lower semiconductor package 3 is directly mounted on the substrate 1 and is electrically connected. On the other hand, the upper semiconductor package 2 is mounted on the substrate 1 via the first spacer 4 to be electrically conductive. Furthermore, the terminal 1 is provided in the board | substrate 1, enabling transmission / reception of the signal with the exterior.

  The lower semiconductor package 3 is disposed at the center and both ends of the first main surface of the substrate 1, and the upper semiconductor package 2 and the lower semiconductor package 3 are separated from the first main surface of the substrate 1. Are arranged alternately on the first main surface of the substrate 1 without contacting each other. Similarly, the lower semiconductor package 3 is disposed at the center and both ends of the second main surface of the substrate 1, and the upper semiconductor package 2 and the lower semiconductor package 3 are the second semiconductor package 2 of the substrate 1. The heights from the main surface are different from each other and are alternately arranged on the second main surface of the substrate 1 without contact.

  As a result, even if the upper or lower semiconductor package 2 or 3 has a large area, it can be mounted with the interval between the adjacent upper semiconductor package 2 and lower semiconductor package 3 shortened. The interval between the mounting positions of the upper semiconductor package 2 and the lower semiconductor package 3 is, for example, 11 mm. The upper semiconductor package 2 is mounted at a position farther from the substrate 1 than the lower semiconductor package 3, but the distance between the main surface of the substrate 1 and the upper semiconductor package 2 is only the thickness of the first spacer 4. In addition, since the transmission path is short, it is possible to exchange signals at high speed.

  Further, a part of the first spacer 4 is disposed at the lower part on the end side of the lower semiconductor package 3. Further, the second spacer 6 is also disposed at the lower part on the end side of the lower semiconductor package 3 located at both ends of the substrate 1.

  The substrate 1 is a glass epoxy substrate having a wiring pattern of 6 layers or 8 layers connected to the inside by vias, and the thickness thereof is, for example, 1.2 mm. The first spacer 4 is a glass epoxy substrate having two layers of wiring patterns connected by vias on both sides thereof, and the thickness thereof is, for example, 0.3 mm. The first spacer 4 is bonded to the substrate 1 and the upper semiconductor package 2 using solder. The second spacers 6 positioned at both ends of the substrate 1 are members having a thickness equivalent to that of the first spacer 4. However, unlike the first spacer 4, the second spacer 6 does not need to be electrically connected to the substrate 1 or the upper semiconductor package 2, and can be made of a resin material that is less expensive than the first spacer 4. . Further, instead of the second spacer 6, a passive component such as a capacitor component having a thickness equivalent to that of the first spacer 4 can be used. Although the positions where the upper semiconductor package 2 and the lower semiconductor package 3 are mounted are different from each other, the configuration of the members is the same.

  Next, the configuration of the semiconductor package according to the first embodiment will be described with reference to FIG. FIG. 2A is a top view of the main part of the semiconductor package according to the first embodiment, and FIG. 2B is a side view of the main part of the semiconductor package according to the first embodiment.

  The semiconductor element 7 constituting the upper or lower semiconductor package 2 or 3 is, for example, a DRAM, and has a planar dimension of, for example, 7 mm × 12 mm, and a thickness of, for example, 0.1 to 0.2 mm. A plurality of terminals 8 are arranged side by side at a central portion along one direction of the circuit formation surface of the semiconductor element 7. The main material of the terminal 8 is, for example, gold, and the interval between the adjacent terminals 8 is, for example, 0.07 mm.

  On the circuit forming surface side of the semiconductor element 7, a polyimide wiring member having a wiring pattern made of a copper film on both surfaces (first surface and second surface opposite to the first surface) via a plurality of terminals 8. 9 is arranged. The planar dimension of the wiring member 9 is, for example, 3 mm × 11.5 mm, and the thickness thereof is, for example, 0.04 mm, which is smaller than the planar dimension of the semiconductor element 7. The surface of the wiring pattern is covered with a nickel film, and a part of the nickel film is covered with a solder resist film to prevent corrosion and electrical short circuit of the copper film constituting the wiring pattern. The wiring patterns on both sides are electrically connected by vias penetrating polyimide. The plurality of terminals 8 provided in the semiconductor element 7 are electrically and mechanically joined to a wiring pattern formed on the first surface of the wiring member 9, and the joints are sealed with a sealing resin 10. To ensure the reliability. For the sealing resin 10, for example, an epoxy resin, a polyimide resin, an elastomer resin, or a silicone resin can be used. A plurality of solder balls 11 are connected to the wiring pattern formed on the second surface of the wiring member 9. The interval between adjacent solder balls 11 is, for example, 0.5 mm. For the solder ball 11, for example, a material mainly composed of a tin-silver-copper alloy having a diameter of 0.2 to 0.3 mm is used. By bonding the semiconductor package 2 to the first spacer 4 using the solder balls 11 and bonding the semiconductor package 3 to the substrate 1, it is possible to function as a semiconductor device.

  In the semiconductor device according to the first embodiment, as described above, a part of the first or second spacer is located below the lower semiconductor package 3, thereby preventing the semiconductor element 7 from cracking. In addition, high reliability can be achieved while ensuring high reliability of the solder connection portion.

  Next, the effect obtained by the first embodiment will be described with reference to FIGS. FIGS. 3A and 3B are a top view and a side view of a principal part of a semiconductor device in which a part of the first and second spacers is not located at the lower part on the end part side of the lower semiconductor package, respectively. FIG. 5 is an enlarged side view of a lower semiconductor package of a semiconductor device in which a part of the first spacer is not in the lower part on the end side of the lower semiconductor package. FIG. FIG. 6 is a graph illustrating the relationship between the solder equivalent nonlinear distortion range and the thickness of the semiconductor element, and FIG. 7 is a solder connection life (relative value) and the semiconductor element. It is a graph explaining the relationship with the thickness.

  As shown in FIG. 3, when the first or second spacers 4 and 6 are not arranged on the main surface of the substrate 1, the surface of the semiconductor element 7 constituting the lower semiconductor package 3 and the substrate 1 side. A space of about 0.4 to 0.5 mm is formed between the main surface and the main surface.

As shown in FIG. 4, the length of the semiconductor element 7 protruding from the wiring member 9 (the length of the overhang portion) is L, the thickness of the semiconductor element 7 is h, and the external force acting on the semiconductor package during assembly and use Is W, and the length of the semiconductor element 7 in the depth direction of the paper is b. Although the location where the external force W acts cannot be specified, the stress generated in the semiconductor element 7 when the external force of the same magnitude is applied is greatest when the external force acts on the end of the semiconductor element 7. At this time, assuming that the end side of the wiring member 9 in the overhang portion is a fixed end and the end side of the semiconductor element 7 is a cantilever with a free end, the maximum bending moment M _max generated in the semiconductor element 7 is expressed by the following equation: It becomes.

Further, the maximum bending stress σ _max generated in the semiconductor element 7 is expressed by the following equation.

  On the other hand, as shown in FIG. 5, when the first spacer 4 is disposed at a part of the lower portion of the overhang portion of the semiconductor element 7 (here, the first spacer 4 is described as a representative example, and the second spacer 6 The description of the effect of the second spacer 6 is omitted, but the same effect is obtained when the second spacer 6 is provided.) Even if an external force W acts on the upper portion of the first spacer 4, a compressive stress is generated in the semiconductor element 7. The bending stress that causes cracking of the semiconductor element 7 is not generated. The bending stress generated in the semiconductor element 7 when the external force W is applied to a place where the first spacer 4 is not present is considered that the end side of the wiring member 9 is a fixed end and the end side of the first spacer 4 is a simple support end. And the bending moment at the load application point is expressed by the following equation.

The bending moment at the fixed end is given by

Even in this condition, the relationship between the maximum bending moment M _max and the maximum bending stress σ _max is expressed by the above equation (2). At this time, the absolute value of the bending moment is maximized when the external force W is applied at the position of L ₂ = L ₁ / √3, and is expressed by the following equation.

At this time, the maximum bending stress σ _max generated in the semiconductor element 7 is as follows.

When the above formula (2) and the above formula (6) are compared, the maximum bending stress σ _max when the first spacer 4 is disposed in a part of the lower portion of the overhang portion of the semiconductor element 7 and the overload of the semiconductor element 7 are compared. The ratio with the maximum bending stress σ _max when the first spacer 4 is not disposed in a part of the lower portion of the hang portion is expressed by the following equation.

Therefore, the bending stress generated in the semiconductor element 7 of the semiconductor device in which the first spacer 4 is arranged in a part of the lower part of the overhang portion of the semiconductor element 7 is applied to the first part of the lower part of the overhang part of the semiconductor element 7. Compared to the bending stress generated in the semiconductor element 7 of the semiconductor device in which the spacer 4 is not disposed, when the position of the end of the first spacer 4 is in the vicinity of the end of the semiconductor element 7 (L ₁ ≈L), 1/5 or less When the position of the end portion of the first spacer 4 is near the center of the overhang portion of the semiconductor element 7 (L ₁ ≈L / 2), it becomes 1/10 or less, and the bending stress can be greatly reduced, so that high reliability is achieved. Can be secured.

  When an external force is applied to the upper semiconductor package 2, the semiconductor element 7 is supported by the lower semiconductor package 3, so that the semiconductor element 7 can be prevented from cracking. However, if the space between the semiconductor element 7 constituting the upper semiconductor package 2 and the semiconductor element 7 constituting the lower semiconductor package 3 is large, the effect of preventing cracking of the semiconductor element 7 cannot be obtained. Therefore, it is necessary to configure the semiconductor device so as to reduce.

  Incidentally, as shown in the above formula (2), the bending stress is inversely proportional to the square of the thickness of the semiconductor element 7. In the semiconductor device in which the first spacer 4 is disposed in a part of the lower portion of the overhang portion of the semiconductor element 7, the tolerance to bending stress is large. Therefore, the first spacer 4 is disposed in a portion of the lower portion of the overhang portion of the semiconductor element 7. The thickness of the semiconductor element 7 can be made smaller than that of a semiconductor device that is not arranged. As a result, a semiconductor device having a thin and high density as a whole can be realized. Furthermore, since the semiconductor element 7 becomes thin, the reliability of the solder connection part with respect to the heat load at the time of use can be improved.

  Next, the improvement in the reliability of the solder connection part due to the thin semiconductor element 7 will be described. While the linear expansion coefficient of the substrate 1 is about 17 ppm / ° C., the linear expansion coefficient of the semiconductor element 7 is about 3 ppm / ° C., which is greatly different. For this reason, the difference in thermal deformation between the substrate 1 and the semiconductor element 7 due to changes in heat during use and temperature of use environment is large, and a large distortion occurs in the solder connecting these. At this time, when the semiconductor element 7 is thin and has low rigidity, the thermal deformation difference between the substrate 1 and the semiconductor element 7 is absorbed not only by the deformation of the solder but also by the deformation of the semiconductor element 7 itself. Become smaller. On the other hand, when the semiconductor element 7 is thick and has high rigidity, the difference in thermal deformation of the semiconductor element 7 is absorbed mainly only by the deformation of the solder, so that the distortion generated in the solder increases.

FIG. 6 shows the distortion generated in the solder connection portion and the thickness of the semiconductor element in the semiconductor device according to the first embodiment (semiconductor device in which the first spacer 4 is arranged in a part of the lower portion of the overhang portion of the semiconductor element 7). The graph figure of the result of having calculated | required the relationship with this by the finite element method is shown. The horizontal axis represents the thickness of the semiconductor element, and the vertical axis represents the considerable non-linear strain range considered to dominate the low cycle life of the solder. It can be confirmed that as the thickness of the semiconductor element increases, the considerable nonlinear distortion range of the solder increases. It is known that the Coffin-Manson rule expressed by the following equation holds for the relationship between the solder equivalent nonlinear strain range Δε _in and the low cycle fatigue life N _f .

Here, C _f and α are coefficients, and α is an approximate value 2 in the case of solder mainly composed of a tin-silver-copper alloy used in the first embodiment.

  FIG. 7 is a graph illustrating the relationship between the solder connection life and the thickness of the semiconductor element obtained by substituting the solder equivalent nonlinear strain range shown in FIG. The vertical axis is the relative solder connection life when the thickness of the semiconductor element is 0.1 mm, and the horizontal axis is the thickness of the semiconductor element. The thinner the semiconductor element is, the more significantly the solder connection life is increased. From this, it becomes possible to use the thin semiconductor element 7, thereby ensuring high reliability in the solder connection portion.

  As described above, according to the first embodiment, it is possible to provide a semiconductor device that prevents cracking of the semiconductor element 7 and ensures high reliability of the solder connection portion, and at the same time enables high-density mounting. .

  Next, a method for manufacturing a semiconductor package constituting the semiconductor device according to the first embodiment will be described in the order of steps with reference to side views of the main part of the semiconductor package shown in FIGS. 8 (a) to 8 (d).

  First, as shown in FIG. 8A, a semiconductor element 7 is prepared. Subsequently, as illustrated in FIG. 8B, the terminals 8 provided on the circuit formation surface of the semiconductor element 7 are bonded to the wiring pattern formed on the first surface of the wiring member 9. In the first embodiment, the terminal 8 provided in the semiconductor element 7 and the wiring pattern formed on the first surface of the wiring member 9 are bonded using ultrasonic waves.

  Subsequently, as illustrated in FIG. 8C, the liquid sealing resin 10 is poured between the semiconductor element 7 and the wiring member 9, and the temperature is increased and cured, whereby the terminal 8 provided in the semiconductor element 7. And the joint between the wiring pattern formed on the first surface of the wiring member 9 is sealed. In the first embodiment, the sealing resin 10 is formed after the terminal 8 provided in the semiconductor element 7 and the wiring pattern formed on the first surface of the wiring member 9 are joined, but the terminal 8 provided in the semiconductor element 7 Before bonding with the wiring pattern formed on the first surface of the wiring member 9, the sealing resin 10 before curing is provided on the first surface of the semiconductor element 7 or the wiring member 9, and then the bonding or resin is cured. It may be selected according to the characteristics of the resin used for sealing.

  Subsequently, as shown in FIG. 8D, the semiconductor package is completed by bonding the solder balls 11 to the wiring pattern formed on the second surface of the wiring member 9.

  Here, the manufacturing method of the semiconductor package manufactured using the semiconductor element 7 separated in advance has been described. However, in the semiconductor package according to the first embodiment, the planar dimension of the wiring member 9 is larger than that of the semiconductor element 7. Since it is small, it can be singulated after the above-described steps of FIGS. 8A to 8D in the state of the semiconductor wafer.

  Next, the manufacturing method of the semiconductor device according to the first embodiment will be described with reference to side views of the main part of the semiconductor device shown in FIGS. 9 (a) to 9 (d) and FIGS. 10 (a) to 10 (d). It demonstrates in order of a process.

  First, the substrate 1 is prepared as shown in FIG. 9A, and the first and second spacers 4 and 6 are arranged on the first main surface of the substrate 1 as shown in FIG. 9B. . At this time, paste-like solder is provided between the first and second spacers 4 and 6 and the connection portion of the substrate 1. Due to the viscosity of the paste-like solder, it is possible to prevent displacement of the positions of the first and second spacers 4 and 6 during the subsequent work.

  Subsequently, as shown in FIG. 9C, the lower semiconductor package 3 is disposed on the first main surface of the substrate 1. At this time, by providing paste-like solder or a flux material having an active effect between the lower semiconductor package 3 and the connection portion of the substrate 1, the position of the lower semiconductor package 3 can be changed during the subsequent operation. Deviation can be prevented. At this time, by controlling the amount of paste-like solder and the size of the solder balls 11 of the lower semiconductor package 3, the semiconductor element 7 and the first or second semiconductor element 7 constituting the lower semiconductor package 3 after mounting are controlled. The gap between the spacers 4 and 6 can be reduced.

  Subsequently, as shown in FIG. 9D, the upper semiconductor package 2 is disposed on the first main surface of the substrate 1. As in the case where the lower semiconductor package 3 is disposed, paste solder or a flux material having an active effect is provided between the upper semiconductor package 2 and the connection portion of the substrate 1 to perform subsequent operations. The position shift of the upper semiconductor package 2 can be prevented. At this time, by controlling the amount of paste-like solder and the size of the solder balls 11 of the upper semiconductor package 2, the semiconductor element 7 and the lower semiconductor package 3 constituting the upper semiconductor package 2 after mounting. The gap between the semiconductor element 7 and the semiconductor element 7 can be reduced.

  Thereafter, the first and second spacers 4 and 6 are heated by raising the temperature of the substrate 1 on which the first and second spacers 4 and 6, the lower semiconductor package 3 and the upper semiconductor package 2 are mounted above the melting temperature of the solder. The lower semiconductor package 3 and the upper semiconductor package 2 are soldered to the first main surface side of the substrate 1, respectively.

  Subsequently, as shown in FIGS. 10A to 10D, the second main surface of the substrate 1 (surface opposite to the first main surface) is used as an object with reference to FIG. 9 described above. In the same order as described, the first and second spacers 4 and 6, the lower semiconductor package 3 and the upper semiconductor package 2 are mounted on the second main surface side of the substrate 1, and the substrate 1 is melted with solder. By raising the temperature above the temperature, the first and second spacers 4, 6, the lower semiconductor package 3 and the upper semiconductor package 2 are soldered to the second main surface side of the substrate 1, respectively.

  When the temperature of the substrate 1 is raised to a temperature equal to or higher than the melting temperature of the solder, the solder on the first main surface side of the substrate 1 previously soldered is also melted, but the first main surface of the substrate 1 is affected by the surface tension of the solder. The first and second spacers 4 and 6 on the side, the lower semiconductor package 3 and the upper semiconductor package 2 can be prevented from dropping from the first main surface side of the substrate 1. Through the above steps, all the first and second spacers 4, 6, the lower semiconductor package 3 and the upper semiconductor package 2 are moved to the first main surface side and the second main surface of the substrate 1 in two temperature raising steps. The semiconductor device can be substantially completed by soldering to the surface side.

  In the first embodiment, a plurality of semiconductor packages are mounted on both main surfaces of the substrate 1, but a plurality of semiconductor packages may be mounted only on one main surface of the substrate 1. In this case, The semiconductor device can be manufactured by performing only the process shown in FIG.

(Embodiment 2)
A semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 11A is a top view of the main part of the semiconductor device according to the second embodiment, and FIG. 11B is a side view of the main part of the semiconductor device according to the second embodiment. The difference from the semiconductor device according to the first embodiment described above is that the first surface of the first and second spacers 4 and 6 has an elastic modulus lower than that of the first and second spacers 4 and 6 by about one digit or more. The elastic body 12 having 1 MPa to 1 GPa is provided.

  In the semiconductor device in which the first or second spacers 4 and 6 are arranged in a part of the lower part of the overhang portion of the semiconductor element 7 constituting the lower semiconductor package 3, bending stress generated in the semiconductor element 7 due to external force is reduced. For this, it is necessary to dynamically support a part of the surface of the semiconductor element 7 on the substrate 1 side by the first or second spacers 4 and 6. Therefore, if the distance between the semiconductor element 7 constituting the lower semiconductor package 3 and the first or second spacers 4 and 6 is increased due to the thickness error or assembly error of each member, the semiconductor element 7 is cracked. It is feared that this will occur.

  In the second embodiment, the elastic body 12 is provided on the first surfaces of the first and second spacers 4 and 6 located in a part of the lower part of the overhang portion of the semiconductor element 7 constituting the lower semiconductor package 3. Thus, even when no external force is applied, the semiconductor element 7 constituting the lower semiconductor package 3 and the first or second spacers 4 and 6 are physically connected via the elastic body 12. As a result, when an external force is applied, the elastic body 12 is compressively deformed and can support a large area of the surface of the semiconductor element 7 on the substrate 1 side, so that the effect of preventing the cracking of the semiconductor element 7 can be obtained more easily. Become.

  When the elastic body 12 provided on the first surface of the first or second spacer 4 or 6 has a low elastic modulus, the reaction force acting on the semiconductor element 7 is reduced even if it is compressively deformed by an external force. It is conceivable that cracking of the film cannot be prevented. On the other hand, when the elastic body 12 provided on the first surface of the first or second spacer 4 or 6 has a high elastic modulus, in the manufacturing process of soldering the lower semiconductor package 3 and the substrate 1, the lower semiconductor package It is considered that it is difficult to obtain a sufficient solder self-alignment effect by restricting the lateral movement of 3. In the manufacturing process of the semiconductor device, the elastic body 12 provided on the first surface of the first or second spacer 4 or 6 is exposed to a temperature higher than the melting temperature of the solder. is there. In the second embodiment, an elastomer resin is used for the elastic body 12 provided on the first surface of the first or second spacer 4 or 6 as a material that can avoid these concerns. However, it is not limited to the elastomer resin, and it is needless to say that it can be used for the elastic body 12 as long as it can avoid the above-mentioned concern even if it is another material such as a silicone resin. .

  Next, a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to side views of the main part of the semiconductor device shown in FIGS. 12 (a) to 12 (e).

  The difference from the semiconductor device manufacturing method according to the first embodiment described above is that, as shown in FIG. 12, before the lower semiconductor package 3 is arranged on the first main surface or the second main surface of the substrate 1. The elastic body 12 is bonded to the first surface of the first or second spacer 4 or 6 mounted on the first main surface or the second main surface of the substrate 1.

  In the method of manufacturing a semiconductor device according to the second embodiment, the first surface of the first or second spacer 4 or 6 located in a part of the lower part of the overhang portion of the semiconductor element 7 constituting the lower semiconductor package is previously formed. After the elastic body 12 is bonded, the first or second spacers 4 and 6 are mounted on the first main surface or the second main surface of the substrate 1. Thereafter, the semiconductor device is substantially completed by arranging and soldering the upper and lower semiconductor packages 2 and 3 in the same manner as in the first embodiment. The element 7 and the elastic body 12 provided on the first surface of the first or second spacer 4 or 6 do not adhere to each other but only contact with each other.

(Embodiment 3)
A semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 13A is a top view of the main part of the semiconductor device according to the third embodiment, and FIG. 13B is a side view of the main part of the semiconductor device according to the third embodiment. The difference from the semiconductor device according to the first embodiment described above is that the circuit formation surface of the semiconductor element 7 constituting the upper and lower semiconductor packages 2, 3, that is, the substrate 1 side of the semiconductor element 7 not sealed with resin. The surface protection member 13 is provided on the surface. For the surface protection member 13, for example, an epoxy resin, a polyimide resin, an elastomer resin, or a silicone resin can be used.

  By providing the surface protection member 13 on the circuit formation surface of the semiconductor element 7, the space between the surface of the semiconductor element 7 on the substrate 1 side and the substrate 1 can be reduced as in the above-described second embodiment. The effect of preventing cracking is more easily obtained. Furthermore, since the circuit formation surface of the semiconductor element 7 is protected without being exposed, malfunction of the semiconductor element 7 due to light or the like can be prevented, and a more reliable semiconductor device can be provided.

  Next, a first manufacturing method of a semiconductor package according to the third embodiment will be described with reference to side views of the main part of the semiconductor package shown in FIGS. 14 (a) to 14 (d).

  The difference from the method of manufacturing the semiconductor device according to the first embodiment described above is that, in FIG. 14C, after forming the sealing resin 10, the surface protection member 13 is applied to the circuit formation surface of the semiconductor element 7. It is that you are. In the first manufacturing method of the semiconductor package according to the third embodiment, after the sealing resin 10 is applied and cured, the sealing is performed on the circuit formation surface of the semiconductor element 7 that is not sealed with the sealing resin 10. A surface protection member 13 made of a material different from the resin 10 is applied and cured.

  When the curing conditions of the sealing resin 10 and the curing conditions of the surface protection member 13 are similar, they can be cured at once. In this case, since the resin curing step can be performed once, the manufacturing cost and the manufacturing time can be reduced. The other manufacturing processes of the semiconductor package are the same as the manufacturing processes of the upper or lower semiconductor packages 2 and 3 according to the first embodiment. The method of manufacturing the semiconductor device by mounting the manufactured semiconductor package on the first main surface and the second main surface of the substrate 1 is the same as that of the first embodiment described above.

  Next, a second method for manufacturing a semiconductor package according to the third embodiment will be described with reference to side views of the main part of the semiconductor package shown in FIGS. 15 (a) to 15 (d).

  In the first manufacturing method of the semiconductor package of the third embodiment described above, different materials are used for the sealing resin 10 and the surface protection member 13, but the second manufacturing method of the semiconductor package of the third embodiment. Then, for the sealing resin 10 and the surface protection member 13, the same material suitable for both the sealing of the joint and the surface protection of the circuit formation surface of the semiconductor element 7 is used, and a plurality of terminals 8 provided in the semiconductor element 7 are provided. Before bonding the wiring pattern formed on the first surface of the wiring member 9, the surface protection member 13 is applied to the entire circuit forming surface of the semiconductor element 7.

  In the second manufacturing method of the semiconductor package of the third embodiment, the entire surface protection member is formed in the step of bonding the plurality of terminals 8 provided in the semiconductor element 7 and the wiring pattern formed on the first surface of the wiring member 9. By increasing the temperature to 13 curing temperature, the bonding of the plurality of terminals provided in the semiconductor element 7 and the wiring pattern formed on the first surface of the wiring member 9, the sealing of the bonding portion, and the formation of the surface protection member 13 are simultaneously performed. Therefore, the manufacturing cost and the manufacturing time can be further reduced.

(Embodiment 4)
A semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. FIG. 16A is a top view of main parts of the semiconductor device according to the fourth embodiment, and FIG. 16B is a side view of main parts of the semiconductor device according to the fourth embodiment. FIG. 17 is a side view of the main part of the semiconductor device studied by the present inventors.

  For example, in the semiconductor device according to the first embodiment described above, since there are an odd number (five) of semiconductor packages respectively mounted on the first main surface or the second main surface of the substrate 1, The lower semiconductor package 3 can be arranged. However, when the number of semiconductor packages mounted on the first main surface or the second main surface of the substrate 1 is an even number, the upper semiconductor package 2 is disposed at one end of the substrate 1. .

  In the semiconductor device according to the fourth embodiment, as shown in FIG. 16, there are an even number (two) of semiconductor packages mounted on the first main surface or the second main surface of the substrate 1. The lower semiconductor package 3 is disposed on both ends of the substrate 1 by disposing the substrate mounting component 14 on the main surface of the central portion.

  However, as shown in FIG. 17, for example, when the substrate mounting component 14 is not disposed in a part of the lower portion of the overhang portion of the semiconductor element 7 constituting the upper semiconductor package 2, the semiconductor is caused by bending stress due to external force. There is a concern about cracking of the element 7. However, in the fourth embodiment, the substrate mounting component 14 is arranged in a part of the lower part of the overhang portion of the semiconductor element 7 constituting the upper semiconductor package 2, so that the substrate mounting component 14 is applied when an external force is applied. However, supporting the semiconductor element 7 can reduce the bending stress and prevent the semiconductor element 7 from cracking. For example, a chip capacitor can be used for the substrate mounting component 14. Since the chip capacitor is a passive component that needs to be mounted somewhere on the substrate 1, the chip capacitor is disposed below the upper semiconductor package 2, for example, so that the substrate 1 is smaller than the substrate 1 shown in FIG. 17. Can be implemented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor device in which a plurality of semiconductor chips are stacked and mounted on a substrate.

FIG. 3A is a top view of the main part of the semiconductor device according to the first embodiment, and FIG. 2B is a side view of the main part of the semiconductor device according to the first embodiment. (A) is a principal part top view of the semiconductor package by this Embodiment 1, (b) is a principal part side view of the semiconductor package by this Embodiment 1. FIG. (A) And (b) is the principal part top view and principal part side view of a semiconductor device which a part of 1st spacer which the present inventors examined, respectively is not in the lower part of the lower semiconductor package. FIG. 6 is an enlarged side view of a lower semiconductor package of a semiconductor device in which a part of the first spacer studied by the present inventors is not under the lower semiconductor package. FIG. 6 is an enlarged side view of a lower semiconductor package of a semiconductor device in which a part of the first spacer according to the first embodiment is located under the lower semiconductor package. It is a graph explaining the relationship between the solder equivalent nonlinear distortion range and the thickness of a semiconductor element. It is a graph explaining the relationship between a solder connection lifetime (relative value) and the thickness of a semiconductor element. (A)-(d) is a principal part side view of the semiconductor package explaining the manufacturing method of the semiconductor package which comprises the semiconductor device by this Embodiment 1 in order of a process. (A)-(d) is a principal part side view of the semiconductor device explaining the manufacturing method of the semiconductor device by this Embodiment 1 in order of a process. (A)-(d) is a principal part side view of the semiconductor device explaining the manufacturing method of the semiconductor device by this Embodiment 1 in order of a process. (A) is a principal part top view of the semiconductor device by this Embodiment 2, (b) is a principal part side view of the semiconductor device by this Embodiment 2. FIG. (A)-(e) is a principal part side view of the semiconductor device explaining the manufacturing method of the semiconductor device by this Embodiment 2 in order of a process. (A) is a principal part top view of the semiconductor device by this Embodiment 3, (b) is a principal part side view of the semiconductor device by this Embodiment 3. FIG. (A)-(d) is a principal part side view of the semiconductor package explaining the 1st manufacturing method of the semiconductor package by this Embodiment 3 in order of a process. (A)-(d) is a principal part side view of the semiconductor package explaining the 2nd manufacturing method of the semiconductor package by this Embodiment 3 in order of a process. (A) is a principal part top view of the semiconductor device by this Embodiment 4, (b) is a principal part side view of the semiconductor device by this Embodiment 4. FIG. It is a principal part side view of the semiconductor device which the present inventors examined.

Explanation of symbols

1 substrate 2 semiconductor package (upper semiconductor package, second semiconductor package)
3 Semiconductor package (lower semiconductor package, first semiconductor package)
4 First Spacer 5 Terminal 6 Second Spacer 7 Semiconductor Element 8 Terminal 9 Wiring Member 10 Sealing Resin 11 Solder Ball 12 Elastic Body 13 Surface Protection Member 14 Board Mounted Component

Claims (25)

Having two or more semiconductor packages on the main surface of the substrate,
The first semiconductor package is directly mounted on the main surface of the substrate,
The second semiconductor package is adjacent to the first semiconductor package and mounted on the main surface of the substrate via a spacer,
A part of the semiconductor element constituting the first semiconductor package is disposed between the semiconductor element constituting the second semiconductor package and the main surface of the substrate,
A part of the spacer is disposed between a semiconductor element constituting the first semiconductor package and a main surface of the substrate.   2. The semiconductor device according to claim 1, wherein the first semiconductor package and the second semiconductor package are respectively formed on a first main surface of the substrate and a second main surface opposite to the first main surface. A semiconductor device which is mounted.   2. The semiconductor device according to claim 1, wherein the first semiconductor package is mounted on main surfaces of both end portions of the substrate.   The semiconductor device according to claim 1, wherein a height of the first semiconductor package from the main surface of the substrate is different from a height of the second semiconductor package from the main surface of the substrate. Semiconductor device.   2. The semiconductor device according to claim 1, wherein an elastic body having an elastic modulus of 1 MPa to 1 GPa is provided on a first surface of the spacer located between a semiconductor element constituting the first semiconductor package and a main surface of the substrate. A semiconductor device is provided.   2. The semiconductor device according to claim 1, wherein an elastomer resin is provided on a first surface of the spacer located between a semiconductor element constituting the first semiconductor package and a main surface of the substrate. A semiconductor device.   2. The semiconductor device according to claim 1, wherein a wiring pattern is formed on each of the first surface of the spacer and the second surface opposite to the first surface, and the wiring pattern and the spacer formed on the first surface of the spacer. And a wiring pattern formed on the second surface of the semiconductor device.   2. The semiconductor device according to claim 1, wherein the spacer is composed of a passive component. The semiconductor device according to claim 1, wherein each of the first and second semiconductor packages includes a wiring member,
A wiring pattern is formed on each of the first surface of the wiring member and the second surface opposite to the first surface, and the wiring pattern formed on the first surface of the wiring member and the second surface of the wiring member are formed. Electrical continuity is taken with the printed wiring pattern,
A semiconductor device, wherein a wiring pattern formed on a first surface of the wiring member and a semiconductor element constituting the first or second semiconductor package are bonded via a first electrode.   10. The semiconductor device according to claim 9, wherein a planar dimension of the wiring member is smaller than a planar dimension of a semiconductor element constituting the first or second semiconductor package.   10. The semiconductor device according to claim 9, wherein a space between a semiconductor element constituting the first or second semiconductor package and the first surface of the wiring member is sealed with resin.   10. The semiconductor device according to claim 9, wherein a surface protection member is provided on the entire surface of the semiconductor element constituting the first or second semiconductor package on the substrate side. 10. The semiconductor device according to claim 9, wherein a gap between a semiconductor element constituting the first or second semiconductor package and the first surface of the wiring member is sealed with resin,
A surface protection member made of a material different from the resin is provided on a surface on the substrate side of the semiconductor element constituting the first or second semiconductor package not sealed with the resin. apparatus. The semiconductor device according to claim 9, wherein a wiring pattern formed on a second surface of the wiring member constituting the first semiconductor package and a main surface of the substrate are bonded via a second electrode,
A semiconductor device, wherein a wiring pattern formed on a second surface of the wiring member constituting the second semiconductor package is bonded to a first surface of the spacer via the second electrode.   15. The semiconductor device according to claim 14, wherein the second electrode is a solder ball. The main surface of the substrate has two or more semiconductor packages and passive elements,
The first semiconductor package is directly mounted on the main surface of the substrate,
The second semiconductor package is adjacent to the first semiconductor package, and is mounted on the main surface of the substrate via a spacer.
The passive element is adjacent to the opposite side of the second semiconductor package to the first semiconductor package and is directly mounted on the main surface of the substrate,
A part of the semiconductor element constituting the first semiconductor package and a part of the passive element are arranged between the semiconductor element constituting the second semiconductor package and the main surface of the substrate,
A part of the spacer is disposed between a semiconductor element constituting the first semiconductor package and a main surface of the substrate.   17. The semiconductor device according to claim 16, wherein the first semiconductor package and the second semiconductor package are respectively formed on a first main surface of the substrate and a second main surface opposite to the first main surface. A semiconductor device which is mounted.   17. The semiconductor device according to claim 16, wherein a height of the first semiconductor package from the main surface of the substrate is different from a height of the second semiconductor package from the main surface of the substrate. Semiconductor device. A method of manufacturing a semiconductor device comprising the following steps:
(A) a step of arranging a spacer in a predetermined region of the main surface of the substrate;
(B) The first semiconductor package in a predetermined region of the main surface of the substrate such that a part of the spacer is disposed between the semiconductor element constituting the first semiconductor package and the main surface of the substrate. Arranging the process,
(C) The first surface of the spacer so that a part of the semiconductor element constituting the first semiconductor package is disposed between the semiconductor element constituting the second semiconductor package and the first surface of the spacer. Disposing the second semiconductor package in
(D) The substrate on which the first and second semiconductor packages are arranged is heated to a predetermined temperature and cooled to join the first semiconductor package to the main surface of the substrate, and the first Bonding the semiconductor package of 2 to the first surface of the spacer;   20. The method of manufacturing a semiconductor device according to claim 19, wherein the first semiconductor package and the substrate, the second semiconductor package and the spacer, and the spacer and the substrate are joined using solder. A method for manufacturing a semiconductor device.   21. The method of manufacturing a semiconductor device according to claim 20, wherein in step (d), the temperature is raised to a solder melting temperature or higher. 20. The method of manufacturing a semiconductor device according to claim 19, further comprising the following steps between the step (a) and the step (b);
(E) A step of bonding an elastic body having an elastic modulus of 1 MPa to 1 GPa to the first surface of the spacer located between the semiconductor element constituting the first semiconductor package and the main surface of the substrate. 20. The method of manufacturing a semiconductor device according to claim 19, further comprising the following steps before the step (a):
(F) bonding a semiconductor element constituting the first or second semiconductor package and a wiring pattern formed on the first surface of the wiring member with a first electrode;
(G) sealing a gap between a semiconductor element constituting the first or second semiconductor package and the first surface of the wiring member with a resin;
(H) a step of heating the first and second semiconductor packages to cure the resin;
(I) forming a surface protection member on a surface of the semiconductor element that is not sealed with the resin and that constitutes the first or second semiconductor package after mounting;
(J) A step of curing the surface protection member by raising the temperature of the first and second semiconductor packages. 20. The method of manufacturing a semiconductor device according to claim 19, further comprising the following steps before the step (a):
(F) bonding a semiconductor element constituting the first or second semiconductor package and a wiring pattern formed on the first surface of the wiring member with a first electrode;
(G) sealing a gap between a semiconductor element constituting the first or second semiconductor package and the first surface of the wiring member with a resin;
(H) a step of forming a surface protection member on a surface of the semiconductor element which is not sealed with the resin and which constitutes the first or second semiconductor package after mounting;
(I) A step of heating the first and second semiconductor packages to cure the resin and the surface protection member. 20. The method of manufacturing a semiconductor device according to claim 19, further comprising the following steps before the step (a):
(F) bonding a semiconductor element constituting the first or second semiconductor package and a wiring pattern formed on the first surface of the wiring member with a first electrode;
(G) forming a surface protection member on the surface of the semiconductor element constituting the first or second semiconductor package after mounting on the substrate side;
(H) A step of heating the first and second semiconductor packages to cure the surface protection member.

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